| 1 | /* |
| 2 | * |
| 3 | * tdfxfb.c |
| 4 | * |
| 5 | * Author: Hannu Mallat <hmallat@cc.hut.fi> |
| 6 | * |
| 7 | * Copyright © 1999 Hannu Mallat |
| 8 | * All rights reserved |
| 9 | * |
| 10 | * Created : Thu Sep 23 18:17:43 1999, hmallat |
| 11 | * Last modified: Tue Nov 2 21:19:47 1999, hmallat |
| 12 | * |
| 13 | * I2C part copied from the i2c-voodoo3.c driver by: |
| 14 | * Frodo Looijaard <frodol@dds.nl>, |
| 15 | * Philip Edelbrock <phil@netroedge.com>, |
| 16 | * Ralph Metzler <rjkm@thp.uni-koeln.de>, and |
| 17 | * Mark D. Studebaker <mdsxyz123@yahoo.com> |
| 18 | * |
| 19 | * Lots of the information here comes from the Daryll Strauss' Banshee |
| 20 | * patches to the XF86 server, and the rest comes from the 3dfx |
| 21 | * Banshee specification. I'm very much indebted to Daryll for his |
| 22 | * work on the X server. |
| 23 | * |
| 24 | * Voodoo3 support was contributed Harold Oga. Lots of additions |
| 25 | * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila |
| 26 | * Kesmarki. Thanks guys! |
| 27 | * |
| 28 | * Voodoo1 and Voodoo2 support aren't relevant to this driver as they |
| 29 | * behave very differently from the Voodoo3/4/5. For anyone wanting to |
| 30 | * use frame buffer on the Voodoo1/2, see the sstfb driver (which is |
| 31 | * located at http://www.sourceforge.net/projects/sstfb). |
| 32 | * |
| 33 | * While I _am_ grateful to 3Dfx for releasing the specs for Banshee, |
| 34 | * I do wish the next version is a bit more complete. Without the XF86 |
| 35 | * patches I couldn't have gotten even this far... for instance, the |
| 36 | * extensions to the VGA register set go completely unmentioned in the |
| 37 | * spec! Also, lots of references are made to the 'SST core', but no |
| 38 | * spec is publicly available, AFAIK. |
| 39 | * |
| 40 | * The structure of this driver comes pretty much from the Permedia |
| 41 | * driver by Ilario Nardinocchi, which in turn is based on skeletonfb. |
| 42 | * |
| 43 | * TODO: |
| 44 | * - multihead support (basically need to support an array of fb_infos) |
| 45 | * - support other architectures (PPC, Alpha); does the fact that the VGA |
| 46 | * core can be accessed only thru I/O (not memory mapped) complicate |
| 47 | * things? |
| 48 | * |
| 49 | * Version history: |
| 50 | * |
| 51 | * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons |
| 52 | * |
| 53 | * 0.1.3 (released 1999-11-02) added Attila's panning support, code |
| 54 | * reorg, hwcursor address page size alignment |
| 55 | * (for mmapping both frame buffer and regs), |
| 56 | * and my changes to get rid of hardcoded |
| 57 | * VGA i/o register locations (uses PCI |
| 58 | * configuration info now) |
| 59 | * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and |
| 60 | * improvements |
| 61 | * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga. |
| 62 | * 0.1.0 (released 1999-10-06) initial version |
| 63 | * |
| 64 | */ |
| 65 | |
| 66 | #include <linux/module.h> |
| 67 | #include <linux/kernel.h> |
| 68 | #include <linux/errno.h> |
| 69 | #include <linux/string.h> |
| 70 | #include <linux/mm.h> |
| 71 | #include <linux/slab.h> |
| 72 | #include <linux/fb.h> |
| 73 | #include <linux/init.h> |
| 74 | #include <linux/pci.h> |
| 75 | #include <asm/io.h> |
| 76 | |
| 77 | #include <video/tdfx.h> |
| 78 | |
| 79 | #define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b) |
| 80 | |
| 81 | #ifdef CONFIG_MTRR |
| 82 | #include <asm/mtrr.h> |
| 83 | #else |
| 84 | /* duplicate asm/mtrr.h defines to work on archs without mtrr */ |
| 85 | #define MTRR_TYPE_WRCOMB 1 |
| 86 | |
| 87 | static inline int mtrr_add(unsigned long base, unsigned long size, |
| 88 | unsigned int type, char increment) |
| 89 | { |
| 90 | return -ENODEV; |
| 91 | } |
| 92 | static inline int mtrr_del(int reg, unsigned long base, |
| 93 | unsigned long size) |
| 94 | { |
| 95 | return -ENODEV; |
| 96 | } |
| 97 | #endif |
| 98 | |
| 99 | #define BANSHEE_MAX_PIXCLOCK 270000 |
| 100 | #define VOODOO3_MAX_PIXCLOCK 300000 |
| 101 | #define VOODOO5_MAX_PIXCLOCK 350000 |
| 102 | |
| 103 | static struct fb_fix_screeninfo tdfx_fix = { |
| 104 | .type = FB_TYPE_PACKED_PIXELS, |
| 105 | .visual = FB_VISUAL_PSEUDOCOLOR, |
| 106 | .ypanstep = 1, |
| 107 | .ywrapstep = 1, |
| 108 | .accel = FB_ACCEL_3DFX_BANSHEE |
| 109 | }; |
| 110 | |
| 111 | static struct fb_var_screeninfo tdfx_var = { |
| 112 | /* "640x480, 8 bpp @ 60 Hz */ |
| 113 | .xres = 640, |
| 114 | .yres = 480, |
| 115 | .xres_virtual = 640, |
| 116 | .yres_virtual = 1024, |
| 117 | .bits_per_pixel = 8, |
| 118 | .red = {0, 8, 0}, |
| 119 | .blue = {0, 8, 0}, |
| 120 | .green = {0, 8, 0}, |
| 121 | .activate = FB_ACTIVATE_NOW, |
| 122 | .height = -1, |
| 123 | .width = -1, |
| 124 | .accel_flags = FB_ACCELF_TEXT, |
| 125 | .pixclock = 39722, |
| 126 | .left_margin = 40, |
| 127 | .right_margin = 24, |
| 128 | .upper_margin = 32, |
| 129 | .lower_margin = 11, |
| 130 | .hsync_len = 96, |
| 131 | .vsync_len = 2, |
| 132 | .vmode = FB_VMODE_NONINTERLACED |
| 133 | }; |
| 134 | |
| 135 | /* |
| 136 | * PCI driver prototypes |
| 137 | */ |
| 138 | static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id); |
| 139 | static void tdfxfb_remove(struct pci_dev *pdev); |
| 140 | |
| 141 | static struct pci_device_id tdfxfb_id_table[] = { |
| 142 | { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE, |
| 143 | PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, |
| 144 | 0xff0000, 0 }, |
| 145 | { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3, |
| 146 | PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, |
| 147 | 0xff0000, 0 }, |
| 148 | { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5, |
| 149 | PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, |
| 150 | 0xff0000, 0 }, |
| 151 | { 0, } |
| 152 | }; |
| 153 | |
| 154 | static struct pci_driver tdfxfb_driver = { |
| 155 | .name = "tdfxfb", |
| 156 | .id_table = tdfxfb_id_table, |
| 157 | .probe = tdfxfb_probe, |
| 158 | .remove = tdfxfb_remove, |
| 159 | }; |
| 160 | |
| 161 | MODULE_DEVICE_TABLE(pci, tdfxfb_id_table); |
| 162 | |
| 163 | /* |
| 164 | * Driver data |
| 165 | */ |
| 166 | static int nopan; |
| 167 | static int nowrap = 1; /* not implemented (yet) */ |
| 168 | static int hwcursor = 1; |
| 169 | static char *mode_option; |
| 170 | /* mtrr option */ |
| 171 | static bool nomtrr; |
| 172 | |
| 173 | /* ------------------------------------------------------------------------- |
| 174 | * Hardware-specific funcions |
| 175 | * ------------------------------------------------------------------------- */ |
| 176 | |
| 177 | static inline u8 vga_inb(struct tdfx_par *par, u32 reg) |
| 178 | { |
| 179 | return inb(par->iobase + reg - 0x300); |
| 180 | } |
| 181 | |
| 182 | static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) |
| 183 | { |
| 184 | outb(val, par->iobase + reg - 0x300); |
| 185 | } |
| 186 | |
| 187 | static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) |
| 188 | { |
| 189 | vga_outb(par, GRA_I, idx); |
| 190 | wmb(); |
| 191 | vga_outb(par, GRA_D, val); |
| 192 | wmb(); |
| 193 | } |
| 194 | |
| 195 | static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) |
| 196 | { |
| 197 | vga_outb(par, SEQ_I, idx); |
| 198 | wmb(); |
| 199 | vga_outb(par, SEQ_D, val); |
| 200 | wmb(); |
| 201 | } |
| 202 | |
| 203 | static inline u8 seq_inb(struct tdfx_par *par, u32 idx) |
| 204 | { |
| 205 | vga_outb(par, SEQ_I, idx); |
| 206 | mb(); |
| 207 | return vga_inb(par, SEQ_D); |
| 208 | } |
| 209 | |
| 210 | static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) |
| 211 | { |
| 212 | vga_outb(par, CRT_I, idx); |
| 213 | wmb(); |
| 214 | vga_outb(par, CRT_D, val); |
| 215 | wmb(); |
| 216 | } |
| 217 | |
| 218 | static inline u8 crt_inb(struct tdfx_par *par, u32 idx) |
| 219 | { |
| 220 | vga_outb(par, CRT_I, idx); |
| 221 | mb(); |
| 222 | return vga_inb(par, CRT_D); |
| 223 | } |
| 224 | |
| 225 | static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val) |
| 226 | { |
| 227 | unsigned char tmp; |
| 228 | |
| 229 | tmp = vga_inb(par, IS1_R); |
| 230 | vga_outb(par, ATT_IW, idx); |
| 231 | vga_outb(par, ATT_IW, val); |
| 232 | } |
| 233 | |
| 234 | static inline void vga_disable_video(struct tdfx_par *par) |
| 235 | { |
| 236 | unsigned char s; |
| 237 | |
| 238 | s = seq_inb(par, 0x01) | 0x20; |
| 239 | seq_outb(par, 0x00, 0x01); |
| 240 | seq_outb(par, 0x01, s); |
| 241 | seq_outb(par, 0x00, 0x03); |
| 242 | } |
| 243 | |
| 244 | static inline void vga_enable_video(struct tdfx_par *par) |
| 245 | { |
| 246 | unsigned char s; |
| 247 | |
| 248 | s = seq_inb(par, 0x01) & 0xdf; |
| 249 | seq_outb(par, 0x00, 0x01); |
| 250 | seq_outb(par, 0x01, s); |
| 251 | seq_outb(par, 0x00, 0x03); |
| 252 | } |
| 253 | |
| 254 | static inline void vga_enable_palette(struct tdfx_par *par) |
| 255 | { |
| 256 | vga_inb(par, IS1_R); |
| 257 | mb(); |
| 258 | vga_outb(par, ATT_IW, 0x20); |
| 259 | } |
| 260 | |
| 261 | static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg) |
| 262 | { |
| 263 | return readl(par->regbase_virt + reg); |
| 264 | } |
| 265 | |
| 266 | static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val) |
| 267 | { |
| 268 | writel(val, par->regbase_virt + reg); |
| 269 | } |
| 270 | |
| 271 | static inline void banshee_make_room(struct tdfx_par *par, int size) |
| 272 | { |
| 273 | /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop |
| 274 | * won't quit if you ask for more. */ |
| 275 | while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1) |
| 276 | cpu_relax(); |
| 277 | } |
| 278 | |
| 279 | static int banshee_wait_idle(struct fb_info *info) |
| 280 | { |
| 281 | struct tdfx_par *par = info->par; |
| 282 | int i = 0; |
| 283 | |
| 284 | banshee_make_room(par, 1); |
| 285 | tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP); |
| 286 | |
| 287 | do { |
| 288 | if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0) |
| 289 | i++; |
| 290 | } while (i < 3); |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | /* |
| 296 | * Set the color of a palette entry in 8bpp mode |
| 297 | */ |
| 298 | static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c) |
| 299 | { |
| 300 | banshee_make_room(par, 2); |
| 301 | tdfx_outl(par, DACADDR, regno); |
| 302 | /* read after write makes it working */ |
| 303 | tdfx_inl(par, DACADDR); |
| 304 | tdfx_outl(par, DACDATA, c); |
| 305 | } |
| 306 | |
| 307 | static u32 do_calc_pll(int freq, int *freq_out) |
| 308 | { |
| 309 | int m, n, k, best_m, best_n, best_k, best_error; |
| 310 | int fref = 14318; |
| 311 | |
| 312 | best_error = freq; |
| 313 | best_n = best_m = best_k = 0; |
| 314 | |
| 315 | for (k = 3; k >= 0; k--) { |
| 316 | for (m = 63; m >= 0; m--) { |
| 317 | /* |
| 318 | * Estimate value of n that produces target frequency |
| 319 | * with current m and k |
| 320 | */ |
| 321 | int n_estimated = ((freq * (m + 2) << k) / fref) - 2; |
| 322 | |
| 323 | /* Search neighborhood of estimated n */ |
| 324 | for (n = max(0, n_estimated); |
| 325 | n <= min(255, n_estimated + 1); |
| 326 | n++) { |
| 327 | /* |
| 328 | * Calculate PLL freqency with current m, k and |
| 329 | * estimated n |
| 330 | */ |
| 331 | int f = (fref * (n + 2) / (m + 2)) >> k; |
| 332 | int error = abs(f - freq); |
| 333 | |
| 334 | /* |
| 335 | * If this is the closest we've come to the |
| 336 | * target frequency then remember n, m and k |
| 337 | */ |
| 338 | if (error < best_error) { |
| 339 | best_error = error; |
| 340 | best_n = n; |
| 341 | best_m = m; |
| 342 | best_k = k; |
| 343 | } |
| 344 | } |
| 345 | } |
| 346 | } |
| 347 | |
| 348 | n = best_n; |
| 349 | m = best_m; |
| 350 | k = best_k; |
| 351 | *freq_out = (fref * (n + 2) / (m + 2)) >> k; |
| 352 | |
| 353 | return (n << 8) | (m << 2) | k; |
| 354 | } |
| 355 | |
| 356 | static void do_write_regs(struct fb_info *info, struct banshee_reg *reg) |
| 357 | { |
| 358 | struct tdfx_par *par = info->par; |
| 359 | int i; |
| 360 | |
| 361 | banshee_wait_idle(info); |
| 362 | |
| 363 | tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01); |
| 364 | |
| 365 | crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */ |
| 366 | |
| 367 | banshee_make_room(par, 3); |
| 368 | tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF); |
| 369 | tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001); |
| 370 | #if 0 |
| 371 | tdfx_outl(par, PLLCTRL1, reg->mempll); |
| 372 | tdfx_outl(par, PLLCTRL2, reg->gfxpll); |
| 373 | #endif |
| 374 | tdfx_outl(par, PLLCTRL0, reg->vidpll); |
| 375 | |
| 376 | vga_outb(par, MISC_W, reg->misc[0x00] | 0x01); |
| 377 | |
| 378 | for (i = 0; i < 5; i++) |
| 379 | seq_outb(par, i, reg->seq[i]); |
| 380 | |
| 381 | for (i = 0; i < 25; i++) |
| 382 | crt_outb(par, i, reg->crt[i]); |
| 383 | |
| 384 | for (i = 0; i < 9; i++) |
| 385 | gra_outb(par, i, reg->gra[i]); |
| 386 | |
| 387 | for (i = 0; i < 21; i++) |
| 388 | att_outb(par, i, reg->att[i]); |
| 389 | |
| 390 | crt_outb(par, 0x1a, reg->ext[0]); |
| 391 | crt_outb(par, 0x1b, reg->ext[1]); |
| 392 | |
| 393 | vga_enable_palette(par); |
| 394 | vga_enable_video(par); |
| 395 | |
| 396 | banshee_make_room(par, 9); |
| 397 | tdfx_outl(par, VGAINIT0, reg->vgainit0); |
| 398 | tdfx_outl(par, DACMODE, reg->dacmode); |
| 399 | tdfx_outl(par, VIDDESKSTRIDE, reg->stride); |
| 400 | tdfx_outl(par, HWCURPATADDR, reg->curspataddr); |
| 401 | |
| 402 | tdfx_outl(par, VIDSCREENSIZE, reg->screensize); |
| 403 | tdfx_outl(par, VIDDESKSTART, reg->startaddr); |
| 404 | tdfx_outl(par, VIDPROCCFG, reg->vidcfg); |
| 405 | tdfx_outl(par, VGAINIT1, reg->vgainit1); |
| 406 | tdfx_outl(par, MISCINIT0, reg->miscinit0); |
| 407 | |
| 408 | banshee_make_room(par, 8); |
| 409 | tdfx_outl(par, SRCBASE, reg->startaddr); |
| 410 | tdfx_outl(par, DSTBASE, reg->startaddr); |
| 411 | tdfx_outl(par, COMMANDEXTRA_2D, 0); |
| 412 | tdfx_outl(par, CLIP0MIN, 0); |
| 413 | tdfx_outl(par, CLIP0MAX, 0x0fff0fff); |
| 414 | tdfx_outl(par, CLIP1MIN, 0); |
| 415 | tdfx_outl(par, CLIP1MAX, 0x0fff0fff); |
| 416 | tdfx_outl(par, SRCXY, 0); |
| 417 | |
| 418 | banshee_wait_idle(info); |
| 419 | } |
| 420 | |
| 421 | static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id) |
| 422 | { |
| 423 | u32 draminit0 = tdfx_inl(par, DRAMINIT0); |
| 424 | u32 draminit1 = tdfx_inl(par, DRAMINIT1); |
| 425 | u32 miscinit1; |
| 426 | int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4; |
| 427 | int chip_size; /* in MB */ |
| 428 | int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM; |
| 429 | |
| 430 | if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) { |
| 431 | /* Banshee/Voodoo3 */ |
| 432 | chip_size = 2; |
| 433 | if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE)) |
| 434 | chip_size = 1; |
| 435 | } else { |
| 436 | /* Voodoo4/5 */ |
| 437 | has_sgram = 0; |
| 438 | chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK; |
| 439 | chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT); |
| 440 | } |
| 441 | |
| 442 | /* disable block writes for SDRAM */ |
| 443 | miscinit1 = tdfx_inl(par, MISCINIT1); |
| 444 | miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS; |
| 445 | miscinit1 |= MISCINIT1_CLUT_INV; |
| 446 | |
| 447 | banshee_make_room(par, 1); |
| 448 | tdfx_outl(par, MISCINIT1, miscinit1); |
| 449 | return num_chips * chip_size * 1024l * 1024; |
| 450 | } |
| 451 | |
| 452 | /* ------------------------------------------------------------------------- */ |
| 453 | |
| 454 | static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
| 455 | { |
| 456 | struct tdfx_par *par = info->par; |
| 457 | u32 lpitch; |
| 458 | |
| 459 | if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 && |
| 460 | var->bits_per_pixel != 24 && var->bits_per_pixel != 32) { |
| 461 | DPRINTK("depth not supported: %u\n", var->bits_per_pixel); |
| 462 | return -EINVAL; |
| 463 | } |
| 464 | |
| 465 | if (var->xres != var->xres_virtual) |
| 466 | var->xres_virtual = var->xres; |
| 467 | |
| 468 | if (var->yres > var->yres_virtual) |
| 469 | var->yres_virtual = var->yres; |
| 470 | |
| 471 | if (var->xoffset) { |
| 472 | DPRINTK("xoffset not supported\n"); |
| 473 | return -EINVAL; |
| 474 | } |
| 475 | var->yoffset = 0; |
| 476 | |
| 477 | /* |
| 478 | * Banshee doesn't support interlace, but Voodoo4/5 and probably |
| 479 | * Voodoo3 do. |
| 480 | * no direct information about device id now? |
| 481 | * use max_pixclock for this... |
| 482 | */ |
| 483 | if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) && |
| 484 | (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) { |
| 485 | DPRINTK("interlace not supported\n"); |
| 486 | return -EINVAL; |
| 487 | } |
| 488 | |
| 489 | if (info->monspecs.hfmax && info->monspecs.vfmax && |
| 490 | info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) { |
| 491 | DPRINTK("mode outside monitor's specs\n"); |
| 492 | return -EINVAL; |
| 493 | } |
| 494 | |
| 495 | var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */ |
| 496 | lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3); |
| 497 | |
| 498 | if (var->xres < 320 || var->xres > 2048) { |
| 499 | DPRINTK("width not supported: %u\n", var->xres); |
| 500 | return -EINVAL; |
| 501 | } |
| 502 | |
| 503 | if (var->yres < 200 || var->yres > 2048) { |
| 504 | DPRINTK("height not supported: %u\n", var->yres); |
| 505 | return -EINVAL; |
| 506 | } |
| 507 | |
| 508 | if (lpitch * var->yres_virtual > info->fix.smem_len) { |
| 509 | var->yres_virtual = info->fix.smem_len / lpitch; |
| 510 | if (var->yres_virtual < var->yres) { |
| 511 | DPRINTK("no memory for screen (%ux%ux%u)\n", |
| 512 | var->xres, var->yres_virtual, |
| 513 | var->bits_per_pixel); |
| 514 | return -EINVAL; |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | if (PICOS2KHZ(var->pixclock) > par->max_pixclock) { |
| 519 | DPRINTK("pixclock too high (%ldKHz)\n", |
| 520 | PICOS2KHZ(var->pixclock)); |
| 521 | return -EINVAL; |
| 522 | } |
| 523 | |
| 524 | var->transp.offset = 0; |
| 525 | var->transp.length = 0; |
| 526 | switch (var->bits_per_pixel) { |
| 527 | case 8: |
| 528 | var->red.length = 8; |
| 529 | var->red.offset = 0; |
| 530 | var->green = var->red; |
| 531 | var->blue = var->red; |
| 532 | break; |
| 533 | case 16: |
| 534 | var->red.offset = 11; |
| 535 | var->red.length = 5; |
| 536 | var->green.offset = 5; |
| 537 | var->green.length = 6; |
| 538 | var->blue.offset = 0; |
| 539 | var->blue.length = 5; |
| 540 | break; |
| 541 | case 32: |
| 542 | var->transp.offset = 24; |
| 543 | var->transp.length = 8; |
| 544 | case 24: |
| 545 | var->red.offset = 16; |
| 546 | var->green.offset = 8; |
| 547 | var->blue.offset = 0; |
| 548 | var->red.length = var->green.length = var->blue.length = 8; |
| 549 | break; |
| 550 | } |
| 551 | var->width = -1; |
| 552 | var->height = -1; |
| 553 | |
| 554 | var->accel_flags = FB_ACCELF_TEXT; |
| 555 | |
| 556 | DPRINTK("Checking graphics mode at %dx%d depth %d\n", |
| 557 | var->xres, var->yres, var->bits_per_pixel); |
| 558 | return 0; |
| 559 | } |
| 560 | |
| 561 | static int tdfxfb_set_par(struct fb_info *info) |
| 562 | { |
| 563 | struct tdfx_par *par = info->par; |
| 564 | u32 hdispend = info->var.xres; |
| 565 | u32 hsyncsta = hdispend + info->var.right_margin; |
| 566 | u32 hsyncend = hsyncsta + info->var.hsync_len; |
| 567 | u32 htotal = hsyncend + info->var.left_margin; |
| 568 | u32 hd, hs, he, ht, hbs, hbe; |
| 569 | u32 vd, vs, ve, vt, vbs, vbe; |
| 570 | struct banshee_reg reg; |
| 571 | int fout, freq; |
| 572 | u32 wd; |
| 573 | u32 cpp = (info->var.bits_per_pixel + 7) >> 3; |
| 574 | |
| 575 | memset(®, 0, sizeof(reg)); |
| 576 | |
| 577 | reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | |
| 578 | VIDCFG_CURS_X11 | |
| 579 | ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | |
| 580 | (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0); |
| 581 | |
| 582 | /* PLL settings */ |
| 583 | freq = PICOS2KHZ(info->var.pixclock); |
| 584 | |
| 585 | reg.vidcfg &= ~VIDCFG_2X; |
| 586 | |
| 587 | if (freq > par->max_pixclock / 2) { |
| 588 | freq = freq > par->max_pixclock ? par->max_pixclock : freq; |
| 589 | reg.dacmode |= DACMODE_2X; |
| 590 | reg.vidcfg |= VIDCFG_2X; |
| 591 | hdispend >>= 1; |
| 592 | hsyncsta >>= 1; |
| 593 | hsyncend >>= 1; |
| 594 | htotal >>= 1; |
| 595 | } |
| 596 | |
| 597 | wd = (hdispend >> 3) - 1; |
| 598 | hd = wd; |
| 599 | hs = (hsyncsta >> 3) - 1; |
| 600 | he = (hsyncend >> 3) - 1; |
| 601 | ht = (htotal >> 3) - 1; |
| 602 | hbs = hd; |
| 603 | hbe = ht; |
| 604 | |
| 605 | if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) { |
| 606 | vd = (info->var.yres << 1) - 1; |
| 607 | vs = vd + (info->var.lower_margin << 1); |
| 608 | ve = vs + (info->var.vsync_len << 1); |
| 609 | vt = ve + (info->var.upper_margin << 1) - 1; |
| 610 | reg.screensize = info->var.xres | (info->var.yres << 13); |
| 611 | reg.vidcfg |= VIDCFG_HALF_MODE; |
| 612 | reg.crt[0x09] = 0x80; |
| 613 | } else { |
| 614 | vd = info->var.yres - 1; |
| 615 | vs = vd + info->var.lower_margin; |
| 616 | ve = vs + info->var.vsync_len; |
| 617 | vt = ve + info->var.upper_margin - 1; |
| 618 | reg.screensize = info->var.xres | (info->var.yres << 12); |
| 619 | reg.vidcfg &= ~VIDCFG_HALF_MODE; |
| 620 | } |
| 621 | vbs = vd; |
| 622 | vbe = vt; |
| 623 | |
| 624 | /* this is all pretty standard VGA register stuffing */ |
| 625 | reg.misc[0x00] = 0x0f | |
| 626 | (info->var.xres < 400 ? 0xa0 : |
| 627 | info->var.xres < 480 ? 0x60 : |
| 628 | info->var.xres < 768 ? 0xe0 : 0x20); |
| 629 | |
| 630 | reg.gra[0x05] = 0x40; |
| 631 | reg.gra[0x06] = 0x05; |
| 632 | reg.gra[0x07] = 0x0f; |
| 633 | reg.gra[0x08] = 0xff; |
| 634 | |
| 635 | reg.att[0x00] = 0x00; |
| 636 | reg.att[0x01] = 0x01; |
| 637 | reg.att[0x02] = 0x02; |
| 638 | reg.att[0x03] = 0x03; |
| 639 | reg.att[0x04] = 0x04; |
| 640 | reg.att[0x05] = 0x05; |
| 641 | reg.att[0x06] = 0x06; |
| 642 | reg.att[0x07] = 0x07; |
| 643 | reg.att[0x08] = 0x08; |
| 644 | reg.att[0x09] = 0x09; |
| 645 | reg.att[0x0a] = 0x0a; |
| 646 | reg.att[0x0b] = 0x0b; |
| 647 | reg.att[0x0c] = 0x0c; |
| 648 | reg.att[0x0d] = 0x0d; |
| 649 | reg.att[0x0e] = 0x0e; |
| 650 | reg.att[0x0f] = 0x0f; |
| 651 | reg.att[0x10] = 0x41; |
| 652 | reg.att[0x12] = 0x0f; |
| 653 | |
| 654 | reg.seq[0x00] = 0x03; |
| 655 | reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */ |
| 656 | reg.seq[0x02] = 0x0f; |
| 657 | reg.seq[0x03] = 0x00; |
| 658 | reg.seq[0x04] = 0x0e; |
| 659 | |
| 660 | reg.crt[0x00] = ht - 4; |
| 661 | reg.crt[0x01] = hd; |
| 662 | reg.crt[0x02] = hbs; |
| 663 | reg.crt[0x03] = 0x80 | (hbe & 0x1f); |
| 664 | reg.crt[0x04] = hs; |
| 665 | reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); |
| 666 | reg.crt[0x06] = vt; |
| 667 | reg.crt[0x07] = ((vs & 0x200) >> 2) | |
| 668 | ((vd & 0x200) >> 3) | |
| 669 | ((vt & 0x200) >> 4) | 0x10 | |
| 670 | ((vbs & 0x100) >> 5) | |
| 671 | ((vs & 0x100) >> 6) | |
| 672 | ((vd & 0x100) >> 7) | |
| 673 | ((vt & 0x100) >> 8); |
| 674 | reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4); |
| 675 | reg.crt[0x10] = vs; |
| 676 | reg.crt[0x11] = (ve & 0x0f) | 0x20; |
| 677 | reg.crt[0x12] = vd; |
| 678 | reg.crt[0x13] = wd; |
| 679 | reg.crt[0x15] = vbs; |
| 680 | reg.crt[0x16] = vbe + 1; |
| 681 | reg.crt[0x17] = 0xc3; |
| 682 | reg.crt[0x18] = 0xff; |
| 683 | |
| 684 | /* Banshee's nonvga stuff */ |
| 685 | reg.ext[0x00] = (((ht & 0x100) >> 8) | |
| 686 | ((hd & 0x100) >> 6) | |
| 687 | ((hbs & 0x100) >> 4) | |
| 688 | ((hbe & 0x40) >> 1) | |
| 689 | ((hs & 0x100) >> 2) | |
| 690 | ((he & 0x20) << 2)); |
| 691 | reg.ext[0x01] = (((vt & 0x400) >> 10) | |
| 692 | ((vd & 0x400) >> 8) | |
| 693 | ((vbs & 0x400) >> 6) | |
| 694 | ((vbe & 0x400) >> 4)); |
| 695 | |
| 696 | reg.vgainit0 = VGAINIT0_8BIT_DAC | |
| 697 | VGAINIT0_EXT_ENABLE | |
| 698 | VGAINIT0_WAKEUP_3C3 | |
| 699 | VGAINIT0_ALT_READBACK | |
| 700 | VGAINIT0_EXTSHIFTOUT; |
| 701 | reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff; |
| 702 | |
| 703 | if (hwcursor) |
| 704 | reg.curspataddr = info->fix.smem_len; |
| 705 | |
| 706 | reg.cursloc = 0; |
| 707 | |
| 708 | reg.cursc0 = 0; |
| 709 | reg.cursc1 = 0xffffff; |
| 710 | |
| 711 | reg.stride = info->var.xres * cpp; |
| 712 | reg.startaddr = info->var.yoffset * reg.stride |
| 713 | + info->var.xoffset * cpp; |
| 714 | |
| 715 | reg.vidpll = do_calc_pll(freq, &fout); |
| 716 | #if 0 |
| 717 | reg.mempll = do_calc_pll(..., &fout); |
| 718 | reg.gfxpll = do_calc_pll(..., &fout); |
| 719 | #endif |
| 720 | |
| 721 | if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) |
| 722 | reg.vidcfg |= VIDCFG_INTERLACE; |
| 723 | reg.miscinit0 = tdfx_inl(par, MISCINIT0); |
| 724 | |
| 725 | #if defined(__BIG_ENDIAN) |
| 726 | switch (info->var.bits_per_pixel) { |
| 727 | case 8: |
| 728 | case 24: |
| 729 | reg.miscinit0 &= ~(1 << 30); |
| 730 | reg.miscinit0 &= ~(1 << 31); |
| 731 | break; |
| 732 | case 16: |
| 733 | reg.miscinit0 |= (1 << 30); |
| 734 | reg.miscinit0 |= (1 << 31); |
| 735 | break; |
| 736 | case 32: |
| 737 | reg.miscinit0 |= (1 << 30); |
| 738 | reg.miscinit0 &= ~(1 << 31); |
| 739 | break; |
| 740 | } |
| 741 | #endif |
| 742 | do_write_regs(info, ®); |
| 743 | |
| 744 | /* Now change fb_fix_screeninfo according to changes in par */ |
| 745 | info->fix.line_length = reg.stride; |
| 746 | info->fix.visual = (info->var.bits_per_pixel == 8) |
| 747 | ? FB_VISUAL_PSEUDOCOLOR |
| 748 | : FB_VISUAL_TRUECOLOR; |
| 749 | DPRINTK("Graphics mode is now set at %dx%d depth %d\n", |
| 750 | info->var.xres, info->var.yres, info->var.bits_per_pixel); |
| 751 | return 0; |
| 752 | } |
| 753 | |
| 754 | /* A handy macro shamelessly pinched from matroxfb */ |
| 755 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) |
| 756 | |
| 757 | static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green, |
| 758 | unsigned blue, unsigned transp, |
| 759 | struct fb_info *info) |
| 760 | { |
| 761 | struct tdfx_par *par = info->par; |
| 762 | u32 rgbcol; |
| 763 | |
| 764 | if (regno >= info->cmap.len || regno > 255) |
| 765 | return 1; |
| 766 | |
| 767 | /* grayscale works only partially under directcolor */ |
| 768 | if (info->var.grayscale) { |
| 769 | /* grayscale = 0.30*R + 0.59*G + 0.11*B */ |
| 770 | blue = (red * 77 + green * 151 + blue * 28) >> 8; |
| 771 | green = blue; |
| 772 | red = blue; |
| 773 | } |
| 774 | |
| 775 | switch (info->fix.visual) { |
| 776 | case FB_VISUAL_PSEUDOCOLOR: |
| 777 | rgbcol = (((u32)red & 0xff00) << 8) | |
| 778 | (((u32)green & 0xff00) << 0) | |
| 779 | (((u32)blue & 0xff00) >> 8); |
| 780 | do_setpalentry(par, regno, rgbcol); |
| 781 | break; |
| 782 | /* Truecolor has no hardware color palettes. */ |
| 783 | case FB_VISUAL_TRUECOLOR: |
| 784 | if (regno < 16) { |
| 785 | rgbcol = (CNVT_TOHW(red, info->var.red.length) << |
| 786 | info->var.red.offset) | |
| 787 | (CNVT_TOHW(green, info->var.green.length) << |
| 788 | info->var.green.offset) | |
| 789 | (CNVT_TOHW(blue, info->var.blue.length) << |
| 790 | info->var.blue.offset) | |
| 791 | (CNVT_TOHW(transp, info->var.transp.length) << |
| 792 | info->var.transp.offset); |
| 793 | par->palette[regno] = rgbcol; |
| 794 | } |
| 795 | |
| 796 | break; |
| 797 | default: |
| 798 | DPRINTK("bad depth %u\n", info->var.bits_per_pixel); |
| 799 | break; |
| 800 | } |
| 801 | |
| 802 | return 0; |
| 803 | } |
| 804 | |
| 805 | /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */ |
| 806 | static int tdfxfb_blank(int blank, struct fb_info *info) |
| 807 | { |
| 808 | struct tdfx_par *par = info->par; |
| 809 | int vgablank = 1; |
| 810 | u32 dacmode = tdfx_inl(par, DACMODE); |
| 811 | |
| 812 | dacmode &= ~(BIT(1) | BIT(3)); |
| 813 | |
| 814 | switch (blank) { |
| 815 | case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */ |
| 816 | vgablank = 0; |
| 817 | break; |
| 818 | case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */ |
| 819 | break; |
| 820 | case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */ |
| 821 | dacmode |= BIT(3); |
| 822 | break; |
| 823 | case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */ |
| 824 | dacmode |= BIT(1); |
| 825 | break; |
| 826 | case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */ |
| 827 | dacmode |= BIT(1) | BIT(3); |
| 828 | break; |
| 829 | } |
| 830 | |
| 831 | banshee_make_room(par, 1); |
| 832 | tdfx_outl(par, DACMODE, dacmode); |
| 833 | if (vgablank) |
| 834 | vga_disable_video(par); |
| 835 | else |
| 836 | vga_enable_video(par); |
| 837 | return 0; |
| 838 | } |
| 839 | |
| 840 | /* |
| 841 | * Set the starting position of the visible screen to var->yoffset |
| 842 | */ |
| 843 | static int tdfxfb_pan_display(struct fb_var_screeninfo *var, |
| 844 | struct fb_info *info) |
| 845 | { |
| 846 | struct tdfx_par *par = info->par; |
| 847 | u32 addr = var->yoffset * info->fix.line_length; |
| 848 | |
| 849 | if (nopan || var->xoffset) |
| 850 | return -EINVAL; |
| 851 | |
| 852 | banshee_make_room(par, 1); |
| 853 | tdfx_outl(par, VIDDESKSTART, addr); |
| 854 | |
| 855 | return 0; |
| 856 | } |
| 857 | |
| 858 | #ifdef CONFIG_FB_3DFX_ACCEL |
| 859 | /* |
| 860 | * FillRect 2D command (solidfill or invert (via ROP_XOR)) |
| 861 | */ |
| 862 | static void tdfxfb_fillrect(struct fb_info *info, |
| 863 | const struct fb_fillrect *rect) |
| 864 | { |
| 865 | struct tdfx_par *par = info->par; |
| 866 | u32 bpp = info->var.bits_per_pixel; |
| 867 | u32 stride = info->fix.line_length; |
| 868 | u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); |
| 869 | int tdfx_rop; |
| 870 | u32 dx = rect->dx; |
| 871 | u32 dy = rect->dy; |
| 872 | u32 dstbase = 0; |
| 873 | |
| 874 | if (rect->rop == ROP_COPY) |
| 875 | tdfx_rop = TDFX_ROP_COPY; |
| 876 | else |
| 877 | tdfx_rop = TDFX_ROP_XOR; |
| 878 | |
| 879 | /* assume always rect->height < 4096 */ |
| 880 | if (dy + rect->height > 4095) { |
| 881 | dstbase = stride * dy; |
| 882 | dy = 0; |
| 883 | } |
| 884 | /* assume always rect->width < 4096 */ |
| 885 | if (dx + rect->width > 4095) { |
| 886 | dstbase += dx * bpp >> 3; |
| 887 | dx = 0; |
| 888 | } |
| 889 | banshee_make_room(par, 6); |
| 890 | tdfx_outl(par, DSTFORMAT, fmt); |
| 891 | if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) { |
| 892 | tdfx_outl(par, COLORFORE, rect->color); |
| 893 | } else { /* FB_VISUAL_TRUECOLOR */ |
| 894 | tdfx_outl(par, COLORFORE, par->palette[rect->color]); |
| 895 | } |
| 896 | tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24)); |
| 897 | tdfx_outl(par, DSTBASE, dstbase); |
| 898 | tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16)); |
| 899 | tdfx_outl(par, LAUNCH_2D, dx | (dy << 16)); |
| 900 | } |
| 901 | |
| 902 | /* |
| 903 | * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) |
| 904 | */ |
| 905 | static void tdfxfb_copyarea(struct fb_info *info, |
| 906 | const struct fb_copyarea *area) |
| 907 | { |
| 908 | struct tdfx_par *par = info->par; |
| 909 | u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy; |
| 910 | u32 bpp = info->var.bits_per_pixel; |
| 911 | u32 stride = info->fix.line_length; |
| 912 | u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24); |
| 913 | u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); |
| 914 | u32 dstbase = 0; |
| 915 | u32 srcbase = 0; |
| 916 | |
| 917 | /* assume always area->height < 4096 */ |
| 918 | if (sy + area->height > 4095) { |
| 919 | srcbase = stride * sy; |
| 920 | sy = 0; |
| 921 | } |
| 922 | /* assume always area->width < 4096 */ |
| 923 | if (sx + area->width > 4095) { |
| 924 | srcbase += sx * bpp >> 3; |
| 925 | sx = 0; |
| 926 | } |
| 927 | /* assume always area->height < 4096 */ |
| 928 | if (dy + area->height > 4095) { |
| 929 | dstbase = stride * dy; |
| 930 | dy = 0; |
| 931 | } |
| 932 | /* assume always area->width < 4096 */ |
| 933 | if (dx + area->width > 4095) { |
| 934 | dstbase += dx * bpp >> 3; |
| 935 | dx = 0; |
| 936 | } |
| 937 | |
| 938 | if (area->sx <= area->dx) { |
| 939 | /* -X */ |
| 940 | blitcmd |= BIT(14); |
| 941 | sx += area->width - 1; |
| 942 | dx += area->width - 1; |
| 943 | } |
| 944 | if (area->sy <= area->dy) { |
| 945 | /* -Y */ |
| 946 | blitcmd |= BIT(15); |
| 947 | sy += area->height - 1; |
| 948 | dy += area->height - 1; |
| 949 | } |
| 950 | |
| 951 | banshee_make_room(par, 8); |
| 952 | |
| 953 | tdfx_outl(par, SRCFORMAT, fmt); |
| 954 | tdfx_outl(par, DSTFORMAT, fmt); |
| 955 | tdfx_outl(par, COMMAND_2D, blitcmd); |
| 956 | tdfx_outl(par, DSTSIZE, area->width | (area->height << 16)); |
| 957 | tdfx_outl(par, DSTXY, dx | (dy << 16)); |
| 958 | tdfx_outl(par, SRCBASE, srcbase); |
| 959 | tdfx_outl(par, DSTBASE, dstbase); |
| 960 | tdfx_outl(par, LAUNCH_2D, sx | (sy << 16)); |
| 961 | } |
| 962 | |
| 963 | static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image) |
| 964 | { |
| 965 | struct tdfx_par *par = info->par; |
| 966 | int size = image->height * ((image->width * image->depth + 7) >> 3); |
| 967 | int fifo_free; |
| 968 | int i, stride = info->fix.line_length; |
| 969 | u32 bpp = info->var.bits_per_pixel; |
| 970 | u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); |
| 971 | u8 *chardata = (u8 *) image->data; |
| 972 | u32 srcfmt; |
| 973 | u32 dx = image->dx; |
| 974 | u32 dy = image->dy; |
| 975 | u32 dstbase = 0; |
| 976 | |
| 977 | if (image->depth != 1) { |
| 978 | #ifdef BROKEN_CODE |
| 979 | banshee_make_room(par, 6 + ((size + 3) >> 2)); |
| 980 | srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) | |
| 981 | 0x400000; |
| 982 | #else |
| 983 | cfb_imageblit(info, image); |
| 984 | #endif |
| 985 | return; |
| 986 | } |
| 987 | banshee_make_room(par, 9); |
| 988 | switch (info->fix.visual) { |
| 989 | case FB_VISUAL_PSEUDOCOLOR: |
| 990 | tdfx_outl(par, COLORFORE, image->fg_color); |
| 991 | tdfx_outl(par, COLORBACK, image->bg_color); |
| 992 | break; |
| 993 | case FB_VISUAL_TRUECOLOR: |
| 994 | default: |
| 995 | tdfx_outl(par, COLORFORE, |
| 996 | par->palette[image->fg_color]); |
| 997 | tdfx_outl(par, COLORBACK, |
| 998 | par->palette[image->bg_color]); |
| 999 | } |
| 1000 | #ifdef __BIG_ENDIAN |
| 1001 | srcfmt = 0x400000 | BIT(20); |
| 1002 | #else |
| 1003 | srcfmt = 0x400000; |
| 1004 | #endif |
| 1005 | /* assume always image->height < 4096 */ |
| 1006 | if (dy + image->height > 4095) { |
| 1007 | dstbase = stride * dy; |
| 1008 | dy = 0; |
| 1009 | } |
| 1010 | /* assume always image->width < 4096 */ |
| 1011 | if (dx + image->width > 4095) { |
| 1012 | dstbase += dx * bpp >> 3; |
| 1013 | dx = 0; |
| 1014 | } |
| 1015 | |
| 1016 | tdfx_outl(par, DSTBASE, dstbase); |
| 1017 | tdfx_outl(par, SRCXY, 0); |
| 1018 | tdfx_outl(par, DSTXY, dx | (dy << 16)); |
| 1019 | tdfx_outl(par, COMMAND_2D, |
| 1020 | COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24)); |
| 1021 | tdfx_outl(par, SRCFORMAT, srcfmt); |
| 1022 | tdfx_outl(par, DSTFORMAT, dstfmt); |
| 1023 | tdfx_outl(par, DSTSIZE, image->width | (image->height << 16)); |
| 1024 | |
| 1025 | /* A count of how many free FIFO entries we've requested. |
| 1026 | * When this goes negative, we need to request more. */ |
| 1027 | fifo_free = 0; |
| 1028 | |
| 1029 | /* Send four bytes at a time of data */ |
| 1030 | for (i = (size >> 2); i > 0; i--) { |
| 1031 | if (--fifo_free < 0) { |
| 1032 | fifo_free = 31; |
| 1033 | banshee_make_room(par, fifo_free); |
| 1034 | } |
| 1035 | tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata); |
| 1036 | chardata += 4; |
| 1037 | } |
| 1038 | |
| 1039 | /* Send the leftovers now */ |
| 1040 | banshee_make_room(par, 3); |
| 1041 | switch (size % 4) { |
| 1042 | case 0: |
| 1043 | break; |
| 1044 | case 1: |
| 1045 | tdfx_outl(par, LAUNCH_2D, *chardata); |
| 1046 | break; |
| 1047 | case 2: |
| 1048 | tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata); |
| 1049 | break; |
| 1050 | case 3: |
| 1051 | tdfx_outl(par, LAUNCH_2D, |
| 1052 | *(u16 *)chardata | (chardata[3] << 24)); |
| 1053 | break; |
| 1054 | } |
| 1055 | } |
| 1056 | #endif /* CONFIG_FB_3DFX_ACCEL */ |
| 1057 | |
| 1058 | static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor) |
| 1059 | { |
| 1060 | struct tdfx_par *par = info->par; |
| 1061 | u32 vidcfg; |
| 1062 | |
| 1063 | if (!hwcursor) |
| 1064 | return -EINVAL; /* just to force soft_cursor() call */ |
| 1065 | |
| 1066 | /* Too large of a cursor or wrong bpp :-( */ |
| 1067 | if (cursor->image.width > 64 || |
| 1068 | cursor->image.height > 64 || |
| 1069 | cursor->image.depth > 1) |
| 1070 | return -EINVAL; |
| 1071 | |
| 1072 | vidcfg = tdfx_inl(par, VIDPROCCFG); |
| 1073 | if (cursor->enable) |
| 1074 | tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE); |
| 1075 | else |
| 1076 | tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE); |
| 1077 | |
| 1078 | /* |
| 1079 | * If the cursor is not be changed this means either we want the |
| 1080 | * current cursor state (if enable is set) or we want to query what |
| 1081 | * we can do with the cursor (if enable is not set) |
| 1082 | */ |
| 1083 | if (!cursor->set) |
| 1084 | return 0; |
| 1085 | |
| 1086 | /* fix cursor color - XFree86 forgets to restore it properly */ |
| 1087 | if (cursor->set & FB_CUR_SETCMAP) { |
| 1088 | struct fb_cmap cmap = info->cmap; |
| 1089 | u32 bg_idx = cursor->image.bg_color; |
| 1090 | u32 fg_idx = cursor->image.fg_color; |
| 1091 | unsigned long bg_color, fg_color; |
| 1092 | |
| 1093 | fg_color = (((u32)cmap.red[fg_idx] & 0xff00) << 8) | |
| 1094 | (((u32)cmap.green[fg_idx] & 0xff00) << 0) | |
| 1095 | (((u32)cmap.blue[fg_idx] & 0xff00) >> 8); |
| 1096 | bg_color = (((u32)cmap.red[bg_idx] & 0xff00) << 8) | |
| 1097 | (((u32)cmap.green[bg_idx] & 0xff00) << 0) | |
| 1098 | (((u32)cmap.blue[bg_idx] & 0xff00) >> 8); |
| 1099 | banshee_make_room(par, 2); |
| 1100 | tdfx_outl(par, HWCURC0, bg_color); |
| 1101 | tdfx_outl(par, HWCURC1, fg_color); |
| 1102 | } |
| 1103 | |
| 1104 | if (cursor->set & FB_CUR_SETPOS) { |
| 1105 | int x = cursor->image.dx; |
| 1106 | int y = cursor->image.dy - info->var.yoffset; |
| 1107 | |
| 1108 | x += 63; |
| 1109 | y += 63; |
| 1110 | banshee_make_room(par, 1); |
| 1111 | tdfx_outl(par, HWCURLOC, (y << 16) + x); |
| 1112 | } |
| 1113 | if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) { |
| 1114 | /* |
| 1115 | * Voodoo 3 and above cards use 2 monochrome cursor patterns. |
| 1116 | * The reason is so the card can fetch 8 words at a time |
| 1117 | * and are stored on chip for use for the next 8 scanlines. |
| 1118 | * This reduces the number of times for access to draw the |
| 1119 | * cursor for each screen refresh. |
| 1120 | * Each pattern is a bitmap of 64 bit wide and 64 bit high |
| 1121 | * (total of 8192 bits or 1024 bytes). The two patterns are |
| 1122 | * stored in such a way that pattern 0 always resides in the |
| 1123 | * lower half (least significant 64 bits) of a 128 bit word |
| 1124 | * and pattern 1 the upper half. If you examine the data of |
| 1125 | * the cursor image the graphics card uses then from the |
| 1126 | * beginning you see line one of pattern 0, line one of |
| 1127 | * pattern 1, line two of pattern 0, line two of pattern 1, |
| 1128 | * etc etc. The linear stride for the cursor is always 16 bytes |
| 1129 | * (128 bits) which is the maximum cursor width times two for |
| 1130 | * the two monochrome patterns. |
| 1131 | */ |
| 1132 | u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len; |
| 1133 | u8 *bitmap = (u8 *)cursor->image.data; |
| 1134 | u8 *mask = (u8 *)cursor->mask; |
| 1135 | int i; |
| 1136 | |
| 1137 | fb_memset(cursorbase, 0, 1024); |
| 1138 | |
| 1139 | for (i = 0; i < cursor->image.height; i++) { |
| 1140 | int h = 0; |
| 1141 | int j = (cursor->image.width + 7) >> 3; |
| 1142 | |
| 1143 | for (; j > 0; j--) { |
| 1144 | u8 data = *mask ^ *bitmap; |
| 1145 | if (cursor->rop == ROP_COPY) |
| 1146 | data = *mask & *bitmap; |
| 1147 | /* Pattern 0. Copy the cursor mask to it */ |
| 1148 | fb_writeb(*mask, cursorbase + h); |
| 1149 | mask++; |
| 1150 | /* Pattern 1. Copy the cursor bitmap to it */ |
| 1151 | fb_writeb(data, cursorbase + h + 8); |
| 1152 | bitmap++; |
| 1153 | h++; |
| 1154 | } |
| 1155 | cursorbase += 16; |
| 1156 | } |
| 1157 | } |
| 1158 | return 0; |
| 1159 | } |
| 1160 | |
| 1161 | static struct fb_ops tdfxfb_ops = { |
| 1162 | .owner = THIS_MODULE, |
| 1163 | .fb_check_var = tdfxfb_check_var, |
| 1164 | .fb_set_par = tdfxfb_set_par, |
| 1165 | .fb_setcolreg = tdfxfb_setcolreg, |
| 1166 | .fb_blank = tdfxfb_blank, |
| 1167 | .fb_pan_display = tdfxfb_pan_display, |
| 1168 | .fb_sync = banshee_wait_idle, |
| 1169 | .fb_cursor = tdfxfb_cursor, |
| 1170 | #ifdef CONFIG_FB_3DFX_ACCEL |
| 1171 | .fb_fillrect = tdfxfb_fillrect, |
| 1172 | .fb_copyarea = tdfxfb_copyarea, |
| 1173 | .fb_imageblit = tdfxfb_imageblit, |
| 1174 | #else |
| 1175 | .fb_fillrect = cfb_fillrect, |
| 1176 | .fb_copyarea = cfb_copyarea, |
| 1177 | .fb_imageblit = cfb_imageblit, |
| 1178 | #endif |
| 1179 | }; |
| 1180 | |
| 1181 | #ifdef CONFIG_FB_3DFX_I2C |
| 1182 | /* The voo GPIO registers don't have individual masks for each bit |
| 1183 | so we always have to read before writing. */ |
| 1184 | |
| 1185 | static void tdfxfb_i2c_setscl(void *data, int val) |
| 1186 | { |
| 1187 | struct tdfxfb_i2c_chan *chan = data; |
| 1188 | struct tdfx_par *par = chan->par; |
| 1189 | unsigned int r; |
| 1190 | |
| 1191 | r = tdfx_inl(par, VIDSERPARPORT); |
| 1192 | if (val) |
| 1193 | r |= I2C_SCL_OUT; |
| 1194 | else |
| 1195 | r &= ~I2C_SCL_OUT; |
| 1196 | tdfx_outl(par, VIDSERPARPORT, r); |
| 1197 | tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ |
| 1198 | } |
| 1199 | |
| 1200 | static void tdfxfb_i2c_setsda(void *data, int val) |
| 1201 | { |
| 1202 | struct tdfxfb_i2c_chan *chan = data; |
| 1203 | struct tdfx_par *par = chan->par; |
| 1204 | unsigned int r; |
| 1205 | |
| 1206 | r = tdfx_inl(par, VIDSERPARPORT); |
| 1207 | if (val) |
| 1208 | r |= I2C_SDA_OUT; |
| 1209 | else |
| 1210 | r &= ~I2C_SDA_OUT; |
| 1211 | tdfx_outl(par, VIDSERPARPORT, r); |
| 1212 | tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ |
| 1213 | } |
| 1214 | |
| 1215 | /* The GPIO pins are open drain, so the pins always remain outputs. |
| 1216 | We rely on the i2c-algo-bit routines to set the pins high before |
| 1217 | reading the input from other chips. */ |
| 1218 | |
| 1219 | static int tdfxfb_i2c_getscl(void *data) |
| 1220 | { |
| 1221 | struct tdfxfb_i2c_chan *chan = data; |
| 1222 | struct tdfx_par *par = chan->par; |
| 1223 | |
| 1224 | return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN)); |
| 1225 | } |
| 1226 | |
| 1227 | static int tdfxfb_i2c_getsda(void *data) |
| 1228 | { |
| 1229 | struct tdfxfb_i2c_chan *chan = data; |
| 1230 | struct tdfx_par *par = chan->par; |
| 1231 | |
| 1232 | return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN)); |
| 1233 | } |
| 1234 | |
| 1235 | static void tdfxfb_ddc_setscl(void *data, int val) |
| 1236 | { |
| 1237 | struct tdfxfb_i2c_chan *chan = data; |
| 1238 | struct tdfx_par *par = chan->par; |
| 1239 | unsigned int r; |
| 1240 | |
| 1241 | r = tdfx_inl(par, VIDSERPARPORT); |
| 1242 | if (val) |
| 1243 | r |= DDC_SCL_OUT; |
| 1244 | else |
| 1245 | r &= ~DDC_SCL_OUT; |
| 1246 | tdfx_outl(par, VIDSERPARPORT, r); |
| 1247 | tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ |
| 1248 | } |
| 1249 | |
| 1250 | static void tdfxfb_ddc_setsda(void *data, int val) |
| 1251 | { |
| 1252 | struct tdfxfb_i2c_chan *chan = data; |
| 1253 | struct tdfx_par *par = chan->par; |
| 1254 | unsigned int r; |
| 1255 | |
| 1256 | r = tdfx_inl(par, VIDSERPARPORT); |
| 1257 | if (val) |
| 1258 | r |= DDC_SDA_OUT; |
| 1259 | else |
| 1260 | r &= ~DDC_SDA_OUT; |
| 1261 | tdfx_outl(par, VIDSERPARPORT, r); |
| 1262 | tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ |
| 1263 | } |
| 1264 | |
| 1265 | static int tdfxfb_ddc_getscl(void *data) |
| 1266 | { |
| 1267 | struct tdfxfb_i2c_chan *chan = data; |
| 1268 | struct tdfx_par *par = chan->par; |
| 1269 | |
| 1270 | return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN)); |
| 1271 | } |
| 1272 | |
| 1273 | static int tdfxfb_ddc_getsda(void *data) |
| 1274 | { |
| 1275 | struct tdfxfb_i2c_chan *chan = data; |
| 1276 | struct tdfx_par *par = chan->par; |
| 1277 | |
| 1278 | return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN)); |
| 1279 | } |
| 1280 | |
| 1281 | static int tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan, const char *name, |
| 1282 | struct device *dev) |
| 1283 | { |
| 1284 | int rc; |
| 1285 | |
| 1286 | strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name)); |
| 1287 | chan->adapter.owner = THIS_MODULE; |
| 1288 | chan->adapter.class = I2C_CLASS_DDC; |
| 1289 | chan->adapter.algo_data = &chan->algo; |
| 1290 | chan->adapter.dev.parent = dev; |
| 1291 | chan->algo.setsda = tdfxfb_ddc_setsda; |
| 1292 | chan->algo.setscl = tdfxfb_ddc_setscl; |
| 1293 | chan->algo.getsda = tdfxfb_ddc_getsda; |
| 1294 | chan->algo.getscl = tdfxfb_ddc_getscl; |
| 1295 | chan->algo.udelay = 10; |
| 1296 | chan->algo.timeout = msecs_to_jiffies(500); |
| 1297 | chan->algo.data = chan; |
| 1298 | |
| 1299 | i2c_set_adapdata(&chan->adapter, chan); |
| 1300 | |
| 1301 | rc = i2c_bit_add_bus(&chan->adapter); |
| 1302 | if (rc == 0) |
| 1303 | DPRINTK("I2C bus %s registered.\n", name); |
| 1304 | else |
| 1305 | chan->par = NULL; |
| 1306 | |
| 1307 | return rc; |
| 1308 | } |
| 1309 | |
| 1310 | static int tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan, const char *name, |
| 1311 | struct device *dev) |
| 1312 | { |
| 1313 | int rc; |
| 1314 | |
| 1315 | strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name)); |
| 1316 | chan->adapter.owner = THIS_MODULE; |
| 1317 | chan->adapter.algo_data = &chan->algo; |
| 1318 | chan->adapter.dev.parent = dev; |
| 1319 | chan->algo.setsda = tdfxfb_i2c_setsda; |
| 1320 | chan->algo.setscl = tdfxfb_i2c_setscl; |
| 1321 | chan->algo.getsda = tdfxfb_i2c_getsda; |
| 1322 | chan->algo.getscl = tdfxfb_i2c_getscl; |
| 1323 | chan->algo.udelay = 10; |
| 1324 | chan->algo.timeout = msecs_to_jiffies(500); |
| 1325 | chan->algo.data = chan; |
| 1326 | |
| 1327 | i2c_set_adapdata(&chan->adapter, chan); |
| 1328 | |
| 1329 | rc = i2c_bit_add_bus(&chan->adapter); |
| 1330 | if (rc == 0) |
| 1331 | DPRINTK("I2C bus %s registered.\n", name); |
| 1332 | else |
| 1333 | chan->par = NULL; |
| 1334 | |
| 1335 | return rc; |
| 1336 | } |
| 1337 | |
| 1338 | static void tdfxfb_create_i2c_busses(struct fb_info *info) |
| 1339 | { |
| 1340 | struct tdfx_par *par = info->par; |
| 1341 | |
| 1342 | tdfx_outl(par, VIDINFORMAT, 0x8160); |
| 1343 | tdfx_outl(par, VIDSERPARPORT, 0xcffc0020); |
| 1344 | |
| 1345 | par->chan[0].par = par; |
| 1346 | par->chan[1].par = par; |
| 1347 | |
| 1348 | tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->dev); |
| 1349 | tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->dev); |
| 1350 | } |
| 1351 | |
| 1352 | static void tdfxfb_delete_i2c_busses(struct tdfx_par *par) |
| 1353 | { |
| 1354 | if (par->chan[0].par) |
| 1355 | i2c_del_adapter(&par->chan[0].adapter); |
| 1356 | par->chan[0].par = NULL; |
| 1357 | |
| 1358 | if (par->chan[1].par) |
| 1359 | i2c_del_adapter(&par->chan[1].adapter); |
| 1360 | par->chan[1].par = NULL; |
| 1361 | } |
| 1362 | |
| 1363 | static int tdfxfb_probe_i2c_connector(struct tdfx_par *par, |
| 1364 | struct fb_monspecs *specs) |
| 1365 | { |
| 1366 | u8 *edid = NULL; |
| 1367 | |
| 1368 | DPRINTK("Probe DDC Bus\n"); |
| 1369 | if (par->chan[0].par) |
| 1370 | edid = fb_ddc_read(&par->chan[0].adapter); |
| 1371 | |
| 1372 | if (edid) { |
| 1373 | fb_edid_to_monspecs(edid, specs); |
| 1374 | kfree(edid); |
| 1375 | return 0; |
| 1376 | } |
| 1377 | return 1; |
| 1378 | } |
| 1379 | #endif /* CONFIG_FB_3DFX_I2C */ |
| 1380 | |
| 1381 | /** |
| 1382 | * tdfxfb_probe - Device Initializiation |
| 1383 | * |
| 1384 | * @pdev: PCI Device to initialize |
| 1385 | * @id: PCI Device ID |
| 1386 | * |
| 1387 | * Initializes and allocates resources for PCI device @pdev. |
| 1388 | * |
| 1389 | */ |
| 1390 | static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
| 1391 | { |
| 1392 | struct tdfx_par *default_par; |
| 1393 | struct fb_info *info; |
| 1394 | int err, lpitch; |
| 1395 | struct fb_monspecs *specs; |
| 1396 | bool found; |
| 1397 | |
| 1398 | err = pci_enable_device(pdev); |
| 1399 | if (err) { |
| 1400 | printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err); |
| 1401 | return err; |
| 1402 | } |
| 1403 | |
| 1404 | info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev); |
| 1405 | |
| 1406 | if (!info) |
| 1407 | return -ENOMEM; |
| 1408 | |
| 1409 | default_par = info->par; |
| 1410 | info->fix = tdfx_fix; |
| 1411 | |
| 1412 | /* Configure the default fb_fix_screeninfo first */ |
| 1413 | switch (pdev->device) { |
| 1414 | case PCI_DEVICE_ID_3DFX_BANSHEE: |
| 1415 | strcpy(info->fix.id, "3Dfx Banshee"); |
| 1416 | default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK; |
| 1417 | break; |
| 1418 | case PCI_DEVICE_ID_3DFX_VOODOO3: |
| 1419 | strcpy(info->fix.id, "3Dfx Voodoo3"); |
| 1420 | default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK; |
| 1421 | break; |
| 1422 | case PCI_DEVICE_ID_3DFX_VOODOO5: |
| 1423 | strcpy(info->fix.id, "3Dfx Voodoo5"); |
| 1424 | default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK; |
| 1425 | break; |
| 1426 | } |
| 1427 | |
| 1428 | info->fix.mmio_start = pci_resource_start(pdev, 0); |
| 1429 | info->fix.mmio_len = pci_resource_len(pdev, 0); |
| 1430 | if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len, |
| 1431 | "tdfx regbase")) { |
| 1432 | printk(KERN_ERR "tdfxfb: Can't reserve regbase\n"); |
| 1433 | goto out_err; |
| 1434 | } |
| 1435 | |
| 1436 | default_par->regbase_virt = |
| 1437 | ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len); |
| 1438 | if (!default_par->regbase_virt) { |
| 1439 | printk(KERN_ERR "fb: Can't remap %s register area.\n", |
| 1440 | info->fix.id); |
| 1441 | goto out_err_regbase; |
| 1442 | } |
| 1443 | |
| 1444 | info->fix.smem_start = pci_resource_start(pdev, 1); |
| 1445 | info->fix.smem_len = do_lfb_size(default_par, pdev->device); |
| 1446 | if (!info->fix.smem_len) { |
| 1447 | printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id); |
| 1448 | goto out_err_regbase; |
| 1449 | } |
| 1450 | |
| 1451 | if (!request_mem_region(info->fix.smem_start, |
| 1452 | pci_resource_len(pdev, 1), "tdfx smem")) { |
| 1453 | printk(KERN_ERR "tdfxfb: Can't reserve smem\n"); |
| 1454 | goto out_err_regbase; |
| 1455 | } |
| 1456 | |
| 1457 | info->screen_base = ioremap_nocache(info->fix.smem_start, |
| 1458 | info->fix.smem_len); |
| 1459 | if (!info->screen_base) { |
| 1460 | printk(KERN_ERR "fb: Can't remap %s framebuffer.\n", |
| 1461 | info->fix.id); |
| 1462 | goto out_err_screenbase; |
| 1463 | } |
| 1464 | |
| 1465 | default_par->iobase = pci_resource_start(pdev, 2); |
| 1466 | |
| 1467 | if (!request_region(pci_resource_start(pdev, 2), |
| 1468 | pci_resource_len(pdev, 2), "tdfx iobase")) { |
| 1469 | printk(KERN_ERR "tdfxfb: Can't reserve iobase\n"); |
| 1470 | goto out_err_screenbase; |
| 1471 | } |
| 1472 | |
| 1473 | printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id, |
| 1474 | info->fix.smem_len >> 10); |
| 1475 | |
| 1476 | default_par->mtrr_handle = -1; |
| 1477 | if (!nomtrr) |
| 1478 | default_par->mtrr_handle = |
| 1479 | mtrr_add(info->fix.smem_start, info->fix.smem_len, |
| 1480 | MTRR_TYPE_WRCOMB, 1); |
| 1481 | |
| 1482 | info->fix.ypanstep = nopan ? 0 : 1; |
| 1483 | info->fix.ywrapstep = nowrap ? 0 : 1; |
| 1484 | |
| 1485 | info->fbops = &tdfxfb_ops; |
| 1486 | info->pseudo_palette = default_par->palette; |
| 1487 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; |
| 1488 | #ifdef CONFIG_FB_3DFX_ACCEL |
| 1489 | info->flags |= FBINFO_HWACCEL_FILLRECT | |
| 1490 | FBINFO_HWACCEL_COPYAREA | |
| 1491 | FBINFO_HWACCEL_IMAGEBLIT | |
| 1492 | FBINFO_READS_FAST; |
| 1493 | #endif |
| 1494 | /* reserve 8192 bits for cursor */ |
| 1495 | /* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */ |
| 1496 | if (hwcursor) |
| 1497 | info->fix.smem_len = (info->fix.smem_len - 1024) & |
| 1498 | (PAGE_MASK << 1); |
| 1499 | specs = &info->monspecs; |
| 1500 | found = false; |
| 1501 | info->var.bits_per_pixel = 8; |
| 1502 | #ifdef CONFIG_FB_3DFX_I2C |
| 1503 | tdfxfb_create_i2c_busses(info); |
| 1504 | err = tdfxfb_probe_i2c_connector(default_par, specs); |
| 1505 | |
| 1506 | if (!err) { |
| 1507 | if (specs->modedb == NULL) |
| 1508 | DPRINTK("Unable to get Mode Database\n"); |
| 1509 | else { |
| 1510 | const struct fb_videomode *m; |
| 1511 | |
| 1512 | fb_videomode_to_modelist(specs->modedb, |
| 1513 | specs->modedb_len, |
| 1514 | &info->modelist); |
| 1515 | m = fb_find_best_display(specs, &info->modelist); |
| 1516 | if (m) { |
| 1517 | fb_videomode_to_var(&info->var, m); |
| 1518 | /* fill all other info->var's fields */ |
| 1519 | if (tdfxfb_check_var(&info->var, info) < 0) |
| 1520 | info->var = tdfx_var; |
| 1521 | else |
| 1522 | found = true; |
| 1523 | } |
| 1524 | } |
| 1525 | } |
| 1526 | #endif |
| 1527 | if (!mode_option && !found) |
| 1528 | mode_option = "640x480@60"; |
| 1529 | |
| 1530 | if (mode_option) { |
| 1531 | err = fb_find_mode(&info->var, info, mode_option, |
| 1532 | specs->modedb, specs->modedb_len, |
| 1533 | NULL, info->var.bits_per_pixel); |
| 1534 | if (!err || err == 4) |
| 1535 | info->var = tdfx_var; |
| 1536 | } |
| 1537 | |
| 1538 | if (found) { |
| 1539 | fb_destroy_modedb(specs->modedb); |
| 1540 | specs->modedb = NULL; |
| 1541 | } |
| 1542 | |
| 1543 | /* maximize virtual vertical length */ |
| 1544 | lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3); |
| 1545 | info->var.yres_virtual = info->fix.smem_len / lpitch; |
| 1546 | if (info->var.yres_virtual < info->var.yres) |
| 1547 | goto out_err_iobase; |
| 1548 | |
| 1549 | if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { |
| 1550 | printk(KERN_ERR "tdfxfb: Can't allocate color map\n"); |
| 1551 | goto out_err_iobase; |
| 1552 | } |
| 1553 | |
| 1554 | if (register_framebuffer(info) < 0) { |
| 1555 | printk(KERN_ERR "tdfxfb: can't register framebuffer\n"); |
| 1556 | fb_dealloc_cmap(&info->cmap); |
| 1557 | goto out_err_iobase; |
| 1558 | } |
| 1559 | /* |
| 1560 | * Our driver data |
| 1561 | */ |
| 1562 | pci_set_drvdata(pdev, info); |
| 1563 | return 0; |
| 1564 | |
| 1565 | out_err_iobase: |
| 1566 | #ifdef CONFIG_FB_3DFX_I2C |
| 1567 | tdfxfb_delete_i2c_busses(default_par); |
| 1568 | #endif |
| 1569 | if (default_par->mtrr_handle >= 0) |
| 1570 | mtrr_del(default_par->mtrr_handle, info->fix.smem_start, |
| 1571 | info->fix.smem_len); |
| 1572 | release_region(pci_resource_start(pdev, 2), |
| 1573 | pci_resource_len(pdev, 2)); |
| 1574 | out_err_screenbase: |
| 1575 | if (info->screen_base) |
| 1576 | iounmap(info->screen_base); |
| 1577 | release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1)); |
| 1578 | out_err_regbase: |
| 1579 | /* |
| 1580 | * Cleanup after anything that was remapped/allocated. |
| 1581 | */ |
| 1582 | if (default_par->regbase_virt) |
| 1583 | iounmap(default_par->regbase_virt); |
| 1584 | release_mem_region(info->fix.mmio_start, info->fix.mmio_len); |
| 1585 | out_err: |
| 1586 | framebuffer_release(info); |
| 1587 | return -ENXIO; |
| 1588 | } |
| 1589 | |
| 1590 | #ifndef MODULE |
| 1591 | static void __init tdfxfb_setup(char *options) |
| 1592 | { |
| 1593 | char *this_opt; |
| 1594 | |
| 1595 | if (!options || !*options) |
| 1596 | return; |
| 1597 | |
| 1598 | while ((this_opt = strsep(&options, ",")) != NULL) { |
| 1599 | if (!*this_opt) |
| 1600 | continue; |
| 1601 | if (!strcmp(this_opt, "nopan")) { |
| 1602 | nopan = 1; |
| 1603 | } else if (!strcmp(this_opt, "nowrap")) { |
| 1604 | nowrap = 1; |
| 1605 | } else if (!strncmp(this_opt, "hwcursor=", 9)) { |
| 1606 | hwcursor = simple_strtoul(this_opt + 9, NULL, 0); |
| 1607 | #ifdef CONFIG_MTRR |
| 1608 | } else if (!strncmp(this_opt, "nomtrr", 6)) { |
| 1609 | nomtrr = 1; |
| 1610 | #endif |
| 1611 | } else { |
| 1612 | mode_option = this_opt; |
| 1613 | } |
| 1614 | } |
| 1615 | } |
| 1616 | #endif |
| 1617 | |
| 1618 | /** |
| 1619 | * tdfxfb_remove - Device removal |
| 1620 | * |
| 1621 | * @pdev: PCI Device to cleanup |
| 1622 | * |
| 1623 | * Releases all resources allocated during the course of the driver's |
| 1624 | * lifetime for the PCI device @pdev. |
| 1625 | * |
| 1626 | */ |
| 1627 | static void tdfxfb_remove(struct pci_dev *pdev) |
| 1628 | { |
| 1629 | struct fb_info *info = pci_get_drvdata(pdev); |
| 1630 | struct tdfx_par *par = info->par; |
| 1631 | |
| 1632 | unregister_framebuffer(info); |
| 1633 | #ifdef CONFIG_FB_3DFX_I2C |
| 1634 | tdfxfb_delete_i2c_busses(par); |
| 1635 | #endif |
| 1636 | if (par->mtrr_handle >= 0) |
| 1637 | mtrr_del(par->mtrr_handle, info->fix.smem_start, |
| 1638 | info->fix.smem_len); |
| 1639 | iounmap(par->regbase_virt); |
| 1640 | iounmap(info->screen_base); |
| 1641 | |
| 1642 | /* Clean up after reserved regions */ |
| 1643 | release_region(pci_resource_start(pdev, 2), |
| 1644 | pci_resource_len(pdev, 2)); |
| 1645 | release_mem_region(pci_resource_start(pdev, 1), |
| 1646 | pci_resource_len(pdev, 1)); |
| 1647 | release_mem_region(pci_resource_start(pdev, 0), |
| 1648 | pci_resource_len(pdev, 0)); |
| 1649 | pci_set_drvdata(pdev, NULL); |
| 1650 | fb_dealloc_cmap(&info->cmap); |
| 1651 | framebuffer_release(info); |
| 1652 | } |
| 1653 | |
| 1654 | static int __init tdfxfb_init(void) |
| 1655 | { |
| 1656 | #ifndef MODULE |
| 1657 | char *option = NULL; |
| 1658 | |
| 1659 | if (fb_get_options("tdfxfb", &option)) |
| 1660 | return -ENODEV; |
| 1661 | |
| 1662 | tdfxfb_setup(option); |
| 1663 | #endif |
| 1664 | return pci_register_driver(&tdfxfb_driver); |
| 1665 | } |
| 1666 | |
| 1667 | static void __exit tdfxfb_exit(void) |
| 1668 | { |
| 1669 | pci_unregister_driver(&tdfxfb_driver); |
| 1670 | } |
| 1671 | |
| 1672 | MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>"); |
| 1673 | MODULE_DESCRIPTION("3Dfx framebuffer device driver"); |
| 1674 | MODULE_LICENSE("GPL"); |
| 1675 | |
| 1676 | module_param(hwcursor, int, 0644); |
| 1677 | MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " |
| 1678 | "(1=enable, 0=disable, default=1)"); |
| 1679 | module_param(mode_option, charp, 0); |
| 1680 | MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); |
| 1681 | #ifdef CONFIG_MTRR |
| 1682 | module_param(nomtrr, bool, 0); |
| 1683 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)"); |
| 1684 | #endif |
| 1685 | |
| 1686 | module_init(tdfxfb_init); |
| 1687 | module_exit(tdfxfb_exit); |