| 1 | /* |
| 2 | * MUSB OTG driver defines |
| 3 | * |
| 4 | * Copyright 2005 Mentor Graphics Corporation |
| 5 | * Copyright (C) 2005-2006 by Texas Instruments |
| 6 | * Copyright (C) 2006-2007 Nokia Corporation |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but |
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 20 | * 02110-1301 USA |
| 21 | * |
| 22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | * |
| 33 | */ |
| 34 | |
| 35 | #ifndef __MUSB_CORE_H__ |
| 36 | #define __MUSB_CORE_H__ |
| 37 | |
| 38 | #include <linux/slab.h> |
| 39 | #include <linux/list.h> |
| 40 | #include <linux/interrupt.h> |
| 41 | #include <linux/errno.h> |
| 42 | #include <linux/timer.h> |
| 43 | #include <linux/device.h> |
| 44 | #include <linux/usb/ch9.h> |
| 45 | #include <linux/usb/gadget.h> |
| 46 | #include <linux/usb.h> |
| 47 | #include <linux/usb/otg.h> |
| 48 | #include <linux/usb/musb.h> |
| 49 | #include <linux/phy/phy.h> |
| 50 | #include <linux/workqueue.h> |
| 51 | |
| 52 | struct musb; |
| 53 | struct musb_hw_ep; |
| 54 | struct musb_ep; |
| 55 | |
| 56 | /* Helper defines for struct musb->hwvers */ |
| 57 | #define MUSB_HWVERS_MAJOR(x) ((x >> 10) & 0x1f) |
| 58 | #define MUSB_HWVERS_MINOR(x) (x & 0x3ff) |
| 59 | #define MUSB_HWVERS_RC 0x8000 |
| 60 | #define MUSB_HWVERS_1300 0x52C |
| 61 | #define MUSB_HWVERS_1400 0x590 |
| 62 | #define MUSB_HWVERS_1800 0x720 |
| 63 | #define MUSB_HWVERS_1900 0x784 |
| 64 | #define MUSB_HWVERS_2000 0x800 |
| 65 | |
| 66 | #include "musb_debug.h" |
| 67 | #include "musb_dma.h" |
| 68 | |
| 69 | #include "musb_io.h" |
| 70 | |
| 71 | #include "musb_gadget.h" |
| 72 | #include <linux/usb/hcd.h> |
| 73 | #include "musb_host.h" |
| 74 | |
| 75 | /* NOTE: otg and peripheral-only state machines start at B_IDLE. |
| 76 | * OTG or host-only go to A_IDLE when ID is sensed. |
| 77 | */ |
| 78 | #define is_peripheral_active(m) (!(m)->is_host) |
| 79 | #define is_host_active(m) ((m)->is_host) |
| 80 | |
| 81 | enum { |
| 82 | MUSB_PORT_MODE_HOST = 1, |
| 83 | MUSB_PORT_MODE_GADGET, |
| 84 | MUSB_PORT_MODE_DUAL_ROLE, |
| 85 | }; |
| 86 | |
| 87 | /****************************** CONSTANTS ********************************/ |
| 88 | |
| 89 | #ifndef MUSB_C_NUM_EPS |
| 90 | #define MUSB_C_NUM_EPS ((u8)16) |
| 91 | #endif |
| 92 | |
| 93 | #ifndef MUSB_MAX_END0_PACKET |
| 94 | #define MUSB_MAX_END0_PACKET ((u16)MUSB_EP0_FIFOSIZE) |
| 95 | #endif |
| 96 | |
| 97 | /* host side ep0 states */ |
| 98 | enum musb_h_ep0_state { |
| 99 | MUSB_EP0_IDLE, |
| 100 | MUSB_EP0_START, /* expect ack of setup */ |
| 101 | MUSB_EP0_IN, /* expect IN DATA */ |
| 102 | MUSB_EP0_OUT, /* expect ack of OUT DATA */ |
| 103 | MUSB_EP0_STATUS, /* expect ack of STATUS */ |
| 104 | } __attribute__ ((packed)); |
| 105 | |
| 106 | /* peripheral side ep0 states */ |
| 107 | enum musb_g_ep0_state { |
| 108 | MUSB_EP0_STAGE_IDLE, /* idle, waiting for SETUP */ |
| 109 | MUSB_EP0_STAGE_SETUP, /* received SETUP */ |
| 110 | MUSB_EP0_STAGE_TX, /* IN data */ |
| 111 | MUSB_EP0_STAGE_RX, /* OUT data */ |
| 112 | MUSB_EP0_STAGE_STATUSIN, /* (after OUT data) */ |
| 113 | MUSB_EP0_STAGE_STATUSOUT, /* (after IN data) */ |
| 114 | MUSB_EP0_STAGE_ACKWAIT, /* after zlp, before statusin */ |
| 115 | } __attribute__ ((packed)); |
| 116 | |
| 117 | /* |
| 118 | * OTG protocol constants. See USB OTG 1.3 spec, |
| 119 | * sections 5.5 "Device Timings" and 6.6.5 "Timers". |
| 120 | */ |
| 121 | #define OTG_TIME_A_WAIT_VRISE 100 /* msec (max) */ |
| 122 | #define OTG_TIME_A_WAIT_BCON 1100 /* min 1 second */ |
| 123 | #define OTG_TIME_A_AIDL_BDIS 200 /* min 200 msec */ |
| 124 | #define OTG_TIME_B_ASE0_BRST 100 /* min 3.125 ms */ |
| 125 | |
| 126 | /****************************** FUNCTIONS ********************************/ |
| 127 | |
| 128 | #define MUSB_HST_MODE(_musb)\ |
| 129 | { (_musb)->is_host = true; } |
| 130 | #define MUSB_DEV_MODE(_musb) \ |
| 131 | { (_musb)->is_host = false; } |
| 132 | |
| 133 | #define test_devctl_hst_mode(_x) \ |
| 134 | (musb_readb((_x)->mregs, MUSB_DEVCTL)&MUSB_DEVCTL_HM) |
| 135 | |
| 136 | #define MUSB_MODE(musb) ((musb)->is_host ? "Host" : "Peripheral") |
| 137 | |
| 138 | /******************************** TYPES *************************************/ |
| 139 | |
| 140 | struct musb_io; |
| 141 | |
| 142 | /** |
| 143 | * struct musb_platform_ops - Operations passed to musb_core by HW glue layer |
| 144 | * @quirks: flags for platform specific quirks |
| 145 | * @enable: enable device |
| 146 | * @disable: disable device |
| 147 | * @ep_offset: returns the end point offset |
| 148 | * @ep_select: selects the specified end point |
| 149 | * @fifo_mode: sets the fifo mode |
| 150 | * @fifo_offset: returns the fifo offset |
| 151 | * @readb: read 8 bits |
| 152 | * @writeb: write 8 bits |
| 153 | * @readw: read 16 bits |
| 154 | * @writew: write 16 bits |
| 155 | * @readl: read 32 bits |
| 156 | * @writel: write 32 bits |
| 157 | * @read_fifo: reads the fifo |
| 158 | * @write_fifo: writes to fifo |
| 159 | * @dma_init: platform specific dma init function |
| 160 | * @dma_exit: platform specific dma exit function |
| 161 | * @init: turns on clocks, sets up platform-specific registers, etc |
| 162 | * @exit: undoes @init |
| 163 | * @set_mode: forcefully changes operating mode |
| 164 | * @try_idle: tries to idle the IP |
| 165 | * @recover: platform-specific babble recovery |
| 166 | * @vbus_status: returns vbus status if possible |
| 167 | * @set_vbus: forces vbus status |
| 168 | * @adjust_channel_params: pre check for standard dma channel_program func |
| 169 | * @pre_root_reset_end: called before the root usb port reset flag gets cleared |
| 170 | * @post_root_reset_end: called after the root usb port reset flag gets cleared |
| 171 | * @phy_callback: optional callback function for the phy to call |
| 172 | */ |
| 173 | struct musb_platform_ops { |
| 174 | |
| 175 | #define MUSB_DMA_UX500 BIT(6) |
| 176 | #define MUSB_DMA_CPPI41 BIT(5) |
| 177 | #define MUSB_DMA_CPPI BIT(4) |
| 178 | #define MUSB_DMA_TUSB_OMAP BIT(3) |
| 179 | #define MUSB_DMA_INVENTRA BIT(2) |
| 180 | #define MUSB_IN_TUSB BIT(1) |
| 181 | #define MUSB_INDEXED_EP BIT(0) |
| 182 | u32 quirks; |
| 183 | |
| 184 | int (*init)(struct musb *musb); |
| 185 | int (*exit)(struct musb *musb); |
| 186 | |
| 187 | void (*enable)(struct musb *musb); |
| 188 | void (*disable)(struct musb *musb); |
| 189 | |
| 190 | u32 (*ep_offset)(u8 epnum, u16 offset); |
| 191 | void (*ep_select)(void __iomem *mbase, u8 epnum); |
| 192 | u16 fifo_mode; |
| 193 | u32 (*fifo_offset)(u8 epnum); |
| 194 | u32 (*busctl_offset)(u8 epnum, u16 offset); |
| 195 | u8 (*readb)(const void __iomem *addr, unsigned offset); |
| 196 | void (*writeb)(void __iomem *addr, unsigned offset, u8 data); |
| 197 | u16 (*readw)(const void __iomem *addr, unsigned offset); |
| 198 | void (*writew)(void __iomem *addr, unsigned offset, u16 data); |
| 199 | u32 (*readl)(const void __iomem *addr, unsigned offset); |
| 200 | void (*writel)(void __iomem *addr, unsigned offset, u32 data); |
| 201 | void (*read_fifo)(struct musb_hw_ep *hw_ep, u16 len, u8 *buf); |
| 202 | void (*write_fifo)(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf); |
| 203 | struct dma_controller * |
| 204 | (*dma_init) (struct musb *musb, void __iomem *base); |
| 205 | void (*dma_exit)(struct dma_controller *c); |
| 206 | int (*set_mode)(struct musb *musb, u8 mode); |
| 207 | void (*try_idle)(struct musb *musb, unsigned long timeout); |
| 208 | int (*recover)(struct musb *musb); |
| 209 | |
| 210 | int (*vbus_status)(struct musb *musb); |
| 211 | void (*set_vbus)(struct musb *musb, int on); |
| 212 | |
| 213 | int (*adjust_channel_params)(struct dma_channel *channel, |
| 214 | u16 packet_sz, u8 *mode, |
| 215 | dma_addr_t *dma_addr, u32 *len); |
| 216 | void (*pre_root_reset_end)(struct musb *musb); |
| 217 | void (*post_root_reset_end)(struct musb *musb); |
| 218 | int (*phy_callback)(enum musb_vbus_id_status status); |
| 219 | }; |
| 220 | |
| 221 | /* |
| 222 | * struct musb_hw_ep - endpoint hardware (bidirectional) |
| 223 | * |
| 224 | * Ordered slightly for better cacheline locality. |
| 225 | */ |
| 226 | struct musb_hw_ep { |
| 227 | struct musb *musb; |
| 228 | void __iomem *fifo; |
| 229 | void __iomem *regs; |
| 230 | |
| 231 | #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) |
| 232 | void __iomem *conf; |
| 233 | #endif |
| 234 | |
| 235 | /* index in musb->endpoints[] */ |
| 236 | u8 epnum; |
| 237 | |
| 238 | /* hardware configuration, possibly dynamic */ |
| 239 | bool is_shared_fifo; |
| 240 | bool tx_double_buffered; |
| 241 | bool rx_double_buffered; |
| 242 | u16 max_packet_sz_tx; |
| 243 | u16 max_packet_sz_rx; |
| 244 | |
| 245 | struct dma_channel *tx_channel; |
| 246 | struct dma_channel *rx_channel; |
| 247 | |
| 248 | #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) |
| 249 | /* TUSB has "asynchronous" and "synchronous" dma modes */ |
| 250 | dma_addr_t fifo_async; |
| 251 | dma_addr_t fifo_sync; |
| 252 | void __iomem *fifo_sync_va; |
| 253 | #endif |
| 254 | |
| 255 | /* currently scheduled peripheral endpoint */ |
| 256 | struct musb_qh *in_qh; |
| 257 | struct musb_qh *out_qh; |
| 258 | |
| 259 | u8 rx_reinit; |
| 260 | u8 tx_reinit; |
| 261 | |
| 262 | /* peripheral side */ |
| 263 | struct musb_ep ep_in; /* TX */ |
| 264 | struct musb_ep ep_out; /* RX */ |
| 265 | }; |
| 266 | |
| 267 | static inline struct musb_request *next_in_request(struct musb_hw_ep *hw_ep) |
| 268 | { |
| 269 | return next_request(&hw_ep->ep_in); |
| 270 | } |
| 271 | |
| 272 | static inline struct musb_request *next_out_request(struct musb_hw_ep *hw_ep) |
| 273 | { |
| 274 | return next_request(&hw_ep->ep_out); |
| 275 | } |
| 276 | |
| 277 | struct musb_csr_regs { |
| 278 | /* FIFO registers */ |
| 279 | u16 txmaxp, txcsr, rxmaxp, rxcsr; |
| 280 | u16 rxfifoadd, txfifoadd; |
| 281 | u8 txtype, txinterval, rxtype, rxinterval; |
| 282 | u8 rxfifosz, txfifosz; |
| 283 | u8 txfunaddr, txhubaddr, txhubport; |
| 284 | u8 rxfunaddr, rxhubaddr, rxhubport; |
| 285 | }; |
| 286 | |
| 287 | struct musb_context_registers { |
| 288 | |
| 289 | u8 power; |
| 290 | u8 intrusbe; |
| 291 | u16 frame; |
| 292 | u8 index, testmode; |
| 293 | |
| 294 | u8 devctl, busctl, misc; |
| 295 | u32 otg_interfsel; |
| 296 | |
| 297 | struct musb_csr_regs index_regs[MUSB_C_NUM_EPS]; |
| 298 | }; |
| 299 | |
| 300 | /* |
| 301 | * struct musb - Driver instance data. |
| 302 | */ |
| 303 | struct musb { |
| 304 | /* device lock */ |
| 305 | spinlock_t lock; |
| 306 | |
| 307 | struct musb_io io; |
| 308 | const struct musb_platform_ops *ops; |
| 309 | struct musb_context_registers context; |
| 310 | |
| 311 | irqreturn_t (*isr)(int, void *); |
| 312 | struct work_struct irq_work; |
| 313 | struct delayed_work deassert_reset_work; |
| 314 | struct delayed_work finish_resume_work; |
| 315 | struct delayed_work gadget_work; |
| 316 | u16 hwvers; |
| 317 | |
| 318 | u16 intrrxe; |
| 319 | u16 intrtxe; |
| 320 | /* this hub status bit is reserved by USB 2.0 and not seen by usbcore */ |
| 321 | #define MUSB_PORT_STAT_RESUME (1 << 31) |
| 322 | |
| 323 | u32 port1_status; |
| 324 | |
| 325 | unsigned long rh_timer; |
| 326 | |
| 327 | enum musb_h_ep0_state ep0_stage; |
| 328 | |
| 329 | /* bulk traffic normally dedicates endpoint hardware, and each |
| 330 | * direction has its own ring of host side endpoints. |
| 331 | * we try to progress the transfer at the head of each endpoint's |
| 332 | * queue until it completes or NAKs too much; then we try the next |
| 333 | * endpoint. |
| 334 | */ |
| 335 | struct musb_hw_ep *bulk_ep; |
| 336 | |
| 337 | struct list_head control; /* of musb_qh */ |
| 338 | struct list_head in_bulk; /* of musb_qh */ |
| 339 | struct list_head out_bulk; /* of musb_qh */ |
| 340 | |
| 341 | struct timer_list otg_timer; |
| 342 | struct notifier_block nb; |
| 343 | |
| 344 | struct dma_controller *dma_controller; |
| 345 | |
| 346 | struct device *controller; |
| 347 | void __iomem *ctrl_base; |
| 348 | void __iomem *mregs; |
| 349 | |
| 350 | #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) |
| 351 | dma_addr_t async; |
| 352 | dma_addr_t sync; |
| 353 | void __iomem *sync_va; |
| 354 | u8 tusb_revision; |
| 355 | #endif |
| 356 | |
| 357 | /* passed down from chip/board specific irq handlers */ |
| 358 | u8 int_usb; |
| 359 | u16 int_rx; |
| 360 | u16 int_tx; |
| 361 | |
| 362 | struct usb_phy *xceiv; |
| 363 | struct phy *phy; |
| 364 | |
| 365 | int nIrq; |
| 366 | unsigned irq_wake:1; |
| 367 | |
| 368 | struct musb_hw_ep endpoints[MUSB_C_NUM_EPS]; |
| 369 | #define control_ep endpoints |
| 370 | |
| 371 | #define VBUSERR_RETRY_COUNT 3 |
| 372 | u16 vbuserr_retry; |
| 373 | u16 epmask; |
| 374 | u8 nr_endpoints; |
| 375 | |
| 376 | int (*board_set_power)(int state); |
| 377 | |
| 378 | u8 min_power; /* vbus for periph, in mA/2 */ |
| 379 | |
| 380 | int port_mode; /* MUSB_PORT_MODE_* */ |
| 381 | bool session; |
| 382 | bool quirk_invalid_vbus; |
| 383 | bool is_host; |
| 384 | |
| 385 | int a_wait_bcon; /* VBUS timeout in msecs */ |
| 386 | unsigned long idle_timeout; /* Next timeout in jiffies */ |
| 387 | |
| 388 | /* active means connected and not suspended */ |
| 389 | unsigned is_active:1; |
| 390 | |
| 391 | unsigned is_multipoint:1; |
| 392 | |
| 393 | unsigned hb_iso_rx:1; /* high bandwidth iso rx? */ |
| 394 | unsigned hb_iso_tx:1; /* high bandwidth iso tx? */ |
| 395 | unsigned dyn_fifo:1; /* dynamic FIFO supported? */ |
| 396 | |
| 397 | unsigned bulk_split:1; |
| 398 | #define can_bulk_split(musb,type) \ |
| 399 | (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split) |
| 400 | |
| 401 | unsigned bulk_combine:1; |
| 402 | #define can_bulk_combine(musb,type) \ |
| 403 | (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine) |
| 404 | |
| 405 | /* is_suspended means USB B_PERIPHERAL suspend */ |
| 406 | unsigned is_suspended:1; |
| 407 | unsigned need_finish_resume :1; |
| 408 | |
| 409 | /* may_wakeup means remote wakeup is enabled */ |
| 410 | unsigned may_wakeup:1; |
| 411 | |
| 412 | /* is_self_powered is reported in device status and the |
| 413 | * config descriptor. is_bus_powered means B_PERIPHERAL |
| 414 | * draws some VBUS current; both can be true. |
| 415 | */ |
| 416 | unsigned is_self_powered:1; |
| 417 | unsigned is_bus_powered:1; |
| 418 | |
| 419 | unsigned set_address:1; |
| 420 | unsigned test_mode:1; |
| 421 | unsigned softconnect:1; |
| 422 | |
| 423 | u8 address; |
| 424 | u8 test_mode_nr; |
| 425 | u16 ackpend; /* ep0 */ |
| 426 | enum musb_g_ep0_state ep0_state; |
| 427 | struct usb_gadget g; /* the gadget */ |
| 428 | struct usb_gadget_driver *gadget_driver; /* its driver */ |
| 429 | struct usb_hcd *hcd; /* the usb hcd */ |
| 430 | |
| 431 | /* |
| 432 | * FIXME: Remove this flag. |
| 433 | * |
| 434 | * This is only added to allow Blackfin to work |
| 435 | * with current driver. For some unknown reason |
| 436 | * Blackfin doesn't work with double buffering |
| 437 | * and that's enabled by default. |
| 438 | * |
| 439 | * We added this flag to forcefully disable double |
| 440 | * buffering until we get it working. |
| 441 | */ |
| 442 | unsigned double_buffer_not_ok:1; |
| 443 | |
| 444 | const struct musb_hdrc_config *config; |
| 445 | |
| 446 | int xceiv_old_state; |
| 447 | #ifdef CONFIG_DEBUG_FS |
| 448 | struct dentry *debugfs_root; |
| 449 | #endif |
| 450 | }; |
| 451 | |
| 452 | /* This must be included after struct musb is defined */ |
| 453 | #include "musb_regs.h" |
| 454 | |
| 455 | static inline struct musb *gadget_to_musb(struct usb_gadget *g) |
| 456 | { |
| 457 | return container_of(g, struct musb, g); |
| 458 | } |
| 459 | |
| 460 | #ifdef CONFIG_BLACKFIN |
| 461 | static inline int musb_read_fifosize(struct musb *musb, |
| 462 | struct musb_hw_ep *hw_ep, u8 epnum) |
| 463 | { |
| 464 | musb->nr_endpoints++; |
| 465 | musb->epmask |= (1 << epnum); |
| 466 | |
| 467 | if (epnum < 5) { |
| 468 | hw_ep->max_packet_sz_tx = 128; |
| 469 | hw_ep->max_packet_sz_rx = 128; |
| 470 | } else { |
| 471 | hw_ep->max_packet_sz_tx = 1024; |
| 472 | hw_ep->max_packet_sz_rx = 1024; |
| 473 | } |
| 474 | hw_ep->is_shared_fifo = false; |
| 475 | |
| 476 | return 0; |
| 477 | } |
| 478 | |
| 479 | static inline void musb_configure_ep0(struct musb *musb) |
| 480 | { |
| 481 | musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE; |
| 482 | musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE; |
| 483 | musb->endpoints[0].is_shared_fifo = true; |
| 484 | } |
| 485 | |
| 486 | #else |
| 487 | |
| 488 | static inline int musb_read_fifosize(struct musb *musb, |
| 489 | struct musb_hw_ep *hw_ep, u8 epnum) |
| 490 | { |
| 491 | void __iomem *mbase = musb->mregs; |
| 492 | u8 reg = 0; |
| 493 | |
| 494 | /* read from core using indexed model */ |
| 495 | reg = musb_readb(mbase, musb->io.ep_offset(epnum, MUSB_FIFOSIZE)); |
| 496 | /* 0's returned when no more endpoints */ |
| 497 | if (!reg) |
| 498 | return -ENODEV; |
| 499 | |
| 500 | musb->nr_endpoints++; |
| 501 | musb->epmask |= (1 << epnum); |
| 502 | |
| 503 | hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f); |
| 504 | |
| 505 | /* shared TX/RX FIFO? */ |
| 506 | if ((reg & 0xf0) == 0xf0) { |
| 507 | hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx; |
| 508 | hw_ep->is_shared_fifo = true; |
| 509 | return 0; |
| 510 | } else { |
| 511 | hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4); |
| 512 | hw_ep->is_shared_fifo = false; |
| 513 | } |
| 514 | |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | static inline void musb_configure_ep0(struct musb *musb) |
| 519 | { |
| 520 | musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE; |
| 521 | musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE; |
| 522 | musb->endpoints[0].is_shared_fifo = true; |
| 523 | } |
| 524 | #endif /* CONFIG_BLACKFIN */ |
| 525 | |
| 526 | |
| 527 | /***************************** Glue it together *****************************/ |
| 528 | |
| 529 | extern const char musb_driver_name[]; |
| 530 | |
| 531 | extern void musb_stop(struct musb *musb); |
| 532 | extern void musb_start(struct musb *musb); |
| 533 | |
| 534 | extern void musb_write_fifo(struct musb_hw_ep *ep, u16 len, const u8 *src); |
| 535 | extern void musb_read_fifo(struct musb_hw_ep *ep, u16 len, u8 *dst); |
| 536 | |
| 537 | extern void musb_load_testpacket(struct musb *); |
| 538 | |
| 539 | extern irqreturn_t musb_interrupt(struct musb *); |
| 540 | |
| 541 | extern void musb_hnp_stop(struct musb *musb); |
| 542 | |
| 543 | static inline void musb_platform_set_vbus(struct musb *musb, int is_on) |
| 544 | { |
| 545 | if (musb->ops->set_vbus) |
| 546 | musb->ops->set_vbus(musb, is_on); |
| 547 | } |
| 548 | |
| 549 | static inline void musb_platform_enable(struct musb *musb) |
| 550 | { |
| 551 | if (musb->ops->enable) |
| 552 | musb->ops->enable(musb); |
| 553 | } |
| 554 | |
| 555 | static inline void musb_platform_disable(struct musb *musb) |
| 556 | { |
| 557 | if (musb->ops->disable) |
| 558 | musb->ops->disable(musb); |
| 559 | } |
| 560 | |
| 561 | static inline int musb_platform_set_mode(struct musb *musb, u8 mode) |
| 562 | { |
| 563 | if (!musb->ops->set_mode) |
| 564 | return 0; |
| 565 | |
| 566 | return musb->ops->set_mode(musb, mode); |
| 567 | } |
| 568 | |
| 569 | static inline void musb_platform_try_idle(struct musb *musb, |
| 570 | unsigned long timeout) |
| 571 | { |
| 572 | if (musb->ops->try_idle) |
| 573 | musb->ops->try_idle(musb, timeout); |
| 574 | } |
| 575 | |
| 576 | static inline int musb_platform_recover(struct musb *musb) |
| 577 | { |
| 578 | if (!musb->ops->recover) |
| 579 | return 0; |
| 580 | |
| 581 | return musb->ops->recover(musb); |
| 582 | } |
| 583 | |
| 584 | static inline int musb_platform_get_vbus_status(struct musb *musb) |
| 585 | { |
| 586 | if (!musb->ops->vbus_status) |
| 587 | return -EINVAL; |
| 588 | |
| 589 | return musb->ops->vbus_status(musb); |
| 590 | } |
| 591 | |
| 592 | static inline int musb_platform_init(struct musb *musb) |
| 593 | { |
| 594 | if (!musb->ops->init) |
| 595 | return -EINVAL; |
| 596 | |
| 597 | return musb->ops->init(musb); |
| 598 | } |
| 599 | |
| 600 | static inline int musb_platform_exit(struct musb *musb) |
| 601 | { |
| 602 | if (!musb->ops->exit) |
| 603 | return -EINVAL; |
| 604 | |
| 605 | return musb->ops->exit(musb); |
| 606 | } |
| 607 | |
| 608 | static inline void musb_platform_pre_root_reset_end(struct musb *musb) |
| 609 | { |
| 610 | if (musb->ops->pre_root_reset_end) |
| 611 | musb->ops->pre_root_reset_end(musb); |
| 612 | } |
| 613 | |
| 614 | static inline void musb_platform_post_root_reset_end(struct musb *musb) |
| 615 | { |
| 616 | if (musb->ops->post_root_reset_end) |
| 617 | musb->ops->post_root_reset_end(musb); |
| 618 | } |
| 619 | |
| 620 | #endif /* __MUSB_CORE_H__ */ |