[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / host / sl811.h

/*
 * SL811HS register declarations and HCD data structures
 *
 * Copyright (C) 2004 Psion Teklogix
 * Copyright (C) 2004 David Brownell
 * Copyright (C) 2001 Cypress Semiconductor Inc. 
 */

/*
 * SL811HS has transfer registers, and control registers.  In host/master
 * mode one set of registers is used; in peripheral/slave mode, another.
 *  - SL11H only has some "A" transfer registers from 0x00-0x04
 *  - SL811HS also has "B" registers from 0x08-0x0c
 *  - SL811S (or HS in slave mode) has four A+B sets, at 00, 10, 20, 30
 */

#define SL811_EP_A(base)	((base) + 0)
#define SL811_EP_B(base)	((base) + 8)

#define SL811_HOST_BUF		0x00
#define SL811_PERIPH_EP0	0x00
#define SL811_PERIPH_EP1	0x10
#define SL811_PERIPH_EP2	0x20
#define SL811_PERIPH_EP3	0x30


/* TRANSFER REGISTERS:  host and peripheral sides are similar
 * except for the control models (master vs slave).
 */
#define SL11H_HOSTCTLREG	0
#	define SL11H_HCTLMASK_ARM	0x01
#	define SL11H_HCTLMASK_ENABLE	0x02
#	define SL11H_HCTLMASK_IN	0x00
#	define SL11H_HCTLMASK_OUT	0x04
#	define SL11H_HCTLMASK_ISOCH	0x10
#	define SL11H_HCTLMASK_AFTERSOF	0x20
#	define SL11H_HCTLMASK_TOGGLE	0x40
#	define SL11H_HCTLMASK_PREAMBLE	0x80
#define SL11H_BUFADDRREG	1
#define SL11H_BUFLNTHREG	2
#define SL11H_PKTSTATREG	3	/* read */
#	define SL11H_STATMASK_ACK	0x01
#	define SL11H_STATMASK_ERROR	0x02
#	define SL11H_STATMASK_TMOUT	0x04
#	define SL11H_STATMASK_SEQ	0x08
#	define SL11H_STATMASK_SETUP	0x10
#	define SL11H_STATMASK_OVF	0x20
#	define SL11H_STATMASK_NAK	0x40
#	define SL11H_STATMASK_STALL	0x80
#define SL11H_PIDEPREG		3	/* write */
#	define	SL_SETUP	0xd0
#	define	SL_IN		0x90
#	define	SL_OUT		0x10
#	define	SL_SOF		0x50
#	define	SL_PREAMBLE	0xc0
#	define	SL_NAK		0xa0
#	define	SL_STALL	0xe0
#	define	SL_DATA0	0x30
#	define	SL_DATA1	0xb0
#define SL11H_XFERCNTREG	4	/* read */
#define SL11H_DEVADDRREG	4	/* write */


/* CONTROL REGISTERS:  host and peripheral are very different.
 */
#define SL11H_CTLREG1		5
#	define SL11H_CTL1MASK_SOF_ENA	0x01
#	define SL11H_CTL1MASK_FORCE	0x18
#		define SL11H_CTL1MASK_NORMAL	0x00
#		define SL11H_CTL1MASK_SE0	0x08	/* reset */
#		define SL11H_CTL1MASK_J		0x10
#		define SL11H_CTL1MASK_K		0x18	/* resume */
#	define SL11H_CTL1MASK_LSPD	0x20
#	define SL11H_CTL1MASK_SUSPEND	0x40
#define SL11H_IRQ_ENABLE	6
#	define SL11H_INTMASK_DONE_A	0x01
#	define SL11H_INTMASK_DONE_B	0x02
#	define SL11H_INTMASK_SOFINTR	0x10
#	define SL11H_INTMASK_INSRMV	0x20	/* to/from SE0 */
#	define SL11H_INTMASK_RD		0x40
#	define SL11H_INTMASK_DP		0x80	/* only in INTSTATREG */
#define SL11S_ADDRESS		7

/* 0x08-0x0c are for the B buffer (not in SL11) */

#define SL11H_IRQ_STATUS	0x0D	/* write to ack */
#define SL11H_HWREVREG		0x0E	/* read */
#	define SL11H_HWRMASK_HWREV	0xF0
#define SL11H_SOFLOWREG		0x0E	/* write */
#define SL11H_SOFTMRREG		0x0F	/* read */

/* a write to this register enables SL811HS features.
 * HOST flag presumably overrides the chip input signal?
 */
#define SL811HS_CTLREG2		0x0F
#	define SL811HS_CTL2MASK_SOF_MASK	0x3F
#	define SL811HS_CTL2MASK_DSWAP		0x40
#	define SL811HS_CTL2MASK_HOST		0x80

#define SL811HS_CTL2_INIT	(SL811HS_CTL2MASK_HOST | 0x2e)


/* DATA BUFFERS: registers from 0x10..0xff are for data buffers;
 * that's 240 bytes, which we'll split evenly between A and B sides.
 * Only ISO can use more than 64 bytes per packet.
 * (The SL11S has 0x40..0xff for buffers.)
 */
#define H_MAXPACKET	120		/* bytes in A or B fifos */

#define SL11H_DATA_START	0x10
#define	SL811HS_PACKET_BUF(is_a)	((is_a) \
		? SL11H_DATA_START \
		: (SL11H_DATA_START + H_MAXPACKET))

/*-------------------------------------------------------------------------*/

#define	LOG2_PERIODIC_SIZE	5	/* arbitrary; this matches OHCI */
#define	PERIODIC_SIZE		(1 << LOG2_PERIODIC_SIZE)

struct sl811 {
	spinlock_t		lock;
	void __iomem		*addr_reg;
	void __iomem		*data_reg;
	struct sl811_platform_data	*board;
	struct proc_dir_entry	*pde;

	unsigned long		stat_insrmv;
	unsigned long		stat_wake;
	unsigned long		stat_sof;
	unsigned long		stat_a;
	unsigned long		stat_b;
	unsigned long		stat_lost;
	unsigned long		stat_overrun;

	/* sw model */
	struct timer_list	timer;
	struct sl811h_ep	*next_periodic;
	struct sl811h_ep	*next_async;

	struct sl811h_ep	*active_a;
	unsigned long		jiffies_a;
	struct sl811h_ep	*active_b;
	unsigned long		jiffies_b;

	u32			port1;
	u8			ctrl1, ctrl2, irq_enable;
	u16			frame;

	/* async schedule: control, bulk */
	struct list_head	async;

	/* periodic schedule: interrupt, iso */
	u16			load[PERIODIC_SIZE];
	struct sl811h_ep	*periodic[PERIODIC_SIZE];
	unsigned		periodic_count;
};

static inline struct sl811 *hcd_to_sl811(struct usb_hcd *hcd)
{
	return (struct sl811 *) (hcd->hcd_priv);
}

static inline struct usb_hcd *sl811_to_hcd(struct sl811 *sl811)
{
	return container_of((void *) sl811, struct usb_hcd, hcd_priv);
}

struct sl811h_ep {
	struct usb_host_endpoint *hep;
	struct usb_device	*udev;

	u8			defctrl;
	u8			maxpacket;
	u8			epnum;
	u8			nextpid;

	u16			error_count;
	u16			nak_count;
	u16			length;		/* of current packet */

	/* periodic schedule */
	u16			period;
	u16			branch;
	u16			load;
	struct sl811h_ep	*next;

	/* async schedule */
	struct list_head	schedule;
};

/*-------------------------------------------------------------------------*/

/* These register utilities should work for the SL811S register API too
 * NOTE:  caller must hold sl811->lock.
 */

static inline u8 sl811_read(struct sl811 *sl811, int reg)
{
	writeb(reg, sl811->addr_reg);
	return readb(sl811->data_reg);
}

static inline void sl811_write(struct sl811 *sl811, int reg, u8 val)
{
	writeb(reg, sl811->addr_reg);
	writeb(val, sl811->data_reg);
}

static inline void
sl811_write_buf(struct sl811 *sl811, int addr, const void *buf, size_t count)
{
	const u8	*data;
	void __iomem	*data_reg;

	if (!count)
		return;
	writeb(addr, sl811->addr_reg);

	data = buf;
	data_reg = sl811->data_reg;
	do {
		writeb(*data++, data_reg);
	} while (--count);
}

static inline void
sl811_read_buf(struct sl811 *sl811, int addr, void *buf, size_t count)
{
	u8 		*data;
	void __iomem	*data_reg;

	if (!count)
		return;
	writeb(addr, sl811->addr_reg);

	data = buf;
	data_reg = sl811->data_reg;
	do {
		*data++ = readb(data_reg);
	} while (--count);
}

/*-------------------------------------------------------------------------*/

#ifdef DEBUG
#define DBG(stuff...)		printk(KERN_DEBUG "sl811: " stuff)
#else
#define DBG(stuff...)		do{}while(0)
#endif

#ifdef VERBOSE
#    define VDBG		DBG
#else
#    define VDBG(stuff...)	do{}while(0)
#endif

#ifdef PACKET_TRACE
#    define PACKET		VDBG
#else
#    define PACKET(stuff...)	do{}while(0)
#endif

#define ERR(stuff...)		printk(KERN_ERR "sl811: " stuff)
#define WARNING(stuff...)	printk(KERN_WARNING "sl811: " stuff)
#define INFO(stuff...)		printk(KERN_INFO "sl811: " stuff)
Commit	Line	Data
	1	/*
	2	* SL811HS register declarations and HCD data structures
	3	*
	4	* Copyright (C) 2004 Psion Teklogix
	5	* Copyright (C) 2004 David Brownell
	6	* Copyright (C) 2001 Cypress Semiconductor Inc.
	7	*/
	8
	9	/*
	10	* SL811HS has transfer registers, and control registers. In host/master
	11	* mode one set of registers is used; in peripheral/slave mode, another.
	12	* - SL11H only has some "A" transfer registers from 0x00-0x04
	13	* - SL811HS also has "B" registers from 0x08-0x0c
	14	* - SL811S (or HS in slave mode) has four A+B sets, at 00, 10, 20, 30
	15	*/
	16
	17	#define SL811_EP_A(base) ((base) + 0)
	18	#define SL811_EP_B(base) ((base) + 8)
	19
	20	#define SL811_HOST_BUF 0x00
	21	#define SL811_PERIPH_EP0 0x00
	22	#define SL811_PERIPH_EP1 0x10
	23	#define SL811_PERIPH_EP2 0x20
	24	#define SL811_PERIPH_EP3 0x30
	25
	26
	27	/* TRANSFER REGISTERS: host and peripheral sides are similar
	28	* except for the control models (master vs slave).
	29	*/
	30	#define SL11H_HOSTCTLREG 0
	31	# define SL11H_HCTLMASK_ARM 0x01
	32	# define SL11H_HCTLMASK_ENABLE 0x02
	33	# define SL11H_HCTLMASK_IN 0x00
	34	# define SL11H_HCTLMASK_OUT 0x04
	35	# define SL11H_HCTLMASK_ISOCH 0x10
	36	# define SL11H_HCTLMASK_AFTERSOF 0x20
	37	# define SL11H_HCTLMASK_TOGGLE 0x40
	38	# define SL11H_HCTLMASK_PREAMBLE 0x80
	39	#define SL11H_BUFADDRREG 1
	40	#define SL11H_BUFLNTHREG 2
	41	#define SL11H_PKTSTATREG 3 /* read */
	42	# define SL11H_STATMASK_ACK 0x01
	43	# define SL11H_STATMASK_ERROR 0x02
	44	# define SL11H_STATMASK_TMOUT 0x04
	45	# define SL11H_STATMASK_SEQ 0x08
	46	# define SL11H_STATMASK_SETUP 0x10
	47	# define SL11H_STATMASK_OVF 0x20
	48	# define SL11H_STATMASK_NAK 0x40
	49	# define SL11H_STATMASK_STALL 0x80
	50	#define SL11H_PIDEPREG 3 /* write */
	51	# define SL_SETUP 0xd0
	52	# define SL_IN 0x90
	53	# define SL_OUT 0x10
	54	# define SL_SOF 0x50
	55	# define SL_PREAMBLE 0xc0
	56	# define SL_NAK 0xa0
	57	# define SL_STALL 0xe0
	58	# define SL_DATA0 0x30
	59	# define SL_DATA1 0xb0
	60	#define SL11H_XFERCNTREG 4 /* read */
	61	#define SL11H_DEVADDRREG 4 /* write */
	62
	63
	64	/* CONTROL REGISTERS: host and peripheral are very different.
	65	*/
	66	#define SL11H_CTLREG1 5
	67	# define SL11H_CTL1MASK_SOF_ENA 0x01
	68	# define SL11H_CTL1MASK_FORCE 0x18
	69	# define SL11H_CTL1MASK_NORMAL 0x00
	70	# define SL11H_CTL1MASK_SE0 0x08 /* reset */
	71	# define SL11H_CTL1MASK_J 0x10
	72	# define SL11H_CTL1MASK_K 0x18 /* resume */
	73	# define SL11H_CTL1MASK_LSPD 0x20
	74	# define SL11H_CTL1MASK_SUSPEND 0x40
	75	#define SL11H_IRQ_ENABLE 6
	76	# define SL11H_INTMASK_DONE_A 0x01
	77	# define SL11H_INTMASK_DONE_B 0x02
	78	# define SL11H_INTMASK_SOFINTR 0x10
	79	# define SL11H_INTMASK_INSRMV 0x20 /* to/from SE0 */
	80	# define SL11H_INTMASK_RD 0x40
	81	# define SL11H_INTMASK_DP 0x80 /* only in INTSTATREG */
	82	#define SL11S_ADDRESS 7
	83
	84	/* 0x08-0x0c are for the B buffer (not in SL11) */
	85
	86	#define SL11H_IRQ_STATUS 0x0D /* write to ack */
	87	#define SL11H_HWREVREG 0x0E /* read */
	88	# define SL11H_HWRMASK_HWREV 0xF0
	89	#define SL11H_SOFLOWREG 0x0E /* write */
	90	#define SL11H_SOFTMRREG 0x0F /* read */
	91
	92	/* a write to this register enables SL811HS features.
	93	* HOST flag presumably overrides the chip input signal?
	94	*/
	95	#define SL811HS_CTLREG2 0x0F
	96	# define SL811HS_CTL2MASK_SOF_MASK 0x3F
	97	# define SL811HS_CTL2MASK_DSWAP 0x40
	98	# define SL811HS_CTL2MASK_HOST 0x80
	99
	100	#define SL811HS_CTL2_INIT (SL811HS_CTL2MASK_HOST \| 0x2e)
	101
	102
	103	/* DATA BUFFERS: registers from 0x10..0xff are for data buffers;
	104	* that's 240 bytes, which we'll split evenly between A and B sides.
	105	* Only ISO can use more than 64 bytes per packet.
	106	* (The SL11S has 0x40..0xff for buffers.)
	107	*/
	108	#define H_MAXPACKET 120 /* bytes in A or B fifos */
	109
	110	#define SL11H_DATA_START 0x10
	111	#define SL811HS_PACKET_BUF(is_a) ((is_a) \
	112	? SL11H_DATA_START \
	113	: (SL11H_DATA_START + H_MAXPACKET))
	114
	115	/-------------------------------------------------------------------------/
	116
	117	#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
	118	#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
	119
	120	struct sl811 {
	121	spinlock_t lock;
	122	void __iomem *addr_reg;
	123	void __iomem *data_reg;
	124	struct sl811_platform_data *board;
	125	struct proc_dir_entry *pde;
	126
	127	unsigned long stat_insrmv;
	128	unsigned long stat_wake;
	129	unsigned long stat_sof;
	130	unsigned long stat_a;
	131	unsigned long stat_b;
	132	unsigned long stat_lost;
	133	unsigned long stat_overrun;
	134
	135	/* sw model */
	136	struct timer_list timer;
	137	struct sl811h_ep *next_periodic;
	138	struct sl811h_ep *next_async;
	139
	140	struct sl811h_ep *active_a;
	141	unsigned long jiffies_a;
	142	struct sl811h_ep *active_b;
	143	unsigned long jiffies_b;
	144
	145	u32 port1;
	146	u8 ctrl1, ctrl2, irq_enable;
	147	u16 frame;
	148
	149	/* async schedule: control, bulk */
	150	struct list_head async;
	151
	152	/* periodic schedule: interrupt, iso */
	153	u16 load[PERIODIC_SIZE];
	154	struct sl811h_ep *periodic[PERIODIC_SIZE];
	155	unsigned periodic_count;
	156	};
	157
	158	static inline struct sl811 hcd_to_sl811(struct usb_hcd hcd)
	159	{
	160	return (struct sl811 *) (hcd->hcd_priv);
	161	}
	162
	163	static inline struct usb_hcd sl811_to_hcd(struct sl811 sl811)
	164	{
	165	return container_of((void *) sl811, struct usb_hcd, hcd_priv);
	166	}
	167
	168	struct sl811h_ep {
	169	struct usb_host_endpoint *hep;
	170	struct usb_device *udev;
	171
	172	u8 defctrl;
	173	u8 maxpacket;
	174	u8 epnum;
	175	u8 nextpid;
	176
	177	u16 error_count;
	178	u16 nak_count;
	179	u16 length; /* of current packet */
	180
	181	/* periodic schedule */
	182	u16 period;
	183	u16 branch;
	184	u16 load;
	185	struct sl811h_ep *next;
	186
	187	/* async schedule */
	188	struct list_head schedule;
	189	};
	190
	191	/-------------------------------------------------------------------------/
	192
	193	/* These register utilities should work for the SL811S register API too
	194	* NOTE: caller must hold sl811->lock.
	195	*/
	196
	197	static inline u8 sl811_read(struct sl811 *sl811, int reg)
	198	{
	199	writeb(reg, sl811->addr_reg);
	200	return readb(sl811->data_reg);
	201	}
	202
	203	static inline void sl811_write(struct sl811 *sl811, int reg, u8 val)
	204	{
	205	writeb(reg, sl811->addr_reg);
	206	writeb(val, sl811->data_reg);
	207	}
	208
	209	static inline void
	210	sl811_write_buf(struct sl811 sl811, int addr, const void buf, size_t count)
	211	{
	212	const u8 *data;
	213	void __iomem *data_reg;
	214
	215	if (!count)
	216	return;
	217	writeb(addr, sl811->addr_reg);
	218
	219	data = buf;
	220	data_reg = sl811->data_reg;
	221	do {
	222	writeb(*data++, data_reg);
	223	} while (--count);
	224	}
	225
	226	static inline void
	227	sl811_read_buf(struct sl811 sl811, int addr, void buf, size_t count)
	228	{
	229	u8 *data;
	230	void __iomem *data_reg;
	231
	232	if (!count)
	233	return;
	234	writeb(addr, sl811->addr_reg);
	235
	236	data = buf;
	237	data_reg = sl811->data_reg;
	238	do {
	239	*data++ = readb(data_reg);
	240	} while (--count);
	241	}
	242
	243	/-------------------------------------------------------------------------/
	244
	245	#ifdef DEBUG
	246	#define DBG(stuff...) printk(KERN_DEBUG "sl811: " stuff)
	247	#else
	248	#define DBG(stuff...) do{}while(0)
	249	#endif
	250
	251	#ifdef VERBOSE
	252	# define VDBG DBG
	253	#else
	254	# define VDBG(stuff...) do{}while(0)
	255	#endif
	256
	257	#ifdef PACKET_TRACE
	258	# define PACKET VDBG
	259	#else
	260	# define PACKET(stuff...) do{}while(0)
	261	#endif
	262
	263	#define ERR(stuff...) printk(KERN_ERR "sl811: " stuff)
	264	#define WARNING(stuff...) printk(KERN_WARNING "sl811: " stuff)
	265	#define INFO(stuff...) printk(KERN_INFO "sl811: " stuff)
	266