| 1 | /*++ |
| 2 | Copyright (c) Realtek Semiconductor Corp. All rights reserved. |
| 3 | |
| 4 | Module Name: |
| 5 | r8185b_init.c |
| 6 | |
| 7 | Abstract: |
| 8 | Hardware Initialization and Hardware IO for RTL8185B |
| 9 | |
| 10 | Major Change History: |
| 11 | When Who What |
| 12 | ---------- --------------- ------------------------------- |
| 13 | 2006-11-15 Xiong Created |
| 14 | |
| 15 | Notes: |
| 16 | This file is ported from RTL8185B Windows driver. |
| 17 | |
| 18 | |
| 19 | --*/ |
| 20 | |
| 21 | /*--------------------------Include File------------------------------------*/ |
| 22 | #include <linux/spinlock.h> |
| 23 | #include "r8180_hw.h" |
| 24 | #include "r8180.h" |
| 25 | #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */ |
| 26 | #include "r8180_93cx6.h" /* Card EEPROM */ |
| 27 | #include "r8180_wx.h" |
| 28 | |
| 29 | #include "ieee80211/dot11d.h" |
| 30 | |
| 31 | |
| 32 | //#define CONFIG_RTL8180_IO_MAP |
| 33 | |
| 34 | #define TC_3W_POLL_MAX_TRY_CNT 5 |
| 35 | static u8 MAC_REG_TABLE[][2]={ |
| 36 | //PAGA 0: |
| 37 | // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185() |
| 38 | // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185(). |
| 39 | // 0x1F0~0x1F8 set in MacConfig_85BASIC() |
| 40 | {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42}, |
| 41 | {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03}, |
| 42 | {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03}, |
| 43 | {0x94, 0x0F}, {0x95, 0x32}, |
| 44 | {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00}, |
| 45 | {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32}, |
| 46 | {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4}, |
| 47 | {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00}, |
| 48 | {0xff, 0x00}, |
| 49 | |
| 50 | //PAGE 1: |
| 51 | // For Flextronics system Logo PCIHCT failure: |
| 52 | // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1 |
| 53 | {0x5e, 0x01}, |
| 54 | {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24}, |
| 55 | {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF}, |
| 56 | {0x82, 0xFF}, {0x83, 0x03}, |
| 57 | {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826 |
| 58 | {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826 |
| 59 | {0xe2, 0x00}, |
| 60 | |
| 61 | |
| 62 | //PAGE 2: |
| 63 | {0x5e, 0x02}, |
| 64 | {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5}, |
| 65 | {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff}, |
| 66 | {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08}, |
| 67 | {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f}, |
| 68 | {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f}, |
| 69 | {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff}, |
| 70 | {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00}, |
| 71 | |
| 72 | //PAGA 0: |
| 73 | {0x5e, 0x00},{0x9f, 0x03} |
| 74 | }; |
| 75 | |
| 76 | |
| 77 | static u8 ZEBRA_AGC[]={ |
| 78 | 0, |
| 79 | 0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72, |
| 80 | 0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62, |
| 81 | 0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07, |
| 82 | 0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 83 | 0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16, |
| 84 | 0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e, |
| 85 | 0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24, |
| 86 | 0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F |
| 87 | }; |
| 88 | |
| 89 | static u32 ZEBRA_RF_RX_GAIN_TABLE[]={ |
| 90 | 0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6, |
| 91 | 0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057, |
| 92 | 0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3, |
| 93 | 0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3, |
| 94 | 0x0183,0x0163,0x0143,0x0123,0x0103 |
| 95 | }; |
| 96 | |
| 97 | static u8 OFDM_CONFIG[]={ |
| 98 | // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX |
| 99 | // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode |
| 100 | // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test |
| 101 | |
| 102 | // 0x00 |
| 103 | 0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50, |
| 104 | 0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00, |
| 105 | // 0x10 |
| 106 | 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26, |
| 107 | 0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB, |
| 108 | // 0x20 |
| 109 | 0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00, |
| 110 | 0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00, |
| 111 | // 0x30 |
| 112 | 0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e, |
| 113 | 0xD8, 0x3C, 0x7B, 0x10, 0x10 |
| 114 | }; |
| 115 | |
| 116 | /*--------------------------------------------------------------- |
| 117 | * Hardware IO |
| 118 | * the code is ported from Windows source code |
| 119 | ----------------------------------------------------------------*/ |
| 120 | |
| 121 | void |
| 122 | PlatformIOWrite1Byte( |
| 123 | struct net_device *dev, |
| 124 | u32 offset, |
| 125 | u8 data |
| 126 | ) |
| 127 | { |
| 128 | write_nic_byte(dev, offset, data); |
| 129 | read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko. |
| 130 | |
| 131 | } |
| 132 | |
| 133 | void |
| 134 | PlatformIOWrite2Byte( |
| 135 | struct net_device *dev, |
| 136 | u32 offset, |
| 137 | u16 data |
| 138 | ) |
| 139 | { |
| 140 | write_nic_word(dev, offset, data); |
| 141 | read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko. |
| 142 | |
| 143 | |
| 144 | } |
| 145 | u8 PlatformIORead1Byte(struct net_device *dev, u32 offset); |
| 146 | |
| 147 | void |
| 148 | PlatformIOWrite4Byte( |
| 149 | struct net_device *dev, |
| 150 | u32 offset, |
| 151 | u32 data |
| 152 | ) |
| 153 | { |
| 154 | //{by amy 080312 |
| 155 | if (offset == PhyAddr) |
| 156 | {//For Base Band configuration. |
| 157 | unsigned char cmdByte; |
| 158 | unsigned long dataBytes; |
| 159 | unsigned char idx; |
| 160 | u8 u1bTmp; |
| 161 | |
| 162 | cmdByte = (u8)(data & 0x000000ff); |
| 163 | dataBytes = data>>8; |
| 164 | |
| 165 | // |
| 166 | // 071010, rcnjko: |
| 167 | // The critical section is only BB read/write race condition. |
| 168 | // Assumption: |
| 169 | // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for |
| 170 | // acquiring the spinlock in such context. |
| 171 | // 2. PlatformIOWrite4Byte() MUST NOT be recursive. |
| 172 | // |
| 173 | // NdisAcquireSpinLock( &(pDevice->IoSpinLock) ); |
| 174 | |
| 175 | for(idx = 0; idx < 30; idx++) |
| 176 | { // Make sure command bit is clear before access it. |
| 177 | u1bTmp = PlatformIORead1Byte(dev, PhyAddr); |
| 178 | if((u1bTmp & BIT7) == 0) |
| 179 | break; |
| 180 | else |
| 181 | mdelay(10); |
| 182 | } |
| 183 | |
| 184 | for(idx=0; idx < 3; idx++) |
| 185 | { |
| 186 | PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] ); |
| 187 | } |
| 188 | write_nic_byte(dev, offset, cmdByte); |
| 189 | |
| 190 | // NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); |
| 191 | } |
| 192 | //by amy 080312} |
| 193 | else{ |
| 194 | write_nic_dword(dev, offset, data); |
| 195 | read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko. |
| 196 | } |
| 197 | } |
| 198 | |
| 199 | u8 |
| 200 | PlatformIORead1Byte( |
| 201 | struct net_device *dev, |
| 202 | u32 offset |
| 203 | ) |
| 204 | { |
| 205 | u8 data = 0; |
| 206 | |
| 207 | data = read_nic_byte(dev, offset); |
| 208 | |
| 209 | |
| 210 | return data; |
| 211 | } |
| 212 | |
| 213 | u16 |
| 214 | PlatformIORead2Byte( |
| 215 | struct net_device *dev, |
| 216 | u32 offset |
| 217 | ) |
| 218 | { |
| 219 | u16 data = 0; |
| 220 | |
| 221 | data = read_nic_word(dev, offset); |
| 222 | |
| 223 | |
| 224 | return data; |
| 225 | } |
| 226 | |
| 227 | u32 |
| 228 | PlatformIORead4Byte( |
| 229 | struct net_device *dev, |
| 230 | u32 offset |
| 231 | ) |
| 232 | { |
| 233 | u32 data = 0; |
| 234 | |
| 235 | data = read_nic_dword(dev, offset); |
| 236 | |
| 237 | |
| 238 | return data; |
| 239 | } |
| 240 | |
| 241 | void SetOutputEnableOfRfPins(struct net_device *dev) |
| 242 | { |
| 243 | write_nic_word(dev, RFPinsEnable, 0x1bff); |
| 244 | } |
| 245 | |
| 246 | static int |
| 247 | HwHSSIThreeWire( |
| 248 | struct net_device *dev, |
| 249 | u8 *pDataBuf, |
| 250 | u8 nDataBufBitCnt, |
| 251 | int bSI, |
| 252 | int bWrite |
| 253 | ) |
| 254 | { |
| 255 | int bResult = 1; |
| 256 | u8 TryCnt; |
| 257 | u8 u1bTmp; |
| 258 | |
| 259 | do |
| 260 | { |
| 261 | // Check if WE and RE are cleared. |
| 262 | for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) |
| 263 | { |
| 264 | u1bTmp = read_nic_byte(dev, SW_3W_CMD1); |
| 265 | if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 ) |
| 266 | { |
| 267 | break; |
| 268 | } |
| 269 | udelay(10); |
| 270 | } |
| 271 | if (TryCnt == TC_3W_POLL_MAX_TRY_CNT) |
| 272 | panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp); |
| 273 | |
| 274 | // RTL8187S HSSI Read/Write Function |
| 275 | u1bTmp = read_nic_byte(dev, RF_SW_CONFIG); |
| 276 | |
| 277 | if(bSI) |
| 278 | { |
| 279 | u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI) |
| 280 | }else |
| 281 | { |
| 282 | u1bTmp &= ~RF_SW_CFG_SI; //reg08[1]=0 Parallel Interface(PI) |
| 283 | } |
| 284 | |
| 285 | write_nic_byte(dev, RF_SW_CONFIG, u1bTmp); |
| 286 | |
| 287 | if(bSI) |
| 288 | { |
| 289 | // jong: HW SI read must set reg84[3]=0. |
| 290 | u1bTmp = read_nic_byte(dev, RFPinsSelect); |
| 291 | u1bTmp &= ~BIT3; |
| 292 | write_nic_byte(dev, RFPinsSelect, u1bTmp ); |
| 293 | } |
| 294 | // Fill up data buffer for write operation. |
| 295 | |
| 296 | if(bWrite) |
| 297 | { |
| 298 | if(nDataBufBitCnt == 16) |
| 299 | { |
| 300 | write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf)); |
| 301 | } |
| 302 | else if(nDataBufBitCnt == 64) // RTL8187S shouldn't enter this case |
| 303 | { |
| 304 | write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf)); |
| 305 | write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4))); |
| 306 | } |
| 307 | else |
| 308 | { |
| 309 | int idx; |
| 310 | int ByteCnt = nDataBufBitCnt / 8; |
| 311 | //printk("%d\n",nDataBufBitCnt); |
| 312 | if ((nDataBufBitCnt % 8) != 0) |
| 313 | panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n", |
| 314 | nDataBufBitCnt); |
| 315 | |
| 316 | if (nDataBufBitCnt > 64) |
| 317 | panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n", |
| 318 | nDataBufBitCnt); |
| 319 | |
| 320 | for(idx = 0; idx < ByteCnt; idx++) |
| 321 | { |
| 322 | write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx)); |
| 323 | } |
| 324 | } |
| 325 | } |
| 326 | else //read |
| 327 | { |
| 328 | if(bSI) |
| 329 | { |
| 330 | // SI - reg274[3:0] : RF register's Address |
| 331 | write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) ); |
| 332 | } |
| 333 | else |
| 334 | { |
| 335 | // PI - reg274[15:12] : RF register's Address |
| 336 | write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12); |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | // Set up command: WE or RE. |
| 341 | if(bWrite) |
| 342 | { |
| 343 | write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE); |
| 344 | } |
| 345 | else |
| 346 | { |
| 347 | write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE); |
| 348 | } |
| 349 | |
| 350 | // Check if DONE is set. |
| 351 | for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) |
| 352 | { |
| 353 | u1bTmp = read_nic_byte(dev, SW_3W_CMD1); |
| 354 | if( (u1bTmp & SW_3W_CMD1_DONE) != 0 ) |
| 355 | { |
| 356 | break; |
| 357 | } |
| 358 | udelay(10); |
| 359 | } |
| 360 | |
| 361 | write_nic_byte(dev, SW_3W_CMD1, 0); |
| 362 | |
| 363 | // Read back data for read operation. |
| 364 | if(bWrite == 0) |
| 365 | { |
| 366 | if(bSI) |
| 367 | { |
| 368 | //Serial Interface : reg363_362[11:0] |
| 369 | *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ; |
| 370 | } |
| 371 | else |
| 372 | { |
| 373 | //Parallel Interface : reg361_360[11:0] |
| 374 | *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ); |
| 375 | } |
| 376 | |
| 377 | *((u16*)pDataBuf) &= 0x0FFF; |
| 378 | } |
| 379 | |
| 380 | }while(0); |
| 381 | |
| 382 | return bResult; |
| 383 | } |
| 384 | |
| 385 | void |
| 386 | RF_WriteReg(struct net_device *dev, u8 offset, u32 data) |
| 387 | { |
| 388 | u32 data2Write; |
| 389 | u8 len; |
| 390 | |
| 391 | /* Pure HW 3-wire. */ |
| 392 | data2Write = (data << 4) | (u32)(offset & 0x0f); |
| 393 | len = 16; |
| 394 | |
| 395 | HwHSSIThreeWire(dev, (u8 *)(&data2Write), len, 1, 1); |
| 396 | } |
| 397 | |
| 398 | u32 RF_ReadReg(struct net_device *dev, u8 offset) |
| 399 | { |
| 400 | u32 data2Write; |
| 401 | u8 wlen; |
| 402 | u32 dataRead; |
| 403 | |
| 404 | data2Write = ((u32)(offset & 0x0f)); |
| 405 | wlen = 16; |
| 406 | HwHSSIThreeWire(dev, (u8 *)(&data2Write), wlen, 1, 0); |
| 407 | dataRead = data2Write; |
| 408 | |
| 409 | return dataRead; |
| 410 | } |
| 411 | |
| 412 | |
| 413 | // by Owen on 04/07/14 for writing BB register successfully |
| 414 | void |
| 415 | WriteBBPortUchar( |
| 416 | struct net_device *dev, |
| 417 | u32 Data |
| 418 | ) |
| 419 | { |
| 420 | //u8 TimeoutCounter; |
| 421 | u8 RegisterContent; |
| 422 | u8 UCharData; |
| 423 | |
| 424 | UCharData = (u8)((Data & 0x0000ff00) >> 8); |
| 425 | PlatformIOWrite4Byte(dev, PhyAddr, Data); |
| 426 | //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--) |
| 427 | { |
| 428 | PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f); |
| 429 | RegisterContent = PlatformIORead1Byte(dev, PhyDataR); |
| 430 | //if(UCharData == RegisterContent) |
| 431 | // break; |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | u8 |
| 436 | ReadBBPortUchar( |
| 437 | struct net_device *dev, |
| 438 | u32 addr |
| 439 | ) |
| 440 | { |
| 441 | //u8 TimeoutCounter; |
| 442 | u8 RegisterContent; |
| 443 | |
| 444 | PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f); |
| 445 | RegisterContent = PlatformIORead1Byte(dev, PhyDataR); |
| 446 | |
| 447 | return RegisterContent; |
| 448 | } |
| 449 | //{by amy 080312 |
| 450 | // |
| 451 | // Description: |
| 452 | // Perform Antenna settings with antenna diversity on 87SE. |
| 453 | // Created by Roger, 2008.01.25. |
| 454 | // |
| 455 | bool |
| 456 | SetAntennaConfig87SE( |
| 457 | struct net_device *dev, |
| 458 | u8 DefaultAnt, // 0: Main, 1: Aux. |
| 459 | bool bAntDiversity // 1:Enable, 0: Disable. |
| 460 | ) |
| 461 | { |
| 462 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 463 | bool bAntennaSwitched = true; |
| 464 | |
| 465 | //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity); |
| 466 | |
| 467 | // Threshold for antenna diversity. |
| 468 | write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09 |
| 469 | |
| 470 | if( bAntDiversity ) // Enable Antenna Diversity. |
| 471 | { |
| 472 | if( DefaultAnt == 1 ) // aux antenna |
| 473 | { |
| 474 | // Mac register, aux antenna |
| 475 | write_nic_byte(dev, ANTSEL, 0x00); |
| 476 | |
| 477 | // Config CCK RX antenna. |
| 478 | write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb |
| 479 | write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7 |
| 480 | |
| 481 | // Config OFDM RX antenna. |
| 482 | write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54 |
| 483 | write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2 |
| 484 | } |
| 485 | else // use main antenna |
| 486 | { |
| 487 | // Mac register, main antenna |
| 488 | write_nic_byte(dev, ANTSEL, 0x03); |
| 489 | //base band |
| 490 | // Config CCK RX antenna. |
| 491 | write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b |
| 492 | write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7 |
| 493 | |
| 494 | // Config OFDM RX antenna. |
| 495 | write_phy_ofdm(dev, 0x0d, 0x5c); // Reg0d : 5c |
| 496 | write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2 |
| 497 | } |
| 498 | } |
| 499 | else // Disable Antenna Diversity. |
| 500 | { |
| 501 | if( DefaultAnt == 1 ) // aux Antenna |
| 502 | { |
| 503 | // Mac register, aux antenna |
| 504 | write_nic_byte(dev, ANTSEL, 0x00); |
| 505 | |
| 506 | // Config CCK RX antenna. |
| 507 | write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb |
| 508 | write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47 |
| 509 | |
| 510 | // Config OFDM RX antenna. |
| 511 | write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54 |
| 512 | write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32 |
| 513 | } |
| 514 | else // main Antenna |
| 515 | { |
| 516 | // Mac register, main antenna |
| 517 | write_nic_byte(dev, ANTSEL, 0x03); |
| 518 | |
| 519 | // Config CCK RX antenna. |
| 520 | write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b |
| 521 | write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47 |
| 522 | |
| 523 | // Config OFDM RX antenna. |
| 524 | write_phy_ofdm(dev, 0x0D, 0x5c); // Reg0d : 5c |
| 525 | write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32 |
| 526 | } |
| 527 | } |
| 528 | priv->CurrAntennaIndex = DefaultAnt; // Update default settings. |
| 529 | return bAntennaSwitched; |
| 530 | } |
| 531 | //by amy 080312 |
| 532 | /*--------------------------------------------------------------- |
| 533 | * Hardware Initialization. |
| 534 | * the code is ported from Windows source code |
| 535 | ----------------------------------------------------------------*/ |
| 536 | |
| 537 | void |
| 538 | ZEBRA_Config_85BASIC_HardCode( |
| 539 | struct net_device *dev |
| 540 | ) |
| 541 | { |
| 542 | |
| 543 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 544 | u32 i; |
| 545 | u32 addr,data; |
| 546 | u32 u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24; |
| 547 | u8 u1b24E; |
| 548 | int d_cut = 0; |
| 549 | |
| 550 | |
| 551 | //============================================================================= |
| 552 | // 87S_PCIE :: RADIOCFG.TXT |
| 553 | //============================================================================= |
| 554 | |
| 555 | |
| 556 | // Page1 : reg16-reg30 |
| 557 | RF_WriteReg(dev, 0x00, 0x013f); mdelay(1); // switch to page1 |
| 558 | u4bRF23= RF_ReadReg(dev, 0x08); mdelay(1); |
| 559 | u4bRF24= RF_ReadReg(dev, 0x09); mdelay(1); |
| 560 | |
| 561 | if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) { |
| 562 | d_cut = 1; |
| 563 | printk(KERN_INFO "rtl8187se: card type changed from C- to D-cut\n"); |
| 564 | } |
| 565 | |
| 566 | // Page0 : reg0-reg15 |
| 567 | |
| 568 | RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);// 1 |
| 569 | |
| 570 | RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1); |
| 571 | |
| 572 | RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);// 2 |
| 573 | |
| 574 | RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);// 3 |
| 575 | |
| 576 | RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); |
| 577 | RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1); |
| 578 | RF_WriteReg(dev, 0x06, 0x0ae6); mdelay(1); |
| 579 | RF_WriteReg(dev, 0x07, 0x00ca); mdelay(1); |
| 580 | RF_WriteReg(dev, 0x08, 0x0e1c); mdelay(1); |
| 581 | RF_WriteReg(dev, 0x09, 0x02f0); mdelay(1); |
| 582 | RF_WriteReg(dev, 0x0a, 0x09d0); mdelay(1); |
| 583 | RF_WriteReg(dev, 0x0b, 0x01ba); mdelay(1); |
| 584 | RF_WriteReg(dev, 0x0c, 0x0640); mdelay(1); |
| 585 | RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); |
| 586 | RF_WriteReg(dev, 0x0e, 0x0020); mdelay(1); |
| 587 | RF_WriteReg(dev, 0x0f, 0x0990); mdelay(1); |
| 588 | |
| 589 | |
| 590 | // Page1 : reg16-reg30 |
| 591 | RF_WriteReg(dev, 0x00, 0x013f); mdelay(1); |
| 592 | |
| 593 | RF_WriteReg(dev, 0x03, 0x0806); mdelay(1); |
| 594 | |
| 595 | RF_WriteReg(dev, 0x04, 0x03a7); mdelay(1); |
| 596 | RF_WriteReg(dev, 0x05, 0x059b); mdelay(1); |
| 597 | RF_WriteReg(dev, 0x06, 0x0081); mdelay(1); |
| 598 | |
| 599 | |
| 600 | RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1); |
| 601 | // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl. |
| 602 | RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1); |
| 603 | RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1); |
| 604 | |
| 605 | if (d_cut) { |
| 606 | RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1); |
| 607 | RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); |
| 608 | RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1); // RX LO buffer |
| 609 | } else { |
| 610 | RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1); |
| 611 | RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); |
| 612 | RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1); // RX LO buffer |
| 613 | } |
| 614 | |
| 615 | RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); |
| 616 | |
| 617 | RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1);// 6 |
| 618 | |
| 619 | RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1); |
| 620 | RF_WriteReg(dev, 0x04, 0x0e50); mdelay(1); |
| 621 | for(i=0;i<=36;i++) |
| 622 | { |
| 623 | RF_WriteReg(dev, 0x01, i); mdelay(1); |
| 624 | RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1); |
| 625 | } |
| 626 | |
| 627 | RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /// 203, 343 |
| 628 | RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); // 400 |
| 629 | |
| 630 | RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30, and HSSI disable 137 |
| 631 | mdelay(10); // Deay 10 ms. //0xfd |
| 632 | |
| 633 | RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); // Z4 synthesizer loop filter setting, 392 |
| 634 | mdelay(10); // Deay 10 ms. //0xfd |
| 635 | |
| 636 | RF_WriteReg(dev, 0x00, 0x0037); mdelay(1); // switch to reg0-reg15, and HSSI disable |
| 637 | mdelay(10); // Deay 10 ms. //0xfd |
| 638 | |
| 639 | RF_WriteReg(dev, 0x04, 0x0160); mdelay(1); // CBC on, Tx Rx disable, High gain |
| 640 | mdelay(10); // Deay 10 ms. //0xfd |
| 641 | |
| 642 | RF_WriteReg(dev, 0x07, 0x0080); mdelay(1); // Z4 setted channel 1 |
| 643 | mdelay(10); // Deay 10 ms. //0xfd |
| 644 | |
| 645 | RF_WriteReg(dev, 0x02, 0x088D); mdelay(1); // LC calibration |
| 646 | mdelay(200); // Deay 200 ms. //0xfd |
| 647 | mdelay(10); // Deay 10 ms. //0xfd |
| 648 | mdelay(10); // Deay 10 ms. //0xfd |
| 649 | |
| 650 | RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30 137, and HSSI disable 137 |
| 651 | mdelay(10); // Deay 10 ms. //0xfd |
| 652 | |
| 653 | RF_WriteReg(dev, 0x07, 0x0000); mdelay(1); |
| 654 | RF_WriteReg(dev, 0x07, 0x0180); mdelay(1); |
| 655 | RF_WriteReg(dev, 0x07, 0x0220); mdelay(1); |
| 656 | RF_WriteReg(dev, 0x07, 0x03E0); mdelay(1); |
| 657 | |
| 658 | // DAC calibration off 20070702 |
| 659 | RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1); |
| 660 | RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1); |
| 661 | //{by amy 080312 |
| 662 | // For crystal calibration, added by Roger, 2007.12.11. |
| 663 | if( priv->bXtalCalibration ) // reg 30. |
| 664 | { // enable crystal calibration. |
| 665 | // RF Reg[30], (1)Xin:[12:9], Xout:[8:5], addr[4:0]. |
| 666 | // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0 |
| 667 | // (3)RF signal on/off when calibration[13], default: on, set BIT13=0. |
| 668 | // So we should minus 4 BITs offset. |
| 669 | RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9); mdelay(1); |
| 670 | printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n", |
| 671 | (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9); |
| 672 | } |
| 673 | else |
| 674 | { // using default value. Xin=6, Xout=6. |
| 675 | RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); |
| 676 | } |
| 677 | //by amy 080312 |
| 678 | |
| 679 | RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); // switch to reg0-reg15, and HSSI enable |
| 680 | RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); // Rx BB start calibration, 00c//+edward |
| 681 | RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); // temperature meter off |
| 682 | RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); // Rx mode |
| 683 | mdelay(10); // Deay 10 ms. //0xfe |
| 684 | mdelay(10); // Deay 10 ms. //0xfe |
| 685 | mdelay(10); // Deay 10 ms. //0xfe |
| 686 | RF_WriteReg(dev, 0x00, 0x0197); mdelay(1); // Rx mode//+edward |
| 687 | RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1); // Rx mode//+edward |
| 688 | RF_WriteReg(dev, 0x00, 0x009f); mdelay(1); // Rx mode//+edward |
| 689 | |
| 690 | RF_WriteReg(dev, 0x01, 0x0000); mdelay(1); // Rx mode//+edward |
| 691 | RF_WriteReg(dev, 0x02, 0x0000); mdelay(1); // Rx mode//+edward |
| 692 | //power save parameters. |
| 693 | u1b24E = read_nic_byte(dev, 0x24E); |
| 694 | write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6)))); |
| 695 | |
| 696 | //============================================================================= |
| 697 | |
| 698 | //============================================================================= |
| 699 | // CCKCONF.TXT |
| 700 | //============================================================================= |
| 701 | |
| 702 | /* [POWER SAVE] Power Saving Parameters by jong. 2007-11-27 |
| 703 | CCK reg0x00[7]=1'b1 :power saving for TX (default) |
| 704 | CCK reg0x00[6]=1'b1: power saving for RX (default) |
| 705 | CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation. |
| 706 | CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1 |
| 707 | CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0 |
| 708 | */ |
| 709 | |
| 710 | write_phy_cck(dev,0x00,0xc8); |
| 711 | write_phy_cck(dev,0x06,0x1c); |
| 712 | write_phy_cck(dev,0x10,0x78); |
| 713 | write_phy_cck(dev,0x2e,0xd0); |
| 714 | write_phy_cck(dev,0x2f,0x06); |
| 715 | write_phy_cck(dev,0x01,0x46); |
| 716 | |
| 717 | // power control |
| 718 | write_nic_byte(dev, CCK_TXAGC, 0x10); |
| 719 | write_nic_byte(dev, OFDM_TXAGC, 0x1B); |
| 720 | write_nic_byte(dev, ANTSEL, 0x03); |
| 721 | |
| 722 | |
| 723 | |
| 724 | //============================================================================= |
| 725 | // AGC.txt |
| 726 | //============================================================================= |
| 727 | |
| 728 | write_phy_ofdm(dev, 0x00, 0x12); |
| 729 | |
| 730 | for (i=0; i<128; i++) |
| 731 | { |
| 732 | |
| 733 | data = ZEBRA_AGC[i+1]; |
| 734 | data = data << 8; |
| 735 | data = data | 0x0000008F; |
| 736 | |
| 737 | addr = i + 0x80; //enable writing AGC table |
| 738 | addr = addr << 8; |
| 739 | addr = addr | 0x0000008E; |
| 740 | |
| 741 | WriteBBPortUchar(dev, data); |
| 742 | WriteBBPortUchar(dev, addr); |
| 743 | WriteBBPortUchar(dev, 0x0000008E); |
| 744 | } |
| 745 | |
| 746 | PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080); // Annie, 2006-05-05 |
| 747 | |
| 748 | //============================================================================= |
| 749 | |
| 750 | //============================================================================= |
| 751 | // OFDMCONF.TXT |
| 752 | //============================================================================= |
| 753 | |
| 754 | for(i=0; i<60; i++) |
| 755 | { |
| 756 | u4bRegOffset=i; |
| 757 | u4bRegValue=OFDM_CONFIG[i]; |
| 758 | |
| 759 | WriteBBPortUchar(dev, |
| 760 | (0x00000080 | |
| 761 | (u4bRegOffset & 0x7f) | |
| 762 | ((u4bRegValue & 0xff) << 8))); |
| 763 | } |
| 764 | |
| 765 | //============================================================================= |
| 766 | //by amy for antenna |
| 767 | //============================================================================= |
| 768 | //{by amy 080312 |
| 769 | // Config Sw/Hw Combinational Antenna Diversity. Added by Roger, 2008.02.26. |
| 770 | SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity); |
| 771 | //by amy 080312} |
| 772 | //by amy for antenna |
| 773 | } |
| 774 | |
| 775 | |
| 776 | void |
| 777 | UpdateInitialGain( |
| 778 | struct net_device *dev |
| 779 | ) |
| 780 | { |
| 781 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 782 | |
| 783 | //lzm add 080826 |
| 784 | if(priv->eRFPowerState != eRfOn) |
| 785 | { |
| 786 | //Don't access BB/RF under disable PLL situation. |
| 787 | //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n")); |
| 788 | // Back to the original state |
| 789 | priv->InitialGain= priv->InitialGainBackUp; |
| 790 | return; |
| 791 | } |
| 792 | |
| 793 | switch (priv->InitialGain) { |
| 794 | case 1: /* m861dBm */ |
| 795 | write_phy_ofdm(dev, 0x17, 0x26); mdelay(1); |
| 796 | write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); |
| 797 | write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1); |
| 798 | break; |
| 799 | |
| 800 | case 2: /* m862dBm */ |
| 801 | write_phy_ofdm(dev, 0x17, 0x36); mdelay(1); |
| 802 | write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); |
| 803 | write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1); |
| 804 | break; |
| 805 | |
| 806 | case 3: /* m863dBm */ |
| 807 | write_phy_ofdm(dev, 0x17, 0x36); mdelay(1); |
| 808 | write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); |
| 809 | write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1); |
| 810 | break; |
| 811 | |
| 812 | case 4: /* m864dBm */ |
| 813 | write_phy_ofdm(dev, 0x17, 0x46); mdelay(1); |
| 814 | write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); |
| 815 | write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1); |
| 816 | break; |
| 817 | |
| 818 | case 5: /* m82dBm */ |
| 819 | write_phy_ofdm(dev, 0x17, 0x46); mdelay(1); |
| 820 | write_phy_ofdm(dev, 0x24, 0x96); mdelay(1); |
| 821 | write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1); |
| 822 | break; |
| 823 | |
| 824 | case 6: /* m78dBm */ |
| 825 | write_phy_ofdm(dev, 0x17, 0x56); mdelay(1); |
| 826 | write_phy_ofdm(dev, 0x24, 0x96); mdelay(1); |
| 827 | write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1); |
| 828 | break; |
| 829 | |
| 830 | case 7: /* m74dBm */ |
| 831 | write_phy_ofdm(dev, 0x17, 0x56); mdelay(1); |
| 832 | write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1); |
| 833 | write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1); |
| 834 | break; |
| 835 | |
| 836 | case 8: |
| 837 | write_phy_ofdm(dev, 0x17, 0x66); mdelay(1); |
| 838 | write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1); |
| 839 | write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1); |
| 840 | break; |
| 841 | |
| 842 | default: /* MP */ |
| 843 | write_phy_ofdm(dev, 0x17, 0x26); mdelay(1); |
| 844 | write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); |
| 845 | write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1); |
| 846 | break; |
| 847 | } |
| 848 | } |
| 849 | // |
| 850 | // Description: |
| 851 | // Tx Power tracking mechanism routine on 87SE. |
| 852 | // Created by Roger, 2007.12.11. |
| 853 | // |
| 854 | void |
| 855 | InitTxPwrTracking87SE( |
| 856 | struct net_device *dev |
| 857 | ) |
| 858 | { |
| 859 | u32 u4bRfReg; |
| 860 | |
| 861 | u4bRfReg = RF_ReadReg(dev, 0x02); |
| 862 | |
| 863 | // Enable Thermal meter indication. |
| 864 | RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1); |
| 865 | } |
| 866 | |
| 867 | void |
| 868 | PhyConfig8185( |
| 869 | struct net_device *dev |
| 870 | ) |
| 871 | { |
| 872 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 873 | write_nic_dword(dev, RCR, priv->ReceiveConfig); |
| 874 | priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03; |
| 875 | /* RF config */ |
| 876 | ZEBRA_Config_85BASIC_HardCode(dev); |
| 877 | //{by amy 080312 |
| 878 | // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06. |
| 879 | if(priv->bDigMechanism) |
| 880 | { |
| 881 | if(priv->InitialGain == 0) |
| 882 | priv->InitialGain = 4; |
| 883 | } |
| 884 | |
| 885 | // |
| 886 | // Enable thermal meter indication to implement TxPower tracking on 87SE. |
| 887 | // We initialize thermal meter here to avoid unsuccessful configuration. |
| 888 | // Added by Roger, 2007.12.11. |
| 889 | // |
| 890 | if(priv->bTxPowerTrack) |
| 891 | InitTxPwrTracking87SE(dev); |
| 892 | |
| 893 | //by amy 080312} |
| 894 | priv->InitialGainBackUp= priv->InitialGain; |
| 895 | UpdateInitialGain(dev); |
| 896 | |
| 897 | return; |
| 898 | } |
| 899 | |
| 900 | void |
| 901 | HwConfigureRTL8185( |
| 902 | struct net_device *dev |
| 903 | ) |
| 904 | { |
| 905 | //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control. |
| 906 | u8 bUNIVERSAL_CONTROL_RL = 0; |
| 907 | u8 bUNIVERSAL_CONTROL_AGC = 1; |
| 908 | u8 bUNIVERSAL_CONTROL_ANT = 1; |
| 909 | u8 bAUTO_RATE_FALLBACK_CTL = 1; |
| 910 | u8 val8; |
| 911 | write_nic_word(dev, BRSR, 0x0fff); |
| 912 | // Retry limit |
| 913 | val8 = read_nic_byte(dev, CW_CONF); |
| 914 | |
| 915 | if(bUNIVERSAL_CONTROL_RL) |
| 916 | val8 = val8 & 0xfd; |
| 917 | else |
| 918 | val8 = val8 | 0x02; |
| 919 | |
| 920 | write_nic_byte(dev, CW_CONF, val8); |
| 921 | |
| 922 | // Tx AGC |
| 923 | val8 = read_nic_byte(dev, TXAGC_CTL); |
| 924 | if(bUNIVERSAL_CONTROL_AGC) |
| 925 | { |
| 926 | write_nic_byte(dev, CCK_TXAGC, 128); |
| 927 | write_nic_byte(dev, OFDM_TXAGC, 128); |
| 928 | val8 = val8 & 0xfe; |
| 929 | } |
| 930 | else |
| 931 | { |
| 932 | val8 = val8 | 0x01 ; |
| 933 | } |
| 934 | |
| 935 | |
| 936 | write_nic_byte(dev, TXAGC_CTL, val8); |
| 937 | |
| 938 | // Tx Antenna including Feedback control |
| 939 | val8 = read_nic_byte(dev, TXAGC_CTL ); |
| 940 | |
| 941 | if(bUNIVERSAL_CONTROL_ANT) |
| 942 | { |
| 943 | write_nic_byte(dev, ANTSEL, 0x00); |
| 944 | val8 = val8 & 0xfd; |
| 945 | } |
| 946 | else |
| 947 | { |
| 948 | val8 = val8 & (val8|0x02); //xiong-2006-11-15 |
| 949 | } |
| 950 | |
| 951 | write_nic_byte(dev, TXAGC_CTL, val8); |
| 952 | |
| 953 | // Auto Rate fallback control |
| 954 | val8 = read_nic_byte(dev, RATE_FALLBACK); |
| 955 | val8 &= 0x7c; |
| 956 | if( bAUTO_RATE_FALLBACK_CTL ) |
| 957 | { |
| 958 | val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1; |
| 959 | |
| 960 | // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting. |
| 961 | PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps. |
| 962 | } |
| 963 | write_nic_byte(dev, RATE_FALLBACK, val8); |
| 964 | } |
| 965 | |
| 966 | static void |
| 967 | MacConfig_85BASIC_HardCode( |
| 968 | struct net_device *dev) |
| 969 | { |
| 970 | //============================================================================ |
| 971 | // MACREG.TXT |
| 972 | //============================================================================ |
| 973 | int nLinesRead = 0; |
| 974 | |
| 975 | u32 u4bRegOffset, u4bRegValue,u4bPageIndex = 0; |
| 976 | int i; |
| 977 | |
| 978 | nLinesRead=sizeof(MAC_REG_TABLE)/2; |
| 979 | |
| 980 | for(i = 0; i < nLinesRead; i++) //nLinesRead=101 |
| 981 | { |
| 982 | u4bRegOffset=MAC_REG_TABLE[i][0]; |
| 983 | u4bRegValue=MAC_REG_TABLE[i][1]; |
| 984 | |
| 985 | if(u4bRegOffset == 0x5e) |
| 986 | { |
| 987 | u4bPageIndex = u4bRegValue; |
| 988 | } |
| 989 | else |
| 990 | { |
| 991 | u4bRegOffset |= (u4bPageIndex << 8); |
| 992 | } |
| 993 | write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue); |
| 994 | } |
| 995 | //============================================================================ |
| 996 | } |
| 997 | |
| 998 | static void |
| 999 | MacConfig_85BASIC( |
| 1000 | struct net_device *dev) |
| 1001 | { |
| 1002 | |
| 1003 | u8 u1DA; |
| 1004 | MacConfig_85BASIC_HardCode(dev); |
| 1005 | |
| 1006 | //============================================================================ |
| 1007 | |
| 1008 | // Follow TID_AC_MAP of WMac. |
| 1009 | write_nic_word(dev, TID_AC_MAP, 0xfa50); |
| 1010 | |
| 1011 | // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko. |
| 1012 | write_nic_word(dev, IntMig, 0x0000); |
| 1013 | |
| 1014 | // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10. |
| 1015 | PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000); |
| 1016 | PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000); |
| 1017 | PlatformIOWrite1Byte(dev, 0x1F8, 0x00); |
| 1018 | |
| 1019 | // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko. |
| 1020 | // power save parameter based on "87SE power save parameters 20071127.doc", as follow. |
| 1021 | |
| 1022 | //Enable DA10 TX power saving |
| 1023 | u1DA = read_nic_byte(dev, PHYPR); |
| 1024 | write_nic_byte(dev, PHYPR, (u1DA | BIT2) ); |
| 1025 | |
| 1026 | //POWER: |
| 1027 | write_nic_word(dev, 0x360, 0x1000); |
| 1028 | write_nic_word(dev, 0x362, 0x1000); |
| 1029 | |
| 1030 | // AFE. |
| 1031 | write_nic_word(dev, 0x370, 0x0560); |
| 1032 | write_nic_word(dev, 0x372, 0x0560); |
| 1033 | write_nic_word(dev, 0x374, 0x0DA4); |
| 1034 | write_nic_word(dev, 0x376, 0x0DA4); |
| 1035 | write_nic_word(dev, 0x378, 0x0560); |
| 1036 | write_nic_word(dev, 0x37A, 0x0560); |
| 1037 | write_nic_word(dev, 0x37C, 0x00EC); |
| 1038 | write_nic_word(dev, 0x37E, 0x00EC);//+edward |
| 1039 | write_nic_byte(dev, 0x24E,0x01); |
| 1040 | } |
| 1041 | |
| 1042 | u8 |
| 1043 | GetSupportedWirelessMode8185( |
| 1044 | struct net_device *dev |
| 1045 | ) |
| 1046 | { |
| 1047 | u8 btSupportedWirelessMode = 0; |
| 1048 | |
| 1049 | btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G); |
| 1050 | return btSupportedWirelessMode; |
| 1051 | } |
| 1052 | |
| 1053 | void |
| 1054 | ActUpdateChannelAccessSetting( |
| 1055 | struct net_device *dev, |
| 1056 | WIRELESS_MODE WirelessMode, |
| 1057 | PCHANNEL_ACCESS_SETTING ChnlAccessSetting |
| 1058 | ) |
| 1059 | { |
| 1060 | struct r8180_priv *priv = ieee80211_priv(dev); |
| 1061 | struct ieee80211_device *ieee = priv->ieee80211; |
| 1062 | AC_CODING eACI; |
| 1063 | AC_PARAM AcParam; |
| 1064 | u8 bFollowLegacySetting = 0; |
| 1065 | u8 u1bAIFS; |
| 1066 | |
| 1067 | // |
| 1068 | // <RJ_TODO_8185B> |
| 1069 | // TODO: We still don't know how to set up these registers, just follow WMAC to |
| 1070 | // verify 8185B FPAG. |
| 1071 | // |
| 1072 | // <RJ_TODO_8185B> |
| 1073 | // Jong said CWmin/CWmax register are not functional in 8185B, |
| 1074 | // so we shall fill channel access realted register into AC parameter registers, |
| 1075 | // even in nQBss. |
| 1076 | // |
| 1077 | ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08. |
| 1078 | ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko. |
| 1079 | ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko. |
| 1080 | ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. |
| 1081 | ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko. |
| 1082 | ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko. |
| 1083 | |
| 1084 | write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer); |
| 1085 | write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29. |
| 1086 | |
| 1087 | u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer ); |
| 1088 | |
| 1089 | write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer); |
| 1090 | |
| 1091 | write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. |
| 1092 | |
| 1093 | { // Legacy 802.11. |
| 1094 | bFollowLegacySetting = 1; |
| 1095 | |
| 1096 | } |
| 1097 | |
| 1098 | // this setting is copied from rtl8187B. xiong-2006-11-13 |
| 1099 | if(bFollowLegacySetting) |
| 1100 | { |
| 1101 | |
| 1102 | |
| 1103 | // |
| 1104 | // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter. |
| 1105 | // 2005.12.01, by rcnjko. |
| 1106 | // |
| 1107 | AcParam.longData = 0; |
| 1108 | AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS. |
| 1109 | AcParam.f.AciAifsn.f.ACM = 0; |
| 1110 | AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin. |
| 1111 | AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax. |
| 1112 | AcParam.f.TXOPLimit = 0; |
| 1113 | |
| 1114 | //lzm reserved 080826 |
| 1115 | // For turbo mode setting. port from 87B by Isaiah 2008-08-01 |
| 1116 | if( ieee->current_network.Turbo_Enable == 1 ) |
| 1117 | AcParam.f.TXOPLimit = 0x01FF; |
| 1118 | // For 87SE with Intel 4965 Ad-Hoc mode have poor throughput (19MB) |
| 1119 | if (ieee->iw_mode == IW_MODE_ADHOC) |
| 1120 | AcParam.f.TXOPLimit = 0x0020; |
| 1121 | |
| 1122 | for(eACI = 0; eACI < AC_MAX; eACI++) |
| 1123 | { |
| 1124 | AcParam.f.AciAifsn.f.ACI = (u8)eACI; |
| 1125 | { |
| 1126 | PAC_PARAM pAcParam = (PAC_PARAM)(&AcParam); |
| 1127 | AC_CODING eACI; |
| 1128 | u8 u1bAIFS; |
| 1129 | u32 u4bAcParam; |
| 1130 | |
| 1131 | // Retrive paramters to udpate. |
| 1132 | eACI = pAcParam->f.AciAifsn.f.ACI; |
| 1133 | u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime; |
| 1134 | u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) | |
| 1135 | (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) | |
| 1136 | (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) | |
| 1137 | (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET)); |
| 1138 | |
| 1139 | switch(eACI) |
| 1140 | { |
| 1141 | case AC1_BK: |
| 1142 | //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); |
| 1143 | break; |
| 1144 | |
| 1145 | case AC0_BE: |
| 1146 | //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam); |
| 1147 | break; |
| 1148 | |
| 1149 | case AC2_VI: |
| 1150 | //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam); |
| 1151 | break; |
| 1152 | |
| 1153 | case AC3_VO: |
| 1154 | //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam); |
| 1155 | break; |
| 1156 | |
| 1157 | default: |
| 1158 | DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI); |
| 1159 | break; |
| 1160 | } |
| 1161 | |
| 1162 | // Cehck ACM bit. |
| 1163 | // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. |
| 1164 | { |
| 1165 | PACI_AIFSN pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn); |
| 1166 | AC_CODING eACI = pAciAifsn->f.ACI; |
| 1167 | |
| 1168 | //modified Joseph |
| 1169 | //for 8187B AsynIORead issue |
| 1170 | u8 AcmCtrl = 0; |
| 1171 | if( pAciAifsn->f.ACM ) |
| 1172 | { // ACM bit is 1. |
| 1173 | switch(eACI) |
| 1174 | { |
| 1175 | case AC0_BE: |
| 1176 | AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN); // or 0x21 |
| 1177 | break; |
| 1178 | |
| 1179 | case AC2_VI: |
| 1180 | AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN); // or 0x42 |
| 1181 | break; |
| 1182 | |
| 1183 | case AC3_VO: |
| 1184 | AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN); // or 0x84 |
| 1185 | break; |
| 1186 | |
| 1187 | default: |
| 1188 | DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI ); |
| 1189 | break; |
| 1190 | } |
| 1191 | } |
| 1192 | else |
| 1193 | { // ACM bit is 0. |
| 1194 | switch(eACI) |
| 1195 | { |
| 1196 | case AC0_BE: |
| 1197 | AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xDE |
| 1198 | break; |
| 1199 | |
| 1200 | case AC2_VI: |
| 1201 | AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xBD |
| 1202 | break; |
| 1203 | |
| 1204 | case AC3_VO: |
| 1205 | AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0x7B |
| 1206 | break; |
| 1207 | |
| 1208 | default: |
| 1209 | break; |
| 1210 | } |
| 1211 | } |
| 1212 | write_nic_byte(dev, ACM_CONTROL, 0); |
| 1213 | } |
| 1214 | } |
| 1215 | } |
| 1216 | } |
| 1217 | } |
| 1218 | |
| 1219 | void |
| 1220 | ActSetWirelessMode8185( |
| 1221 | struct net_device *dev, |
| 1222 | u8 btWirelessMode |
| 1223 | ) |
| 1224 | { |
| 1225 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1226 | struct ieee80211_device *ieee = priv->ieee80211; |
| 1227 | u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev); |
| 1228 | |
| 1229 | if( (btWirelessMode & btSupportedWirelessMode) == 0 ) |
| 1230 | { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko. |
| 1231 | DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n", |
| 1232 | btWirelessMode, btSupportedWirelessMode); |
| 1233 | return; |
| 1234 | } |
| 1235 | |
| 1236 | // 1. Assign wireless mode to swtich if necessary. |
| 1237 | if (btWirelessMode == WIRELESS_MODE_AUTO) |
| 1238 | { |
| 1239 | if((btSupportedWirelessMode & WIRELESS_MODE_A)) |
| 1240 | { |
| 1241 | btWirelessMode = WIRELESS_MODE_A; |
| 1242 | } |
| 1243 | else if((btSupportedWirelessMode & WIRELESS_MODE_G)) |
| 1244 | { |
| 1245 | btWirelessMode = WIRELESS_MODE_G; |
| 1246 | } |
| 1247 | else if((btSupportedWirelessMode & WIRELESS_MODE_B)) |
| 1248 | { |
| 1249 | btWirelessMode = WIRELESS_MODE_B; |
| 1250 | } |
| 1251 | else |
| 1252 | { |
| 1253 | DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n", |
| 1254 | btSupportedWirelessMode); |
| 1255 | btWirelessMode = WIRELESS_MODE_B; |
| 1256 | } |
| 1257 | } |
| 1258 | |
| 1259 | /* 2. Swtich band: RF or BB specific actions, |
| 1260 | * for example, refresh tables in omc8255, or change initial gain if necessary. |
| 1261 | * Nothing to do for Zebra to switch band. |
| 1262 | * Update current wireless mode if we swtich to specified band successfully. */ |
| 1263 | ieee->mode = (WIRELESS_MODE)btWirelessMode; |
| 1264 | |
| 1265 | // 3. Change related setting. |
| 1266 | if( ieee->mode == WIRELESS_MODE_A ){ |
| 1267 | DMESG("WIRELESS_MODE_A\n"); |
| 1268 | } |
| 1269 | else if( ieee->mode == WIRELESS_MODE_B ){ |
| 1270 | DMESG("WIRELESS_MODE_B\n"); |
| 1271 | } |
| 1272 | else if( ieee->mode == WIRELESS_MODE_G ){ |
| 1273 | DMESG("WIRELESS_MODE_G\n"); |
| 1274 | } |
| 1275 | ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting); |
| 1276 | } |
| 1277 | |
| 1278 | void rtl8185b_irq_enable(struct net_device *dev) |
| 1279 | { |
| 1280 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1281 | |
| 1282 | priv->irq_enabled = 1; |
| 1283 | write_nic_dword(dev, IMR, priv->IntrMask); |
| 1284 | } |
| 1285 | //by amy for power save |
| 1286 | void |
| 1287 | DrvIFIndicateDisassociation( |
| 1288 | struct net_device *dev, |
| 1289 | u16 reason |
| 1290 | ) |
| 1291 | { |
| 1292 | // nothing is needed after disassociation request. |
| 1293 | } |
| 1294 | void |
| 1295 | MgntDisconnectIBSS( |
| 1296 | struct net_device *dev |
| 1297 | ) |
| 1298 | { |
| 1299 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1300 | u8 i; |
| 1301 | |
| 1302 | DrvIFIndicateDisassociation(dev, unspec_reason); |
| 1303 | for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x55; |
| 1304 | |
| 1305 | priv->ieee80211->state = IEEE80211_NOLINK; |
| 1306 | |
| 1307 | //Stop Beacon. |
| 1308 | |
| 1309 | // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST |
| 1310 | // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck. |
| 1311 | // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send. |
| 1312 | |
| 1313 | // Disable Beacon Queue Own bit, suggested by jong |
| 1314 | ieee80211_stop_send_beacons(priv->ieee80211); |
| 1315 | |
| 1316 | priv->ieee80211->link_change(dev); |
| 1317 | notify_wx_assoc_event(priv->ieee80211); |
| 1318 | } |
| 1319 | void |
| 1320 | MlmeDisassociateRequest( |
| 1321 | struct net_device *dev, |
| 1322 | u8* asSta, |
| 1323 | u8 asRsn |
| 1324 | ) |
| 1325 | { |
| 1326 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1327 | u8 i; |
| 1328 | |
| 1329 | SendDisassociation(priv->ieee80211, asSta, asRsn ); |
| 1330 | |
| 1331 | if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){ |
| 1332 | //ShuChen TODO: change media status. |
| 1333 | //ShuChen TODO: What to do when disassociate. |
| 1334 | DrvIFIndicateDisassociation(dev, unspec_reason); |
| 1335 | |
| 1336 | |
| 1337 | for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22; |
| 1338 | ieee80211_disassociate(priv->ieee80211); |
| 1339 | } |
| 1340 | |
| 1341 | } |
| 1342 | |
| 1343 | void |
| 1344 | MgntDisconnectAP( |
| 1345 | struct net_device *dev, |
| 1346 | u8 asRsn |
| 1347 | ) |
| 1348 | { |
| 1349 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1350 | |
| 1351 | // |
| 1352 | // Commented out by rcnjko, 2005.01.27: |
| 1353 | // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE(). |
| 1354 | // |
| 1355 | // //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success |
| 1356 | |
| 1357 | // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking. |
| 1358 | // 2004.10.11, by rcnjko. |
| 1359 | MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn ); |
| 1360 | |
| 1361 | priv->ieee80211->state = IEEE80211_NOLINK; |
| 1362 | } |
| 1363 | bool |
| 1364 | MgntDisconnect( |
| 1365 | struct net_device *dev, |
| 1366 | u8 asRsn |
| 1367 | ) |
| 1368 | { |
| 1369 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1370 | // |
| 1371 | // Schedule an workitem to wake up for ps mode, 070109, by rcnjko. |
| 1372 | // |
| 1373 | |
| 1374 | if(IS_DOT11D_ENABLE(priv->ieee80211)) |
| 1375 | Dot11d_Reset(priv->ieee80211); |
| 1376 | // In adhoc mode, update beacon frame. |
| 1377 | if( priv->ieee80211->state == IEEE80211_LINKED ) |
| 1378 | { |
| 1379 | if( priv->ieee80211->iw_mode == IW_MODE_ADHOC ) |
| 1380 | { |
| 1381 | MgntDisconnectIBSS(dev); |
| 1382 | } |
| 1383 | if( priv->ieee80211->iw_mode == IW_MODE_INFRA ) |
| 1384 | { |
| 1385 | // We clear key here instead of MgntDisconnectAP() because that |
| 1386 | // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS, |
| 1387 | // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is |
| 1388 | // used to handle disassociation related things to AP, e.g. send Disassoc |
| 1389 | // frame to AP. 2005.01.27, by rcnjko. |
| 1390 | MgntDisconnectAP(dev, asRsn); |
| 1391 | } |
| 1392 | // Inidicate Disconnect, 2005.02.23, by rcnjko. |
| 1393 | } |
| 1394 | return true; |
| 1395 | } |
| 1396 | // |
| 1397 | // Description: |
| 1398 | // Chang RF Power State. |
| 1399 | // Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE. |
| 1400 | // |
| 1401 | // Assumption: |
| 1402 | // PASSIVE LEVEL. |
| 1403 | // |
| 1404 | bool |
| 1405 | SetRFPowerState( |
| 1406 | struct net_device *dev, |
| 1407 | RT_RF_POWER_STATE eRFPowerState |
| 1408 | ) |
| 1409 | { |
| 1410 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1411 | bool bResult = false; |
| 1412 | |
| 1413 | if(eRFPowerState == priv->eRFPowerState) |
| 1414 | { |
| 1415 | return bResult; |
| 1416 | } |
| 1417 | |
| 1418 | bResult = SetZebraRFPowerState8185(dev, eRFPowerState); |
| 1419 | |
| 1420 | return bResult; |
| 1421 | } |
| 1422 | void |
| 1423 | HalEnableRx8185Dummy( |
| 1424 | struct net_device *dev |
| 1425 | ) |
| 1426 | { |
| 1427 | } |
| 1428 | void |
| 1429 | HalDisableRx8185Dummy( |
| 1430 | struct net_device *dev |
| 1431 | ) |
| 1432 | { |
| 1433 | } |
| 1434 | |
| 1435 | bool |
| 1436 | MgntActSet_RF_State( |
| 1437 | struct net_device *dev, |
| 1438 | RT_RF_POWER_STATE StateToSet, |
| 1439 | u32 ChangeSource |
| 1440 | ) |
| 1441 | { |
| 1442 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1443 | bool bActionAllowed = false; |
| 1444 | bool bConnectBySSID = false; |
| 1445 | RT_RF_POWER_STATE rtState; |
| 1446 | u16 RFWaitCounter = 0; |
| 1447 | unsigned long flag; |
| 1448 | // |
| 1449 | // Prevent the race condition of RF state change. By Bruce, 2007-11-28. |
| 1450 | // Only one thread can change the RF state at one time, and others should wait to be executed. |
| 1451 | // |
| 1452 | while(true) |
| 1453 | { |
| 1454 | spin_lock_irqsave(&priv->rf_ps_lock,flag); |
| 1455 | if(priv->RFChangeInProgress) |
| 1456 | { |
| 1457 | spin_unlock_irqrestore(&priv->rf_ps_lock,flag); |
| 1458 | // Set RF after the previous action is done. |
| 1459 | while(priv->RFChangeInProgress) |
| 1460 | { |
| 1461 | RFWaitCounter ++; |
| 1462 | udelay(1000); // 1 ms |
| 1463 | |
| 1464 | // Wait too long, return FALSE to avoid to be stuck here. |
| 1465 | if(RFWaitCounter > 1000) // 1sec |
| 1466 | { |
| 1467 | printk("MgntActSet_RF_State(): Wait too long to set RF\n"); |
| 1468 | // TODO: Reset RF state? |
| 1469 | return false; |
| 1470 | } |
| 1471 | } |
| 1472 | } |
| 1473 | else |
| 1474 | { |
| 1475 | priv->RFChangeInProgress = true; |
| 1476 | spin_unlock_irqrestore(&priv->rf_ps_lock,flag); |
| 1477 | break; |
| 1478 | } |
| 1479 | } |
| 1480 | rtState = priv->eRFPowerState; |
| 1481 | |
| 1482 | switch(StateToSet) |
| 1483 | { |
| 1484 | case eRfOn: |
| 1485 | // |
| 1486 | // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or |
| 1487 | // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02. |
| 1488 | // |
| 1489 | priv->RfOffReason &= (~ChangeSource); |
| 1490 | |
| 1491 | if(! priv->RfOffReason) |
| 1492 | { |
| 1493 | priv->RfOffReason = 0; |
| 1494 | bActionAllowed = true; |
| 1495 | |
| 1496 | if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest) |
| 1497 | { |
| 1498 | bConnectBySSID = true; |
| 1499 | } |
| 1500 | } |
| 1501 | else |
| 1502 | ; |
| 1503 | break; |
| 1504 | |
| 1505 | case eRfOff: |
| 1506 | // 070125, rcnjko: we always keep connected in AP mode. |
| 1507 | |
| 1508 | if (priv->RfOffReason > RF_CHANGE_BY_IPS) |
| 1509 | { |
| 1510 | // |
| 1511 | // 060808, Annie: |
| 1512 | // Disconnect to current BSS when radio off. Asked by QuanTa. |
| 1513 | // |
| 1514 | |
| 1515 | // |
| 1516 | // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(), |
| 1517 | // because we do NOT need to set ssid to dummy ones. |
| 1518 | // |
| 1519 | MgntDisconnect( dev, disas_lv_ss ); |
| 1520 | |
| 1521 | // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI. |
| 1522 | } |
| 1523 | |
| 1524 | priv->RfOffReason |= ChangeSource; |
| 1525 | bActionAllowed = true; |
| 1526 | break; |
| 1527 | case eRfSleep: |
| 1528 | priv->RfOffReason |= ChangeSource; |
| 1529 | bActionAllowed = true; |
| 1530 | break; |
| 1531 | default: |
| 1532 | break; |
| 1533 | } |
| 1534 | |
| 1535 | if(bActionAllowed) |
| 1536 | { |
| 1537 | // Config HW to the specified mode. |
| 1538 | SetRFPowerState(dev, StateToSet); |
| 1539 | |
| 1540 | // Turn on RF. |
| 1541 | if(StateToSet == eRfOn) |
| 1542 | { |
| 1543 | HalEnableRx8185Dummy(dev); |
| 1544 | if(bConnectBySSID) |
| 1545 | { |
| 1546 | // by amy not supported |
| 1547 | } |
| 1548 | } |
| 1549 | // Turn off RF. |
| 1550 | else if(StateToSet == eRfOff) |
| 1551 | { |
| 1552 | HalDisableRx8185Dummy(dev); |
| 1553 | } |
| 1554 | } |
| 1555 | |
| 1556 | // Release RF spinlock |
| 1557 | spin_lock_irqsave(&priv->rf_ps_lock,flag); |
| 1558 | priv->RFChangeInProgress = false; |
| 1559 | spin_unlock_irqrestore(&priv->rf_ps_lock,flag); |
| 1560 | return bActionAllowed; |
| 1561 | } |
| 1562 | void |
| 1563 | InactivePowerSave( |
| 1564 | struct net_device *dev |
| 1565 | ) |
| 1566 | { |
| 1567 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1568 | // |
| 1569 | // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem |
| 1570 | // is really scheduled. |
| 1571 | // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the |
| 1572 | // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing |
| 1573 | // blocks the IPS procedure of switching RF. |
| 1574 | // |
| 1575 | priv->bSwRfProcessing = true; |
| 1576 | |
| 1577 | MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS); |
| 1578 | |
| 1579 | // |
| 1580 | // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20. |
| 1581 | // |
| 1582 | |
| 1583 | priv->bSwRfProcessing = false; |
| 1584 | } |
| 1585 | |
| 1586 | // |
| 1587 | // Description: |
| 1588 | // Enter the inactive power save mode. RF will be off |
| 1589 | // |
| 1590 | void |
| 1591 | IPSEnter( |
| 1592 | struct net_device *dev |
| 1593 | ) |
| 1594 | { |
| 1595 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1596 | RT_RF_POWER_STATE rtState; |
| 1597 | if (priv->bInactivePs) |
| 1598 | { |
| 1599 | rtState = priv->eRFPowerState; |
| 1600 | |
| 1601 | // |
| 1602 | // Do not enter IPS in the following conditions: |
| 1603 | // (1) RF is already OFF or Sleep |
| 1604 | // (2) bSwRfProcessing (indicates the IPS is still under going) |
| 1605 | // (3) Connectted (only disconnected can trigger IPS) |
| 1606 | // (4) IBSS (send Beacon) |
| 1607 | // (5) AP mode (send Beacon) |
| 1608 | // |
| 1609 | if (rtState == eRfOn && !priv->bSwRfProcessing |
| 1610 | && (priv->ieee80211->state != IEEE80211_LINKED )) |
| 1611 | { |
| 1612 | priv->eInactivePowerState = eRfOff; |
| 1613 | InactivePowerSave(dev); |
| 1614 | } |
| 1615 | } |
| 1616 | } |
| 1617 | void |
| 1618 | IPSLeave( |
| 1619 | struct net_device *dev |
| 1620 | ) |
| 1621 | { |
| 1622 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1623 | RT_RF_POWER_STATE rtState; |
| 1624 | if (priv->bInactivePs) |
| 1625 | { |
| 1626 | rtState = priv->eRFPowerState; |
| 1627 | if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS) |
| 1628 | { |
| 1629 | priv->eInactivePowerState = eRfOn; |
| 1630 | InactivePowerSave(dev); |
| 1631 | } |
| 1632 | } |
| 1633 | } |
| 1634 | |
| 1635 | void rtl8185b_adapter_start(struct net_device *dev) |
| 1636 | { |
| 1637 | struct r8180_priv *priv = ieee80211_priv(dev); |
| 1638 | struct ieee80211_device *ieee = priv->ieee80211; |
| 1639 | |
| 1640 | u8 SupportedWirelessMode; |
| 1641 | u8 InitWirelessMode; |
| 1642 | u8 bInvalidWirelessMode = 0; |
| 1643 | u8 tmpu8; |
| 1644 | u8 btCR9346; |
| 1645 | u8 TmpU1b; |
| 1646 | u8 btPSR; |
| 1647 | |
| 1648 | write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0)); |
| 1649 | rtl8180_reset(dev); |
| 1650 | |
| 1651 | priv->dma_poll_mask = 0; |
| 1652 | priv->dma_poll_stop_mask = 0; |
| 1653 | |
| 1654 | HwConfigureRTL8185(dev); |
| 1655 | write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]); |
| 1656 | write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff ); |
| 1657 | write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); // default network type to 'No Link' |
| 1658 | write_nic_word(dev, BcnItv, 100); |
| 1659 | write_nic_word(dev, AtimWnd, 2); |
| 1660 | PlatformIOWrite2Byte(dev, FEMR, 0xFFFF); |
| 1661 | write_nic_byte(dev, WPA_CONFIG, 0); |
| 1662 | MacConfig_85BASIC(dev); |
| 1663 | // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko. |
| 1664 | // BT_DEMO_BOARD type |
| 1665 | PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a); |
| 1666 | |
| 1667 | //----------------------------------------------------------------------------- |
| 1668 | // Set up PHY related. |
| 1669 | //----------------------------------------------------------------------------- |
| 1670 | // Enable Config3.PARAM_En to revise AnaaParm. |
| 1671 | write_nic_byte(dev, CR9346, 0xc0); // enable config register write |
| 1672 | tmpu8 = read_nic_byte(dev, CONFIG3); |
| 1673 | write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) ); |
| 1674 | // Turn on Analog power. |
| 1675 | // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko. |
| 1676 | write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON); |
| 1677 | write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON); |
| 1678 | write_nic_word(dev, ANAPARAM3, 0x0010); |
| 1679 | |
| 1680 | write_nic_byte(dev, CONFIG3, tmpu8); |
| 1681 | write_nic_byte(dev, CR9346, 0x00); |
| 1682 | // enable EEM0 and EEM1 in 9346CR |
| 1683 | btCR9346 = read_nic_byte(dev, CR9346); |
| 1684 | write_nic_byte(dev, CR9346, (btCR9346|0xC0) ); |
| 1685 | |
| 1686 | // B cut use LED1 to control HW RF on/off |
| 1687 | TmpU1b = read_nic_byte(dev, CONFIG5); |
| 1688 | TmpU1b = TmpU1b & ~BIT3; |
| 1689 | write_nic_byte(dev,CONFIG5, TmpU1b); |
| 1690 | |
| 1691 | // disable EEM0 and EEM1 in 9346CR |
| 1692 | btCR9346 &= ~(0xC0); |
| 1693 | write_nic_byte(dev, CR9346, btCR9346); |
| 1694 | |
| 1695 | //Enable Led (suggested by Jong) |
| 1696 | // B-cut RF Radio on/off 5e[3]=0 |
| 1697 | btPSR = read_nic_byte(dev, PSR); |
| 1698 | write_nic_byte(dev, PSR, (btPSR | BIT3)); |
| 1699 | // setup initial timing for RFE. |
| 1700 | write_nic_word(dev, RFPinsOutput, 0x0480); |
| 1701 | SetOutputEnableOfRfPins(dev); |
| 1702 | write_nic_word(dev, RFPinsSelect, 0x2488); |
| 1703 | |
| 1704 | // PHY config. |
| 1705 | PhyConfig8185(dev); |
| 1706 | |
| 1707 | // We assume RegWirelessMode has already been initialized before, |
| 1708 | // however, we has to validate the wireless mode here and provide a |
| 1709 | // reasonable initialized value if necessary. 2005.01.13, by rcnjko. |
| 1710 | SupportedWirelessMode = GetSupportedWirelessMode8185(dev); |
| 1711 | if( (ieee->mode != WIRELESS_MODE_B) && |
| 1712 | (ieee->mode != WIRELESS_MODE_G) && |
| 1713 | (ieee->mode != WIRELESS_MODE_A) && |
| 1714 | (ieee->mode != WIRELESS_MODE_AUTO)) |
| 1715 | { // It should be one of B, G, A, or AUTO. |
| 1716 | bInvalidWirelessMode = 1; |
| 1717 | } |
| 1718 | else |
| 1719 | { // One of B, G, A, or AUTO. |
| 1720 | // Check if the wireless mode is supported by RF. |
| 1721 | if( (ieee->mode != WIRELESS_MODE_AUTO) && |
| 1722 | (ieee->mode & SupportedWirelessMode) == 0 ) |
| 1723 | { |
| 1724 | bInvalidWirelessMode = 1; |
| 1725 | } |
| 1726 | } |
| 1727 | |
| 1728 | if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO) |
| 1729 | { // Auto or other invalid value. |
| 1730 | // Assigne a wireless mode to initialize. |
| 1731 | if((SupportedWirelessMode & WIRELESS_MODE_A)) |
| 1732 | { |
| 1733 | InitWirelessMode = WIRELESS_MODE_A; |
| 1734 | } |
| 1735 | else if((SupportedWirelessMode & WIRELESS_MODE_G)) |
| 1736 | { |
| 1737 | InitWirelessMode = WIRELESS_MODE_G; |
| 1738 | } |
| 1739 | else if((SupportedWirelessMode & WIRELESS_MODE_B)) |
| 1740 | { |
| 1741 | InitWirelessMode = WIRELESS_MODE_B; |
| 1742 | } |
| 1743 | else |
| 1744 | { |
| 1745 | DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n", |
| 1746 | SupportedWirelessMode); |
| 1747 | InitWirelessMode = WIRELESS_MODE_B; |
| 1748 | } |
| 1749 | |
| 1750 | // Initialize RegWirelessMode if it is not a valid one. |
| 1751 | if(bInvalidWirelessMode) |
| 1752 | { |
| 1753 | ieee->mode = (WIRELESS_MODE)InitWirelessMode; |
| 1754 | } |
| 1755 | } |
| 1756 | else |
| 1757 | { // One of B, G, A. |
| 1758 | InitWirelessMode = ieee->mode; |
| 1759 | } |
| 1760 | //by amy for power save |
| 1761 | priv->eRFPowerState = eRfOff; |
| 1762 | priv->RfOffReason = 0; |
| 1763 | { |
| 1764 | MgntActSet_RF_State(dev, eRfOn, 0); |
| 1765 | } |
| 1766 | // |
| 1767 | // If inactive power mode is enabled, disable rf while in disconnected state. |
| 1768 | // |
| 1769 | if (priv->bInactivePs) |
| 1770 | { |
| 1771 | MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS); |
| 1772 | } |
| 1773 | //by amy for power save |
| 1774 | |
| 1775 | ActSetWirelessMode8185(dev, (u8)(InitWirelessMode)); |
| 1776 | |
| 1777 | //----------------------------------------------------------------------------- |
| 1778 | |
| 1779 | rtl8185b_irq_enable(dev); |
| 1780 | |
| 1781 | netif_start_queue(dev); |
| 1782 | } |
| 1783 | |
| 1784 | void rtl8185b_rx_enable(struct net_device *dev) |
| 1785 | { |
| 1786 | u8 cmd; |
| 1787 | /* for now we accept data, management & ctl frame*/ |
| 1788 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1789 | |
| 1790 | if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode"); |
| 1791 | |
| 1792 | if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \ |
| 1793 | dev->flags & IFF_PROMISC){ |
| 1794 | priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM); |
| 1795 | priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP; |
| 1796 | } |
| 1797 | |
| 1798 | if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){ |
| 1799 | priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV; |
| 1800 | } |
| 1801 | |
| 1802 | if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR) |
| 1803 | priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32; |
| 1804 | |
| 1805 | write_nic_dword(dev, RCR, priv->ReceiveConfig); |
| 1806 | |
| 1807 | fix_rx_fifo(dev); |
| 1808 | |
| 1809 | cmd=read_nic_byte(dev,CMD); |
| 1810 | write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT)); |
| 1811 | |
| 1812 | } |
| 1813 | |
| 1814 | void rtl8185b_tx_enable(struct net_device *dev) |
| 1815 | { |
| 1816 | u8 cmd; |
| 1817 | u8 byte; |
| 1818 | struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); |
| 1819 | |
| 1820 | write_nic_dword(dev, TCR, priv->TransmitConfig); |
| 1821 | byte = read_nic_byte(dev, MSR); |
| 1822 | byte |= MSR_LINK_ENEDCA; |
| 1823 | write_nic_byte(dev, MSR, byte); |
| 1824 | |
| 1825 | fix_tx_fifo(dev); |
| 1826 | |
| 1827 | cmd=read_nic_byte(dev,CMD); |
| 1828 | write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT)); |
| 1829 | } |
| 1830 | |