| 1 | /* |
| 2 | * xilinx_spi.c |
| 3 | * |
| 4 | * Xilinx SPI controller driver (master mode only) |
| 5 | * |
| 6 | * Author: MontaVista Software, Inc. |
| 7 | * source@mvista.com |
| 8 | * |
| 9 | * 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the |
| 10 | * terms of the GNU General Public License version 2. This program is licensed |
| 11 | * "as is" without any warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | |
| 19 | #include <linux/of_platform.h> |
| 20 | #include <linux/of_device.h> |
| 21 | #include <linux/of_spi.h> |
| 22 | |
| 23 | #include <linux/spi/spi.h> |
| 24 | #include <linux/spi/spi_bitbang.h> |
| 25 | #include <linux/io.h> |
| 26 | |
| 27 | #define XILINX_SPI_NAME "xilinx_spi" |
| 28 | |
| 29 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) |
| 30 | * Product Specification", DS464 |
| 31 | */ |
| 32 | #define XSPI_CR_OFFSET 0x62 /* 16-bit Control Register */ |
| 33 | |
| 34 | #define XSPI_CR_ENABLE 0x02 |
| 35 | #define XSPI_CR_MASTER_MODE 0x04 |
| 36 | #define XSPI_CR_CPOL 0x08 |
| 37 | #define XSPI_CR_CPHA 0x10 |
| 38 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) |
| 39 | #define XSPI_CR_TXFIFO_RESET 0x20 |
| 40 | #define XSPI_CR_RXFIFO_RESET 0x40 |
| 41 | #define XSPI_CR_MANUAL_SSELECT 0x80 |
| 42 | #define XSPI_CR_TRANS_INHIBIT 0x100 |
| 43 | |
| 44 | #define XSPI_SR_OFFSET 0x67 /* 8-bit Status Register */ |
| 45 | |
| 46 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ |
| 47 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ |
| 48 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ |
| 49 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ |
| 50 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ |
| 51 | |
| 52 | #define XSPI_TXD_OFFSET 0x6b /* 8-bit Data Transmit Register */ |
| 53 | #define XSPI_RXD_OFFSET 0x6f /* 8-bit Data Receive Register */ |
| 54 | |
| 55 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ |
| 56 | |
| 57 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 |
| 58 | * IPIF registers are 32 bit |
| 59 | */ |
| 60 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ |
| 61 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 |
| 62 | |
| 63 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ |
| 64 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ |
| 65 | |
| 66 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ |
| 67 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while |
| 68 | * disabled */ |
| 69 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ |
| 70 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ |
| 71 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ |
| 72 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ |
| 73 | |
| 74 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ |
| 75 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ |
| 76 | |
| 77 | struct xilinx_spi { |
| 78 | /* bitbang has to be first */ |
| 79 | struct spi_bitbang bitbang; |
| 80 | struct completion done; |
| 81 | |
| 82 | void __iomem *regs; /* virt. address of the control registers */ |
| 83 | |
| 84 | u32 irq; |
| 85 | |
| 86 | u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */ |
| 87 | |
| 88 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
| 89 | const u8 *tx_ptr; /* pointer in the Rx buffer */ |
| 90 | int remaining_bytes; /* the number of bytes left to transfer */ |
| 91 | }; |
| 92 | |
| 93 | static void xspi_init_hw(void __iomem *regs_base) |
| 94 | { |
| 95 | /* Reset the SPI device */ |
| 96 | out_be32(regs_base + XIPIF_V123B_RESETR_OFFSET, |
| 97 | XIPIF_V123B_RESET_MASK); |
| 98 | /* Disable all the interrupts just in case */ |
| 99 | out_be32(regs_base + XIPIF_V123B_IIER_OFFSET, 0); |
| 100 | /* Enable the global IPIF interrupt */ |
| 101 | out_be32(regs_base + XIPIF_V123B_DGIER_OFFSET, |
| 102 | XIPIF_V123B_GINTR_ENABLE); |
| 103 | /* Deselect the slave on the SPI bus */ |
| 104 | out_be32(regs_base + XSPI_SSR_OFFSET, 0xffff); |
| 105 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
| 106 | * put SPI controller into master mode, and enable it */ |
| 107 | out_be16(regs_base + XSPI_CR_OFFSET, |
| 108 | XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
| 109 | | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE); |
| 110 | } |
| 111 | |
| 112 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) |
| 113 | { |
| 114 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
| 115 | |
| 116 | if (is_on == BITBANG_CS_INACTIVE) { |
| 117 | /* Deselect the slave on the SPI bus */ |
| 118 | out_be32(xspi->regs + XSPI_SSR_OFFSET, 0xffff); |
| 119 | } else if (is_on == BITBANG_CS_ACTIVE) { |
| 120 | /* Set the SPI clock phase and polarity */ |
| 121 | u16 cr = in_be16(xspi->regs + XSPI_CR_OFFSET) |
| 122 | & ~XSPI_CR_MODE_MASK; |
| 123 | if (spi->mode & SPI_CPHA) |
| 124 | cr |= XSPI_CR_CPHA; |
| 125 | if (spi->mode & SPI_CPOL) |
| 126 | cr |= XSPI_CR_CPOL; |
| 127 | out_be16(xspi->regs + XSPI_CR_OFFSET, cr); |
| 128 | |
| 129 | /* We do not check spi->max_speed_hz here as the SPI clock |
| 130 | * frequency is not software programmable (the IP block design |
| 131 | * parameter) |
| 132 | */ |
| 133 | |
| 134 | /* Activate the chip select */ |
| 135 | out_be32(xspi->regs + XSPI_SSR_OFFSET, |
| 136 | ~(0x0001 << spi->chip_select)); |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a |
| 141 | * custom txrx_bufs(). We have nothing to setup here as the SPI IP block |
| 142 | * supports just 8 bits per word, and SPI clock can't be changed in software. |
| 143 | * Check for 8 bits per word. Chip select delay calculations could be |
| 144 | * added here as soon as bitbang_work() can be made aware of the delay value. |
| 145 | */ |
| 146 | static int xilinx_spi_setup_transfer(struct spi_device *spi, |
| 147 | struct spi_transfer *t) |
| 148 | { |
| 149 | u8 bits_per_word; |
| 150 | |
| 151 | bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; |
| 152 | if (bits_per_word != 8) { |
| 153 | dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", |
| 154 | __func__, bits_per_word); |
| 155 | return -EINVAL; |
| 156 | } |
| 157 | |
| 158 | return 0; |
| 159 | } |
| 160 | |
| 161 | /* the spi->mode bits understood by this driver: */ |
| 162 | #define MODEBITS (SPI_CPOL | SPI_CPHA) |
| 163 | |
| 164 | static int xilinx_spi_setup(struct spi_device *spi) |
| 165 | { |
| 166 | struct spi_bitbang *bitbang; |
| 167 | struct xilinx_spi *xspi; |
| 168 | int retval; |
| 169 | |
| 170 | xspi = spi_master_get_devdata(spi->master); |
| 171 | bitbang = &xspi->bitbang; |
| 172 | |
| 173 | if (!spi->bits_per_word) |
| 174 | spi->bits_per_word = 8; |
| 175 | |
| 176 | if (spi->mode & ~MODEBITS) { |
| 177 | dev_err(&spi->dev, "%s, unsupported mode bits %x\n", |
| 178 | __func__, spi->mode & ~MODEBITS); |
| 179 | return -EINVAL; |
| 180 | } |
| 181 | |
| 182 | retval = xilinx_spi_setup_transfer(spi, NULL); |
| 183 | if (retval < 0) |
| 184 | return retval; |
| 185 | |
| 186 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", |
| 187 | __func__, spi->mode & MODEBITS, spi->bits_per_word, 0); |
| 188 | |
| 189 | return 0; |
| 190 | } |
| 191 | |
| 192 | static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) |
| 193 | { |
| 194 | u8 sr; |
| 195 | |
| 196 | /* Fill the Tx FIFO with as many bytes as possible */ |
| 197 | sr = in_8(xspi->regs + XSPI_SR_OFFSET); |
| 198 | while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { |
| 199 | if (xspi->tx_ptr) { |
| 200 | out_8(xspi->regs + XSPI_TXD_OFFSET, *xspi->tx_ptr++); |
| 201 | } else { |
| 202 | out_8(xspi->regs + XSPI_TXD_OFFSET, 0); |
| 203 | } |
| 204 | xspi->remaining_bytes--; |
| 205 | sr = in_8(xspi->regs + XSPI_SR_OFFSET); |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
| 210 | { |
| 211 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
| 212 | u32 ipif_ier; |
| 213 | u16 cr; |
| 214 | |
| 215 | /* We get here with transmitter inhibited */ |
| 216 | |
| 217 | xspi->tx_ptr = t->tx_buf; |
| 218 | xspi->rx_ptr = t->rx_buf; |
| 219 | xspi->remaining_bytes = t->len; |
| 220 | INIT_COMPLETION(xspi->done); |
| 221 | |
| 222 | xilinx_spi_fill_tx_fifo(xspi); |
| 223 | |
| 224 | /* Enable the transmit empty interrupt, which we use to determine |
| 225 | * progress on the transmission. |
| 226 | */ |
| 227 | ipif_ier = in_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET); |
| 228 | out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, |
| 229 | ipif_ier | XSPI_INTR_TX_EMPTY); |
| 230 | |
| 231 | /* Start the transfer by not inhibiting the transmitter any longer */ |
| 232 | cr = in_be16(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT; |
| 233 | out_be16(xspi->regs + XSPI_CR_OFFSET, cr); |
| 234 | |
| 235 | wait_for_completion(&xspi->done); |
| 236 | |
| 237 | /* Disable the transmit empty interrupt */ |
| 238 | out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, ipif_ier); |
| 239 | |
| 240 | return t->len - xspi->remaining_bytes; |
| 241 | } |
| 242 | |
| 243 | |
| 244 | /* This driver supports single master mode only. Hence Tx FIFO Empty |
| 245 | * is the only interrupt we care about. |
| 246 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode |
| 247 | * Fault are not to happen. |
| 248 | */ |
| 249 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) |
| 250 | { |
| 251 | struct xilinx_spi *xspi = dev_id; |
| 252 | u32 ipif_isr; |
| 253 | |
| 254 | /* Get the IPIF interrupts, and clear them immediately */ |
| 255 | ipif_isr = in_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
| 256 | out_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET, ipif_isr); |
| 257 | |
| 258 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ |
| 259 | u16 cr; |
| 260 | u8 sr; |
| 261 | |
| 262 | /* A transmit has just completed. Process received data and |
| 263 | * check for more data to transmit. Always inhibit the |
| 264 | * transmitter while the Isr refills the transmit register/FIFO, |
| 265 | * or make sure it is stopped if we're done. |
| 266 | */ |
| 267 | cr = in_be16(xspi->regs + XSPI_CR_OFFSET); |
| 268 | out_be16(xspi->regs + XSPI_CR_OFFSET, |
| 269 | cr | XSPI_CR_TRANS_INHIBIT); |
| 270 | |
| 271 | /* Read out all the data from the Rx FIFO */ |
| 272 | sr = in_8(xspi->regs + XSPI_SR_OFFSET); |
| 273 | while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { |
| 274 | u8 data; |
| 275 | |
| 276 | data = in_8(xspi->regs + XSPI_RXD_OFFSET); |
| 277 | if (xspi->rx_ptr) { |
| 278 | *xspi->rx_ptr++ = data; |
| 279 | } |
| 280 | sr = in_8(xspi->regs + XSPI_SR_OFFSET); |
| 281 | } |
| 282 | |
| 283 | /* See if there is more data to send */ |
| 284 | if (xspi->remaining_bytes > 0) { |
| 285 | xilinx_spi_fill_tx_fifo(xspi); |
| 286 | /* Start the transfer by not inhibiting the |
| 287 | * transmitter any longer |
| 288 | */ |
| 289 | out_be16(xspi->regs + XSPI_CR_OFFSET, cr); |
| 290 | } else { |
| 291 | /* No more data to send. |
| 292 | * Indicate the transfer is completed. |
| 293 | */ |
| 294 | complete(&xspi->done); |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | return IRQ_HANDLED; |
| 299 | } |
| 300 | |
| 301 | static int __init xilinx_spi_of_probe(struct of_device *ofdev, |
| 302 | const struct of_device_id *match) |
| 303 | { |
| 304 | struct spi_master *master; |
| 305 | struct xilinx_spi *xspi; |
| 306 | struct resource r_irq_struct; |
| 307 | struct resource r_mem_struct; |
| 308 | |
| 309 | struct resource *r_irq = &r_irq_struct; |
| 310 | struct resource *r_mem = &r_mem_struct; |
| 311 | int rc = 0; |
| 312 | const u32 *prop; |
| 313 | int len; |
| 314 | |
| 315 | /* Get resources(memory, IRQ) associated with the device */ |
| 316 | master = spi_alloc_master(&ofdev->dev, sizeof(struct xilinx_spi)); |
| 317 | |
| 318 | if (master == NULL) { |
| 319 | return -ENOMEM; |
| 320 | } |
| 321 | |
| 322 | dev_set_drvdata(&ofdev->dev, master); |
| 323 | |
| 324 | rc = of_address_to_resource(ofdev->node, 0, r_mem); |
| 325 | if (rc) { |
| 326 | dev_warn(&ofdev->dev, "invalid address\n"); |
| 327 | goto put_master; |
| 328 | } |
| 329 | |
| 330 | rc = of_irq_to_resource(ofdev->node, 0, r_irq); |
| 331 | if (rc == NO_IRQ) { |
| 332 | dev_warn(&ofdev->dev, "no IRQ found\n"); |
| 333 | goto put_master; |
| 334 | } |
| 335 | |
| 336 | xspi = spi_master_get_devdata(master); |
| 337 | xspi->bitbang.master = spi_master_get(master); |
| 338 | xspi->bitbang.chipselect = xilinx_spi_chipselect; |
| 339 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; |
| 340 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; |
| 341 | xspi->bitbang.master->setup = xilinx_spi_setup; |
| 342 | init_completion(&xspi->done); |
| 343 | |
| 344 | xspi->irq = r_irq->start; |
| 345 | |
| 346 | if (!request_mem_region(r_mem->start, |
| 347 | r_mem->end - r_mem->start + 1, XILINX_SPI_NAME)) { |
| 348 | rc = -ENXIO; |
| 349 | dev_warn(&ofdev->dev, "memory request failure\n"); |
| 350 | goto put_master; |
| 351 | } |
| 352 | |
| 353 | xspi->regs = ioremap(r_mem->start, r_mem->end - r_mem->start + 1); |
| 354 | if (xspi->regs == NULL) { |
| 355 | rc = -ENOMEM; |
| 356 | dev_warn(&ofdev->dev, "ioremap failure\n"); |
| 357 | goto release_mem; |
| 358 | } |
| 359 | xspi->irq = r_irq->start; |
| 360 | |
| 361 | /* dynamic bus assignment */ |
| 362 | master->bus_num = -1; |
| 363 | |
| 364 | /* number of slave select bits is required */ |
| 365 | prop = of_get_property(ofdev->node, "xlnx,num-ss-bits", &len); |
| 366 | if (!prop || len < sizeof(*prop)) { |
| 367 | dev_warn(&ofdev->dev, "no 'xlnx,num-ss-bits' property\n"); |
| 368 | goto unmap_io; |
| 369 | } |
| 370 | master->num_chipselect = *prop; |
| 371 | |
| 372 | /* SPI controller initializations */ |
| 373 | xspi_init_hw(xspi->regs); |
| 374 | |
| 375 | /* Register for SPI Interrupt */ |
| 376 | rc = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi); |
| 377 | if (rc != 0) { |
| 378 | dev_warn(&ofdev->dev, "irq request failure: %d\n", xspi->irq); |
| 379 | goto unmap_io; |
| 380 | } |
| 381 | |
| 382 | rc = spi_bitbang_start(&xspi->bitbang); |
| 383 | if (rc != 0) { |
| 384 | dev_err(&ofdev->dev, "spi_bitbang_start FAILED\n"); |
| 385 | goto free_irq; |
| 386 | } |
| 387 | |
| 388 | dev_info(&ofdev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n", |
| 389 | (unsigned int)r_mem->start, (u32)xspi->regs, xspi->irq); |
| 390 | |
| 391 | /* Add any subnodes on the SPI bus */ |
| 392 | of_register_spi_devices(master, ofdev->node); |
| 393 | |
| 394 | return rc; |
| 395 | |
| 396 | free_irq: |
| 397 | free_irq(xspi->irq, xspi); |
| 398 | unmap_io: |
| 399 | iounmap(xspi->regs); |
| 400 | release_mem: |
| 401 | release_mem_region(r_mem->start, resource_size(r_mem)); |
| 402 | put_master: |
| 403 | spi_master_put(master); |
| 404 | return rc; |
| 405 | } |
| 406 | |
| 407 | static int __devexit xilinx_spi_remove(struct of_device *ofdev) |
| 408 | { |
| 409 | struct xilinx_spi *xspi; |
| 410 | struct spi_master *master; |
| 411 | struct resource r_mem; |
| 412 | |
| 413 | master = platform_get_drvdata(ofdev); |
| 414 | xspi = spi_master_get_devdata(master); |
| 415 | |
| 416 | spi_bitbang_stop(&xspi->bitbang); |
| 417 | free_irq(xspi->irq, xspi); |
| 418 | iounmap(xspi->regs); |
| 419 | if (!of_address_to_resource(ofdev->node, 0, &r_mem)) |
| 420 | release_mem_region(r_mem.start, resource_size(&r_mem)); |
| 421 | dev_set_drvdata(&ofdev->dev, 0); |
| 422 | spi_master_put(xspi->bitbang.master); |
| 423 | |
| 424 | return 0; |
| 425 | } |
| 426 | |
| 427 | /* work with hotplug and coldplug */ |
| 428 | MODULE_ALIAS("platform:" XILINX_SPI_NAME); |
| 429 | |
| 430 | static int __exit xilinx_spi_of_remove(struct of_device *op) |
| 431 | { |
| 432 | return xilinx_spi_remove(op); |
| 433 | } |
| 434 | |
| 435 | static struct of_device_id xilinx_spi_of_match[] = { |
| 436 | { .compatible = "xlnx,xps-spi-2.00.a", }, |
| 437 | { .compatible = "xlnx,xps-spi-2.00.b", }, |
| 438 | {} |
| 439 | }; |
| 440 | |
| 441 | MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); |
| 442 | |
| 443 | static struct of_platform_driver xilinx_spi_of_driver = { |
| 444 | .owner = THIS_MODULE, |
| 445 | .name = "xilinx-xps-spi", |
| 446 | .match_table = xilinx_spi_of_match, |
| 447 | .probe = xilinx_spi_of_probe, |
| 448 | .remove = __exit_p(xilinx_spi_of_remove), |
| 449 | .driver = { |
| 450 | .name = "xilinx-xps-spi", |
| 451 | .owner = THIS_MODULE, |
| 452 | }, |
| 453 | }; |
| 454 | |
| 455 | static int __init xilinx_spi_init(void) |
| 456 | { |
| 457 | return of_register_platform_driver(&xilinx_spi_of_driver); |
| 458 | } |
| 459 | module_init(xilinx_spi_init); |
| 460 | |
| 461 | static void __exit xilinx_spi_exit(void) |
| 462 | { |
| 463 | of_unregister_platform_driver(&xilinx_spi_of_driver); |
| 464 | } |
| 465 | module_exit(xilinx_spi_exit); |
| 466 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
| 467 | MODULE_DESCRIPTION("Xilinx SPI driver"); |
| 468 | MODULE_LICENSE("GPL"); |