| 1 | /* |
| 2 | * Copyright IBM Corp. 2000, 2009 |
| 3 | * Author(s): Utz Bacher <utz.bacher@de.ibm.com> |
| 4 | * Jan Glauber <jang@linux.vnet.ibm.com> |
| 5 | */ |
| 6 | #ifndef _CIO_QDIO_H |
| 7 | #define _CIO_QDIO_H |
| 8 | |
| 9 | #include <asm/page.h> |
| 10 | #include <asm/schid.h> |
| 11 | #include <asm/debug.h> |
| 12 | #include "chsc.h" |
| 13 | |
| 14 | #define QDIO_BUSY_BIT_PATIENCE (100 << 12) /* 100 microseconds */ |
| 15 | #define QDIO_BUSY_BIT_RETRY_DELAY 10 /* 10 milliseconds */ |
| 16 | #define QDIO_BUSY_BIT_RETRIES 1000 /* = 10s retry time */ |
| 17 | #define QDIO_INPUT_THRESHOLD (500 << 12) /* 500 microseconds */ |
| 18 | |
| 19 | enum qdio_irq_states { |
| 20 | QDIO_IRQ_STATE_INACTIVE, |
| 21 | QDIO_IRQ_STATE_ESTABLISHED, |
| 22 | QDIO_IRQ_STATE_ACTIVE, |
| 23 | QDIO_IRQ_STATE_STOPPED, |
| 24 | QDIO_IRQ_STATE_CLEANUP, |
| 25 | QDIO_IRQ_STATE_ERR, |
| 26 | NR_QDIO_IRQ_STATES, |
| 27 | }; |
| 28 | |
| 29 | /* used as intparm in do_IO */ |
| 30 | #define QDIO_DOING_ESTABLISH 1 |
| 31 | #define QDIO_DOING_ACTIVATE 2 |
| 32 | #define QDIO_DOING_CLEANUP 3 |
| 33 | |
| 34 | #define SLSB_STATE_NOT_INIT 0x0 |
| 35 | #define SLSB_STATE_EMPTY 0x1 |
| 36 | #define SLSB_STATE_PRIMED 0x2 |
| 37 | #define SLSB_STATE_PENDING 0x3 |
| 38 | #define SLSB_STATE_HALTED 0xe |
| 39 | #define SLSB_STATE_ERROR 0xf |
| 40 | #define SLSB_TYPE_INPUT 0x0 |
| 41 | #define SLSB_TYPE_OUTPUT 0x20 |
| 42 | #define SLSB_OWNER_PROG 0x80 |
| 43 | #define SLSB_OWNER_CU 0x40 |
| 44 | |
| 45 | #define SLSB_P_INPUT_NOT_INIT \ |
| 46 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT) /* 0x80 */ |
| 47 | #define SLSB_P_INPUT_ACK \ |
| 48 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x81 */ |
| 49 | #define SLSB_CU_INPUT_EMPTY \ |
| 50 | (SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x41 */ |
| 51 | #define SLSB_P_INPUT_PRIMED \ |
| 52 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED) /* 0x82 */ |
| 53 | #define SLSB_P_INPUT_HALTED \ |
| 54 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED) /* 0x8e */ |
| 55 | #define SLSB_P_INPUT_ERROR \ |
| 56 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR) /* 0x8f */ |
| 57 | #define SLSB_P_OUTPUT_NOT_INIT \ |
| 58 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */ |
| 59 | #define SLSB_P_OUTPUT_EMPTY \ |
| 60 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY) /* 0xa1 */ |
| 61 | #define SLSB_P_OUTPUT_PENDING \ |
| 62 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_PENDING) /* 0xa3 */ |
| 63 | #define SLSB_CU_OUTPUT_PRIMED \ |
| 64 | (SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED) /* 0x62 */ |
| 65 | #define SLSB_P_OUTPUT_HALTED \ |
| 66 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED) /* 0xae */ |
| 67 | #define SLSB_P_OUTPUT_ERROR \ |
| 68 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR) /* 0xaf */ |
| 69 | |
| 70 | #define SLSB_ERROR_DURING_LOOKUP 0xff |
| 71 | |
| 72 | /* additional CIWs returned by extended Sense-ID */ |
| 73 | #define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */ |
| 74 | #define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */ |
| 75 | |
| 76 | /* flags for st qdio sch data */ |
| 77 | #define CHSC_FLAG_QDIO_CAPABILITY 0x80 |
| 78 | #define CHSC_FLAG_VALIDITY 0x40 |
| 79 | |
| 80 | /* SIGA flags */ |
| 81 | #define QDIO_SIGA_WRITE 0x00 |
| 82 | #define QDIO_SIGA_READ 0x01 |
| 83 | #define QDIO_SIGA_SYNC 0x02 |
| 84 | #define QDIO_SIGA_WRITEQ 0x04 |
| 85 | #define QDIO_SIGA_QEBSM_FLAG 0x80 |
| 86 | |
| 87 | #ifdef CONFIG_64BIT |
| 88 | static inline int do_sqbs(u64 token, unsigned char state, int queue, |
| 89 | int *start, int *count) |
| 90 | { |
| 91 | register unsigned long _ccq asm ("0") = *count; |
| 92 | register unsigned long _token asm ("1") = token; |
| 93 | unsigned long _queuestart = ((unsigned long)queue << 32) | *start; |
| 94 | |
| 95 | asm volatile( |
| 96 | " .insn rsy,0xeb000000008A,%1,0,0(%2)" |
| 97 | : "+d" (_ccq), "+d" (_queuestart) |
| 98 | : "d" ((unsigned long)state), "d" (_token) |
| 99 | : "memory", "cc"); |
| 100 | *count = _ccq & 0xff; |
| 101 | *start = _queuestart & 0xff; |
| 102 | |
| 103 | return (_ccq >> 32) & 0xff; |
| 104 | } |
| 105 | |
| 106 | static inline int do_eqbs(u64 token, unsigned char *state, int queue, |
| 107 | int *start, int *count, int ack) |
| 108 | { |
| 109 | register unsigned long _ccq asm ("0") = *count; |
| 110 | register unsigned long _token asm ("1") = token; |
| 111 | unsigned long _queuestart = ((unsigned long)queue << 32) | *start; |
| 112 | unsigned long _state = (unsigned long)ack << 63; |
| 113 | |
| 114 | asm volatile( |
| 115 | " .insn rrf,0xB99c0000,%1,%2,0,0" |
| 116 | : "+d" (_ccq), "+d" (_queuestart), "+d" (_state) |
| 117 | : "d" (_token) |
| 118 | : "memory", "cc"); |
| 119 | *count = _ccq & 0xff; |
| 120 | *start = _queuestart & 0xff; |
| 121 | *state = _state & 0xff; |
| 122 | |
| 123 | return (_ccq >> 32) & 0xff; |
| 124 | } |
| 125 | #else |
| 126 | static inline int do_sqbs(u64 token, unsigned char state, int queue, |
| 127 | int *start, int *count) { return 0; } |
| 128 | static inline int do_eqbs(u64 token, unsigned char *state, int queue, |
| 129 | int *start, int *count, int ack) { return 0; } |
| 130 | #endif /* CONFIG_64BIT */ |
| 131 | |
| 132 | struct qdio_irq; |
| 133 | |
| 134 | struct siga_flag { |
| 135 | u8 input:1; |
| 136 | u8 output:1; |
| 137 | u8 sync:1; |
| 138 | u8 sync_after_ai:1; |
| 139 | u8 sync_out_after_pci:1; |
| 140 | u8:3; |
| 141 | } __attribute__ ((packed)); |
| 142 | |
| 143 | struct chsc_ssqd_area { |
| 144 | struct chsc_header request; |
| 145 | u16:10; |
| 146 | u8 ssid:2; |
| 147 | u8 fmt:4; |
| 148 | u16 first_sch; |
| 149 | u16:16; |
| 150 | u16 last_sch; |
| 151 | u32:32; |
| 152 | struct chsc_header response; |
| 153 | u32:32; |
| 154 | struct qdio_ssqd_desc qdio_ssqd; |
| 155 | } __attribute__ ((packed)); |
| 156 | |
| 157 | struct scssc_area { |
| 158 | struct chsc_header request; |
| 159 | u16 operation_code; |
| 160 | u16:16; |
| 161 | u32:32; |
| 162 | u32:32; |
| 163 | u64 summary_indicator_addr; |
| 164 | u64 subchannel_indicator_addr; |
| 165 | u32 ks:4; |
| 166 | u32 kc:4; |
| 167 | u32:21; |
| 168 | u32 isc:3; |
| 169 | u32 word_with_d_bit; |
| 170 | u32:32; |
| 171 | struct subchannel_id schid; |
| 172 | u32 reserved[1004]; |
| 173 | struct chsc_header response; |
| 174 | u32:32; |
| 175 | } __attribute__ ((packed)); |
| 176 | |
| 177 | struct qdio_dev_perf_stat { |
| 178 | unsigned int adapter_int; |
| 179 | unsigned int qdio_int; |
| 180 | unsigned int pci_request_int; |
| 181 | |
| 182 | unsigned int tasklet_inbound; |
| 183 | unsigned int tasklet_inbound_resched; |
| 184 | unsigned int tasklet_inbound_resched2; |
| 185 | unsigned int tasklet_outbound; |
| 186 | |
| 187 | unsigned int siga_read; |
| 188 | unsigned int siga_write; |
| 189 | unsigned int siga_sync; |
| 190 | |
| 191 | unsigned int inbound_call; |
| 192 | unsigned int inbound_handler; |
| 193 | unsigned int stop_polling; |
| 194 | unsigned int inbound_queue_full; |
| 195 | unsigned int outbound_call; |
| 196 | unsigned int outbound_handler; |
| 197 | unsigned int outbound_queue_full; |
| 198 | unsigned int fast_requeue; |
| 199 | unsigned int target_full; |
| 200 | unsigned int eqbs; |
| 201 | unsigned int eqbs_partial; |
| 202 | unsigned int sqbs; |
| 203 | unsigned int sqbs_partial; |
| 204 | unsigned int int_discarded; |
| 205 | } ____cacheline_aligned; |
| 206 | |
| 207 | struct qdio_queue_perf_stat { |
| 208 | /* |
| 209 | * Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128. |
| 210 | * Since max. 127 SBALs are scanned reuse entry for 128 as queue full |
| 211 | * aka 127 SBALs found. |
| 212 | */ |
| 213 | unsigned int nr_sbals[8]; |
| 214 | unsigned int nr_sbal_error; |
| 215 | unsigned int nr_sbal_nop; |
| 216 | unsigned int nr_sbal_total; |
| 217 | }; |
| 218 | |
| 219 | enum qdio_queue_irq_states { |
| 220 | QDIO_QUEUE_IRQS_DISABLED, |
| 221 | }; |
| 222 | |
| 223 | struct qdio_input_q { |
| 224 | /* input buffer acknowledgement flag */ |
| 225 | int polling; |
| 226 | /* first ACK'ed buffer */ |
| 227 | int ack_start; |
| 228 | /* how much sbals are acknowledged with qebsm */ |
| 229 | int ack_count; |
| 230 | /* last time of noticing incoming data */ |
| 231 | u64 timestamp; |
| 232 | /* upper-layer polling flag */ |
| 233 | unsigned long queue_irq_state; |
| 234 | /* callback to start upper-layer polling */ |
| 235 | void (*queue_start_poll) (struct ccw_device *, int, unsigned long); |
| 236 | }; |
| 237 | |
| 238 | struct qdio_output_q { |
| 239 | /* PCIs are enabled for the queue */ |
| 240 | int pci_out_enabled; |
| 241 | /* cq: use asynchronous output buffers */ |
| 242 | int use_cq; |
| 243 | /* cq: aobs used for particual SBAL */ |
| 244 | struct qaob **aobs; |
| 245 | /* cq: sbal state related to asynchronous operation */ |
| 246 | struct qdio_outbuf_state *sbal_state; |
| 247 | /* timer to check for more outbound work */ |
| 248 | struct timer_list timer; |
| 249 | /* used SBALs before tasklet schedule */ |
| 250 | int scan_threshold; |
| 251 | }; |
| 252 | |
| 253 | /* |
| 254 | * Note on cache alignment: grouped slsb and write mostly data at the beginning |
| 255 | * sbal[] is read-only and starts on a new cacheline followed by read mostly. |
| 256 | */ |
| 257 | struct qdio_q { |
| 258 | struct slsb slsb; |
| 259 | |
| 260 | union { |
| 261 | struct qdio_input_q in; |
| 262 | struct qdio_output_q out; |
| 263 | } u; |
| 264 | |
| 265 | /* |
| 266 | * inbound: next buffer the program should check for |
| 267 | * outbound: next buffer to check if adapter processed it |
| 268 | */ |
| 269 | int first_to_check; |
| 270 | |
| 271 | /* first_to_check of the last time */ |
| 272 | int last_move; |
| 273 | |
| 274 | /* beginning position for calling the program */ |
| 275 | int first_to_kick; |
| 276 | |
| 277 | /* number of buffers in use by the adapter */ |
| 278 | atomic_t nr_buf_used; |
| 279 | |
| 280 | /* error condition during a data transfer */ |
| 281 | unsigned int qdio_error; |
| 282 | |
| 283 | /* last scan of the queue */ |
| 284 | u64 timestamp; |
| 285 | |
| 286 | struct tasklet_struct tasklet; |
| 287 | struct qdio_queue_perf_stat q_stats; |
| 288 | |
| 289 | struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned; |
| 290 | |
| 291 | /* queue number */ |
| 292 | int nr; |
| 293 | |
| 294 | /* bitmask of queue number */ |
| 295 | int mask; |
| 296 | |
| 297 | /* input or output queue */ |
| 298 | int is_input_q; |
| 299 | |
| 300 | /* list of thinint input queues */ |
| 301 | struct list_head entry; |
| 302 | |
| 303 | /* upper-layer program handler */ |
| 304 | qdio_handler_t (*handler); |
| 305 | |
| 306 | struct dentry *debugfs_q; |
| 307 | struct qdio_irq *irq_ptr; |
| 308 | struct sl *sl; |
| 309 | /* |
| 310 | * A page is allocated under this pointer and used for slib and sl. |
| 311 | * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2. |
| 312 | */ |
| 313 | struct slib *slib; |
| 314 | } __attribute__ ((aligned(256))); |
| 315 | |
| 316 | struct qdio_irq { |
| 317 | struct qib qib; |
| 318 | u32 *dsci; /* address of device state change indicator */ |
| 319 | struct ccw_device *cdev; |
| 320 | struct dentry *debugfs_dev; |
| 321 | struct dentry *debugfs_perf; |
| 322 | |
| 323 | unsigned long int_parm; |
| 324 | struct subchannel_id schid; |
| 325 | unsigned long sch_token; /* QEBSM facility */ |
| 326 | |
| 327 | enum qdio_irq_states state; |
| 328 | |
| 329 | struct siga_flag siga_flag; /* siga sync information from qdioac */ |
| 330 | |
| 331 | int nr_input_qs; |
| 332 | int nr_output_qs; |
| 333 | |
| 334 | struct ccw1 ccw; |
| 335 | struct ciw equeue; |
| 336 | struct ciw aqueue; |
| 337 | |
| 338 | struct qdio_ssqd_desc ssqd_desc; |
| 339 | void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *); |
| 340 | |
| 341 | int perf_stat_enabled; |
| 342 | |
| 343 | struct qdr *qdr; |
| 344 | unsigned long chsc_page; |
| 345 | |
| 346 | struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ]; |
| 347 | struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ]; |
| 348 | |
| 349 | debug_info_t *debug_area; |
| 350 | struct mutex setup_mutex; |
| 351 | struct qdio_dev_perf_stat perf_stat; |
| 352 | }; |
| 353 | |
| 354 | /* helper functions */ |
| 355 | #define queue_type(q) q->irq_ptr->qib.qfmt |
| 356 | #define SCH_NO(q) (q->irq_ptr->schid.sch_no) |
| 357 | |
| 358 | #define is_thinint_irq(irq) \ |
| 359 | (irq->qib.qfmt == QDIO_IQDIO_QFMT || \ |
| 360 | css_general_characteristics.aif_osa) |
| 361 | |
| 362 | #define qperf(__qdev, __attr) ((__qdev)->perf_stat.(__attr)) |
| 363 | |
| 364 | #define qperf_inc(__q, __attr) \ |
| 365 | ({ \ |
| 366 | struct qdio_irq *qdev = (__q)->irq_ptr; \ |
| 367 | if (qdev->perf_stat_enabled) \ |
| 368 | (qdev->perf_stat.__attr)++; \ |
| 369 | }) |
| 370 | |
| 371 | static inline void account_sbals_error(struct qdio_q *q, int count) |
| 372 | { |
| 373 | q->q_stats.nr_sbal_error += count; |
| 374 | q->q_stats.nr_sbal_total += count; |
| 375 | } |
| 376 | |
| 377 | /* the highest iqdio queue is used for multicast */ |
| 378 | static inline int multicast_outbound(struct qdio_q *q) |
| 379 | { |
| 380 | return (q->irq_ptr->nr_output_qs > 1) && |
| 381 | (q->nr == q->irq_ptr->nr_output_qs - 1); |
| 382 | } |
| 383 | |
| 384 | #define pci_out_supported(q) \ |
| 385 | (q->irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED) |
| 386 | #define is_qebsm(q) (q->irq_ptr->sch_token != 0) |
| 387 | |
| 388 | #define need_siga_in(q) (q->irq_ptr->siga_flag.input) |
| 389 | #define need_siga_out(q) (q->irq_ptr->siga_flag.output) |
| 390 | #define need_siga_sync(q) (unlikely(q->irq_ptr->siga_flag.sync)) |
| 391 | #define need_siga_sync_after_ai(q) \ |
| 392 | (unlikely(q->irq_ptr->siga_flag.sync_after_ai)) |
| 393 | #define need_siga_sync_out_after_pci(q) \ |
| 394 | (unlikely(q->irq_ptr->siga_flag.sync_out_after_pci)) |
| 395 | |
| 396 | #define for_each_input_queue(irq_ptr, q, i) \ |
| 397 | for (i = 0, q = irq_ptr->input_qs[0]; \ |
| 398 | i < irq_ptr->nr_input_qs; \ |
| 399 | q = irq_ptr->input_qs[++i]) |
| 400 | #define for_each_output_queue(irq_ptr, q, i) \ |
| 401 | for (i = 0, q = irq_ptr->output_qs[0]; \ |
| 402 | i < irq_ptr->nr_output_qs; \ |
| 403 | q = irq_ptr->output_qs[++i]) |
| 404 | |
| 405 | #define prev_buf(bufnr) \ |
| 406 | ((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK) |
| 407 | #define next_buf(bufnr) \ |
| 408 | ((bufnr + 1) & QDIO_MAX_BUFFERS_MASK) |
| 409 | #define add_buf(bufnr, inc) \ |
| 410 | ((bufnr + inc) & QDIO_MAX_BUFFERS_MASK) |
| 411 | #define sub_buf(bufnr, dec) \ |
| 412 | ((bufnr - dec) & QDIO_MAX_BUFFERS_MASK) |
| 413 | |
| 414 | #define queue_irqs_enabled(q) \ |
| 415 | (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0) |
| 416 | #define queue_irqs_disabled(q) \ |
| 417 | (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0) |
| 418 | |
| 419 | extern u64 last_ai_time; |
| 420 | |
| 421 | /* prototypes for thin interrupt */ |
| 422 | void qdio_setup_thinint(struct qdio_irq *irq_ptr); |
| 423 | int qdio_establish_thinint(struct qdio_irq *irq_ptr); |
| 424 | void qdio_shutdown_thinint(struct qdio_irq *irq_ptr); |
| 425 | void tiqdio_add_input_queues(struct qdio_irq *irq_ptr); |
| 426 | void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr); |
| 427 | void tiqdio_inbound_processing(unsigned long q); |
| 428 | int tiqdio_allocate_memory(void); |
| 429 | void tiqdio_free_memory(void); |
| 430 | int tiqdio_register_thinints(void); |
| 431 | void tiqdio_unregister_thinints(void); |
| 432 | void clear_nonshared_ind(struct qdio_irq *); |
| 433 | int test_nonshared_ind(struct qdio_irq *); |
| 434 | |
| 435 | /* prototypes for setup */ |
| 436 | void qdio_inbound_processing(unsigned long data); |
| 437 | void qdio_outbound_processing(unsigned long data); |
| 438 | void qdio_outbound_timer(unsigned long data); |
| 439 | void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm, |
| 440 | struct irb *irb); |
| 441 | int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs, |
| 442 | int nr_output_qs); |
| 443 | void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr); |
| 444 | int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr, |
| 445 | struct subchannel_id *schid, |
| 446 | struct qdio_ssqd_desc *data); |
| 447 | int qdio_setup_irq(struct qdio_initialize *init_data); |
| 448 | void qdio_print_subchannel_info(struct qdio_irq *irq_ptr, |
| 449 | struct ccw_device *cdev); |
| 450 | void qdio_release_memory(struct qdio_irq *irq_ptr); |
| 451 | int qdio_setup_create_sysfs(struct ccw_device *cdev); |
| 452 | void qdio_setup_destroy_sysfs(struct ccw_device *cdev); |
| 453 | int qdio_setup_init(void); |
| 454 | void qdio_setup_exit(void); |
| 455 | int qdio_enable_async_operation(struct qdio_output_q *q); |
| 456 | void qdio_disable_async_operation(struct qdio_output_q *q); |
| 457 | struct qaob *qdio_allocate_aob(void); |
| 458 | |
| 459 | int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr, |
| 460 | unsigned char *state); |
| 461 | #endif /* _CIO_QDIO_H */ |