| 1 | /* |
| 2 | * SuperH On-Chip RTC Support |
| 3 | * |
| 4 | * Copyright (C) 2006 - 2009 Paul Mundt |
| 5 | * Copyright (C) 2006 Jamie Lenehan |
| 6 | * Copyright (C) 2008 Angelo Castello |
| 7 | * |
| 8 | * Based on the old arch/sh/kernel/cpu/rtc.c by: |
| 9 | * |
| 10 | * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> |
| 11 | * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka |
| 12 | * |
| 13 | * This file is subject to the terms and conditions of the GNU General Public |
| 14 | * License. See the file "COPYING" in the main directory of this archive |
| 15 | * for more details. |
| 16 | */ |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/bcd.h> |
| 20 | #include <linux/rtc.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/seq_file.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/spinlock.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/log2.h> |
| 28 | #include <linux/clk.h> |
| 29 | #include <linux/slab.h> |
| 30 | #include <asm/rtc.h> |
| 31 | |
| 32 | #define DRV_NAME "sh-rtc" |
| 33 | #define DRV_VERSION "0.2.3" |
| 34 | |
| 35 | #define RTC_REG(r) ((r) * rtc_reg_size) |
| 36 | |
| 37 | #define R64CNT RTC_REG(0) |
| 38 | |
| 39 | #define RSECCNT RTC_REG(1) /* RTC sec */ |
| 40 | #define RMINCNT RTC_REG(2) /* RTC min */ |
| 41 | #define RHRCNT RTC_REG(3) /* RTC hour */ |
| 42 | #define RWKCNT RTC_REG(4) /* RTC week */ |
| 43 | #define RDAYCNT RTC_REG(5) /* RTC day */ |
| 44 | #define RMONCNT RTC_REG(6) /* RTC month */ |
| 45 | #define RYRCNT RTC_REG(7) /* RTC year */ |
| 46 | #define RSECAR RTC_REG(8) /* ALARM sec */ |
| 47 | #define RMINAR RTC_REG(9) /* ALARM min */ |
| 48 | #define RHRAR RTC_REG(10) /* ALARM hour */ |
| 49 | #define RWKAR RTC_REG(11) /* ALARM week */ |
| 50 | #define RDAYAR RTC_REG(12) /* ALARM day */ |
| 51 | #define RMONAR RTC_REG(13) /* ALARM month */ |
| 52 | #define RCR1 RTC_REG(14) /* Control */ |
| 53 | #define RCR2 RTC_REG(15) /* Control */ |
| 54 | |
| 55 | /* |
| 56 | * Note on RYRAR and RCR3: Up until this point most of the register |
| 57 | * definitions are consistent across all of the available parts. However, |
| 58 | * the placement of the optional RYRAR and RCR3 (the RYRAR control |
| 59 | * register used to control RYRCNT/RYRAR compare) varies considerably |
| 60 | * across various parts, occasionally being mapped in to a completely |
| 61 | * unrelated address space. For proper RYRAR support a separate resource |
| 62 | * would have to be handed off, but as this is purely optional in |
| 63 | * practice, we simply opt not to support it, thereby keeping the code |
| 64 | * quite a bit more simplified. |
| 65 | */ |
| 66 | |
| 67 | /* ALARM Bits - or with BCD encoded value */ |
| 68 | #define AR_ENB 0x80 /* Enable for alarm cmp */ |
| 69 | |
| 70 | /* Period Bits */ |
| 71 | #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */ |
| 72 | #define PF_COUNT 0x200 /* Half periodic counter */ |
| 73 | #define PF_OXS 0x400 /* Periodic One x Second */ |
| 74 | #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */ |
| 75 | #define PF_MASK 0xf00 |
| 76 | |
| 77 | /* RCR1 Bits */ |
| 78 | #define RCR1_CF 0x80 /* Carry Flag */ |
| 79 | #define RCR1_CIE 0x10 /* Carry Interrupt Enable */ |
| 80 | #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ |
| 81 | #define RCR1_AF 0x01 /* Alarm Flag */ |
| 82 | |
| 83 | /* RCR2 Bits */ |
| 84 | #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ |
| 85 | #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ |
| 86 | #define RCR2_RTCEN 0x08 /* ENable RTC */ |
| 87 | #define RCR2_ADJ 0x04 /* ADJustment (30-second) */ |
| 88 | #define RCR2_RESET 0x02 /* Reset bit */ |
| 89 | #define RCR2_START 0x01 /* Start bit */ |
| 90 | |
| 91 | struct sh_rtc { |
| 92 | void __iomem *regbase; |
| 93 | unsigned long regsize; |
| 94 | struct resource *res; |
| 95 | int alarm_irq; |
| 96 | int periodic_irq; |
| 97 | int carry_irq; |
| 98 | struct clk *clk; |
| 99 | struct rtc_device *rtc_dev; |
| 100 | spinlock_t lock; |
| 101 | unsigned long capabilities; /* See asm/rtc.h for cap bits */ |
| 102 | unsigned short periodic_freq; |
| 103 | }; |
| 104 | |
| 105 | static int __sh_rtc_interrupt(struct sh_rtc *rtc) |
| 106 | { |
| 107 | unsigned int tmp, pending; |
| 108 | |
| 109 | tmp = readb(rtc->regbase + RCR1); |
| 110 | pending = tmp & RCR1_CF; |
| 111 | tmp &= ~RCR1_CF; |
| 112 | writeb(tmp, rtc->regbase + RCR1); |
| 113 | |
| 114 | /* Users have requested One x Second IRQ */ |
| 115 | if (pending && rtc->periodic_freq & PF_OXS) |
| 116 | rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); |
| 117 | |
| 118 | return pending; |
| 119 | } |
| 120 | |
| 121 | static int __sh_rtc_alarm(struct sh_rtc *rtc) |
| 122 | { |
| 123 | unsigned int tmp, pending; |
| 124 | |
| 125 | tmp = readb(rtc->regbase + RCR1); |
| 126 | pending = tmp & RCR1_AF; |
| 127 | tmp &= ~(RCR1_AF | RCR1_AIE); |
| 128 | writeb(tmp, rtc->regbase + RCR1); |
| 129 | |
| 130 | if (pending) |
| 131 | rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); |
| 132 | |
| 133 | return pending; |
| 134 | } |
| 135 | |
| 136 | static int __sh_rtc_periodic(struct sh_rtc *rtc) |
| 137 | { |
| 138 | struct rtc_device *rtc_dev = rtc->rtc_dev; |
| 139 | struct rtc_task *irq_task; |
| 140 | unsigned int tmp, pending; |
| 141 | |
| 142 | tmp = readb(rtc->regbase + RCR2); |
| 143 | pending = tmp & RCR2_PEF; |
| 144 | tmp &= ~RCR2_PEF; |
| 145 | writeb(tmp, rtc->regbase + RCR2); |
| 146 | |
| 147 | if (!pending) |
| 148 | return 0; |
| 149 | |
| 150 | /* Half period enabled than one skipped and the next notified */ |
| 151 | if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT)) |
| 152 | rtc->periodic_freq &= ~PF_COUNT; |
| 153 | else { |
| 154 | if (rtc->periodic_freq & PF_HP) |
| 155 | rtc->periodic_freq |= PF_COUNT; |
| 156 | if (rtc->periodic_freq & PF_KOU) { |
| 157 | spin_lock(&rtc_dev->irq_task_lock); |
| 158 | irq_task = rtc_dev->irq_task; |
| 159 | if (irq_task) |
| 160 | irq_task->func(irq_task->private_data); |
| 161 | spin_unlock(&rtc_dev->irq_task_lock); |
| 162 | } else |
| 163 | rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF); |
| 164 | } |
| 165 | |
| 166 | return pending; |
| 167 | } |
| 168 | |
| 169 | static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id) |
| 170 | { |
| 171 | struct sh_rtc *rtc = dev_id; |
| 172 | int ret; |
| 173 | |
| 174 | spin_lock(&rtc->lock); |
| 175 | ret = __sh_rtc_interrupt(rtc); |
| 176 | spin_unlock(&rtc->lock); |
| 177 | |
| 178 | return IRQ_RETVAL(ret); |
| 179 | } |
| 180 | |
| 181 | static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) |
| 182 | { |
| 183 | struct sh_rtc *rtc = dev_id; |
| 184 | int ret; |
| 185 | |
| 186 | spin_lock(&rtc->lock); |
| 187 | ret = __sh_rtc_alarm(rtc); |
| 188 | spin_unlock(&rtc->lock); |
| 189 | |
| 190 | return IRQ_RETVAL(ret); |
| 191 | } |
| 192 | |
| 193 | static irqreturn_t sh_rtc_periodic(int irq, void *dev_id) |
| 194 | { |
| 195 | struct sh_rtc *rtc = dev_id; |
| 196 | int ret; |
| 197 | |
| 198 | spin_lock(&rtc->lock); |
| 199 | ret = __sh_rtc_periodic(rtc); |
| 200 | spin_unlock(&rtc->lock); |
| 201 | |
| 202 | return IRQ_RETVAL(ret); |
| 203 | } |
| 204 | |
| 205 | static irqreturn_t sh_rtc_shared(int irq, void *dev_id) |
| 206 | { |
| 207 | struct sh_rtc *rtc = dev_id; |
| 208 | int ret; |
| 209 | |
| 210 | spin_lock(&rtc->lock); |
| 211 | ret = __sh_rtc_interrupt(rtc); |
| 212 | ret |= __sh_rtc_alarm(rtc); |
| 213 | ret |= __sh_rtc_periodic(rtc); |
| 214 | spin_unlock(&rtc->lock); |
| 215 | |
| 216 | return IRQ_RETVAL(ret); |
| 217 | } |
| 218 | |
| 219 | static int sh_rtc_irq_set_state(struct device *dev, int enable) |
| 220 | { |
| 221 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
| 222 | unsigned int tmp; |
| 223 | |
| 224 | spin_lock_irq(&rtc->lock); |
| 225 | |
| 226 | tmp = readb(rtc->regbase + RCR2); |
| 227 | |
| 228 | if (enable) { |
| 229 | rtc->periodic_freq |= PF_KOU; |
| 230 | tmp &= ~RCR2_PEF; /* Clear PES bit */ |
| 231 | tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */ |
| 232 | } else { |
| 233 | rtc->periodic_freq &= ~PF_KOU; |
| 234 | tmp &= ~(RCR2_PESMASK | RCR2_PEF); |
| 235 | } |
| 236 | |
| 237 | writeb(tmp, rtc->regbase + RCR2); |
| 238 | |
| 239 | spin_unlock_irq(&rtc->lock); |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | static int sh_rtc_irq_set_freq(struct device *dev, int freq) |
| 245 | { |
| 246 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
| 247 | int tmp, ret = 0; |
| 248 | |
| 249 | spin_lock_irq(&rtc->lock); |
| 250 | tmp = rtc->periodic_freq & PF_MASK; |
| 251 | |
| 252 | switch (freq) { |
| 253 | case 0: |
| 254 | rtc->periodic_freq = 0x00; |
| 255 | break; |
| 256 | case 1: |
| 257 | rtc->periodic_freq = 0x60; |
| 258 | break; |
| 259 | case 2: |
| 260 | rtc->periodic_freq = 0x50; |
| 261 | break; |
| 262 | case 4: |
| 263 | rtc->periodic_freq = 0x40; |
| 264 | break; |
| 265 | case 8: |
| 266 | rtc->periodic_freq = 0x30 | PF_HP; |
| 267 | break; |
| 268 | case 16: |
| 269 | rtc->periodic_freq = 0x30; |
| 270 | break; |
| 271 | case 32: |
| 272 | rtc->periodic_freq = 0x20 | PF_HP; |
| 273 | break; |
| 274 | case 64: |
| 275 | rtc->periodic_freq = 0x20; |
| 276 | break; |
| 277 | case 128: |
| 278 | rtc->periodic_freq = 0x10 | PF_HP; |
| 279 | break; |
| 280 | case 256: |
| 281 | rtc->periodic_freq = 0x10; |
| 282 | break; |
| 283 | default: |
| 284 | ret = -ENOTSUPP; |
| 285 | } |
| 286 | |
| 287 | if (ret == 0) |
| 288 | rtc->periodic_freq |= tmp; |
| 289 | |
| 290 | spin_unlock_irq(&rtc->lock); |
| 291 | return ret; |
| 292 | } |
| 293 | |
| 294 | static inline void sh_rtc_setaie(struct device *dev, unsigned int enable) |
| 295 | { |
| 296 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
| 297 | unsigned int tmp; |
| 298 | |
| 299 | spin_lock_irq(&rtc->lock); |
| 300 | |
| 301 | tmp = readb(rtc->regbase + RCR1); |
| 302 | |
| 303 | if (enable) |
| 304 | tmp |= RCR1_AIE; |
| 305 | else |
| 306 | tmp &= ~RCR1_AIE; |
| 307 | |
| 308 | writeb(tmp, rtc->regbase + RCR1); |
| 309 | |
| 310 | spin_unlock_irq(&rtc->lock); |
| 311 | } |
| 312 | |
| 313 | static int sh_rtc_proc(struct device *dev, struct seq_file *seq) |
| 314 | { |
| 315 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
| 316 | unsigned int tmp; |
| 317 | |
| 318 | tmp = readb(rtc->regbase + RCR1); |
| 319 | seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no"); |
| 320 | |
| 321 | tmp = readb(rtc->regbase + RCR2); |
| 322 | seq_printf(seq, "periodic_IRQ\t: %s\n", |
| 323 | (tmp & RCR2_PESMASK) ? "yes" : "no"); |
| 324 | |
| 325 | return 0; |
| 326 | } |
| 327 | |
| 328 | static inline void sh_rtc_setcie(struct device *dev, unsigned int enable) |
| 329 | { |
| 330 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
| 331 | unsigned int tmp; |
| 332 | |
| 333 | spin_lock_irq(&rtc->lock); |
| 334 | |
| 335 | tmp = readb(rtc->regbase + RCR1); |
| 336 | |
| 337 | if (!enable) |
| 338 | tmp &= ~RCR1_CIE; |
| 339 | else |
| 340 | tmp |= RCR1_CIE; |
| 341 | |
| 342 | writeb(tmp, rtc->regbase + RCR1); |
| 343 | |
| 344 | spin_unlock_irq(&rtc->lock); |
| 345 | } |
| 346 | |
| 347 | static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) |
| 348 | { |
| 349 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
| 350 | unsigned int ret = 0; |
| 351 | |
| 352 | switch (cmd) { |
| 353 | case RTC_AIE_OFF: |
| 354 | case RTC_AIE_ON: |
| 355 | sh_rtc_setaie(dev, cmd == RTC_AIE_ON); |
| 356 | break; |
| 357 | case RTC_UIE_OFF: |
| 358 | rtc->periodic_freq &= ~PF_OXS; |
| 359 | sh_rtc_setcie(dev, 0); |
| 360 | break; |
| 361 | case RTC_UIE_ON: |
| 362 | rtc->periodic_freq |= PF_OXS; |
| 363 | sh_rtc_setcie(dev, 1); |
| 364 | break; |
| 365 | default: |
| 366 | ret = -ENOIOCTLCMD; |
| 367 | } |
| 368 | |
| 369 | return ret; |
| 370 | } |
| 371 | |
| 372 | static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm) |
| 373 | { |
| 374 | struct platform_device *pdev = to_platform_device(dev); |
| 375 | struct sh_rtc *rtc = platform_get_drvdata(pdev); |
| 376 | unsigned int sec128, sec2, yr, yr100, cf_bit; |
| 377 | |
| 378 | do { |
| 379 | unsigned int tmp; |
| 380 | |
| 381 | spin_lock_irq(&rtc->lock); |
| 382 | |
| 383 | tmp = readb(rtc->regbase + RCR1); |
| 384 | tmp &= ~RCR1_CF; /* Clear CF-bit */ |
| 385 | tmp |= RCR1_CIE; |
| 386 | writeb(tmp, rtc->regbase + RCR1); |
| 387 | |
| 388 | sec128 = readb(rtc->regbase + R64CNT); |
| 389 | |
| 390 | tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT)); |
| 391 | tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT)); |
| 392 | tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT)); |
| 393 | tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT)); |
| 394 | tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT)); |
| 395 | tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1; |
| 396 | |
| 397 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
| 398 | yr = readw(rtc->regbase + RYRCNT); |
| 399 | yr100 = bcd2bin(yr >> 8); |
| 400 | yr &= 0xff; |
| 401 | } else { |
| 402 | yr = readb(rtc->regbase + RYRCNT); |
| 403 | yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20); |
| 404 | } |
| 405 | |
| 406 | tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900; |
| 407 | |
| 408 | sec2 = readb(rtc->regbase + R64CNT); |
| 409 | cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF; |
| 410 | |
| 411 | spin_unlock_irq(&rtc->lock); |
| 412 | } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); |
| 413 | |
| 414 | #if RTC_BIT_INVERTED != 0 |
| 415 | if ((sec128 & RTC_BIT_INVERTED)) |
| 416 | tm->tm_sec--; |
| 417 | #endif |
| 418 | |
| 419 | /* only keep the carry interrupt enabled if UIE is on */ |
| 420 | if (!(rtc->periodic_freq & PF_OXS)) |
| 421 | sh_rtc_setcie(dev, 0); |
| 422 | |
| 423 | dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " |
| 424 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
| 425 | __func__, |
| 426 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
| 427 | tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); |
| 428 | |
| 429 | return rtc_valid_tm(tm); |
| 430 | } |
| 431 | |
| 432 | static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) |
| 433 | { |
| 434 | struct platform_device *pdev = to_platform_device(dev); |
| 435 | struct sh_rtc *rtc = platform_get_drvdata(pdev); |
| 436 | unsigned int tmp; |
| 437 | int year; |
| 438 | |
| 439 | spin_lock_irq(&rtc->lock); |
| 440 | |
| 441 | /* Reset pre-scaler & stop RTC */ |
| 442 | tmp = readb(rtc->regbase + RCR2); |
| 443 | tmp |= RCR2_RESET; |
| 444 | tmp &= ~RCR2_START; |
| 445 | writeb(tmp, rtc->regbase + RCR2); |
| 446 | |
| 447 | writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT); |
| 448 | writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT); |
| 449 | writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT); |
| 450 | writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT); |
| 451 | writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT); |
| 452 | writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT); |
| 453 | |
| 454 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
| 455 | year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) | |
| 456 | bin2bcd(tm->tm_year % 100); |
| 457 | writew(year, rtc->regbase + RYRCNT); |
| 458 | } else { |
| 459 | year = tm->tm_year % 100; |
| 460 | writeb(bin2bcd(year), rtc->regbase + RYRCNT); |
| 461 | } |
| 462 | |
| 463 | /* Start RTC */ |
| 464 | tmp = readb(rtc->regbase + RCR2); |
| 465 | tmp &= ~RCR2_RESET; |
| 466 | tmp |= RCR2_RTCEN | RCR2_START; |
| 467 | writeb(tmp, rtc->regbase + RCR2); |
| 468 | |
| 469 | spin_unlock_irq(&rtc->lock); |
| 470 | |
| 471 | return 0; |
| 472 | } |
| 473 | |
| 474 | static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) |
| 475 | { |
| 476 | unsigned int byte; |
| 477 | int value = 0xff; /* return 0xff for ignored values */ |
| 478 | |
| 479 | byte = readb(rtc->regbase + reg_off); |
| 480 | if (byte & AR_ENB) { |
| 481 | byte &= ~AR_ENB; /* strip the enable bit */ |
| 482 | value = bcd2bin(byte); |
| 483 | } |
| 484 | |
| 485 | return value; |
| 486 | } |
| 487 | |
| 488 | static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) |
| 489 | { |
| 490 | struct platform_device *pdev = to_platform_device(dev); |
| 491 | struct sh_rtc *rtc = platform_get_drvdata(pdev); |
| 492 | struct rtc_time *tm = &wkalrm->time; |
| 493 | |
| 494 | spin_lock_irq(&rtc->lock); |
| 495 | |
| 496 | tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR); |
| 497 | tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR); |
| 498 | tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR); |
| 499 | tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR); |
| 500 | tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR); |
| 501 | tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR); |
| 502 | if (tm->tm_mon > 0) |
| 503 | tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ |
| 504 | tm->tm_year = 0xffff; |
| 505 | |
| 506 | wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0; |
| 507 | |
| 508 | spin_unlock_irq(&rtc->lock); |
| 509 | |
| 510 | return 0; |
| 511 | } |
| 512 | |
| 513 | static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc, |
| 514 | int value, int reg_off) |
| 515 | { |
| 516 | /* < 0 for a value that is ignored */ |
| 517 | if (value < 0) |
| 518 | writeb(0, rtc->regbase + reg_off); |
| 519 | else |
| 520 | writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); |
| 521 | } |
| 522 | |
| 523 | static int sh_rtc_check_alarm(struct rtc_time *tm) |
| 524 | { |
| 525 | /* |
| 526 | * The original rtc says anything > 0xc0 is "don't care" or "match |
| 527 | * all" - most users use 0xff but rtc-dev uses -1 for the same thing. |
| 528 | * The original rtc doesn't support years - some things use -1 and |
| 529 | * some 0xffff. We use -1 to make out tests easier. |
| 530 | */ |
| 531 | if (tm->tm_year == 0xffff) |
| 532 | tm->tm_year = -1; |
| 533 | if (tm->tm_mon >= 0xff) |
| 534 | tm->tm_mon = -1; |
| 535 | if (tm->tm_mday >= 0xff) |
| 536 | tm->tm_mday = -1; |
| 537 | if (tm->tm_wday >= 0xff) |
| 538 | tm->tm_wday = -1; |
| 539 | if (tm->tm_hour >= 0xff) |
| 540 | tm->tm_hour = -1; |
| 541 | if (tm->tm_min >= 0xff) |
| 542 | tm->tm_min = -1; |
| 543 | if (tm->tm_sec >= 0xff) |
| 544 | tm->tm_sec = -1; |
| 545 | |
| 546 | if (tm->tm_year > 9999 || |
| 547 | tm->tm_mon >= 12 || |
| 548 | tm->tm_mday == 0 || tm->tm_mday >= 32 || |
| 549 | tm->tm_wday >= 7 || |
| 550 | tm->tm_hour >= 24 || |
| 551 | tm->tm_min >= 60 || |
| 552 | tm->tm_sec >= 60) |
| 553 | return -EINVAL; |
| 554 | |
| 555 | return 0; |
| 556 | } |
| 557 | |
| 558 | static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) |
| 559 | { |
| 560 | struct platform_device *pdev = to_platform_device(dev); |
| 561 | struct sh_rtc *rtc = platform_get_drvdata(pdev); |
| 562 | unsigned int rcr1; |
| 563 | struct rtc_time *tm = &wkalrm->time; |
| 564 | int mon, err; |
| 565 | |
| 566 | err = sh_rtc_check_alarm(tm); |
| 567 | if (unlikely(err < 0)) |
| 568 | return err; |
| 569 | |
| 570 | spin_lock_irq(&rtc->lock); |
| 571 | |
| 572 | /* disable alarm interrupt and clear the alarm flag */ |
| 573 | rcr1 = readb(rtc->regbase + RCR1); |
| 574 | rcr1 &= ~(RCR1_AF | RCR1_AIE); |
| 575 | writeb(rcr1, rtc->regbase + RCR1); |
| 576 | |
| 577 | /* set alarm time */ |
| 578 | sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR); |
| 579 | sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR); |
| 580 | sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR); |
| 581 | sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR); |
| 582 | sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR); |
| 583 | mon = tm->tm_mon; |
| 584 | if (mon >= 0) |
| 585 | mon += 1; |
| 586 | sh_rtc_write_alarm_value(rtc, mon, RMONAR); |
| 587 | |
| 588 | if (wkalrm->enabled) { |
| 589 | rcr1 |= RCR1_AIE; |
| 590 | writeb(rcr1, rtc->regbase + RCR1); |
| 591 | } |
| 592 | |
| 593 | spin_unlock_irq(&rtc->lock); |
| 594 | |
| 595 | return 0; |
| 596 | } |
| 597 | |
| 598 | static struct rtc_class_ops sh_rtc_ops = { |
| 599 | .ioctl = sh_rtc_ioctl, |
| 600 | .read_time = sh_rtc_read_time, |
| 601 | .set_time = sh_rtc_set_time, |
| 602 | .read_alarm = sh_rtc_read_alarm, |
| 603 | .set_alarm = sh_rtc_set_alarm, |
| 604 | .irq_set_state = sh_rtc_irq_set_state, |
| 605 | .irq_set_freq = sh_rtc_irq_set_freq, |
| 606 | .proc = sh_rtc_proc, |
| 607 | }; |
| 608 | |
| 609 | static int __init sh_rtc_probe(struct platform_device *pdev) |
| 610 | { |
| 611 | struct sh_rtc *rtc; |
| 612 | struct resource *res; |
| 613 | struct rtc_time r; |
| 614 | char clk_name[6]; |
| 615 | int clk_id, ret; |
| 616 | |
| 617 | rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL); |
| 618 | if (unlikely(!rtc)) |
| 619 | return -ENOMEM; |
| 620 | |
| 621 | spin_lock_init(&rtc->lock); |
| 622 | |
| 623 | /* get periodic/carry/alarm irqs */ |
| 624 | ret = platform_get_irq(pdev, 0); |
| 625 | if (unlikely(ret <= 0)) { |
| 626 | ret = -ENOENT; |
| 627 | dev_err(&pdev->dev, "No IRQ resource\n"); |
| 628 | goto err_badres; |
| 629 | } |
| 630 | |
| 631 | rtc->periodic_irq = ret; |
| 632 | rtc->carry_irq = platform_get_irq(pdev, 1); |
| 633 | rtc->alarm_irq = platform_get_irq(pdev, 2); |
| 634 | |
| 635 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); |
| 636 | if (unlikely(res == NULL)) { |
| 637 | ret = -ENOENT; |
| 638 | dev_err(&pdev->dev, "No IO resource\n"); |
| 639 | goto err_badres; |
| 640 | } |
| 641 | |
| 642 | rtc->regsize = resource_size(res); |
| 643 | |
| 644 | rtc->res = request_mem_region(res->start, rtc->regsize, pdev->name); |
| 645 | if (unlikely(!rtc->res)) { |
| 646 | ret = -EBUSY; |
| 647 | goto err_badres; |
| 648 | } |
| 649 | |
| 650 | rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize); |
| 651 | if (unlikely(!rtc->regbase)) { |
| 652 | ret = -EINVAL; |
| 653 | goto err_badmap; |
| 654 | } |
| 655 | |
| 656 | clk_id = pdev->id; |
| 657 | /* With a single device, the clock id is still "rtc0" */ |
| 658 | if (clk_id < 0) |
| 659 | clk_id = 0; |
| 660 | |
| 661 | snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); |
| 662 | |
| 663 | rtc->clk = clk_get(&pdev->dev, clk_name); |
| 664 | if (IS_ERR(rtc->clk)) { |
| 665 | /* |
| 666 | * No error handling for rtc->clk intentionally, not all |
| 667 | * platforms will have a unique clock for the RTC, and |
| 668 | * the clk API can handle the struct clk pointer being |
| 669 | * NULL. |
| 670 | */ |
| 671 | rtc->clk = NULL; |
| 672 | } |
| 673 | |
| 674 | clk_enable(rtc->clk); |
| 675 | |
| 676 | rtc->capabilities = RTC_DEF_CAPABILITIES; |
| 677 | if (pdev->dev.platform_data) { |
| 678 | struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data; |
| 679 | |
| 680 | /* |
| 681 | * Some CPUs have special capabilities in addition to the |
| 682 | * default set. Add those in here. |
| 683 | */ |
| 684 | rtc->capabilities |= pinfo->capabilities; |
| 685 | } |
| 686 | |
| 687 | if (rtc->carry_irq <= 0) { |
| 688 | /* register shared periodic/carry/alarm irq */ |
| 689 | ret = request_irq(rtc->periodic_irq, sh_rtc_shared, |
| 690 | IRQF_DISABLED, "sh-rtc", rtc); |
| 691 | if (unlikely(ret)) { |
| 692 | dev_err(&pdev->dev, |
| 693 | "request IRQ failed with %d, IRQ %d\n", ret, |
| 694 | rtc->periodic_irq); |
| 695 | goto err_unmap; |
| 696 | } |
| 697 | } else { |
| 698 | /* register periodic/carry/alarm irqs */ |
| 699 | ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, |
| 700 | IRQF_DISABLED, "sh-rtc period", rtc); |
| 701 | if (unlikely(ret)) { |
| 702 | dev_err(&pdev->dev, |
| 703 | "request period IRQ failed with %d, IRQ %d\n", |
| 704 | ret, rtc->periodic_irq); |
| 705 | goto err_unmap; |
| 706 | } |
| 707 | |
| 708 | ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, |
| 709 | IRQF_DISABLED, "sh-rtc carry", rtc); |
| 710 | if (unlikely(ret)) { |
| 711 | dev_err(&pdev->dev, |
| 712 | "request carry IRQ failed with %d, IRQ %d\n", |
| 713 | ret, rtc->carry_irq); |
| 714 | free_irq(rtc->periodic_irq, rtc); |
| 715 | goto err_unmap; |
| 716 | } |
| 717 | |
| 718 | ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, |
| 719 | IRQF_DISABLED, "sh-rtc alarm", rtc); |
| 720 | if (unlikely(ret)) { |
| 721 | dev_err(&pdev->dev, |
| 722 | "request alarm IRQ failed with %d, IRQ %d\n", |
| 723 | ret, rtc->alarm_irq); |
| 724 | free_irq(rtc->carry_irq, rtc); |
| 725 | free_irq(rtc->periodic_irq, rtc); |
| 726 | goto err_unmap; |
| 727 | } |
| 728 | } |
| 729 | |
| 730 | platform_set_drvdata(pdev, rtc); |
| 731 | |
| 732 | /* everything disabled by default */ |
| 733 | sh_rtc_irq_set_freq(&pdev->dev, 0); |
| 734 | sh_rtc_irq_set_state(&pdev->dev, 0); |
| 735 | sh_rtc_setaie(&pdev->dev, 0); |
| 736 | sh_rtc_setcie(&pdev->dev, 0); |
| 737 | |
| 738 | rtc->rtc_dev = rtc_device_register("sh", &pdev->dev, |
| 739 | &sh_rtc_ops, THIS_MODULE); |
| 740 | if (IS_ERR(rtc->rtc_dev)) { |
| 741 | ret = PTR_ERR(rtc->rtc_dev); |
| 742 | free_irq(rtc->periodic_irq, rtc); |
| 743 | free_irq(rtc->carry_irq, rtc); |
| 744 | free_irq(rtc->alarm_irq, rtc); |
| 745 | goto err_unmap; |
| 746 | } |
| 747 | |
| 748 | rtc->rtc_dev->max_user_freq = 256; |
| 749 | |
| 750 | /* reset rtc to epoch 0 if time is invalid */ |
| 751 | if (rtc_read_time(rtc->rtc_dev, &r) < 0) { |
| 752 | rtc_time_to_tm(0, &r); |
| 753 | rtc_set_time(rtc->rtc_dev, &r); |
| 754 | } |
| 755 | |
| 756 | device_init_wakeup(&pdev->dev, 1); |
| 757 | return 0; |
| 758 | |
| 759 | err_unmap: |
| 760 | clk_disable(rtc->clk); |
| 761 | clk_put(rtc->clk); |
| 762 | iounmap(rtc->regbase); |
| 763 | err_badmap: |
| 764 | release_resource(rtc->res); |
| 765 | err_badres: |
| 766 | kfree(rtc); |
| 767 | |
| 768 | return ret; |
| 769 | } |
| 770 | |
| 771 | static int __exit sh_rtc_remove(struct platform_device *pdev) |
| 772 | { |
| 773 | struct sh_rtc *rtc = platform_get_drvdata(pdev); |
| 774 | |
| 775 | rtc_device_unregister(rtc->rtc_dev); |
| 776 | sh_rtc_irq_set_state(&pdev->dev, 0); |
| 777 | |
| 778 | sh_rtc_setaie(&pdev->dev, 0); |
| 779 | sh_rtc_setcie(&pdev->dev, 0); |
| 780 | |
| 781 | free_irq(rtc->periodic_irq, rtc); |
| 782 | |
| 783 | if (rtc->carry_irq > 0) { |
| 784 | free_irq(rtc->carry_irq, rtc); |
| 785 | free_irq(rtc->alarm_irq, rtc); |
| 786 | } |
| 787 | |
| 788 | iounmap(rtc->regbase); |
| 789 | release_resource(rtc->res); |
| 790 | |
| 791 | clk_disable(rtc->clk); |
| 792 | clk_put(rtc->clk); |
| 793 | |
| 794 | platform_set_drvdata(pdev, NULL); |
| 795 | |
| 796 | kfree(rtc); |
| 797 | |
| 798 | return 0; |
| 799 | } |
| 800 | |
| 801 | static void sh_rtc_set_irq_wake(struct device *dev, int enabled) |
| 802 | { |
| 803 | struct platform_device *pdev = to_platform_device(dev); |
| 804 | struct sh_rtc *rtc = platform_get_drvdata(pdev); |
| 805 | |
| 806 | set_irq_wake(rtc->periodic_irq, enabled); |
| 807 | |
| 808 | if (rtc->carry_irq > 0) { |
| 809 | set_irq_wake(rtc->carry_irq, enabled); |
| 810 | set_irq_wake(rtc->alarm_irq, enabled); |
| 811 | } |
| 812 | } |
| 813 | |
| 814 | static int sh_rtc_suspend(struct device *dev) |
| 815 | { |
| 816 | if (device_may_wakeup(dev)) |
| 817 | sh_rtc_set_irq_wake(dev, 1); |
| 818 | |
| 819 | return 0; |
| 820 | } |
| 821 | |
| 822 | static int sh_rtc_resume(struct device *dev) |
| 823 | { |
| 824 | if (device_may_wakeup(dev)) |
| 825 | sh_rtc_set_irq_wake(dev, 0); |
| 826 | |
| 827 | return 0; |
| 828 | } |
| 829 | |
| 830 | static const struct dev_pm_ops sh_rtc_dev_pm_ops = { |
| 831 | .suspend = sh_rtc_suspend, |
| 832 | .resume = sh_rtc_resume, |
| 833 | }; |
| 834 | |
| 835 | static struct platform_driver sh_rtc_platform_driver = { |
| 836 | .driver = { |
| 837 | .name = DRV_NAME, |
| 838 | .owner = THIS_MODULE, |
| 839 | .pm = &sh_rtc_dev_pm_ops, |
| 840 | }, |
| 841 | .remove = __exit_p(sh_rtc_remove), |
| 842 | }; |
| 843 | |
| 844 | static int __init sh_rtc_init(void) |
| 845 | { |
| 846 | return platform_driver_probe(&sh_rtc_platform_driver, sh_rtc_probe); |
| 847 | } |
| 848 | |
| 849 | static void __exit sh_rtc_exit(void) |
| 850 | { |
| 851 | platform_driver_unregister(&sh_rtc_platform_driver); |
| 852 | } |
| 853 | |
| 854 | module_init(sh_rtc_init); |
| 855 | module_exit(sh_rtc_exit); |
| 856 | |
| 857 | MODULE_DESCRIPTION("SuperH on-chip RTC driver"); |
| 858 | MODULE_VERSION(DRV_VERSION); |
| 859 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, " |
| 860 | "Jamie Lenehan <lenehan@twibble.org>, " |
| 861 | "Angelo Castello <angelo.castello@st.com>"); |
| 862 | MODULE_LICENSE("GPL"); |
| 863 | MODULE_ALIAS("platform:" DRV_NAME); |