| 1 | /* $Id: sungem.h,v 1.10.2.4 2002/03/11 08:54:48 davem Exp $ |
| 2 | * sungem.h: Definitions for Sun GEM ethernet driver. |
| 3 | * |
| 4 | * Copyright (C) 2000 David S. Miller (davem@redhat.com) |
| 5 | */ |
| 6 | |
| 7 | #ifndef _SUNGEM_H |
| 8 | #define _SUNGEM_H |
| 9 | |
| 10 | /* Global Registers */ |
| 11 | #define GREG_SEBSTATE 0x0000UL /* SEB State Register */ |
| 12 | #define GREG_CFG 0x0004UL /* Configuration Register */ |
| 13 | #define GREG_STAT 0x000CUL /* Status Register */ |
| 14 | #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */ |
| 15 | #define GREG_IACK 0x0014UL /* Interrupt ACK Register */ |
| 16 | #define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */ |
| 17 | #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */ |
| 18 | #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */ |
| 19 | #define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */ |
| 20 | #define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */ |
| 21 | #define GREG_SWRST 0x1010UL /* Software Reset Register */ |
| 22 | |
| 23 | /* Global SEB State Register */ |
| 24 | #define GREG_SEBSTATE_ARB 0x00000003 /* State of Arbiter */ |
| 25 | #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */ |
| 26 | |
| 27 | /* Global Configuration Register */ |
| 28 | #define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */ |
| 29 | #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */ |
| 30 | #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */ |
| 31 | #define GREG_CFG_RONPAULBIT 0x00000800 /* Use mem read multiple for PCI read |
| 32 | * after infinite burst (Apple) */ |
| 33 | #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */ |
| 34 | |
| 35 | /* Global Interrupt Status Register. |
| 36 | * |
| 37 | * Reading this register automatically clears bits 0 through 6. |
| 38 | * This auto-clearing does not occur when the alias at GREG_STAT2 |
| 39 | * is read instead. The rest of the interrupt bits only clear when |
| 40 | * the secondary interrupt status register corresponding to that |
| 41 | * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by |
| 42 | * reading PCS_ISTAT). |
| 43 | */ |
| 44 | #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */ |
| 45 | #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */ |
| 46 | #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */ |
| 47 | #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */ |
| 48 | #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */ |
| 49 | #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */ |
| 50 | #define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */ |
| 51 | #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */ |
| 52 | #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */ |
| 53 | #define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */ |
| 54 | #define GREG_STAT_MIF 0x00020000 /* MIF signalled interrupt */ |
| 55 | #define GREG_STAT_PCIERR 0x00040000 /* PCI Error interrupt */ |
| 56 | #define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */ |
| 57 | #define GREG_STAT_TXNR_SHIFT 19 |
| 58 | |
| 59 | #define GREG_STAT_ABNORMAL (GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \ |
| 60 | GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \ |
| 61 | GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR) |
| 62 | |
| 63 | #define GREG_STAT_NAPI (GREG_STAT_TXALL | GREG_STAT_TXINTME | \ |
| 64 | GREG_STAT_RXDONE | GREG_STAT_ABNORMAL) |
| 65 | |
| 66 | /* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT. |
| 67 | * Bits set in GREG_IMASK will prevent that interrupt type from being |
| 68 | * signalled to the cpu. GREG_IACK can be used to clear specific top-level |
| 69 | * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6. |
| 70 | * Setting the bit will clear that interrupt, clear bits will have no effect |
| 71 | * on GREG_STAT. |
| 72 | */ |
| 73 | |
| 74 | /* Global PCI Error Status Register */ |
| 75 | #define GREG_PCIESTAT_BADACK 0x00000001 /* No ACK64# during ABS64 cycle */ |
| 76 | #define GREG_PCIESTAT_DTRTO 0x00000002 /* Delayed transaction timeout */ |
| 77 | #define GREG_PCIESTAT_OTHER 0x00000004 /* Other PCI error, check cfg space */ |
| 78 | |
| 79 | /* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT. |
| 80 | * Bits set in GREG_PCIEMASK will prevent that interrupt type from being |
| 81 | * signalled to the cpu. |
| 82 | */ |
| 83 | |
| 84 | /* Global BIF Configuration Register */ |
| 85 | #define GREG_BIFCFG_SLOWCLK 0x00000001 /* Set if PCI runs < 25Mhz */ |
| 86 | #define GREG_BIFCFG_B64DIS 0x00000002 /* Disable 64bit wide data cycle*/ |
| 87 | #define GREG_BIFCFG_M66EN 0x00000004 /* Set if on 66Mhz PCI segment */ |
| 88 | |
| 89 | /* Global BIF Diagnostics Register */ |
| 90 | #define GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */ |
| 91 | #define GREG_BIFDIAG_BIFSM 0xff000000 /* BIF state machine */ |
| 92 | |
| 93 | /* Global Software Reset Register. |
| 94 | * |
| 95 | * This register is used to perform a global reset of the RX and TX portions |
| 96 | * of the GEM asic. Setting the RX or TX reset bit will start the reset. |
| 97 | * The driver _MUST_ poll these bits until they clear. One may not attempt |
| 98 | * to program any other part of GEM until the bits clear. |
| 99 | */ |
| 100 | #define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */ |
| 101 | #define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */ |
| 102 | #define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */ |
| 103 | #define GREG_SWRST_CACHESIZE 0x00ff0000 /* RIO only: cache line size */ |
| 104 | #define GREG_SWRST_CACHE_SHIFT 16 |
| 105 | |
| 106 | /* TX DMA Registers */ |
| 107 | #define TXDMA_KICK 0x2000UL /* TX Kick Register */ |
| 108 | #define TXDMA_CFG 0x2004UL /* TX Configuration Register */ |
| 109 | #define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */ |
| 110 | #define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */ |
| 111 | #define TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */ |
| 112 | #define TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */ |
| 113 | #define TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */ |
| 114 | #define TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */ |
| 115 | #define TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */ |
| 116 | #define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */ |
| 117 | #define TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */ |
| 118 | #define TXDMA_DPHI 0x2034UL /* TX Data Pointer High */ |
| 119 | #define TXDMA_TXDONE 0x2100UL /* TX Completion Register */ |
| 120 | #define TXDMA_FADDR 0x2104UL /* TX FIFO Address */ |
| 121 | #define TXDMA_FTAG 0x2108UL /* TX FIFO Tag */ |
| 122 | #define TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */ |
| 123 | #define TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */ |
| 124 | #define TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */ |
| 125 | #define TXDMA_FSZ 0x2118UL /* TX FIFO Size */ |
| 126 | |
| 127 | /* TX Kick Register. |
| 128 | * |
| 129 | * This 13-bit register is programmed by the driver to hold the descriptor |
| 130 | * entry index which follows the last valid transmit descriptor. |
| 131 | */ |
| 132 | |
| 133 | /* TX Completion Register. |
| 134 | * |
| 135 | * This 13-bit register is updated by GEM to hold to descriptor entry index |
| 136 | * which follows the last descriptor already processed by GEM. Note that |
| 137 | * this value is mirrored in GREG_STAT which eliminates the need to even |
| 138 | * access this register in the driver during interrupt processing. |
| 139 | */ |
| 140 | |
| 141 | /* TX Configuration Register. |
| 142 | * |
| 143 | * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature |
| 144 | * that was meant to be used with jumbo packets. It should be set to the |
| 145 | * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors. |
| 146 | */ |
| 147 | #define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */ |
| 148 | #define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */ |
| 149 | #define TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */ |
| 150 | #define TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */ |
| 151 | #define TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */ |
| 152 | #define TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */ |
| 153 | #define TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */ |
| 154 | #define TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */ |
| 155 | #define TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */ |
| 156 | #define TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */ |
| 157 | #define TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */ |
| 158 | #define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */ |
| 159 | #define TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */ |
| 160 | #define TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/ |
| 161 | |
| 162 | /* TX Descriptor Base Low/High. |
| 163 | * |
| 164 | * These two registers store the 53 most significant bits of the base address |
| 165 | * of the TX descriptor table. The 11 least significant bits are always |
| 166 | * zero. As a result, the TX descriptor table must be 2K aligned. |
| 167 | */ |
| 168 | |
| 169 | /* The rest of the TXDMA_* registers are for diagnostics and debug, I will document |
| 170 | * them later. -DaveM |
| 171 | */ |
| 172 | |
| 173 | /* WakeOnLan Registers */ |
| 174 | #define WOL_MATCH0 0x3000UL |
| 175 | #define WOL_MATCH1 0x3004UL |
| 176 | #define WOL_MATCH2 0x3008UL |
| 177 | #define WOL_MCOUNT 0x300CUL |
| 178 | #define WOL_WAKECSR 0x3010UL |
| 179 | |
| 180 | /* WOL Match count register |
| 181 | */ |
| 182 | #define WOL_MCOUNT_N 0x00000010 |
| 183 | #define WOL_MCOUNT_M 0x00000000 /* 0 << 8 */ |
| 184 | |
| 185 | #define WOL_WAKECSR_ENABLE 0x00000001 |
| 186 | #define WOL_WAKECSR_MII 0x00000002 |
| 187 | #define WOL_WAKECSR_SEEN 0x00000004 |
| 188 | #define WOL_WAKECSR_FILT_UCAST 0x00000008 |
| 189 | #define WOL_WAKECSR_FILT_MCAST 0x00000010 |
| 190 | #define WOL_WAKECSR_FILT_BCAST 0x00000020 |
| 191 | #define WOL_WAKECSR_FILT_SEEN 0x00000040 |
| 192 | |
| 193 | |
| 194 | /* Receive DMA Registers */ |
| 195 | #define RXDMA_CFG 0x4000UL /* RX Configuration Register */ |
| 196 | #define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */ |
| 197 | #define RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */ |
| 198 | #define RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */ |
| 199 | #define RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */ |
| 200 | #define RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */ |
| 201 | #define RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */ |
| 202 | #define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */ |
| 203 | #define RXDMA_PTHRESH 0x4020UL /* Pause Thresholds */ |
| 204 | #define RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */ |
| 205 | #define RXDMA_DPHI 0x4028UL /* RX Data Pointer High */ |
| 206 | #define RXDMA_KICK 0x4100UL /* RX Kick Register */ |
| 207 | #define RXDMA_DONE 0x4104UL /* RX Completion Register */ |
| 208 | #define RXDMA_BLANK 0x4108UL /* RX Blanking Register */ |
| 209 | #define RXDMA_FADDR 0x410CUL /* RX FIFO Address */ |
| 210 | #define RXDMA_FTAG 0x4110UL /* RX FIFO Tag */ |
| 211 | #define RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */ |
| 212 | #define RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */ |
| 213 | #define RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */ |
| 214 | #define RXDMA_FSZ 0x4120UL /* RX FIFO Size */ |
| 215 | |
| 216 | /* RX Configuration Register. */ |
| 217 | #define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */ |
| 218 | #define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */ |
| 219 | #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */ |
| 220 | #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */ |
| 221 | #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */ |
| 222 | #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */ |
| 223 | #define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */ |
| 224 | #define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */ |
| 225 | #define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */ |
| 226 | #define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */ |
| 227 | #define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */ |
| 228 | #define RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */ |
| 229 | #define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */ |
| 230 | #define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */ |
| 231 | #define RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */ |
| 232 | #define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */ |
| 233 | #define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */ |
| 234 | #define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */ |
| 235 | #define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */ |
| 236 | #define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */ |
| 237 | #define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */ |
| 238 | |
| 239 | /* RX Descriptor Base Low/High. |
| 240 | * |
| 241 | * These two registers store the 53 most significant bits of the base address |
| 242 | * of the RX descriptor table. The 11 least significant bits are always |
| 243 | * zero. As a result, the RX descriptor table must be 2K aligned. |
| 244 | */ |
| 245 | |
| 246 | /* RX PAUSE Thresholds. |
| 247 | * |
| 248 | * These values determine when XOFF and XON PAUSE frames are emitted by |
| 249 | * GEM. The thresholds measure RX FIFO occupancy in units of 64 bytes. |
| 250 | */ |
| 251 | #define RXDMA_PTHRESH_OFF 0x000001ff /* XOFF emitted w/FIFO > this */ |
| 252 | #define RXDMA_PTHRESH_ON 0x001ff000 /* XON emitted w/FIFO < this */ |
| 253 | |
| 254 | /* RX Kick Register. |
| 255 | * |
| 256 | * This 13-bit register is written by the host CPU and holds the last |
| 257 | * valid RX descriptor number plus one. This is, if 'N' is written to |
| 258 | * this register, it means that all RX descriptors up to but excluding |
| 259 | * 'N' are valid. |
| 260 | * |
| 261 | * The hardware requires that RX descriptors are posted in increments |
| 262 | * of 4. This means 'N' must be a multiple of four. For the best |
| 263 | * performance, the first new descriptor being posted should be (PCI) |
| 264 | * cache line aligned. |
| 265 | */ |
| 266 | |
| 267 | /* RX Completion Register. |
| 268 | * |
| 269 | * This 13-bit register is updated by GEM to indicate which RX descriptors |
| 270 | * have already been used for receive frames. All descriptors up to but |
| 271 | * excluding the value in this register are ready to be processed. GEM |
| 272 | * updates this register value after the RX FIFO empties completely into |
| 273 | * the RX descriptor's buffer, but before the RX_DONE bit is set in the |
| 274 | * interrupt status register. |
| 275 | */ |
| 276 | |
| 277 | /* RX Blanking Register. */ |
| 278 | #define RXDMA_BLANK_IPKTS 0x000001ff /* RX_DONE asserted after this |
| 279 | * many packets received since |
| 280 | * previous RX_DONE. |
| 281 | */ |
| 282 | #define RXDMA_BLANK_ITIME 0x000ff000 /* RX_DONE asserted after this |
| 283 | * many clocks (measured in 2048 |
| 284 | * PCI clocks) were counted since |
| 285 | * the previous RX_DONE. |
| 286 | */ |
| 287 | |
| 288 | /* RX FIFO Size. |
| 289 | * |
| 290 | * This 11-bit read-only register indicates how large, in units of 64-bytes, |
| 291 | * the RX FIFO is. The driver uses this to properly configure the RX PAUSE |
| 292 | * thresholds. |
| 293 | */ |
| 294 | |
| 295 | /* The rest of the RXDMA_* registers are for diagnostics and debug, I will document |
| 296 | * them later. -DaveM |
| 297 | */ |
| 298 | |
| 299 | /* MAC Registers */ |
| 300 | #define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/ |
| 301 | #define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/ |
| 302 | #define MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */ |
| 303 | #define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */ |
| 304 | #define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */ |
| 305 | #define MAC_CSTAT 0x6018UL /* MAC Control Status Register */ |
| 306 | #define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */ |
| 307 | #define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */ |
| 308 | #define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */ |
| 309 | #define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/ |
| 310 | #define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/ |
| 311 | #define MAC_MCCFG 0x6038UL /* MAC Control Config Register */ |
| 312 | #define MAC_XIFCFG 0x603CUL /* XIF Configuration Register */ |
| 313 | #define MAC_IPG0 0x6040UL /* InterPacketGap0 Register */ |
| 314 | #define MAC_IPG1 0x6044UL /* InterPacketGap1 Register */ |
| 315 | #define MAC_IPG2 0x6048UL /* InterPacketGap2 Register */ |
| 316 | #define MAC_STIME 0x604CUL /* SlotTime Register */ |
| 317 | #define MAC_MINFSZ 0x6050UL /* MinFrameSize Register */ |
| 318 | #define MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */ |
| 319 | #define MAC_PASIZE 0x6058UL /* PA Size Register */ |
| 320 | #define MAC_JAMSIZE 0x605CUL /* JamSize Register */ |
| 321 | #define MAC_ATTLIM 0x6060UL /* Attempt Limit Register */ |
| 322 | #define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */ |
| 323 | #define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */ |
| 324 | #define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */ |
| 325 | #define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */ |
| 326 | #define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */ |
| 327 | #define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */ |
| 328 | #define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */ |
| 329 | #define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */ |
| 330 | #define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */ |
| 331 | #define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */ |
| 332 | #define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */ |
| 333 | #define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */ |
| 334 | #define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */ |
| 335 | #define MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */ |
| 336 | #define MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */ |
| 337 | #define MAC_HASH0 0x60C0UL /* Hash Table 0 Register */ |
| 338 | #define MAC_HASH1 0x60C4UL /* Hash Table 1 Register */ |
| 339 | #define MAC_HASH2 0x60C8UL /* Hash Table 2 Register */ |
| 340 | #define MAC_HASH3 0x60CCUL /* Hash Table 3 Register */ |
| 341 | #define MAC_HASH4 0x60D0UL /* Hash Table 4 Register */ |
| 342 | #define MAC_HASH5 0x60D4UL /* Hash Table 5 Register */ |
| 343 | #define MAC_HASH6 0x60D8UL /* Hash Table 6 Register */ |
| 344 | #define MAC_HASH7 0x60DCUL /* Hash Table 7 Register */ |
| 345 | #define MAC_HASH8 0x60E0UL /* Hash Table 8 Register */ |
| 346 | #define MAC_HASH9 0x60E4UL /* Hash Table 9 Register */ |
| 347 | #define MAC_HASH10 0x60E8UL /* Hash Table 10 Register */ |
| 348 | #define MAC_HASH11 0x60ECUL /* Hash Table 11 Register */ |
| 349 | #define MAC_HASH12 0x60F0UL /* Hash Table 12 Register */ |
| 350 | #define MAC_HASH13 0x60F4UL /* Hash Table 13 Register */ |
| 351 | #define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */ |
| 352 | #define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */ |
| 353 | #define MAC_NCOLL 0x6100UL /* Normal Collision Counter */ |
| 354 | #define MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */ |
| 355 | #define MAC_ECOLL 0x6108UL /* Excessive Collision Counter */ |
| 356 | #define MAC_LCOLL 0x610CUL /* Late Collision Counter */ |
| 357 | #define MAC_DTIMER 0x6110UL /* Defer Timer */ |
| 358 | #define MAC_PATMPS 0x6114UL /* Peak Attempts Register */ |
| 359 | #define MAC_RFCTR 0x6118UL /* Receive Frame Counter */ |
| 360 | #define MAC_LERR 0x611CUL /* Length Error Counter */ |
| 361 | #define MAC_AERR 0x6120UL /* Alignment Error Counter */ |
| 362 | #define MAC_FCSERR 0x6124UL /* FCS Error Counter */ |
| 363 | #define MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */ |
| 364 | #define MAC_RANDSEED 0x6130UL /* Random Number Seed Register */ |
| 365 | #define MAC_SMACHINE 0x6134UL /* State Machine Register */ |
| 366 | |
| 367 | /* TX MAC Software Reset Command. */ |
| 368 | #define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */ |
| 369 | |
| 370 | /* RX MAC Software Reset Command. */ |
| 371 | #define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */ |
| 372 | |
| 373 | /* Send Pause Command. */ |
| 374 | #define MAC_SNDPAUSE_TS 0x0000ffff /* The pause_time operand used in |
| 375 | * Send_Pause and flow-control |
| 376 | * handshakes. |
| 377 | */ |
| 378 | #define MAC_SNDPAUSE_SP 0x00010000 /* Setting this bit instructs the MAC |
| 379 | * to send a Pause Flow Control |
| 380 | * frame onto the network. |
| 381 | */ |
| 382 | |
| 383 | /* TX MAC Status Register. */ |
| 384 | #define MAC_TXSTAT_XMIT 0x00000001 /* Frame Transmitted */ |
| 385 | #define MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */ |
| 386 | #define MAC_TXSTAT_MPE 0x00000004 /* Max Packet Size Error */ |
| 387 | #define MAC_TXSTAT_NCE 0x00000008 /* Normal Collision Cntr Expire */ |
| 388 | #define MAC_TXSTAT_ECE 0x00000010 /* Excess Collision Cntr Expire */ |
| 389 | #define MAC_TXSTAT_LCE 0x00000020 /* Late Collision Cntr Expire */ |
| 390 | #define MAC_TXSTAT_FCE 0x00000040 /* First Collision Cntr Expire */ |
| 391 | #define MAC_TXSTAT_DTE 0x00000080 /* Defer Timer Expire */ |
| 392 | #define MAC_TXSTAT_PCE 0x00000100 /* Peak Attempts Cntr Expire */ |
| 393 | |
| 394 | /* RX MAC Status Register. */ |
| 395 | #define MAC_RXSTAT_RCV 0x00000001 /* Frame Received */ |
| 396 | #define MAC_RXSTAT_OFLW 0x00000002 /* Receive Overflow */ |
| 397 | #define MAC_RXSTAT_FCE 0x00000004 /* Frame Cntr Expire */ |
| 398 | #define MAC_RXSTAT_ACE 0x00000008 /* Align Error Cntr Expire */ |
| 399 | #define MAC_RXSTAT_CCE 0x00000010 /* CRC Error Cntr Expire */ |
| 400 | #define MAC_RXSTAT_LCE 0x00000020 /* Length Error Cntr Expire */ |
| 401 | #define MAC_RXSTAT_VCE 0x00000040 /* Code Violation Cntr Expire */ |
| 402 | |
| 403 | /* MAC Control Status Register. */ |
| 404 | #define MAC_CSTAT_PRCV 0x00000001 /* Pause Received */ |
| 405 | #define MAC_CSTAT_PS 0x00000002 /* Paused State */ |
| 406 | #define MAC_CSTAT_NPS 0x00000004 /* Not Paused State */ |
| 407 | #define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */ |
| 408 | |
| 409 | /* The layout of the MAC_{TX,RX,C}MASK registers is identical to that |
| 410 | * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent |
| 411 | * that interrupt type from being signalled to front end of GEM. For |
| 412 | * the interrupt to actually get sent to the cpu, it is necessary to |
| 413 | * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well. |
| 414 | */ |
| 415 | |
| 416 | /* TX MAC Configuration Register. |
| 417 | * |
| 418 | * NOTE: The TX MAC Enable bit must be cleared and polled until |
| 419 | * zero before any other bits in this register are changed. |
| 420 | * |
| 421 | * Also, enabling the Carrier Extension feature of GEM is |
| 422 | * a 3 step process 1) Set TX Carrier Extension 2) Set |
| 423 | * RX Carrier Extension 3) Set Slot Time to 0x200. This |
| 424 | * mode must be enabled when in half-duplex at 1Gbps, else |
| 425 | * it must be disabled. |
| 426 | */ |
| 427 | #define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */ |
| 428 | #define MAC_TXCFG_ICS 0x00000002 /* Ignore Carrier Sense */ |
| 429 | #define MAC_TXCFG_ICOLL 0x00000004 /* Ignore Collisions */ |
| 430 | #define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */ |
| 431 | #define MAC_TXCFG_NGU 0x00000010 /* Never Give Up */ |
| 432 | #define MAC_TXCFG_NGUL 0x00000020 /* Never Give Up Limit */ |
| 433 | #define MAC_TXCFG_NBO 0x00000040 /* No Backoff */ |
| 434 | #define MAC_TXCFG_SD 0x00000080 /* Slow Down */ |
| 435 | #define MAC_TXCFG_NFCS 0x00000100 /* No FCS */ |
| 436 | #define MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */ |
| 437 | |
| 438 | /* RX MAC Configuration Register. |
| 439 | * |
| 440 | * NOTE: The RX MAC Enable bit must be cleared and polled until |
| 441 | * zero before any other bits in this register are changed. |
| 442 | * |
| 443 | * Similar rules apply to the Hash Filter Enable bit when |
| 444 | * programming the hash table registers, and the Address Filter |
| 445 | * Enable bit when programming the address filter registers. |
| 446 | */ |
| 447 | #define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */ |
| 448 | #define MAC_RXCFG_SPAD 0x00000002 /* Strip Pad */ |
| 449 | #define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */ |
| 450 | #define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */ |
| 451 | #define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */ |
| 452 | #define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */ |
| 453 | #define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */ |
| 454 | #define MAC_RXCFG_DDE 0x00000080 /* Disable Discard on Error */ |
| 455 | #define MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */ |
| 456 | |
| 457 | /* MAC Control Config Register. */ |
| 458 | #define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */ |
| 459 | #define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */ |
| 460 | #define MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */ |
| 461 | |
| 462 | /* XIF Configuration Register. |
| 463 | * |
| 464 | * NOTE: When leaving or entering loopback mode, a global hardware |
| 465 | * init of GEM should be performed. |
| 466 | */ |
| 467 | #define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */ |
| 468 | #define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */ |
| 469 | #define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */ |
| 470 | #define MAC_XIFCFG_GMII 0x00000008 /* Use GMII clocks + datapath */ |
| 471 | #define MAC_XIFCFG_MBOE 0x00000010 /* Controls MII_BUF_EN pin */ |
| 472 | #define MAC_XIFCFG_LLED 0x00000020 /* Force LINKLED# active (low) */ |
| 473 | #define MAC_XIFCFG_FLED 0x00000040 /* Force FDPLXLED# active (low) */ |
| 474 | |
| 475 | /* InterPacketGap0 Register. This 8-bit value is used as an extension |
| 476 | * to the InterPacketGap1 Register. Specifically it contributes to the |
| 477 | * timing of the RX-to-TX IPG. This value is ignored and presumed to |
| 478 | * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit |
| 479 | * is cleared in the TX MAC Configuration Register. |
| 480 | * |
| 481 | * This value in this register in terms of media byte time. |
| 482 | * |
| 483 | * Recommended value: 0x00 |
| 484 | */ |
| 485 | |
| 486 | /* InterPacketGap1 Register. This 8-bit value defines the first 2/3 |
| 487 | * portion of the Inter Packet Gap. |
| 488 | * |
| 489 | * This value in this register in terms of media byte time. |
| 490 | * |
| 491 | * Recommended value: 0x08 |
| 492 | */ |
| 493 | |
| 494 | /* InterPacketGap2 Register. This 8-bit value defines the second 1/3 |
| 495 | * portion of the Inter Packet Gap. |
| 496 | * |
| 497 | * This value in this register in terms of media byte time. |
| 498 | * |
| 499 | * Recommended value: 0x04 |
| 500 | */ |
| 501 | |
| 502 | /* Slot Time Register. This 10-bit value specifies the slot time |
| 503 | * parameter in units of media byte time. It determines the physical |
| 504 | * span of the network. |
| 505 | * |
| 506 | * Recommended value: 0x40 |
| 507 | */ |
| 508 | |
| 509 | /* Minimum Frame Size Register. This 10-bit register specifies the |
| 510 | * smallest sized frame the TXMAC will send onto the medium, and the |
| 511 | * RXMAC will receive from the medium. |
| 512 | * |
| 513 | * Recommended value: 0x40 |
| 514 | */ |
| 515 | |
| 516 | /* Maximum Frame and Burst Size Register. |
| 517 | * |
| 518 | * This register specifies two things. First it specifies the maximum |
| 519 | * sized frame the TXMAC will send and the RXMAC will recognize as |
| 520 | * valid. Second, it specifies the maximum run length of a burst of |
| 521 | * packets sent in half-duplex gigabit modes. |
| 522 | * |
| 523 | * Recommended value: 0x200005ee |
| 524 | */ |
| 525 | #define MAC_MAXFSZ_MFS 0x00007fff /* Max Frame Size */ |
| 526 | #define MAC_MAXFSZ_MBS 0x7fff0000 /* Max Burst Size */ |
| 527 | |
| 528 | /* PA Size Register. This 10-bit register specifies the number of preamble |
| 529 | * bytes which will be transmitted at the beginning of each frame. A |
| 530 | * value of two or greater should be programmed here. |
| 531 | * |
| 532 | * Recommended value: 0x07 |
| 533 | */ |
| 534 | |
| 535 | /* Jam Size Register. This 4-bit register specifies the duration of |
| 536 | * the jam in units of media byte time. |
| 537 | * |
| 538 | * Recommended value: 0x04 |
| 539 | */ |
| 540 | |
| 541 | /* Attempts Limit Register. This 8-bit register specifies the number |
| 542 | * of attempts that the TXMAC will make to transmit a frame, before it |
| 543 | * resets its Attempts Counter. After reaching the Attempts Limit the |
| 544 | * TXMAC may or may not drop the frame, as determined by the NGU |
| 545 | * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC |
| 546 | * Configuration Register. |
| 547 | * |
| 548 | * Recommended value: 0x10 |
| 549 | */ |
| 550 | |
| 551 | /* MAX Control Type Register. This 16-bit register specifies the |
| 552 | * "type" field of a MAC Control frame. The TXMAC uses this field to |
| 553 | * encapsulate the MAC Control frame for transmission, and the RXMAC |
| 554 | * uses it for decoding valid MAC Control frames received from the |
| 555 | * network. |
| 556 | * |
| 557 | * Recommended value: 0x8808 |
| 558 | */ |
| 559 | |
| 560 | /* MAC Address Registers. Each of these registers specify the |
| 561 | * ethernet MAC of the interface, 16-bits at a time. Register |
| 562 | * 0 specifies bits [47:32], register 1 bits [31:16], and register |
| 563 | * 2 bits [15:0]. |
| 564 | * |
| 565 | * Registers 3 through and including 5 specify an alternate |
| 566 | * MAC address for the interface. |
| 567 | * |
| 568 | * Registers 6 through and including 8 specify the MAC Control |
| 569 | * Address, which must be the reserved multicast address for MAC |
| 570 | * Control frames. |
| 571 | * |
| 572 | * Example: To program primary station address a:b:c:d:e:f into |
| 573 | * the chip. |
| 574 | * MAC_Address_2 = (a << 8) | b |
| 575 | * MAC_Address_1 = (c << 8) | d |
| 576 | * MAC_Address_0 = (e << 8) | f |
| 577 | */ |
| 578 | |
| 579 | /* Address Filter Registers. Registers 0 through 2 specify bit |
| 580 | * fields [47:32] through [15:0], respectively, of the address |
| 581 | * filter. The Address Filter 2&1 Mask Register denotes the 8-bit |
| 582 | * nibble mask for Address Filter Registers 2 and 1. The Address |
| 583 | * Filter 0 Mask Register denotes the 16-bit mask for the Address |
| 584 | * Filter Register 0. |
| 585 | */ |
| 586 | |
| 587 | /* Hash Table Registers. Registers 0 through 15 specify bit fields |
| 588 | * [255:240] through [15:0], respectively, of the hash table. |
| 589 | */ |
| 590 | |
| 591 | /* Statistics Registers. All of these registers are 16-bits and |
| 592 | * track occurrences of a specific event. GEM can be configured |
| 593 | * to interrupt the host cpu when any of these counters overflow. |
| 594 | * They should all be explicitly initialized to zero when the interface |
| 595 | * is brought up. |
| 596 | */ |
| 597 | |
| 598 | /* Random Number Seed Register. This 10-bit value is used as the |
| 599 | * RNG seed inside GEM for the CSMA/CD backoff algorithm. It is |
| 600 | * recommended to program this register to the 10 LSB of the |
| 601 | * interfaces MAC address. |
| 602 | */ |
| 603 | |
| 604 | /* Pause Timer, read-only. This 16-bit timer is used to time the pause |
| 605 | * interval as indicated by a received pause flow control frame. |
| 606 | * A non-zero value in this timer indicates that the MAC is currently in |
| 607 | * the paused state. |
| 608 | */ |
| 609 | |
| 610 | /* MIF Registers */ |
| 611 | #define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */ |
| 612 | #define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */ |
| 613 | #define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */ |
| 614 | #define MIF_FRAME 0x620CUL /* MIF Frame/Output Register */ |
| 615 | #define MIF_CFG 0x6210UL /* MIF Configuration Register */ |
| 616 | #define MIF_MASK 0x6214UL /* MIF Mask Register */ |
| 617 | #define MIF_STATUS 0x6218UL /* MIF Status Register */ |
| 618 | #define MIF_SMACHINE 0x621CUL /* MIF State Machine Register */ |
| 619 | |
| 620 | /* MIF Bit-Bang Clock. This 1-bit register is used to generate the |
| 621 | * MDC clock waveform on the MII Management Interface when the MIF is |
| 622 | * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into |
| 623 | * this register will create a rising edge on the MDC, while writing |
| 624 | * a '0' after a '1' will create a falling edge. For every bit that |
| 625 | * is transferred on the management interface, both edges have to be |
| 626 | * generated. |
| 627 | */ |
| 628 | |
| 629 | /* MIF Bit-Bang Data. This 1-bit register is used to generate the |
| 630 | * outgoing data (MDO) on the MII Management Interface when the MIF |
| 631 | * is programmed in the "Bit-Bang" mode. The daa will be steered to the |
| 632 | * appropriate MDIO based on the state of the PHY_Select bit in the MIF |
| 633 | * Configuration Register. |
| 634 | */ |
| 635 | |
| 636 | /* MIF Big-Band Output Enable. THis 1-bit register is used to enable |
| 637 | * ('1') or disable ('0') the I-directional driver on the MII when the |
| 638 | * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled |
| 639 | * when data bits are transferred from the MIF to the transceiver, and it |
| 640 | * should be disabled when the interface is idle or when data bits are |
| 641 | * transferred from the transceiver to the MIF (data portion of a read |
| 642 | * instruction). Only one MDIO will be enabled at a given time, depending |
| 643 | * on the state of the PHY_Select bit in the MIF Configuration Register. |
| 644 | */ |
| 645 | |
| 646 | /* MIF Configuration Register. This 15-bit register controls the operation |
| 647 | * of the MIF. |
| 648 | */ |
| 649 | #define MIF_CFG_PSELECT 0x00000001 /* Xcvr slct: 0=mdio0 1=mdio1 */ |
| 650 | #define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */ |
| 651 | #define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */ |
| 652 | #define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */ |
| 653 | #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */ |
| 654 | #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */ |
| 655 | #define MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */ |
| 656 | |
| 657 | /* MIF Frame/Output Register. This 32-bit register allows the host to |
| 658 | * communicate with a transceiver in frame mode (as opposed to big-bang |
| 659 | * mode). Writes by the host specify an instrution. After being issued |
| 660 | * the host must poll this register for completion. Also, after |
| 661 | * completion this register holds the data returned by the transceiver |
| 662 | * if applicable. |
| 663 | */ |
| 664 | #define MIF_FRAME_ST 0xc0000000 /* STart of frame */ |
| 665 | #define MIF_FRAME_OP 0x30000000 /* OPcode */ |
| 666 | #define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */ |
| 667 | #define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */ |
| 668 | #define MIF_FRAME_TAMSB 0x00020000 /* Turn Around MSB */ |
| 669 | #define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */ |
| 670 | #define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */ |
| 671 | |
| 672 | /* MIF Status Register. This register reports status when the MIF is |
| 673 | * operating in the poll mode. The poll status field is auto-clearing |
| 674 | * on read. |
| 675 | */ |
| 676 | #define MIF_STATUS_DATA 0xffff0000 /* Live image of XCVR reg */ |
| 677 | #define MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */ |
| 678 | |
| 679 | /* MIF Mask Register. This 16-bit register is used when in poll mode |
| 680 | * to say which bits of the polled register will cause an interrupt |
| 681 | * when changed. |
| 682 | */ |
| 683 | |
| 684 | /* PCS/Serialink Registers */ |
| 685 | #define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */ |
| 686 | #define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */ |
| 687 | #define PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */ |
| 688 | #define PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */ |
| 689 | #define PCS_CFG 0x9010UL /* PCS Configuration Register */ |
| 690 | #define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */ |
| 691 | #define PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */ |
| 692 | #define PCS_DMODE 0x9050UL /* Datapath Mode Register */ |
| 693 | #define PCS_SCTRL 0x9054UL /* Serialink Control Register */ |
| 694 | #define PCS_SOS 0x9058UL /* Shared Output Select Reg */ |
| 695 | #define PCS_SSTATE 0x905CUL /* Serialink State Register */ |
| 696 | |
| 697 | /* PCD MII Control Register. */ |
| 698 | #define PCS_MIICTRL_SPD 0x00000040 /* Read as one, writes ignored */ |
| 699 | #define PCS_MIICTRL_CT 0x00000080 /* Force COL signal active */ |
| 700 | #define PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */ |
| 701 | #define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */ |
| 702 | #define PCS_MIICTRL_ISO 0x00000400 /* Read as zero, writes ignored */ |
| 703 | #define PCS_MIICTRL_PD 0x00000800 /* Read as zero, writes ignored */ |
| 704 | #define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */ |
| 705 | #define PCS_MIICTRL_SS 0x00002000 /* Read as zero, writes ignored */ |
| 706 | #define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit |
| 707 | * input side of Serialink |
| 708 | */ |
| 709 | #define PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */ |
| 710 | |
| 711 | /* PCS MII Status Register. */ |
| 712 | #define PCS_MIISTAT_EC 0x00000001 /* Ext Capability: Read as zero */ |
| 713 | #define PCS_MIISTAT_JD 0x00000002 /* Jabber Detect: Read as zero */ |
| 714 | #define PCS_MIISTAT_LS 0x00000004 /* Link Status: 1=up 0=down */ |
| 715 | #define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */ |
| 716 | #define PCS_MIISTAT_RF 0x00000010 /* Remote Fault */ |
| 717 | #define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */ |
| 718 | #define PCS_MIISTAT_ES 0x00000100 /* Extended Status, always 1 */ |
| 719 | |
| 720 | /* PCS MII Advertisement Register. */ |
| 721 | #define PCS_MIIADV_FD 0x00000020 /* Advertise Full Duplex */ |
| 722 | #define PCS_MIIADV_HD 0x00000040 /* Advertise Half Duplex */ |
| 723 | #define PCS_MIIADV_SP 0x00000080 /* Advertise Symmetric Pause */ |
| 724 | #define PCS_MIIADV_AP 0x00000100 /* Advertise Asymmetric Pause */ |
| 725 | #define PCS_MIIADV_RF 0x00003000 /* Remote Fault */ |
| 726 | #define PCS_MIIADV_ACK 0x00004000 /* Read-only */ |
| 727 | #define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */ |
| 728 | |
| 729 | /* PCS MII Link Partner Ability Register. This register is equivalent |
| 730 | * to the Link Partnet Ability Register of the standard MII register set. |
| 731 | * It's layout corresponds to the PCS MII Advertisement Register. |
| 732 | */ |
| 733 | |
| 734 | /* PCS Configuration Register. */ |
| 735 | #define PCS_CFG_ENABLE 0x00000001 /* Must be zero while changing |
| 736 | * PCS MII advertisement reg. |
| 737 | */ |
| 738 | #define PCS_CFG_SDO 0x00000002 /* Signal detect override */ |
| 739 | #define PCS_CFG_SDL 0x00000004 /* Signal detect active low */ |
| 740 | #define PCS_CFG_JS 0x00000018 /* Jitter-study: |
| 741 | * 0 = normal operation |
| 742 | * 1 = high-frequency test pattern |
| 743 | * 2 = low-frequency test pattern |
| 744 | * 3 = reserved |
| 745 | */ |
| 746 | #define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */ |
| 747 | |
| 748 | /* PCS Interrupt Status Register. This register is self-clearing |
| 749 | * when read. |
| 750 | */ |
| 751 | #define PCS_ISTAT_LSC 0x00000004 /* Link Status Change */ |
| 752 | |
| 753 | /* Datapath Mode Register. */ |
| 754 | #define PCS_DMODE_SM 0x00000001 /* 1 = use internal Serialink */ |
| 755 | #define PCS_DMODE_ESM 0x00000002 /* External SERDES mode */ |
| 756 | #define PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */ |
| 757 | #define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */ |
| 758 | |
| 759 | /* Serialink Control Register. |
| 760 | * |
| 761 | * NOTE: When in SERDES mode, the loopback bit has inverse logic. |
| 762 | */ |
| 763 | #define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */ |
| 764 | #define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */ |
| 765 | #define PCS_SCTRL_LOCK 0x00000004 /* Lock to reference clock */ |
| 766 | #define PCS_SCTRL_EMP 0x00000018 /* Output driver emphasis */ |
| 767 | #define PCS_SCTRL_STEST 0x000001c0 /* Self test patterns */ |
| 768 | #define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */ |
| 769 | #define PCS_SCTRL_RXZ 0x00000c00 /* PLL input to Serialink */ |
| 770 | #define PCS_SCTRL_RXP 0x00003000 /* PLL input to Serialink */ |
| 771 | #define PCS_SCTRL_TXZ 0x0000c000 /* PLL input to Serialink */ |
| 772 | #define PCS_SCTRL_TXP 0x00030000 /* PLL input to Serialink */ |
| 773 | |
| 774 | /* Shared Output Select Register. For test and debug, allows multiplexing |
| 775 | * test outputs into the PROM address pins. Set to zero for normal |
| 776 | * operation. |
| 777 | */ |
| 778 | #define PCS_SOS_PADDR 0x00000003 /* PROM Address */ |
| 779 | |
| 780 | /* PROM Image Space */ |
| 781 | #define PROM_START 0x100000UL /* Expansion ROM run time access*/ |
| 782 | #define PROM_SIZE 0x0fffffUL /* Size of ROM */ |
| 783 | #define PROM_END 0x200000UL /* End of ROM */ |
| 784 | |
| 785 | /* MII definitions missing from mii.h */ |
| 786 | |
| 787 | #define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */ |
| 788 | #define LPA_PAUSE 0x0400 |
| 789 | |
| 790 | /* More PHY registers (specific to Broadcom models) */ |
| 791 | |
| 792 | /* MII BCM5201 MULTIPHY interrupt register */ |
| 793 | #define MII_BCM5201_INTERRUPT 0x1A |
| 794 | #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000 |
| 795 | |
| 796 | #define MII_BCM5201_AUXMODE2 0x1B |
| 797 | #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008 |
| 798 | |
| 799 | #define MII_BCM5201_MULTIPHY 0x1E |
| 800 | |
| 801 | /* MII BCM5201 MULTIPHY register bits */ |
| 802 | #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002 |
| 803 | #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008 |
| 804 | |
| 805 | /* MII BCM5400 1000-BASET Control register */ |
| 806 | #define MII_BCM5400_GB_CONTROL 0x09 |
| 807 | #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200 |
| 808 | |
| 809 | /* MII BCM5400 AUXCONTROL register */ |
| 810 | #define MII_BCM5400_AUXCONTROL 0x18 |
| 811 | #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004 |
| 812 | |
| 813 | /* MII BCM5400 AUXSTATUS register */ |
| 814 | #define MII_BCM5400_AUXSTATUS 0x19 |
| 815 | #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700 |
| 816 | #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 |
| 817 | |
| 818 | /* When it can, GEM internally caches 4 aligned TX descriptors |
| 819 | * at a time, so that it can use full cacheline DMA reads. |
| 820 | * |
| 821 | * Note that unlike HME, there is no ownership bit in the descriptor |
| 822 | * control word. The same functionality is obtained via the TX-Kick |
| 823 | * and TX-Complete registers. As a result, GEM need not write back |
| 824 | * updated values to the TX descriptor ring, it only performs reads. |
| 825 | * |
| 826 | * Since TX descriptors are never modified by GEM, the driver can |
| 827 | * use the buffer DMA address as a place to keep track of allocated |
| 828 | * DMA mappings for a transmitted packet. |
| 829 | */ |
| 830 | struct gem_txd { |
| 831 | __le64 control_word; |
| 832 | __le64 buffer; |
| 833 | }; |
| 834 | |
| 835 | #define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */ |
| 836 | #define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */ |
| 837 | #define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */ |
| 838 | #define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */ |
| 839 | #define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */ |
| 840 | #define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */ |
| 841 | #define TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */ |
| 842 | #define TXDCTRL_NOCRC 0x0000000200000000ULL /* No CRC Present */ |
| 843 | |
| 844 | /* GEM requires that RX descriptors are provided four at a time, |
| 845 | * aligned. Also, the RX ring may not wrap around. This means that |
| 846 | * there will be at least 4 unused desciptor entries in the middle |
| 847 | * of the RX ring at all times. |
| 848 | * |
| 849 | * Similar to HME, GEM assumes that it can write garbage bytes before |
| 850 | * the beginning of the buffer and right after the end in order to DMA |
| 851 | * whole cachelines. |
| 852 | * |
| 853 | * Unlike for TX, GEM does update the status word in the RX descriptors |
| 854 | * when packets arrive. Therefore an ownership bit does exist in the |
| 855 | * RX descriptors. It is advisory, GEM clears it but does not check |
| 856 | * it in any way. So when buffers are posted to the RX ring (via the |
| 857 | * RX Kick register) by the driver it must make sure the buffers are |
| 858 | * truly ready and that the ownership bits are set properly. |
| 859 | * |
| 860 | * Even though GEM modifies the RX descriptors, it guarantees that the |
| 861 | * buffer DMA address field will stay the same when it performs these |
| 862 | * updates. Therefore it can be used to keep track of DMA mappings |
| 863 | * by the host driver just as in the TX descriptor case above. |
| 864 | */ |
| 865 | struct gem_rxd { |
| 866 | __le64 status_word; |
| 867 | __le64 buffer; |
| 868 | }; |
| 869 | |
| 870 | #define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */ |
| 871 | #define RXDCTRL_BUFSZ 0x000000007fff0000ULL /* Buffer Size */ |
| 872 | #define RXDCTRL_OWN 0x0000000080000000ULL /* GEM owns this entry */ |
| 873 | #define RXDCTRL_HASHVAL 0x0ffff00000000000ULL /* Hash Value */ |
| 874 | #define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */ |
| 875 | #define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */ |
| 876 | #define RXDCTRL_BAD 0x4000000000000000ULL /* Frame has bad CRC */ |
| 877 | |
| 878 | #define RXDCTRL_FRESH(gp) \ |
| 879 | ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \ |
| 880 | RXDCTRL_OWN) |
| 881 | |
| 882 | #define TX_RING_SIZE 128 |
| 883 | #define RX_RING_SIZE 128 |
| 884 | |
| 885 | #if TX_RING_SIZE == 32 |
| 886 | #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_32 |
| 887 | #elif TX_RING_SIZE == 64 |
| 888 | #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_64 |
| 889 | #elif TX_RING_SIZE == 128 |
| 890 | #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_128 |
| 891 | #elif TX_RING_SIZE == 256 |
| 892 | #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_256 |
| 893 | #elif TX_RING_SIZE == 512 |
| 894 | #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_512 |
| 895 | #elif TX_RING_SIZE == 1024 |
| 896 | #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_1K |
| 897 | #elif TX_RING_SIZE == 2048 |
| 898 | #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_2K |
| 899 | #elif TX_RING_SIZE == 4096 |
| 900 | #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_4K |
| 901 | #elif TX_RING_SIZE == 8192 |
| 902 | #define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_8K |
| 903 | #else |
| 904 | #error TX_RING_SIZE value is illegal... |
| 905 | #endif |
| 906 | |
| 907 | #if RX_RING_SIZE == 32 |
| 908 | #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_32 |
| 909 | #elif RX_RING_SIZE == 64 |
| 910 | #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_64 |
| 911 | #elif RX_RING_SIZE == 128 |
| 912 | #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_128 |
| 913 | #elif RX_RING_SIZE == 256 |
| 914 | #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_256 |
| 915 | #elif RX_RING_SIZE == 512 |
| 916 | #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_512 |
| 917 | #elif RX_RING_SIZE == 1024 |
| 918 | #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_1K |
| 919 | #elif RX_RING_SIZE == 2048 |
| 920 | #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_2K |
| 921 | #elif RX_RING_SIZE == 4096 |
| 922 | #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_4K |
| 923 | #elif RX_RING_SIZE == 8192 |
| 924 | #define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_8K |
| 925 | #else |
| 926 | #error RX_RING_SIZE is illegal... |
| 927 | #endif |
| 928 | |
| 929 | #define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1)) |
| 930 | #define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1)) |
| 931 | |
| 932 | #define TX_BUFFS_AVAIL(GP) \ |
| 933 | (((GP)->tx_old <= (GP)->tx_new) ? \ |
| 934 | (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \ |
| 935 | (GP)->tx_old - (GP)->tx_new - 1) |
| 936 | |
| 937 | #define RX_OFFSET 2 |
| 938 | #define RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64) |
| 939 | |
| 940 | #define RX_COPY_THRESHOLD 256 |
| 941 | |
| 942 | #if TX_RING_SIZE < 128 |
| 943 | #define INIT_BLOCK_TX_RING_SIZE 128 |
| 944 | #else |
| 945 | #define INIT_BLOCK_TX_RING_SIZE TX_RING_SIZE |
| 946 | #endif |
| 947 | |
| 948 | #if RX_RING_SIZE < 128 |
| 949 | #define INIT_BLOCK_RX_RING_SIZE 128 |
| 950 | #else |
| 951 | #define INIT_BLOCK_RX_RING_SIZE RX_RING_SIZE |
| 952 | #endif |
| 953 | |
| 954 | struct gem_init_block { |
| 955 | struct gem_txd txd[INIT_BLOCK_TX_RING_SIZE]; |
| 956 | struct gem_rxd rxd[INIT_BLOCK_RX_RING_SIZE]; |
| 957 | }; |
| 958 | |
| 959 | enum gem_phy_type { |
| 960 | phy_mii_mdio0, |
| 961 | phy_mii_mdio1, |
| 962 | phy_serialink, |
| 963 | phy_serdes, |
| 964 | }; |
| 965 | |
| 966 | enum link_state { |
| 967 | link_down = 0, /* No link, will retry */ |
| 968 | link_aneg, /* Autoneg in progress */ |
| 969 | link_force_try, /* Try Forced link speed */ |
| 970 | link_force_ret, /* Forced mode worked, retrying autoneg */ |
| 971 | link_force_ok, /* Stay in forced mode */ |
| 972 | link_up /* Link is up */ |
| 973 | }; |
| 974 | |
| 975 | struct gem { |
| 976 | spinlock_t lock; |
| 977 | spinlock_t tx_lock; |
| 978 | void __iomem *regs; |
| 979 | int rx_new, rx_old; |
| 980 | int tx_new, tx_old; |
| 981 | |
| 982 | unsigned int has_wol : 1; /* chip supports wake-on-lan */ |
| 983 | unsigned int asleep : 1; /* chip asleep, protected by pm_mutex */ |
| 984 | unsigned int asleep_wol : 1; /* was asleep with WOL enabled */ |
| 985 | unsigned int opened : 1; /* driver opened, protected by pm_mutex */ |
| 986 | unsigned int running : 1; /* chip running, protected by lock */ |
| 987 | |
| 988 | /* cell enable count, protected by lock */ |
| 989 | int cell_enabled; |
| 990 | |
| 991 | struct mutex pm_mutex; |
| 992 | |
| 993 | u32 msg_enable; |
| 994 | u32 status; |
| 995 | |
| 996 | struct napi_struct napi; |
| 997 | struct net_device_stats net_stats; |
| 998 | |
| 999 | int tx_fifo_sz; |
| 1000 | int rx_fifo_sz; |
| 1001 | int rx_pause_off; |
| 1002 | int rx_pause_on; |
| 1003 | int rx_buf_sz; |
| 1004 | u64 pause_entered; |
| 1005 | u16 pause_last_time_recvd; |
| 1006 | u32 mac_rx_cfg; |
| 1007 | u32 swrst_base; |
| 1008 | |
| 1009 | int want_autoneg; |
| 1010 | int last_forced_speed; |
| 1011 | enum link_state lstate; |
| 1012 | struct timer_list link_timer; |
| 1013 | int timer_ticks; |
| 1014 | int wake_on_lan; |
| 1015 | struct work_struct reset_task; |
| 1016 | volatile int reset_task_pending; |
| 1017 | |
| 1018 | enum gem_phy_type phy_type; |
| 1019 | struct mii_phy phy_mii; |
| 1020 | int mii_phy_addr; |
| 1021 | |
| 1022 | struct gem_init_block *init_block; |
| 1023 | struct sk_buff *rx_skbs[RX_RING_SIZE]; |
| 1024 | struct sk_buff *tx_skbs[TX_RING_SIZE]; |
| 1025 | dma_addr_t gblock_dvma; |
| 1026 | |
| 1027 | struct pci_dev *pdev; |
| 1028 | struct net_device *dev; |
| 1029 | #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC) |
| 1030 | struct device_node *of_node; |
| 1031 | #endif |
| 1032 | }; |
| 1033 | |
| 1034 | #define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) \ |
| 1035 | && gp->phy_mii.def && gp->phy_mii.def->ops) |
| 1036 | |
| 1037 | #define ALIGNED_RX_SKB_ADDR(addr) \ |
| 1038 | ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr)) |
| 1039 | static __inline__ struct sk_buff *gem_alloc_skb(int size, |
| 1040 | gfp_t gfp_flags) |
| 1041 | { |
| 1042 | struct sk_buff *skb = alloc_skb(size + 64, gfp_flags); |
| 1043 | |
| 1044 | if (skb) { |
| 1045 | int offset = (int) ALIGNED_RX_SKB_ADDR(skb->data); |
| 1046 | if (offset) |
| 1047 | skb_reserve(skb, offset); |
| 1048 | } |
| 1049 | |
| 1050 | return skb; |
| 1051 | } |
| 1052 | |
| 1053 | #endif /* _SUNGEM_H */ |