| 1 | /* |
| 2 | * smc91x.c |
| 3 | * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. |
| 4 | * |
| 5 | * Copyright (C) 1996 by Erik Stahlman |
| 6 | * Copyright (C) 2001 Standard Microsystems Corporation |
| 7 | * Developed by Simple Network Magic Corporation |
| 8 | * Copyright (C) 2003 Monta Vista Software, Inc. |
| 9 | * Unified SMC91x driver by Nicolas Pitre |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 24 | * |
| 25 | * Arguments: |
| 26 | * io = for the base address |
| 27 | * irq = for the IRQ |
| 28 | * nowait = 0 for normal wait states, 1 eliminates additional wait states |
| 29 | * |
| 30 | * original author: |
| 31 | * Erik Stahlman <erik@vt.edu> |
| 32 | * |
| 33 | * hardware multicast code: |
| 34 | * Peter Cammaert <pc@denkart.be> |
| 35 | * |
| 36 | * contributors: |
| 37 | * Daris A Nevil <dnevil@snmc.com> |
| 38 | * Nicolas Pitre <nico@fluxnic.net> |
| 39 | * Russell King <rmk@arm.linux.org.uk> |
| 40 | * |
| 41 | * History: |
| 42 | * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet |
| 43 | * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" |
| 44 | * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 |
| 45 | * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 |
| 46 | * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 |
| 47 | * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support |
| 48 | * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, |
| 49 | * more bus abstraction, big cleanup, etc. |
| 50 | * 29/09/03 Russell King - add driver model support |
| 51 | * - ethtool support |
| 52 | * - convert to use generic MII interface |
| 53 | * - add link up/down notification |
| 54 | * - don't try to handle full negotiation in |
| 55 | * smc_phy_configure |
| 56 | * - clean up (and fix stack overrun) in PHY |
| 57 | * MII read/write functions |
| 58 | * 22/09/04 Nicolas Pitre big update (see commit log for details) |
| 59 | */ |
| 60 | static const char version[] = |
| 61 | "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>\n"; |
| 62 | |
| 63 | /* Debugging level */ |
| 64 | #ifndef SMC_DEBUG |
| 65 | #define SMC_DEBUG 0 |
| 66 | #endif |
| 67 | |
| 68 | |
| 69 | #include <linux/init.h> |
| 70 | #include <linux/module.h> |
| 71 | #include <linux/kernel.h> |
| 72 | #include <linux/sched.h> |
| 73 | #include <linux/slab.h> |
| 74 | #include <linux/delay.h> |
| 75 | #include <linux/interrupt.h> |
| 76 | #include <linux/errno.h> |
| 77 | #include <linux/ioport.h> |
| 78 | #include <linux/crc32.h> |
| 79 | #include <linux/platform_device.h> |
| 80 | #include <linux/spinlock.h> |
| 81 | #include <linux/ethtool.h> |
| 82 | #include <linux/mii.h> |
| 83 | #include <linux/workqueue.h> |
| 84 | |
| 85 | #include <linux/netdevice.h> |
| 86 | #include <linux/etherdevice.h> |
| 87 | #include <linux/skbuff.h> |
| 88 | |
| 89 | #include <asm/io.h> |
| 90 | |
| 91 | #include "smc91x.h" |
| 92 | |
| 93 | #ifndef SMC_NOWAIT |
| 94 | # define SMC_NOWAIT 0 |
| 95 | #endif |
| 96 | static int nowait = SMC_NOWAIT; |
| 97 | module_param(nowait, int, 0400); |
| 98 | MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); |
| 99 | |
| 100 | /* |
| 101 | * Transmit timeout, default 5 seconds. |
| 102 | */ |
| 103 | static int watchdog = 1000; |
| 104 | module_param(watchdog, int, 0400); |
| 105 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); |
| 106 | |
| 107 | MODULE_LICENSE("GPL"); |
| 108 | MODULE_ALIAS("platform:smc91x"); |
| 109 | |
| 110 | /* |
| 111 | * The internal workings of the driver. If you are changing anything |
| 112 | * here with the SMC stuff, you should have the datasheet and know |
| 113 | * what you are doing. |
| 114 | */ |
| 115 | #define CARDNAME "smc91x" |
| 116 | |
| 117 | /* |
| 118 | * Use power-down feature of the chip |
| 119 | */ |
| 120 | #define POWER_DOWN 1 |
| 121 | |
| 122 | /* |
| 123 | * Wait time for memory to be free. This probably shouldn't be |
| 124 | * tuned that much, as waiting for this means nothing else happens |
| 125 | * in the system |
| 126 | */ |
| 127 | #define MEMORY_WAIT_TIME 16 |
| 128 | |
| 129 | /* |
| 130 | * The maximum number of processing loops allowed for each call to the |
| 131 | * IRQ handler. |
| 132 | */ |
| 133 | #define MAX_IRQ_LOOPS 8 |
| 134 | |
| 135 | /* |
| 136 | * This selects whether TX packets are sent one by one to the SMC91x internal |
| 137 | * memory and throttled until transmission completes. This may prevent |
| 138 | * RX overruns a litle by keeping much of the memory free for RX packets |
| 139 | * but to the expense of reduced TX throughput and increased IRQ overhead. |
| 140 | * Note this is not a cure for a too slow data bus or too high IRQ latency. |
| 141 | */ |
| 142 | #define THROTTLE_TX_PKTS 0 |
| 143 | |
| 144 | /* |
| 145 | * The MII clock high/low times. 2x this number gives the MII clock period |
| 146 | * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) |
| 147 | */ |
| 148 | #define MII_DELAY 1 |
| 149 | |
| 150 | #if SMC_DEBUG > 0 |
| 151 | #define DBG(n, args...) \ |
| 152 | do { \ |
| 153 | if (SMC_DEBUG >= (n)) \ |
| 154 | printk(args); \ |
| 155 | } while (0) |
| 156 | |
| 157 | #define PRINTK(args...) printk(args) |
| 158 | #else |
| 159 | #define DBG(n, args...) do { } while(0) |
| 160 | #define PRINTK(args...) printk(KERN_DEBUG args) |
| 161 | #endif |
| 162 | |
| 163 | #if SMC_DEBUG > 3 |
| 164 | static void PRINT_PKT(u_char *buf, int length) |
| 165 | { |
| 166 | int i; |
| 167 | int remainder; |
| 168 | int lines; |
| 169 | |
| 170 | lines = length / 16; |
| 171 | remainder = length % 16; |
| 172 | |
| 173 | for (i = 0; i < lines ; i ++) { |
| 174 | int cur; |
| 175 | for (cur = 0; cur < 8; cur++) { |
| 176 | u_char a, b; |
| 177 | a = *buf++; |
| 178 | b = *buf++; |
| 179 | printk("%02x%02x ", a, b); |
| 180 | } |
| 181 | printk("\n"); |
| 182 | } |
| 183 | for (i = 0; i < remainder/2 ; i++) { |
| 184 | u_char a, b; |
| 185 | a = *buf++; |
| 186 | b = *buf++; |
| 187 | printk("%02x%02x ", a, b); |
| 188 | } |
| 189 | printk("\n"); |
| 190 | } |
| 191 | #else |
| 192 | #define PRINT_PKT(x...) do { } while(0) |
| 193 | #endif |
| 194 | |
| 195 | |
| 196 | /* this enables an interrupt in the interrupt mask register */ |
| 197 | #define SMC_ENABLE_INT(lp, x) do { \ |
| 198 | unsigned char mask; \ |
| 199 | unsigned long smc_enable_flags; \ |
| 200 | spin_lock_irqsave(&lp->lock, smc_enable_flags); \ |
| 201 | mask = SMC_GET_INT_MASK(lp); \ |
| 202 | mask |= (x); \ |
| 203 | SMC_SET_INT_MASK(lp, mask); \ |
| 204 | spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \ |
| 205 | } while (0) |
| 206 | |
| 207 | /* this disables an interrupt from the interrupt mask register */ |
| 208 | #define SMC_DISABLE_INT(lp, x) do { \ |
| 209 | unsigned char mask; \ |
| 210 | unsigned long smc_disable_flags; \ |
| 211 | spin_lock_irqsave(&lp->lock, smc_disable_flags); \ |
| 212 | mask = SMC_GET_INT_MASK(lp); \ |
| 213 | mask &= ~(x); \ |
| 214 | SMC_SET_INT_MASK(lp, mask); \ |
| 215 | spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \ |
| 216 | } while (0) |
| 217 | |
| 218 | /* |
| 219 | * Wait while MMU is busy. This is usually in the order of a few nanosecs |
| 220 | * if at all, but let's avoid deadlocking the system if the hardware |
| 221 | * decides to go south. |
| 222 | */ |
| 223 | #define SMC_WAIT_MMU_BUSY(lp) do { \ |
| 224 | if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \ |
| 225 | unsigned long timeout = jiffies + 2; \ |
| 226 | while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \ |
| 227 | if (time_after(jiffies, timeout)) { \ |
| 228 | printk("%s: timeout %s line %d\n", \ |
| 229 | dev->name, __FILE__, __LINE__); \ |
| 230 | break; \ |
| 231 | } \ |
| 232 | cpu_relax(); \ |
| 233 | } \ |
| 234 | } \ |
| 235 | } while (0) |
| 236 | |
| 237 | |
| 238 | /* |
| 239 | * this does a soft reset on the device |
| 240 | */ |
| 241 | static void smc_reset(struct net_device *dev) |
| 242 | { |
| 243 | struct smc_local *lp = netdev_priv(dev); |
| 244 | void __iomem *ioaddr = lp->base; |
| 245 | unsigned int ctl, cfg; |
| 246 | struct sk_buff *pending_skb; |
| 247 | |
| 248 | DBG(2, "%s: %s\n", dev->name, __func__); |
| 249 | |
| 250 | /* Disable all interrupts, block TX tasklet */ |
| 251 | spin_lock_irq(&lp->lock); |
| 252 | SMC_SELECT_BANK(lp, 2); |
| 253 | SMC_SET_INT_MASK(lp, 0); |
| 254 | pending_skb = lp->pending_tx_skb; |
| 255 | lp->pending_tx_skb = NULL; |
| 256 | spin_unlock_irq(&lp->lock); |
| 257 | |
| 258 | /* free any pending tx skb */ |
| 259 | if (pending_skb) { |
| 260 | dev_kfree_skb(pending_skb); |
| 261 | dev->stats.tx_errors++; |
| 262 | dev->stats.tx_aborted_errors++; |
| 263 | } |
| 264 | |
| 265 | /* |
| 266 | * This resets the registers mostly to defaults, but doesn't |
| 267 | * affect EEPROM. That seems unnecessary |
| 268 | */ |
| 269 | SMC_SELECT_BANK(lp, 0); |
| 270 | SMC_SET_RCR(lp, RCR_SOFTRST); |
| 271 | |
| 272 | /* |
| 273 | * Setup the Configuration Register |
| 274 | * This is necessary because the CONFIG_REG is not affected |
| 275 | * by a soft reset |
| 276 | */ |
| 277 | SMC_SELECT_BANK(lp, 1); |
| 278 | |
| 279 | cfg = CONFIG_DEFAULT; |
| 280 | |
| 281 | /* |
| 282 | * Setup for fast accesses if requested. If the card/system |
| 283 | * can't handle it then there will be no recovery except for |
| 284 | * a hard reset or power cycle |
| 285 | */ |
| 286 | if (lp->cfg.flags & SMC91X_NOWAIT) |
| 287 | cfg |= CONFIG_NO_WAIT; |
| 288 | |
| 289 | /* |
| 290 | * Release from possible power-down state |
| 291 | * Configuration register is not affected by Soft Reset |
| 292 | */ |
| 293 | cfg |= CONFIG_EPH_POWER_EN; |
| 294 | |
| 295 | SMC_SET_CONFIG(lp, cfg); |
| 296 | |
| 297 | /* this should pause enough for the chip to be happy */ |
| 298 | /* |
| 299 | * elaborate? What does the chip _need_? --jgarzik |
| 300 | * |
| 301 | * This seems to be undocumented, but something the original |
| 302 | * driver(s) have always done. Suspect undocumented timing |
| 303 | * info/determined empirically. --rmk |
| 304 | */ |
| 305 | udelay(1); |
| 306 | |
| 307 | /* Disable transmit and receive functionality */ |
| 308 | SMC_SELECT_BANK(lp, 0); |
| 309 | SMC_SET_RCR(lp, RCR_CLEAR); |
| 310 | SMC_SET_TCR(lp, TCR_CLEAR); |
| 311 | |
| 312 | SMC_SELECT_BANK(lp, 1); |
| 313 | ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE; |
| 314 | |
| 315 | /* |
| 316 | * Set the control register to automatically release successfully |
| 317 | * transmitted packets, to make the best use out of our limited |
| 318 | * memory |
| 319 | */ |
| 320 | if(!THROTTLE_TX_PKTS) |
| 321 | ctl |= CTL_AUTO_RELEASE; |
| 322 | else |
| 323 | ctl &= ~CTL_AUTO_RELEASE; |
| 324 | SMC_SET_CTL(lp, ctl); |
| 325 | |
| 326 | /* Reset the MMU */ |
| 327 | SMC_SELECT_BANK(lp, 2); |
| 328 | SMC_SET_MMU_CMD(lp, MC_RESET); |
| 329 | SMC_WAIT_MMU_BUSY(lp); |
| 330 | } |
| 331 | |
| 332 | /* |
| 333 | * Enable Interrupts, Receive, and Transmit |
| 334 | */ |
| 335 | static void smc_enable(struct net_device *dev) |
| 336 | { |
| 337 | struct smc_local *lp = netdev_priv(dev); |
| 338 | void __iomem *ioaddr = lp->base; |
| 339 | int mask; |
| 340 | |
| 341 | DBG(2, "%s: %s\n", dev->name, __func__); |
| 342 | |
| 343 | /* see the header file for options in TCR/RCR DEFAULT */ |
| 344 | SMC_SELECT_BANK(lp, 0); |
| 345 | SMC_SET_TCR(lp, lp->tcr_cur_mode); |
| 346 | SMC_SET_RCR(lp, lp->rcr_cur_mode); |
| 347 | |
| 348 | SMC_SELECT_BANK(lp, 1); |
| 349 | SMC_SET_MAC_ADDR(lp, dev->dev_addr); |
| 350 | |
| 351 | /* now, enable interrupts */ |
| 352 | mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; |
| 353 | if (lp->version >= (CHIP_91100 << 4)) |
| 354 | mask |= IM_MDINT; |
| 355 | SMC_SELECT_BANK(lp, 2); |
| 356 | SMC_SET_INT_MASK(lp, mask); |
| 357 | |
| 358 | /* |
| 359 | * From this point the register bank must _NOT_ be switched away |
| 360 | * to something else than bank 2 without proper locking against |
| 361 | * races with any tasklet or interrupt handlers until smc_shutdown() |
| 362 | * or smc_reset() is called. |
| 363 | */ |
| 364 | } |
| 365 | |
| 366 | /* |
| 367 | * this puts the device in an inactive state |
| 368 | */ |
| 369 | static void smc_shutdown(struct net_device *dev) |
| 370 | { |
| 371 | struct smc_local *lp = netdev_priv(dev); |
| 372 | void __iomem *ioaddr = lp->base; |
| 373 | struct sk_buff *pending_skb; |
| 374 | |
| 375 | DBG(2, "%s: %s\n", CARDNAME, __func__); |
| 376 | |
| 377 | /* no more interrupts for me */ |
| 378 | spin_lock_irq(&lp->lock); |
| 379 | SMC_SELECT_BANK(lp, 2); |
| 380 | SMC_SET_INT_MASK(lp, 0); |
| 381 | pending_skb = lp->pending_tx_skb; |
| 382 | lp->pending_tx_skb = NULL; |
| 383 | spin_unlock_irq(&lp->lock); |
| 384 | if (pending_skb) |
| 385 | dev_kfree_skb(pending_skb); |
| 386 | |
| 387 | /* and tell the card to stay away from that nasty outside world */ |
| 388 | SMC_SELECT_BANK(lp, 0); |
| 389 | SMC_SET_RCR(lp, RCR_CLEAR); |
| 390 | SMC_SET_TCR(lp, TCR_CLEAR); |
| 391 | |
| 392 | #ifdef POWER_DOWN |
| 393 | /* finally, shut the chip down */ |
| 394 | SMC_SELECT_BANK(lp, 1); |
| 395 | SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN); |
| 396 | #endif |
| 397 | } |
| 398 | |
| 399 | /* |
| 400 | * This is the procedure to handle the receipt of a packet. |
| 401 | */ |
| 402 | static inline void smc_rcv(struct net_device *dev) |
| 403 | { |
| 404 | struct smc_local *lp = netdev_priv(dev); |
| 405 | void __iomem *ioaddr = lp->base; |
| 406 | unsigned int packet_number, status, packet_len; |
| 407 | |
| 408 | DBG(3, "%s: %s\n", dev->name, __func__); |
| 409 | |
| 410 | packet_number = SMC_GET_RXFIFO(lp); |
| 411 | if (unlikely(packet_number & RXFIFO_REMPTY)) { |
| 412 | PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name); |
| 413 | return; |
| 414 | } |
| 415 | |
| 416 | /* read from start of packet */ |
| 417 | SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC); |
| 418 | |
| 419 | /* First two words are status and packet length */ |
| 420 | SMC_GET_PKT_HDR(lp, status, packet_len); |
| 421 | packet_len &= 0x07ff; /* mask off top bits */ |
| 422 | DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", |
| 423 | dev->name, packet_number, status, |
| 424 | packet_len, packet_len); |
| 425 | |
| 426 | back: |
| 427 | if (unlikely(packet_len < 6 || status & RS_ERRORS)) { |
| 428 | if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) { |
| 429 | /* accept VLAN packets */ |
| 430 | status &= ~RS_TOOLONG; |
| 431 | goto back; |
| 432 | } |
| 433 | if (packet_len < 6) { |
| 434 | /* bloody hardware */ |
| 435 | printk(KERN_ERR "%s: fubar (rxlen %u status %x\n", |
| 436 | dev->name, packet_len, status); |
| 437 | status |= RS_TOOSHORT; |
| 438 | } |
| 439 | SMC_WAIT_MMU_BUSY(lp); |
| 440 | SMC_SET_MMU_CMD(lp, MC_RELEASE); |
| 441 | dev->stats.rx_errors++; |
| 442 | if (status & RS_ALGNERR) |
| 443 | dev->stats.rx_frame_errors++; |
| 444 | if (status & (RS_TOOSHORT | RS_TOOLONG)) |
| 445 | dev->stats.rx_length_errors++; |
| 446 | if (status & RS_BADCRC) |
| 447 | dev->stats.rx_crc_errors++; |
| 448 | } else { |
| 449 | struct sk_buff *skb; |
| 450 | unsigned char *data; |
| 451 | unsigned int data_len; |
| 452 | |
| 453 | /* set multicast stats */ |
| 454 | if (status & RS_MULTICAST) |
| 455 | dev->stats.multicast++; |
| 456 | |
| 457 | /* |
| 458 | * Actual payload is packet_len - 6 (or 5 if odd byte). |
| 459 | * We want skb_reserve(2) and the final ctrl word |
| 460 | * (2 bytes, possibly containing the payload odd byte). |
| 461 | * Furthermore, we add 2 bytes to allow rounding up to |
| 462 | * multiple of 4 bytes on 32 bit buses. |
| 463 | * Hence packet_len - 6 + 2 + 2 + 2. |
| 464 | */ |
| 465 | skb = dev_alloc_skb(packet_len); |
| 466 | if (unlikely(skb == NULL)) { |
| 467 | printk(KERN_NOTICE "%s: Low memory, packet dropped.\n", |
| 468 | dev->name); |
| 469 | SMC_WAIT_MMU_BUSY(lp); |
| 470 | SMC_SET_MMU_CMD(lp, MC_RELEASE); |
| 471 | dev->stats.rx_dropped++; |
| 472 | return; |
| 473 | } |
| 474 | |
| 475 | /* Align IP header to 32 bits */ |
| 476 | skb_reserve(skb, 2); |
| 477 | |
| 478 | /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ |
| 479 | if (lp->version == 0x90) |
| 480 | status |= RS_ODDFRAME; |
| 481 | |
| 482 | /* |
| 483 | * If odd length: packet_len - 5, |
| 484 | * otherwise packet_len - 6. |
| 485 | * With the trailing ctrl byte it's packet_len - 4. |
| 486 | */ |
| 487 | data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6); |
| 488 | data = skb_put(skb, data_len); |
| 489 | SMC_PULL_DATA(lp, data, packet_len - 4); |
| 490 | |
| 491 | SMC_WAIT_MMU_BUSY(lp); |
| 492 | SMC_SET_MMU_CMD(lp, MC_RELEASE); |
| 493 | |
| 494 | PRINT_PKT(data, packet_len - 4); |
| 495 | |
| 496 | skb->protocol = eth_type_trans(skb, dev); |
| 497 | netif_rx(skb); |
| 498 | dev->stats.rx_packets++; |
| 499 | dev->stats.rx_bytes += data_len; |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | #ifdef CONFIG_SMP |
| 504 | /* |
| 505 | * On SMP we have the following problem: |
| 506 | * |
| 507 | * A = smc_hardware_send_pkt() |
| 508 | * B = smc_hard_start_xmit() |
| 509 | * C = smc_interrupt() |
| 510 | * |
| 511 | * A and B can never be executed simultaneously. However, at least on UP, |
| 512 | * it is possible (and even desirable) for C to interrupt execution of |
| 513 | * A or B in order to have better RX reliability and avoid overruns. |
| 514 | * C, just like A and B, must have exclusive access to the chip and |
| 515 | * each of them must lock against any other concurrent access. |
| 516 | * Unfortunately this is not possible to have C suspend execution of A or |
| 517 | * B taking place on another CPU. On UP this is no an issue since A and B |
| 518 | * are run from softirq context and C from hard IRQ context, and there is |
| 519 | * no other CPU where concurrent access can happen. |
| 520 | * If ever there is a way to force at least B and C to always be executed |
| 521 | * on the same CPU then we could use read/write locks to protect against |
| 522 | * any other concurrent access and C would always interrupt B. But life |
| 523 | * isn't that easy in a SMP world... |
| 524 | */ |
| 525 | #define smc_special_trylock(lock, flags) \ |
| 526 | ({ \ |
| 527 | int __ret; \ |
| 528 | local_irq_save(flags); \ |
| 529 | __ret = spin_trylock(lock); \ |
| 530 | if (!__ret) \ |
| 531 | local_irq_restore(flags); \ |
| 532 | __ret; \ |
| 533 | }) |
| 534 | #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags) |
| 535 | #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags) |
| 536 | #else |
| 537 | #define smc_special_trylock(lock, flags) (1) |
| 538 | #define smc_special_lock(lock, flags) do { } while (0) |
| 539 | #define smc_special_unlock(lock, flags) do { } while (0) |
| 540 | #endif |
| 541 | |
| 542 | /* |
| 543 | * This is called to actually send a packet to the chip. |
| 544 | */ |
| 545 | static void smc_hardware_send_pkt(unsigned long data) |
| 546 | { |
| 547 | struct net_device *dev = (struct net_device *)data; |
| 548 | struct smc_local *lp = netdev_priv(dev); |
| 549 | void __iomem *ioaddr = lp->base; |
| 550 | struct sk_buff *skb; |
| 551 | unsigned int packet_no, len; |
| 552 | unsigned char *buf; |
| 553 | unsigned long flags; |
| 554 | |
| 555 | DBG(3, "%s: %s\n", dev->name, __func__); |
| 556 | |
| 557 | if (!smc_special_trylock(&lp->lock, flags)) { |
| 558 | netif_stop_queue(dev); |
| 559 | tasklet_schedule(&lp->tx_task); |
| 560 | return; |
| 561 | } |
| 562 | |
| 563 | skb = lp->pending_tx_skb; |
| 564 | if (unlikely(!skb)) { |
| 565 | smc_special_unlock(&lp->lock, flags); |
| 566 | return; |
| 567 | } |
| 568 | lp->pending_tx_skb = NULL; |
| 569 | |
| 570 | packet_no = SMC_GET_AR(lp); |
| 571 | if (unlikely(packet_no & AR_FAILED)) { |
| 572 | printk("%s: Memory allocation failed.\n", dev->name); |
| 573 | dev->stats.tx_errors++; |
| 574 | dev->stats.tx_fifo_errors++; |
| 575 | smc_special_unlock(&lp->lock, flags); |
| 576 | goto done; |
| 577 | } |
| 578 | |
| 579 | /* point to the beginning of the packet */ |
| 580 | SMC_SET_PN(lp, packet_no); |
| 581 | SMC_SET_PTR(lp, PTR_AUTOINC); |
| 582 | |
| 583 | buf = skb->data; |
| 584 | len = skb->len; |
| 585 | DBG(2, "%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", |
| 586 | dev->name, packet_no, len, len, buf); |
| 587 | PRINT_PKT(buf, len); |
| 588 | |
| 589 | /* |
| 590 | * Send the packet length (+6 for status words, length, and ctl. |
| 591 | * The card will pad to 64 bytes with zeroes if packet is too small. |
| 592 | */ |
| 593 | SMC_PUT_PKT_HDR(lp, 0, len + 6); |
| 594 | |
| 595 | /* send the actual data */ |
| 596 | SMC_PUSH_DATA(lp, buf, len & ~1); |
| 597 | |
| 598 | /* Send final ctl word with the last byte if there is one */ |
| 599 | SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp)); |
| 600 | |
| 601 | /* |
| 602 | * If THROTTLE_TX_PKTS is set, we stop the queue here. This will |
| 603 | * have the effect of having at most one packet queued for TX |
| 604 | * in the chip's memory at all time. |
| 605 | * |
| 606 | * If THROTTLE_TX_PKTS is not set then the queue is stopped only |
| 607 | * when memory allocation (MC_ALLOC) does not succeed right away. |
| 608 | */ |
| 609 | if (THROTTLE_TX_PKTS) |
| 610 | netif_stop_queue(dev); |
| 611 | |
| 612 | /* queue the packet for TX */ |
| 613 | SMC_SET_MMU_CMD(lp, MC_ENQUEUE); |
| 614 | smc_special_unlock(&lp->lock, flags); |
| 615 | |
| 616 | dev->trans_start = jiffies; |
| 617 | dev->stats.tx_packets++; |
| 618 | dev->stats.tx_bytes += len; |
| 619 | |
| 620 | SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT); |
| 621 | |
| 622 | done: if (!THROTTLE_TX_PKTS) |
| 623 | netif_wake_queue(dev); |
| 624 | |
| 625 | dev_kfree_skb(skb); |
| 626 | } |
| 627 | |
| 628 | /* |
| 629 | * Since I am not sure if I will have enough room in the chip's ram |
| 630 | * to store the packet, I call this routine which either sends it |
| 631 | * now, or set the card to generates an interrupt when ready |
| 632 | * for the packet. |
| 633 | */ |
| 634 | static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 635 | { |
| 636 | struct smc_local *lp = netdev_priv(dev); |
| 637 | void __iomem *ioaddr = lp->base; |
| 638 | unsigned int numPages, poll_count, status; |
| 639 | unsigned long flags; |
| 640 | |
| 641 | DBG(3, "%s: %s\n", dev->name, __func__); |
| 642 | |
| 643 | BUG_ON(lp->pending_tx_skb != NULL); |
| 644 | |
| 645 | /* |
| 646 | * The MMU wants the number of pages to be the number of 256 bytes |
| 647 | * 'pages', minus 1 (since a packet can't ever have 0 pages :)) |
| 648 | * |
| 649 | * The 91C111 ignores the size bits, but earlier models don't. |
| 650 | * |
| 651 | * Pkt size for allocating is data length +6 (for additional status |
| 652 | * words, length and ctl) |
| 653 | * |
| 654 | * If odd size then last byte is included in ctl word. |
| 655 | */ |
| 656 | numPages = ((skb->len & ~1) + (6 - 1)) >> 8; |
| 657 | if (unlikely(numPages > 7)) { |
| 658 | printk("%s: Far too big packet error.\n", dev->name); |
| 659 | dev->stats.tx_errors++; |
| 660 | dev->stats.tx_dropped++; |
| 661 | dev_kfree_skb(skb); |
| 662 | return NETDEV_TX_OK; |
| 663 | } |
| 664 | |
| 665 | smc_special_lock(&lp->lock, flags); |
| 666 | |
| 667 | /* now, try to allocate the memory */ |
| 668 | SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages); |
| 669 | |
| 670 | /* |
| 671 | * Poll the chip for a short amount of time in case the |
| 672 | * allocation succeeds quickly. |
| 673 | */ |
| 674 | poll_count = MEMORY_WAIT_TIME; |
| 675 | do { |
| 676 | status = SMC_GET_INT(lp); |
| 677 | if (status & IM_ALLOC_INT) { |
| 678 | SMC_ACK_INT(lp, IM_ALLOC_INT); |
| 679 | break; |
| 680 | } |
| 681 | } while (--poll_count); |
| 682 | |
| 683 | smc_special_unlock(&lp->lock, flags); |
| 684 | |
| 685 | lp->pending_tx_skb = skb; |
| 686 | if (!poll_count) { |
| 687 | /* oh well, wait until the chip finds memory later */ |
| 688 | netif_stop_queue(dev); |
| 689 | DBG(2, "%s: TX memory allocation deferred.\n", dev->name); |
| 690 | SMC_ENABLE_INT(lp, IM_ALLOC_INT); |
| 691 | } else { |
| 692 | /* |
| 693 | * Allocation succeeded: push packet to the chip's own memory |
| 694 | * immediately. |
| 695 | */ |
| 696 | smc_hardware_send_pkt((unsigned long)dev); |
| 697 | } |
| 698 | |
| 699 | return NETDEV_TX_OK; |
| 700 | } |
| 701 | |
| 702 | /* |
| 703 | * This handles a TX interrupt, which is only called when: |
| 704 | * - a TX error occurred, or |
| 705 | * - CTL_AUTO_RELEASE is not set and TX of a packet completed. |
| 706 | */ |
| 707 | static void smc_tx(struct net_device *dev) |
| 708 | { |
| 709 | struct smc_local *lp = netdev_priv(dev); |
| 710 | void __iomem *ioaddr = lp->base; |
| 711 | unsigned int saved_packet, packet_no, tx_status, pkt_len; |
| 712 | |
| 713 | DBG(3, "%s: %s\n", dev->name, __func__); |
| 714 | |
| 715 | /* If the TX FIFO is empty then nothing to do */ |
| 716 | packet_no = SMC_GET_TXFIFO(lp); |
| 717 | if (unlikely(packet_no & TXFIFO_TEMPTY)) { |
| 718 | PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name); |
| 719 | return; |
| 720 | } |
| 721 | |
| 722 | /* select packet to read from */ |
| 723 | saved_packet = SMC_GET_PN(lp); |
| 724 | SMC_SET_PN(lp, packet_no); |
| 725 | |
| 726 | /* read the first word (status word) from this packet */ |
| 727 | SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ); |
| 728 | SMC_GET_PKT_HDR(lp, tx_status, pkt_len); |
| 729 | DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n", |
| 730 | dev->name, tx_status, packet_no); |
| 731 | |
| 732 | if (!(tx_status & ES_TX_SUC)) |
| 733 | dev->stats.tx_errors++; |
| 734 | |
| 735 | if (tx_status & ES_LOSTCARR) |
| 736 | dev->stats.tx_carrier_errors++; |
| 737 | |
| 738 | if (tx_status & (ES_LATCOL | ES_16COL)) { |
| 739 | PRINTK("%s: %s occurred on last xmit\n", dev->name, |
| 740 | (tx_status & ES_LATCOL) ? |
| 741 | "late collision" : "too many collisions"); |
| 742 | dev->stats.tx_window_errors++; |
| 743 | if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) { |
| 744 | printk(KERN_INFO "%s: unexpectedly large number of " |
| 745 | "bad collisions. Please check duplex " |
| 746 | "setting.\n", dev->name); |
| 747 | } |
| 748 | } |
| 749 | |
| 750 | /* kill the packet */ |
| 751 | SMC_WAIT_MMU_BUSY(lp); |
| 752 | SMC_SET_MMU_CMD(lp, MC_FREEPKT); |
| 753 | |
| 754 | /* Don't restore Packet Number Reg until busy bit is cleared */ |
| 755 | SMC_WAIT_MMU_BUSY(lp); |
| 756 | SMC_SET_PN(lp, saved_packet); |
| 757 | |
| 758 | /* re-enable transmit */ |
| 759 | SMC_SELECT_BANK(lp, 0); |
| 760 | SMC_SET_TCR(lp, lp->tcr_cur_mode); |
| 761 | SMC_SELECT_BANK(lp, 2); |
| 762 | } |
| 763 | |
| 764 | |
| 765 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ |
| 766 | |
| 767 | static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) |
| 768 | { |
| 769 | struct smc_local *lp = netdev_priv(dev); |
| 770 | void __iomem *ioaddr = lp->base; |
| 771 | unsigned int mii_reg, mask; |
| 772 | |
| 773 | mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); |
| 774 | mii_reg |= MII_MDOE; |
| 775 | |
| 776 | for (mask = 1 << (bits - 1); mask; mask >>= 1) { |
| 777 | if (val & mask) |
| 778 | mii_reg |= MII_MDO; |
| 779 | else |
| 780 | mii_reg &= ~MII_MDO; |
| 781 | |
| 782 | SMC_SET_MII(lp, mii_reg); |
| 783 | udelay(MII_DELAY); |
| 784 | SMC_SET_MII(lp, mii_reg | MII_MCLK); |
| 785 | udelay(MII_DELAY); |
| 786 | } |
| 787 | } |
| 788 | |
| 789 | static unsigned int smc_mii_in(struct net_device *dev, int bits) |
| 790 | { |
| 791 | struct smc_local *lp = netdev_priv(dev); |
| 792 | void __iomem *ioaddr = lp->base; |
| 793 | unsigned int mii_reg, mask, val; |
| 794 | |
| 795 | mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); |
| 796 | SMC_SET_MII(lp, mii_reg); |
| 797 | |
| 798 | for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { |
| 799 | if (SMC_GET_MII(lp) & MII_MDI) |
| 800 | val |= mask; |
| 801 | |
| 802 | SMC_SET_MII(lp, mii_reg); |
| 803 | udelay(MII_DELAY); |
| 804 | SMC_SET_MII(lp, mii_reg | MII_MCLK); |
| 805 | udelay(MII_DELAY); |
| 806 | } |
| 807 | |
| 808 | return val; |
| 809 | } |
| 810 | |
| 811 | /* |
| 812 | * Reads a register from the MII Management serial interface |
| 813 | */ |
| 814 | static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) |
| 815 | { |
| 816 | struct smc_local *lp = netdev_priv(dev); |
| 817 | void __iomem *ioaddr = lp->base; |
| 818 | unsigned int phydata; |
| 819 | |
| 820 | SMC_SELECT_BANK(lp, 3); |
| 821 | |
| 822 | /* Idle - 32 ones */ |
| 823 | smc_mii_out(dev, 0xffffffff, 32); |
| 824 | |
| 825 | /* Start code (01) + read (10) + phyaddr + phyreg */ |
| 826 | smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); |
| 827 | |
| 828 | /* Turnaround (2bits) + phydata */ |
| 829 | phydata = smc_mii_in(dev, 18); |
| 830 | |
| 831 | /* Return to idle state */ |
| 832 | SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); |
| 833 | |
| 834 | DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", |
| 835 | __func__, phyaddr, phyreg, phydata); |
| 836 | |
| 837 | SMC_SELECT_BANK(lp, 2); |
| 838 | return phydata; |
| 839 | } |
| 840 | |
| 841 | /* |
| 842 | * Writes a register to the MII Management serial interface |
| 843 | */ |
| 844 | static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, |
| 845 | int phydata) |
| 846 | { |
| 847 | struct smc_local *lp = netdev_priv(dev); |
| 848 | void __iomem *ioaddr = lp->base; |
| 849 | |
| 850 | SMC_SELECT_BANK(lp, 3); |
| 851 | |
| 852 | /* Idle - 32 ones */ |
| 853 | smc_mii_out(dev, 0xffffffff, 32); |
| 854 | |
| 855 | /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ |
| 856 | smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); |
| 857 | |
| 858 | /* Return to idle state */ |
| 859 | SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); |
| 860 | |
| 861 | DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", |
| 862 | __func__, phyaddr, phyreg, phydata); |
| 863 | |
| 864 | SMC_SELECT_BANK(lp, 2); |
| 865 | } |
| 866 | |
| 867 | /* |
| 868 | * Finds and reports the PHY address |
| 869 | */ |
| 870 | static void smc_phy_detect(struct net_device *dev) |
| 871 | { |
| 872 | struct smc_local *lp = netdev_priv(dev); |
| 873 | int phyaddr; |
| 874 | |
| 875 | DBG(2, "%s: %s\n", dev->name, __func__); |
| 876 | |
| 877 | lp->phy_type = 0; |
| 878 | |
| 879 | /* |
| 880 | * Scan all 32 PHY addresses if necessary, starting at |
| 881 | * PHY#1 to PHY#31, and then PHY#0 last. |
| 882 | */ |
| 883 | for (phyaddr = 1; phyaddr < 33; ++phyaddr) { |
| 884 | unsigned int id1, id2; |
| 885 | |
| 886 | /* Read the PHY identifiers */ |
| 887 | id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); |
| 888 | id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); |
| 889 | |
| 890 | DBG(3, "%s: phy_id1=0x%x, phy_id2=0x%x\n", |
| 891 | dev->name, id1, id2); |
| 892 | |
| 893 | /* Make sure it is a valid identifier */ |
| 894 | if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && |
| 895 | id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { |
| 896 | /* Save the PHY's address */ |
| 897 | lp->mii.phy_id = phyaddr & 31; |
| 898 | lp->phy_type = id1 << 16 | id2; |
| 899 | break; |
| 900 | } |
| 901 | } |
| 902 | } |
| 903 | |
| 904 | /* |
| 905 | * Sets the PHY to a configuration as determined by the user |
| 906 | */ |
| 907 | static int smc_phy_fixed(struct net_device *dev) |
| 908 | { |
| 909 | struct smc_local *lp = netdev_priv(dev); |
| 910 | void __iomem *ioaddr = lp->base; |
| 911 | int phyaddr = lp->mii.phy_id; |
| 912 | int bmcr, cfg1; |
| 913 | |
| 914 | DBG(3, "%s: %s\n", dev->name, __func__); |
| 915 | |
| 916 | /* Enter Link Disable state */ |
| 917 | cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); |
| 918 | cfg1 |= PHY_CFG1_LNKDIS; |
| 919 | smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); |
| 920 | |
| 921 | /* |
| 922 | * Set our fixed capabilities |
| 923 | * Disable auto-negotiation |
| 924 | */ |
| 925 | bmcr = 0; |
| 926 | |
| 927 | if (lp->ctl_rfduplx) |
| 928 | bmcr |= BMCR_FULLDPLX; |
| 929 | |
| 930 | if (lp->ctl_rspeed == 100) |
| 931 | bmcr |= BMCR_SPEED100; |
| 932 | |
| 933 | /* Write our capabilities to the phy control register */ |
| 934 | smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); |
| 935 | |
| 936 | /* Re-Configure the Receive/Phy Control register */ |
| 937 | SMC_SELECT_BANK(lp, 0); |
| 938 | SMC_SET_RPC(lp, lp->rpc_cur_mode); |
| 939 | SMC_SELECT_BANK(lp, 2); |
| 940 | |
| 941 | return 1; |
| 942 | } |
| 943 | |
| 944 | /* |
| 945 | * smc_phy_reset - reset the phy |
| 946 | * @dev: net device |
| 947 | * @phy: phy address |
| 948 | * |
| 949 | * Issue a software reset for the specified PHY and |
| 950 | * wait up to 100ms for the reset to complete. We should |
| 951 | * not access the PHY for 50ms after issuing the reset. |
| 952 | * |
| 953 | * The time to wait appears to be dependent on the PHY. |
| 954 | * |
| 955 | * Must be called with lp->lock locked. |
| 956 | */ |
| 957 | static int smc_phy_reset(struct net_device *dev, int phy) |
| 958 | { |
| 959 | struct smc_local *lp = netdev_priv(dev); |
| 960 | unsigned int bmcr; |
| 961 | int timeout; |
| 962 | |
| 963 | smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); |
| 964 | |
| 965 | for (timeout = 2; timeout; timeout--) { |
| 966 | spin_unlock_irq(&lp->lock); |
| 967 | msleep(50); |
| 968 | spin_lock_irq(&lp->lock); |
| 969 | |
| 970 | bmcr = smc_phy_read(dev, phy, MII_BMCR); |
| 971 | if (!(bmcr & BMCR_RESET)) |
| 972 | break; |
| 973 | } |
| 974 | |
| 975 | return bmcr & BMCR_RESET; |
| 976 | } |
| 977 | |
| 978 | /* |
| 979 | * smc_phy_powerdown - powerdown phy |
| 980 | * @dev: net device |
| 981 | * |
| 982 | * Power down the specified PHY |
| 983 | */ |
| 984 | static void smc_phy_powerdown(struct net_device *dev) |
| 985 | { |
| 986 | struct smc_local *lp = netdev_priv(dev); |
| 987 | unsigned int bmcr; |
| 988 | int phy = lp->mii.phy_id; |
| 989 | |
| 990 | if (lp->phy_type == 0) |
| 991 | return; |
| 992 | |
| 993 | /* We need to ensure that no calls to smc_phy_configure are |
| 994 | pending. |
| 995 | */ |
| 996 | cancel_work_sync(&lp->phy_configure); |
| 997 | |
| 998 | bmcr = smc_phy_read(dev, phy, MII_BMCR); |
| 999 | smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); |
| 1000 | } |
| 1001 | |
| 1002 | /* |
| 1003 | * smc_phy_check_media - check the media status and adjust TCR |
| 1004 | * @dev: net device |
| 1005 | * @init: set true for initialisation |
| 1006 | * |
| 1007 | * Select duplex mode depending on negotiation state. This |
| 1008 | * also updates our carrier state. |
| 1009 | */ |
| 1010 | static void smc_phy_check_media(struct net_device *dev, int init) |
| 1011 | { |
| 1012 | struct smc_local *lp = netdev_priv(dev); |
| 1013 | void __iomem *ioaddr = lp->base; |
| 1014 | |
| 1015 | if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { |
| 1016 | /* duplex state has changed */ |
| 1017 | if (lp->mii.full_duplex) { |
| 1018 | lp->tcr_cur_mode |= TCR_SWFDUP; |
| 1019 | } else { |
| 1020 | lp->tcr_cur_mode &= ~TCR_SWFDUP; |
| 1021 | } |
| 1022 | |
| 1023 | SMC_SELECT_BANK(lp, 0); |
| 1024 | SMC_SET_TCR(lp, lp->tcr_cur_mode); |
| 1025 | } |
| 1026 | } |
| 1027 | |
| 1028 | /* |
| 1029 | * Configures the specified PHY through the MII management interface |
| 1030 | * using Autonegotiation. |
| 1031 | * Calls smc_phy_fixed() if the user has requested a certain config. |
| 1032 | * If RPC ANEG bit is set, the media selection is dependent purely on |
| 1033 | * the selection by the MII (either in the MII BMCR reg or the result |
| 1034 | * of autonegotiation.) If the RPC ANEG bit is cleared, the selection |
| 1035 | * is controlled by the RPC SPEED and RPC DPLX bits. |
| 1036 | */ |
| 1037 | static void smc_phy_configure(struct work_struct *work) |
| 1038 | { |
| 1039 | struct smc_local *lp = |
| 1040 | container_of(work, struct smc_local, phy_configure); |
| 1041 | struct net_device *dev = lp->dev; |
| 1042 | void __iomem *ioaddr = lp->base; |
| 1043 | int phyaddr = lp->mii.phy_id; |
| 1044 | int my_phy_caps; /* My PHY capabilities */ |
| 1045 | int my_ad_caps; /* My Advertised capabilities */ |
| 1046 | int status; |
| 1047 | |
| 1048 | DBG(3, "%s:smc_program_phy()\n", dev->name); |
| 1049 | |
| 1050 | spin_lock_irq(&lp->lock); |
| 1051 | |
| 1052 | /* |
| 1053 | * We should not be called if phy_type is zero. |
| 1054 | */ |
| 1055 | if (lp->phy_type == 0) |
| 1056 | goto smc_phy_configure_exit; |
| 1057 | |
| 1058 | if (smc_phy_reset(dev, phyaddr)) { |
| 1059 | printk("%s: PHY reset timed out\n", dev->name); |
| 1060 | goto smc_phy_configure_exit; |
| 1061 | } |
| 1062 | |
| 1063 | /* |
| 1064 | * Enable PHY Interrupts (for register 18) |
| 1065 | * Interrupts listed here are disabled |
| 1066 | */ |
| 1067 | smc_phy_write(dev, phyaddr, PHY_MASK_REG, |
| 1068 | PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | |
| 1069 | PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | |
| 1070 | PHY_INT_SPDDET | PHY_INT_DPLXDET); |
| 1071 | |
| 1072 | /* Configure the Receive/Phy Control register */ |
| 1073 | SMC_SELECT_BANK(lp, 0); |
| 1074 | SMC_SET_RPC(lp, lp->rpc_cur_mode); |
| 1075 | |
| 1076 | /* If the user requested no auto neg, then go set his request */ |
| 1077 | if (lp->mii.force_media) { |
| 1078 | smc_phy_fixed(dev); |
| 1079 | goto smc_phy_configure_exit; |
| 1080 | } |
| 1081 | |
| 1082 | /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ |
| 1083 | my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); |
| 1084 | |
| 1085 | if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { |
| 1086 | printk(KERN_INFO "Auto negotiation NOT supported\n"); |
| 1087 | smc_phy_fixed(dev); |
| 1088 | goto smc_phy_configure_exit; |
| 1089 | } |
| 1090 | |
| 1091 | my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ |
| 1092 | |
| 1093 | if (my_phy_caps & BMSR_100BASE4) |
| 1094 | my_ad_caps |= ADVERTISE_100BASE4; |
| 1095 | if (my_phy_caps & BMSR_100FULL) |
| 1096 | my_ad_caps |= ADVERTISE_100FULL; |
| 1097 | if (my_phy_caps & BMSR_100HALF) |
| 1098 | my_ad_caps |= ADVERTISE_100HALF; |
| 1099 | if (my_phy_caps & BMSR_10FULL) |
| 1100 | my_ad_caps |= ADVERTISE_10FULL; |
| 1101 | if (my_phy_caps & BMSR_10HALF) |
| 1102 | my_ad_caps |= ADVERTISE_10HALF; |
| 1103 | |
| 1104 | /* Disable capabilities not selected by our user */ |
| 1105 | if (lp->ctl_rspeed != 100) |
| 1106 | my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); |
| 1107 | |
| 1108 | if (!lp->ctl_rfduplx) |
| 1109 | my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); |
| 1110 | |
| 1111 | /* Update our Auto-Neg Advertisement Register */ |
| 1112 | smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); |
| 1113 | lp->mii.advertising = my_ad_caps; |
| 1114 | |
| 1115 | /* |
| 1116 | * Read the register back. Without this, it appears that when |
| 1117 | * auto-negotiation is restarted, sometimes it isn't ready and |
| 1118 | * the link does not come up. |
| 1119 | */ |
| 1120 | status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); |
| 1121 | |
| 1122 | DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps); |
| 1123 | DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps); |
| 1124 | |
| 1125 | /* Restart auto-negotiation process in order to advertise my caps */ |
| 1126 | smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); |
| 1127 | |
| 1128 | smc_phy_check_media(dev, 1); |
| 1129 | |
| 1130 | smc_phy_configure_exit: |
| 1131 | SMC_SELECT_BANK(lp, 2); |
| 1132 | spin_unlock_irq(&lp->lock); |
| 1133 | } |
| 1134 | |
| 1135 | /* |
| 1136 | * smc_phy_interrupt |
| 1137 | * |
| 1138 | * Purpose: Handle interrupts relating to PHY register 18. This is |
| 1139 | * called from the "hard" interrupt handler under our private spinlock. |
| 1140 | */ |
| 1141 | static void smc_phy_interrupt(struct net_device *dev) |
| 1142 | { |
| 1143 | struct smc_local *lp = netdev_priv(dev); |
| 1144 | int phyaddr = lp->mii.phy_id; |
| 1145 | int phy18; |
| 1146 | |
| 1147 | DBG(2, "%s: %s\n", dev->name, __func__); |
| 1148 | |
| 1149 | if (lp->phy_type == 0) |
| 1150 | return; |
| 1151 | |
| 1152 | for(;;) { |
| 1153 | smc_phy_check_media(dev, 0); |
| 1154 | |
| 1155 | /* Read PHY Register 18, Status Output */ |
| 1156 | phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); |
| 1157 | if ((phy18 & PHY_INT_INT) == 0) |
| 1158 | break; |
| 1159 | } |
| 1160 | } |
| 1161 | |
| 1162 | /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ |
| 1163 | |
| 1164 | static void smc_10bt_check_media(struct net_device *dev, int init) |
| 1165 | { |
| 1166 | struct smc_local *lp = netdev_priv(dev); |
| 1167 | void __iomem *ioaddr = lp->base; |
| 1168 | unsigned int old_carrier, new_carrier; |
| 1169 | |
| 1170 | old_carrier = netif_carrier_ok(dev) ? 1 : 0; |
| 1171 | |
| 1172 | SMC_SELECT_BANK(lp, 0); |
| 1173 | new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0; |
| 1174 | SMC_SELECT_BANK(lp, 2); |
| 1175 | |
| 1176 | if (init || (old_carrier != new_carrier)) { |
| 1177 | if (!new_carrier) { |
| 1178 | netif_carrier_off(dev); |
| 1179 | } else { |
| 1180 | netif_carrier_on(dev); |
| 1181 | } |
| 1182 | if (netif_msg_link(lp)) |
| 1183 | printk(KERN_INFO "%s: link %s\n", dev->name, |
| 1184 | new_carrier ? "up" : "down"); |
| 1185 | } |
| 1186 | } |
| 1187 | |
| 1188 | static void smc_eph_interrupt(struct net_device *dev) |
| 1189 | { |
| 1190 | struct smc_local *lp = netdev_priv(dev); |
| 1191 | void __iomem *ioaddr = lp->base; |
| 1192 | unsigned int ctl; |
| 1193 | |
| 1194 | smc_10bt_check_media(dev, 0); |
| 1195 | |
| 1196 | SMC_SELECT_BANK(lp, 1); |
| 1197 | ctl = SMC_GET_CTL(lp); |
| 1198 | SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE); |
| 1199 | SMC_SET_CTL(lp, ctl); |
| 1200 | SMC_SELECT_BANK(lp, 2); |
| 1201 | } |
| 1202 | |
| 1203 | /* |
| 1204 | * This is the main routine of the driver, to handle the device when |
| 1205 | * it needs some attention. |
| 1206 | */ |
| 1207 | static irqreturn_t smc_interrupt(int irq, void *dev_id) |
| 1208 | { |
| 1209 | struct net_device *dev = dev_id; |
| 1210 | struct smc_local *lp = netdev_priv(dev); |
| 1211 | void __iomem *ioaddr = lp->base; |
| 1212 | int status, mask, timeout, card_stats; |
| 1213 | int saved_pointer; |
| 1214 | |
| 1215 | DBG(3, "%s: %s\n", dev->name, __func__); |
| 1216 | |
| 1217 | spin_lock(&lp->lock); |
| 1218 | |
| 1219 | /* A preamble may be used when there is a potential race |
| 1220 | * between the interruptible transmit functions and this |
| 1221 | * ISR. */ |
| 1222 | SMC_INTERRUPT_PREAMBLE; |
| 1223 | |
| 1224 | saved_pointer = SMC_GET_PTR(lp); |
| 1225 | mask = SMC_GET_INT_MASK(lp); |
| 1226 | SMC_SET_INT_MASK(lp, 0); |
| 1227 | |
| 1228 | /* set a timeout value, so I don't stay here forever */ |
| 1229 | timeout = MAX_IRQ_LOOPS; |
| 1230 | |
| 1231 | do { |
| 1232 | status = SMC_GET_INT(lp); |
| 1233 | |
| 1234 | DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", |
| 1235 | dev->name, status, mask, |
| 1236 | ({ int meminfo; SMC_SELECT_BANK(lp, 0); |
| 1237 | meminfo = SMC_GET_MIR(lp); |
| 1238 | SMC_SELECT_BANK(lp, 2); meminfo; }), |
| 1239 | SMC_GET_FIFO(lp)); |
| 1240 | |
| 1241 | status &= mask; |
| 1242 | if (!status) |
| 1243 | break; |
| 1244 | |
| 1245 | if (status & IM_TX_INT) { |
| 1246 | /* do this before RX as it will free memory quickly */ |
| 1247 | DBG(3, "%s: TX int\n", dev->name); |
| 1248 | smc_tx(dev); |
| 1249 | SMC_ACK_INT(lp, IM_TX_INT); |
| 1250 | if (THROTTLE_TX_PKTS) |
| 1251 | netif_wake_queue(dev); |
| 1252 | } else if (status & IM_RCV_INT) { |
| 1253 | DBG(3, "%s: RX irq\n", dev->name); |
| 1254 | smc_rcv(dev); |
| 1255 | } else if (status & IM_ALLOC_INT) { |
| 1256 | DBG(3, "%s: Allocation irq\n", dev->name); |
| 1257 | tasklet_hi_schedule(&lp->tx_task); |
| 1258 | mask &= ~IM_ALLOC_INT; |
| 1259 | } else if (status & IM_TX_EMPTY_INT) { |
| 1260 | DBG(3, "%s: TX empty\n", dev->name); |
| 1261 | mask &= ~IM_TX_EMPTY_INT; |
| 1262 | |
| 1263 | /* update stats */ |
| 1264 | SMC_SELECT_BANK(lp, 0); |
| 1265 | card_stats = SMC_GET_COUNTER(lp); |
| 1266 | SMC_SELECT_BANK(lp, 2); |
| 1267 | |
| 1268 | /* single collisions */ |
| 1269 | dev->stats.collisions += card_stats & 0xF; |
| 1270 | card_stats >>= 4; |
| 1271 | |
| 1272 | /* multiple collisions */ |
| 1273 | dev->stats.collisions += card_stats & 0xF; |
| 1274 | } else if (status & IM_RX_OVRN_INT) { |
| 1275 | DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name, |
| 1276 | ({ int eph_st; SMC_SELECT_BANK(lp, 0); |
| 1277 | eph_st = SMC_GET_EPH_STATUS(lp); |
| 1278 | SMC_SELECT_BANK(lp, 2); eph_st; })); |
| 1279 | SMC_ACK_INT(lp, IM_RX_OVRN_INT); |
| 1280 | dev->stats.rx_errors++; |
| 1281 | dev->stats.rx_fifo_errors++; |
| 1282 | } else if (status & IM_EPH_INT) { |
| 1283 | smc_eph_interrupt(dev); |
| 1284 | } else if (status & IM_MDINT) { |
| 1285 | SMC_ACK_INT(lp, IM_MDINT); |
| 1286 | smc_phy_interrupt(dev); |
| 1287 | } else if (status & IM_ERCV_INT) { |
| 1288 | SMC_ACK_INT(lp, IM_ERCV_INT); |
| 1289 | PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name); |
| 1290 | } |
| 1291 | } while (--timeout); |
| 1292 | |
| 1293 | /* restore register states */ |
| 1294 | SMC_SET_PTR(lp, saved_pointer); |
| 1295 | SMC_SET_INT_MASK(lp, mask); |
| 1296 | spin_unlock(&lp->lock); |
| 1297 | |
| 1298 | #ifndef CONFIG_NET_POLL_CONTROLLER |
| 1299 | if (timeout == MAX_IRQ_LOOPS) |
| 1300 | PRINTK("%s: spurious interrupt (mask = 0x%02x)\n", |
| 1301 | dev->name, mask); |
| 1302 | #endif |
| 1303 | DBG(3, "%s: Interrupt done (%d loops)\n", |
| 1304 | dev->name, MAX_IRQ_LOOPS - timeout); |
| 1305 | |
| 1306 | /* |
| 1307 | * We return IRQ_HANDLED unconditionally here even if there was |
| 1308 | * nothing to do. There is a possibility that a packet might |
| 1309 | * get enqueued into the chip right after TX_EMPTY_INT is raised |
| 1310 | * but just before the CPU acknowledges the IRQ. |
| 1311 | * Better take an unneeded IRQ in some occasions than complexifying |
| 1312 | * the code for all cases. |
| 1313 | */ |
| 1314 | return IRQ_HANDLED; |
| 1315 | } |
| 1316 | |
| 1317 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1318 | /* |
| 1319 | * Polling receive - used by netconsole and other diagnostic tools |
| 1320 | * to allow network i/o with interrupts disabled. |
| 1321 | */ |
| 1322 | static void smc_poll_controller(struct net_device *dev) |
| 1323 | { |
| 1324 | disable_irq(dev->irq); |
| 1325 | smc_interrupt(dev->irq, dev); |
| 1326 | enable_irq(dev->irq); |
| 1327 | } |
| 1328 | #endif |
| 1329 | |
| 1330 | /* Our watchdog timed out. Called by the networking layer */ |
| 1331 | static void smc_timeout(struct net_device *dev) |
| 1332 | { |
| 1333 | struct smc_local *lp = netdev_priv(dev); |
| 1334 | void __iomem *ioaddr = lp->base; |
| 1335 | int status, mask, eph_st, meminfo, fifo; |
| 1336 | |
| 1337 | DBG(2, "%s: %s\n", dev->name, __func__); |
| 1338 | |
| 1339 | spin_lock_irq(&lp->lock); |
| 1340 | status = SMC_GET_INT(lp); |
| 1341 | mask = SMC_GET_INT_MASK(lp); |
| 1342 | fifo = SMC_GET_FIFO(lp); |
| 1343 | SMC_SELECT_BANK(lp, 0); |
| 1344 | eph_st = SMC_GET_EPH_STATUS(lp); |
| 1345 | meminfo = SMC_GET_MIR(lp); |
| 1346 | SMC_SELECT_BANK(lp, 2); |
| 1347 | spin_unlock_irq(&lp->lock); |
| 1348 | PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x " |
| 1349 | "MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n", |
| 1350 | dev->name, status, mask, meminfo, fifo, eph_st ); |
| 1351 | |
| 1352 | smc_reset(dev); |
| 1353 | smc_enable(dev); |
| 1354 | |
| 1355 | /* |
| 1356 | * Reconfiguring the PHY doesn't seem like a bad idea here, but |
| 1357 | * smc_phy_configure() calls msleep() which calls schedule_timeout() |
| 1358 | * which calls schedule(). Hence we use a work queue. |
| 1359 | */ |
| 1360 | if (lp->phy_type != 0) |
| 1361 | schedule_work(&lp->phy_configure); |
| 1362 | |
| 1363 | /* We can accept TX packets again */ |
| 1364 | dev->trans_start = jiffies; |
| 1365 | netif_wake_queue(dev); |
| 1366 | } |
| 1367 | |
| 1368 | /* |
| 1369 | * This routine will, depending on the values passed to it, |
| 1370 | * either make it accept multicast packets, go into |
| 1371 | * promiscuous mode (for TCPDUMP and cousins) or accept |
| 1372 | * a select set of multicast packets |
| 1373 | */ |
| 1374 | static void smc_set_multicast_list(struct net_device *dev) |
| 1375 | { |
| 1376 | struct smc_local *lp = netdev_priv(dev); |
| 1377 | void __iomem *ioaddr = lp->base; |
| 1378 | unsigned char multicast_table[8]; |
| 1379 | int update_multicast = 0; |
| 1380 | |
| 1381 | DBG(2, "%s: %s\n", dev->name, __func__); |
| 1382 | |
| 1383 | if (dev->flags & IFF_PROMISC) { |
| 1384 | DBG(2, "%s: RCR_PRMS\n", dev->name); |
| 1385 | lp->rcr_cur_mode |= RCR_PRMS; |
| 1386 | } |
| 1387 | |
| 1388 | /* BUG? I never disable promiscuous mode if multicasting was turned on. |
| 1389 | Now, I turn off promiscuous mode, but I don't do anything to multicasting |
| 1390 | when promiscuous mode is turned on. |
| 1391 | */ |
| 1392 | |
| 1393 | /* |
| 1394 | * Here, I am setting this to accept all multicast packets. |
| 1395 | * I don't need to zero the multicast table, because the flag is |
| 1396 | * checked before the table is |
| 1397 | */ |
| 1398 | else if (dev->flags & IFF_ALLMULTI || dev->mc_count > 16) { |
| 1399 | DBG(2, "%s: RCR_ALMUL\n", dev->name); |
| 1400 | lp->rcr_cur_mode |= RCR_ALMUL; |
| 1401 | } |
| 1402 | |
| 1403 | /* |
| 1404 | * This sets the internal hardware table to filter out unwanted |
| 1405 | * multicast packets before they take up memory. |
| 1406 | * |
| 1407 | * The SMC chip uses a hash table where the high 6 bits of the CRC of |
| 1408 | * address are the offset into the table. If that bit is 1, then the |
| 1409 | * multicast packet is accepted. Otherwise, it's dropped silently. |
| 1410 | * |
| 1411 | * To use the 6 bits as an offset into the table, the high 3 bits are |
| 1412 | * the number of the 8 bit register, while the low 3 bits are the bit |
| 1413 | * within that register. |
| 1414 | */ |
| 1415 | else if (dev->mc_count) { |
| 1416 | int i; |
| 1417 | struct dev_mc_list *cur_addr; |
| 1418 | |
| 1419 | /* table for flipping the order of 3 bits */ |
| 1420 | static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7}; |
| 1421 | |
| 1422 | /* start with a table of all zeros: reject all */ |
| 1423 | memset(multicast_table, 0, sizeof(multicast_table)); |
| 1424 | |
| 1425 | cur_addr = dev->mc_list; |
| 1426 | for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) { |
| 1427 | int position; |
| 1428 | |
| 1429 | /* do we have a pointer here? */ |
| 1430 | if (!cur_addr) |
| 1431 | break; |
| 1432 | /* make sure this is a multicast address - |
| 1433 | shouldn't this be a given if we have it here ? */ |
| 1434 | if (!(*cur_addr->dmi_addr & 1)) |
| 1435 | continue; |
| 1436 | |
| 1437 | /* only use the low order bits */ |
| 1438 | position = crc32_le(~0, cur_addr->dmi_addr, 6) & 0x3f; |
| 1439 | |
| 1440 | /* do some messy swapping to put the bit in the right spot */ |
| 1441 | multicast_table[invert3[position&7]] |= |
| 1442 | (1<<invert3[(position>>3)&7]); |
| 1443 | } |
| 1444 | |
| 1445 | /* be sure I get rid of flags I might have set */ |
| 1446 | lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); |
| 1447 | |
| 1448 | /* now, the table can be loaded into the chipset */ |
| 1449 | update_multicast = 1; |
| 1450 | } else { |
| 1451 | DBG(2, "%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name); |
| 1452 | lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); |
| 1453 | |
| 1454 | /* |
| 1455 | * since I'm disabling all multicast entirely, I need to |
| 1456 | * clear the multicast list |
| 1457 | */ |
| 1458 | memset(multicast_table, 0, sizeof(multicast_table)); |
| 1459 | update_multicast = 1; |
| 1460 | } |
| 1461 | |
| 1462 | spin_lock_irq(&lp->lock); |
| 1463 | SMC_SELECT_BANK(lp, 0); |
| 1464 | SMC_SET_RCR(lp, lp->rcr_cur_mode); |
| 1465 | if (update_multicast) { |
| 1466 | SMC_SELECT_BANK(lp, 3); |
| 1467 | SMC_SET_MCAST(lp, multicast_table); |
| 1468 | } |
| 1469 | SMC_SELECT_BANK(lp, 2); |
| 1470 | spin_unlock_irq(&lp->lock); |
| 1471 | } |
| 1472 | |
| 1473 | |
| 1474 | /* |
| 1475 | * Open and Initialize the board |
| 1476 | * |
| 1477 | * Set up everything, reset the card, etc.. |
| 1478 | */ |
| 1479 | static int |
| 1480 | smc_open(struct net_device *dev) |
| 1481 | { |
| 1482 | struct smc_local *lp = netdev_priv(dev); |
| 1483 | |
| 1484 | DBG(2, "%s: %s\n", dev->name, __func__); |
| 1485 | |
| 1486 | /* |
| 1487 | * Check that the address is valid. If its not, refuse |
| 1488 | * to bring the device up. The user must specify an |
| 1489 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx |
| 1490 | */ |
| 1491 | if (!is_valid_ether_addr(dev->dev_addr)) { |
| 1492 | PRINTK("%s: no valid ethernet hw addr\n", __func__); |
| 1493 | return -EINVAL; |
| 1494 | } |
| 1495 | |
| 1496 | /* Setup the default Register Modes */ |
| 1497 | lp->tcr_cur_mode = TCR_DEFAULT; |
| 1498 | lp->rcr_cur_mode = RCR_DEFAULT; |
| 1499 | lp->rpc_cur_mode = RPC_DEFAULT | |
| 1500 | lp->cfg.leda << RPC_LSXA_SHFT | |
| 1501 | lp->cfg.ledb << RPC_LSXB_SHFT; |
| 1502 | |
| 1503 | /* |
| 1504 | * If we are not using a MII interface, we need to |
| 1505 | * monitor our own carrier signal to detect faults. |
| 1506 | */ |
| 1507 | if (lp->phy_type == 0) |
| 1508 | lp->tcr_cur_mode |= TCR_MON_CSN; |
| 1509 | |
| 1510 | /* reset the hardware */ |
| 1511 | smc_reset(dev); |
| 1512 | smc_enable(dev); |
| 1513 | |
| 1514 | /* Configure the PHY, initialize the link state */ |
| 1515 | if (lp->phy_type != 0) |
| 1516 | smc_phy_configure(&lp->phy_configure); |
| 1517 | else { |
| 1518 | spin_lock_irq(&lp->lock); |
| 1519 | smc_10bt_check_media(dev, 1); |
| 1520 | spin_unlock_irq(&lp->lock); |
| 1521 | } |
| 1522 | |
| 1523 | netif_start_queue(dev); |
| 1524 | return 0; |
| 1525 | } |
| 1526 | |
| 1527 | /* |
| 1528 | * smc_close |
| 1529 | * |
| 1530 | * this makes the board clean up everything that it can |
| 1531 | * and not talk to the outside world. Caused by |
| 1532 | * an 'ifconfig ethX down' |
| 1533 | */ |
| 1534 | static int smc_close(struct net_device *dev) |
| 1535 | { |
| 1536 | struct smc_local *lp = netdev_priv(dev); |
| 1537 | |
| 1538 | DBG(2, "%s: %s\n", dev->name, __func__); |
| 1539 | |
| 1540 | netif_stop_queue(dev); |
| 1541 | netif_carrier_off(dev); |
| 1542 | |
| 1543 | /* clear everything */ |
| 1544 | smc_shutdown(dev); |
| 1545 | tasklet_kill(&lp->tx_task); |
| 1546 | smc_phy_powerdown(dev); |
| 1547 | return 0; |
| 1548 | } |
| 1549 | |
| 1550 | /* |
| 1551 | * Ethtool support |
| 1552 | */ |
| 1553 | static int |
| 1554 | smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 1555 | { |
| 1556 | struct smc_local *lp = netdev_priv(dev); |
| 1557 | int ret; |
| 1558 | |
| 1559 | cmd->maxtxpkt = 1; |
| 1560 | cmd->maxrxpkt = 1; |
| 1561 | |
| 1562 | if (lp->phy_type != 0) { |
| 1563 | spin_lock_irq(&lp->lock); |
| 1564 | ret = mii_ethtool_gset(&lp->mii, cmd); |
| 1565 | spin_unlock_irq(&lp->lock); |
| 1566 | } else { |
| 1567 | cmd->supported = SUPPORTED_10baseT_Half | |
| 1568 | SUPPORTED_10baseT_Full | |
| 1569 | SUPPORTED_TP | SUPPORTED_AUI; |
| 1570 | |
| 1571 | if (lp->ctl_rspeed == 10) |
| 1572 | cmd->speed = SPEED_10; |
| 1573 | else if (lp->ctl_rspeed == 100) |
| 1574 | cmd->speed = SPEED_100; |
| 1575 | |
| 1576 | cmd->autoneg = AUTONEG_DISABLE; |
| 1577 | cmd->transceiver = XCVR_INTERNAL; |
| 1578 | cmd->port = 0; |
| 1579 | cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF; |
| 1580 | |
| 1581 | ret = 0; |
| 1582 | } |
| 1583 | |
| 1584 | return ret; |
| 1585 | } |
| 1586 | |
| 1587 | static int |
| 1588 | smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 1589 | { |
| 1590 | struct smc_local *lp = netdev_priv(dev); |
| 1591 | int ret; |
| 1592 | |
| 1593 | if (lp->phy_type != 0) { |
| 1594 | spin_lock_irq(&lp->lock); |
| 1595 | ret = mii_ethtool_sset(&lp->mii, cmd); |
| 1596 | spin_unlock_irq(&lp->lock); |
| 1597 | } else { |
| 1598 | if (cmd->autoneg != AUTONEG_DISABLE || |
| 1599 | cmd->speed != SPEED_10 || |
| 1600 | (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) || |
| 1601 | (cmd->port != PORT_TP && cmd->port != PORT_AUI)) |
| 1602 | return -EINVAL; |
| 1603 | |
| 1604 | // lp->port = cmd->port; |
| 1605 | lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL; |
| 1606 | |
| 1607 | // if (netif_running(dev)) |
| 1608 | // smc_set_port(dev); |
| 1609 | |
| 1610 | ret = 0; |
| 1611 | } |
| 1612 | |
| 1613 | return ret; |
| 1614 | } |
| 1615 | |
| 1616 | static void |
| 1617 | smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
| 1618 | { |
| 1619 | strncpy(info->driver, CARDNAME, sizeof(info->driver)); |
| 1620 | strncpy(info->version, version, sizeof(info->version)); |
| 1621 | strncpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info)); |
| 1622 | } |
| 1623 | |
| 1624 | static int smc_ethtool_nwayreset(struct net_device *dev) |
| 1625 | { |
| 1626 | struct smc_local *lp = netdev_priv(dev); |
| 1627 | int ret = -EINVAL; |
| 1628 | |
| 1629 | if (lp->phy_type != 0) { |
| 1630 | spin_lock_irq(&lp->lock); |
| 1631 | ret = mii_nway_restart(&lp->mii); |
| 1632 | spin_unlock_irq(&lp->lock); |
| 1633 | } |
| 1634 | |
| 1635 | return ret; |
| 1636 | } |
| 1637 | |
| 1638 | static u32 smc_ethtool_getmsglevel(struct net_device *dev) |
| 1639 | { |
| 1640 | struct smc_local *lp = netdev_priv(dev); |
| 1641 | return lp->msg_enable; |
| 1642 | } |
| 1643 | |
| 1644 | static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) |
| 1645 | { |
| 1646 | struct smc_local *lp = netdev_priv(dev); |
| 1647 | lp->msg_enable = level; |
| 1648 | } |
| 1649 | |
| 1650 | static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word) |
| 1651 | { |
| 1652 | u16 ctl; |
| 1653 | struct smc_local *lp = netdev_priv(dev); |
| 1654 | void __iomem *ioaddr = lp->base; |
| 1655 | |
| 1656 | spin_lock_irq(&lp->lock); |
| 1657 | /* load word into GP register */ |
| 1658 | SMC_SELECT_BANK(lp, 1); |
| 1659 | SMC_SET_GP(lp, word); |
| 1660 | /* set the address to put the data in EEPROM */ |
| 1661 | SMC_SELECT_BANK(lp, 2); |
| 1662 | SMC_SET_PTR(lp, addr); |
| 1663 | /* tell it to write */ |
| 1664 | SMC_SELECT_BANK(lp, 1); |
| 1665 | ctl = SMC_GET_CTL(lp); |
| 1666 | SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE)); |
| 1667 | /* wait for it to finish */ |
| 1668 | do { |
| 1669 | udelay(1); |
| 1670 | } while (SMC_GET_CTL(lp) & CTL_STORE); |
| 1671 | /* clean up */ |
| 1672 | SMC_SET_CTL(lp, ctl); |
| 1673 | SMC_SELECT_BANK(lp, 2); |
| 1674 | spin_unlock_irq(&lp->lock); |
| 1675 | return 0; |
| 1676 | } |
| 1677 | |
| 1678 | static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word) |
| 1679 | { |
| 1680 | u16 ctl; |
| 1681 | struct smc_local *lp = netdev_priv(dev); |
| 1682 | void __iomem *ioaddr = lp->base; |
| 1683 | |
| 1684 | spin_lock_irq(&lp->lock); |
| 1685 | /* set the EEPROM address to get the data from */ |
| 1686 | SMC_SELECT_BANK(lp, 2); |
| 1687 | SMC_SET_PTR(lp, addr | PTR_READ); |
| 1688 | /* tell it to load */ |
| 1689 | SMC_SELECT_BANK(lp, 1); |
| 1690 | SMC_SET_GP(lp, 0xffff); /* init to known */ |
| 1691 | ctl = SMC_GET_CTL(lp); |
| 1692 | SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD)); |
| 1693 | /* wait for it to finish */ |
| 1694 | do { |
| 1695 | udelay(1); |
| 1696 | } while (SMC_GET_CTL(lp) & CTL_RELOAD); |
| 1697 | /* read word from GP register */ |
| 1698 | *word = SMC_GET_GP(lp); |
| 1699 | /* clean up */ |
| 1700 | SMC_SET_CTL(lp, ctl); |
| 1701 | SMC_SELECT_BANK(lp, 2); |
| 1702 | spin_unlock_irq(&lp->lock); |
| 1703 | return 0; |
| 1704 | } |
| 1705 | |
| 1706 | static int smc_ethtool_geteeprom_len(struct net_device *dev) |
| 1707 | { |
| 1708 | return 0x23 * 2; |
| 1709 | } |
| 1710 | |
| 1711 | static int smc_ethtool_geteeprom(struct net_device *dev, |
| 1712 | struct ethtool_eeprom *eeprom, u8 *data) |
| 1713 | { |
| 1714 | int i; |
| 1715 | int imax; |
| 1716 | |
| 1717 | DBG(1, "Reading %d bytes at %d(0x%x)\n", |
| 1718 | eeprom->len, eeprom->offset, eeprom->offset); |
| 1719 | imax = smc_ethtool_geteeprom_len(dev); |
| 1720 | for (i = 0; i < eeprom->len; i += 2) { |
| 1721 | int ret; |
| 1722 | u16 wbuf; |
| 1723 | int offset = i + eeprom->offset; |
| 1724 | if (offset > imax) |
| 1725 | break; |
| 1726 | ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf); |
| 1727 | if (ret != 0) |
| 1728 | return ret; |
| 1729 | DBG(2, "Read 0x%x from 0x%x\n", wbuf, offset >> 1); |
| 1730 | data[i] = (wbuf >> 8) & 0xff; |
| 1731 | data[i+1] = wbuf & 0xff; |
| 1732 | } |
| 1733 | return 0; |
| 1734 | } |
| 1735 | |
| 1736 | static int smc_ethtool_seteeprom(struct net_device *dev, |
| 1737 | struct ethtool_eeprom *eeprom, u8 *data) |
| 1738 | { |
| 1739 | int i; |
| 1740 | int imax; |
| 1741 | |
| 1742 | DBG(1, "Writing %d bytes to %d(0x%x)\n", |
| 1743 | eeprom->len, eeprom->offset, eeprom->offset); |
| 1744 | imax = smc_ethtool_geteeprom_len(dev); |
| 1745 | for (i = 0; i < eeprom->len; i += 2) { |
| 1746 | int ret; |
| 1747 | u16 wbuf; |
| 1748 | int offset = i + eeprom->offset; |
| 1749 | if (offset > imax) |
| 1750 | break; |
| 1751 | wbuf = (data[i] << 8) | data[i + 1]; |
| 1752 | DBG(2, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1); |
| 1753 | ret = smc_write_eeprom_word(dev, offset >> 1, wbuf); |
| 1754 | if (ret != 0) |
| 1755 | return ret; |
| 1756 | } |
| 1757 | return 0; |
| 1758 | } |
| 1759 | |
| 1760 | |
| 1761 | static const struct ethtool_ops smc_ethtool_ops = { |
| 1762 | .get_settings = smc_ethtool_getsettings, |
| 1763 | .set_settings = smc_ethtool_setsettings, |
| 1764 | .get_drvinfo = smc_ethtool_getdrvinfo, |
| 1765 | |
| 1766 | .get_msglevel = smc_ethtool_getmsglevel, |
| 1767 | .set_msglevel = smc_ethtool_setmsglevel, |
| 1768 | .nway_reset = smc_ethtool_nwayreset, |
| 1769 | .get_link = ethtool_op_get_link, |
| 1770 | .get_eeprom_len = smc_ethtool_geteeprom_len, |
| 1771 | .get_eeprom = smc_ethtool_geteeprom, |
| 1772 | .set_eeprom = smc_ethtool_seteeprom, |
| 1773 | }; |
| 1774 | |
| 1775 | static const struct net_device_ops smc_netdev_ops = { |
| 1776 | .ndo_open = smc_open, |
| 1777 | .ndo_stop = smc_close, |
| 1778 | .ndo_start_xmit = smc_hard_start_xmit, |
| 1779 | .ndo_tx_timeout = smc_timeout, |
| 1780 | .ndo_set_multicast_list = smc_set_multicast_list, |
| 1781 | .ndo_change_mtu = eth_change_mtu, |
| 1782 | .ndo_validate_addr = eth_validate_addr, |
| 1783 | .ndo_set_mac_address = eth_mac_addr, |
| 1784 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 1785 | .ndo_poll_controller = smc_poll_controller, |
| 1786 | #endif |
| 1787 | }; |
| 1788 | |
| 1789 | /* |
| 1790 | * smc_findirq |
| 1791 | * |
| 1792 | * This routine has a simple purpose -- make the SMC chip generate an |
| 1793 | * interrupt, so an auto-detect routine can detect it, and find the IRQ, |
| 1794 | */ |
| 1795 | /* |
| 1796 | * does this still work? |
| 1797 | * |
| 1798 | * I just deleted auto_irq.c, since it was never built... |
| 1799 | * --jgarzik |
| 1800 | */ |
| 1801 | static int __devinit smc_findirq(struct smc_local *lp) |
| 1802 | { |
| 1803 | void __iomem *ioaddr = lp->base; |
| 1804 | int timeout = 20; |
| 1805 | unsigned long cookie; |
| 1806 | |
| 1807 | DBG(2, "%s: %s\n", CARDNAME, __func__); |
| 1808 | |
| 1809 | cookie = probe_irq_on(); |
| 1810 | |
| 1811 | /* |
| 1812 | * What I try to do here is trigger an ALLOC_INT. This is done |
| 1813 | * by allocating a small chunk of memory, which will give an interrupt |
| 1814 | * when done. |
| 1815 | */ |
| 1816 | /* enable ALLOCation interrupts ONLY */ |
| 1817 | SMC_SELECT_BANK(lp, 2); |
| 1818 | SMC_SET_INT_MASK(lp, IM_ALLOC_INT); |
| 1819 | |
| 1820 | /* |
| 1821 | * Allocate 512 bytes of memory. Note that the chip was just |
| 1822 | * reset so all the memory is available |
| 1823 | */ |
| 1824 | SMC_SET_MMU_CMD(lp, MC_ALLOC | 1); |
| 1825 | |
| 1826 | /* |
| 1827 | * Wait until positive that the interrupt has been generated |
| 1828 | */ |
| 1829 | do { |
| 1830 | int int_status; |
| 1831 | udelay(10); |
| 1832 | int_status = SMC_GET_INT(lp); |
| 1833 | if (int_status & IM_ALLOC_INT) |
| 1834 | break; /* got the interrupt */ |
| 1835 | } while (--timeout); |
| 1836 | |
| 1837 | /* |
| 1838 | * there is really nothing that I can do here if timeout fails, |
| 1839 | * as autoirq_report will return a 0 anyway, which is what I |
| 1840 | * want in this case. Plus, the clean up is needed in both |
| 1841 | * cases. |
| 1842 | */ |
| 1843 | |
| 1844 | /* and disable all interrupts again */ |
| 1845 | SMC_SET_INT_MASK(lp, 0); |
| 1846 | |
| 1847 | /* and return what I found */ |
| 1848 | return probe_irq_off(cookie); |
| 1849 | } |
| 1850 | |
| 1851 | /* |
| 1852 | * Function: smc_probe(unsigned long ioaddr) |
| 1853 | * |
| 1854 | * Purpose: |
| 1855 | * Tests to see if a given ioaddr points to an SMC91x chip. |
| 1856 | * Returns a 0 on success |
| 1857 | * |
| 1858 | * Algorithm: |
| 1859 | * (1) see if the high byte of BANK_SELECT is 0x33 |
| 1860 | * (2) compare the ioaddr with the base register's address |
| 1861 | * (3) see if I recognize the chip ID in the appropriate register |
| 1862 | * |
| 1863 | * Here I do typical initialization tasks. |
| 1864 | * |
| 1865 | * o Initialize the structure if needed |
| 1866 | * o print out my vanity message if not done so already |
| 1867 | * o print out what type of hardware is detected |
| 1868 | * o print out the ethernet address |
| 1869 | * o find the IRQ |
| 1870 | * o set up my private data |
| 1871 | * o configure the dev structure with my subroutines |
| 1872 | * o actually GRAB the irq. |
| 1873 | * o GRAB the region |
| 1874 | */ |
| 1875 | static int __devinit smc_probe(struct net_device *dev, void __iomem *ioaddr, |
| 1876 | unsigned long irq_flags) |
| 1877 | { |
| 1878 | struct smc_local *lp = netdev_priv(dev); |
| 1879 | static int version_printed = 0; |
| 1880 | int retval; |
| 1881 | unsigned int val, revision_register; |
| 1882 | const char *version_string; |
| 1883 | |
| 1884 | DBG(2, "%s: %s\n", CARDNAME, __func__); |
| 1885 | |
| 1886 | /* First, see if the high byte is 0x33 */ |
| 1887 | val = SMC_CURRENT_BANK(lp); |
| 1888 | DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val); |
| 1889 | if ((val & 0xFF00) != 0x3300) { |
| 1890 | if ((val & 0xFF) == 0x33) { |
| 1891 | printk(KERN_WARNING |
| 1892 | "%s: Detected possible byte-swapped interface" |
| 1893 | " at IOADDR %p\n", CARDNAME, ioaddr); |
| 1894 | } |
| 1895 | retval = -ENODEV; |
| 1896 | goto err_out; |
| 1897 | } |
| 1898 | |
| 1899 | /* |
| 1900 | * The above MIGHT indicate a device, but I need to write to |
| 1901 | * further test this. |
| 1902 | */ |
| 1903 | SMC_SELECT_BANK(lp, 0); |
| 1904 | val = SMC_CURRENT_BANK(lp); |
| 1905 | if ((val & 0xFF00) != 0x3300) { |
| 1906 | retval = -ENODEV; |
| 1907 | goto err_out; |
| 1908 | } |
| 1909 | |
| 1910 | /* |
| 1911 | * well, we've already written once, so hopefully another |
| 1912 | * time won't hurt. This time, I need to switch the bank |
| 1913 | * register to bank 1, so I can access the base address |
| 1914 | * register |
| 1915 | */ |
| 1916 | SMC_SELECT_BANK(lp, 1); |
| 1917 | val = SMC_GET_BASE(lp); |
| 1918 | val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; |
| 1919 | if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { |
| 1920 | printk("%s: IOADDR %p doesn't match configuration (%x).\n", |
| 1921 | CARDNAME, ioaddr, val); |
| 1922 | } |
| 1923 | |
| 1924 | /* |
| 1925 | * check if the revision register is something that I |
| 1926 | * recognize. These might need to be added to later, |
| 1927 | * as future revisions could be added. |
| 1928 | */ |
| 1929 | SMC_SELECT_BANK(lp, 3); |
| 1930 | revision_register = SMC_GET_REV(lp); |
| 1931 | DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register); |
| 1932 | version_string = chip_ids[ (revision_register >> 4) & 0xF]; |
| 1933 | if (!version_string || (revision_register & 0xff00) != 0x3300) { |
| 1934 | /* I don't recognize this chip, so... */ |
| 1935 | printk("%s: IO %p: Unrecognized revision register 0x%04x" |
| 1936 | ", Contact author.\n", CARDNAME, |
| 1937 | ioaddr, revision_register); |
| 1938 | |
| 1939 | retval = -ENODEV; |
| 1940 | goto err_out; |
| 1941 | } |
| 1942 | |
| 1943 | /* At this point I'll assume that the chip is an SMC91x. */ |
| 1944 | if (version_printed++ == 0) |
| 1945 | printk("%s", version); |
| 1946 | |
| 1947 | /* fill in some of the fields */ |
| 1948 | dev->base_addr = (unsigned long)ioaddr; |
| 1949 | lp->base = ioaddr; |
| 1950 | lp->version = revision_register & 0xff; |
| 1951 | spin_lock_init(&lp->lock); |
| 1952 | |
| 1953 | /* Get the MAC address */ |
| 1954 | SMC_SELECT_BANK(lp, 1); |
| 1955 | SMC_GET_MAC_ADDR(lp, dev->dev_addr); |
| 1956 | |
| 1957 | /* now, reset the chip, and put it into a known state */ |
| 1958 | smc_reset(dev); |
| 1959 | |
| 1960 | /* |
| 1961 | * If dev->irq is 0, then the device has to be banged on to see |
| 1962 | * what the IRQ is. |
| 1963 | * |
| 1964 | * This banging doesn't always detect the IRQ, for unknown reasons. |
| 1965 | * a workaround is to reset the chip and try again. |
| 1966 | * |
| 1967 | * Interestingly, the DOS packet driver *SETS* the IRQ on the card to |
| 1968 | * be what is requested on the command line. I don't do that, mostly |
| 1969 | * because the card that I have uses a non-standard method of accessing |
| 1970 | * the IRQs, and because this _should_ work in most configurations. |
| 1971 | * |
| 1972 | * Specifying an IRQ is done with the assumption that the user knows |
| 1973 | * what (s)he is doing. No checking is done!!!! |
| 1974 | */ |
| 1975 | if (dev->irq < 1) { |
| 1976 | int trials; |
| 1977 | |
| 1978 | trials = 3; |
| 1979 | while (trials--) { |
| 1980 | dev->irq = smc_findirq(lp); |
| 1981 | if (dev->irq) |
| 1982 | break; |
| 1983 | /* kick the card and try again */ |
| 1984 | smc_reset(dev); |
| 1985 | } |
| 1986 | } |
| 1987 | if (dev->irq == 0) { |
| 1988 | printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n", |
| 1989 | dev->name); |
| 1990 | retval = -ENODEV; |
| 1991 | goto err_out; |
| 1992 | } |
| 1993 | dev->irq = irq_canonicalize(dev->irq); |
| 1994 | |
| 1995 | /* Fill in the fields of the device structure with ethernet values. */ |
| 1996 | ether_setup(dev); |
| 1997 | |
| 1998 | dev->watchdog_timeo = msecs_to_jiffies(watchdog); |
| 1999 | dev->netdev_ops = &smc_netdev_ops; |
| 2000 | dev->ethtool_ops = &smc_ethtool_ops; |
| 2001 | |
| 2002 | tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev); |
| 2003 | INIT_WORK(&lp->phy_configure, smc_phy_configure); |
| 2004 | lp->dev = dev; |
| 2005 | lp->mii.phy_id_mask = 0x1f; |
| 2006 | lp->mii.reg_num_mask = 0x1f; |
| 2007 | lp->mii.force_media = 0; |
| 2008 | lp->mii.full_duplex = 0; |
| 2009 | lp->mii.dev = dev; |
| 2010 | lp->mii.mdio_read = smc_phy_read; |
| 2011 | lp->mii.mdio_write = smc_phy_write; |
| 2012 | |
| 2013 | /* |
| 2014 | * Locate the phy, if any. |
| 2015 | */ |
| 2016 | if (lp->version >= (CHIP_91100 << 4)) |
| 2017 | smc_phy_detect(dev); |
| 2018 | |
| 2019 | /* then shut everything down to save power */ |
| 2020 | smc_shutdown(dev); |
| 2021 | smc_phy_powerdown(dev); |
| 2022 | |
| 2023 | /* Set default parameters */ |
| 2024 | lp->msg_enable = NETIF_MSG_LINK; |
| 2025 | lp->ctl_rfduplx = 0; |
| 2026 | lp->ctl_rspeed = 10; |
| 2027 | |
| 2028 | if (lp->version >= (CHIP_91100 << 4)) { |
| 2029 | lp->ctl_rfduplx = 1; |
| 2030 | lp->ctl_rspeed = 100; |
| 2031 | } |
| 2032 | |
| 2033 | /* Grab the IRQ */ |
| 2034 | retval = request_irq(dev->irq, &smc_interrupt, irq_flags, dev->name, dev); |
| 2035 | if (retval) |
| 2036 | goto err_out; |
| 2037 | |
| 2038 | #ifdef CONFIG_ARCH_PXA |
| 2039 | # ifdef SMC_USE_PXA_DMA |
| 2040 | lp->cfg.flags |= SMC91X_USE_DMA; |
| 2041 | # endif |
| 2042 | if (lp->cfg.flags & SMC91X_USE_DMA) { |
| 2043 | int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW, |
| 2044 | smc_pxa_dma_irq, NULL); |
| 2045 | if (dma >= 0) |
| 2046 | dev->dma = dma; |
| 2047 | } |
| 2048 | #endif |
| 2049 | |
| 2050 | retval = register_netdev(dev); |
| 2051 | if (retval == 0) { |
| 2052 | /* now, print out the card info, in a short format.. */ |
| 2053 | printk("%s: %s (rev %d) at %p IRQ %d", |
| 2054 | dev->name, version_string, revision_register & 0x0f, |
| 2055 | lp->base, dev->irq); |
| 2056 | |
| 2057 | if (dev->dma != (unsigned char)-1) |
| 2058 | printk(" DMA %d", dev->dma); |
| 2059 | |
| 2060 | printk("%s%s\n", |
| 2061 | lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "", |
| 2062 | THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); |
| 2063 | |
| 2064 | if (!is_valid_ether_addr(dev->dev_addr)) { |
| 2065 | printk("%s: Invalid ethernet MAC address. Please " |
| 2066 | "set using ifconfig\n", dev->name); |
| 2067 | } else { |
| 2068 | /* Print the Ethernet address */ |
| 2069 | printk("%s: Ethernet addr: %pM\n", |
| 2070 | dev->name, dev->dev_addr); |
| 2071 | } |
| 2072 | |
| 2073 | if (lp->phy_type == 0) { |
| 2074 | PRINTK("%s: No PHY found\n", dev->name); |
| 2075 | } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { |
| 2076 | PRINTK("%s: PHY LAN83C183 (LAN91C111 Internal)\n", dev->name); |
| 2077 | } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { |
| 2078 | PRINTK("%s: PHY LAN83C180\n", dev->name); |
| 2079 | } |
| 2080 | } |
| 2081 | |
| 2082 | err_out: |
| 2083 | #ifdef CONFIG_ARCH_PXA |
| 2084 | if (retval && dev->dma != (unsigned char)-1) |
| 2085 | pxa_free_dma(dev->dma); |
| 2086 | #endif |
| 2087 | return retval; |
| 2088 | } |
| 2089 | |
| 2090 | static int smc_enable_device(struct platform_device *pdev) |
| 2091 | { |
| 2092 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 2093 | struct smc_local *lp = netdev_priv(ndev); |
| 2094 | unsigned long flags; |
| 2095 | unsigned char ecor, ecsr; |
| 2096 | void __iomem *addr; |
| 2097 | struct resource * res; |
| 2098 | |
| 2099 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); |
| 2100 | if (!res) |
| 2101 | return 0; |
| 2102 | |
| 2103 | /* |
| 2104 | * Map the attribute space. This is overkill, but clean. |
| 2105 | */ |
| 2106 | addr = ioremap(res->start, ATTRIB_SIZE); |
| 2107 | if (!addr) |
| 2108 | return -ENOMEM; |
| 2109 | |
| 2110 | /* |
| 2111 | * Reset the device. We must disable IRQs around this |
| 2112 | * since a reset causes the IRQ line become active. |
| 2113 | */ |
| 2114 | local_irq_save(flags); |
| 2115 | ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; |
| 2116 | writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); |
| 2117 | readb(addr + (ECOR << SMC_IO_SHIFT)); |
| 2118 | |
| 2119 | /* |
| 2120 | * Wait 100us for the chip to reset. |
| 2121 | */ |
| 2122 | udelay(100); |
| 2123 | |
| 2124 | /* |
| 2125 | * The device will ignore all writes to the enable bit while |
| 2126 | * reset is asserted, even if the reset bit is cleared in the |
| 2127 | * same write. Must clear reset first, then enable the device. |
| 2128 | */ |
| 2129 | writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); |
| 2130 | writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); |
| 2131 | |
| 2132 | /* |
| 2133 | * Set the appropriate byte/word mode. |
| 2134 | */ |
| 2135 | ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; |
| 2136 | if (!SMC_16BIT(lp)) |
| 2137 | ecsr |= ECSR_IOIS8; |
| 2138 | writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); |
| 2139 | local_irq_restore(flags); |
| 2140 | |
| 2141 | iounmap(addr); |
| 2142 | |
| 2143 | /* |
| 2144 | * Wait for the chip to wake up. We could poll the control |
| 2145 | * register in the main register space, but that isn't mapped |
| 2146 | * yet. We know this is going to take 750us. |
| 2147 | */ |
| 2148 | msleep(1); |
| 2149 | |
| 2150 | return 0; |
| 2151 | } |
| 2152 | |
| 2153 | static int smc_request_attrib(struct platform_device *pdev, |
| 2154 | struct net_device *ndev) |
| 2155 | { |
| 2156 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); |
| 2157 | struct smc_local *lp __maybe_unused = netdev_priv(ndev); |
| 2158 | |
| 2159 | if (!res) |
| 2160 | return 0; |
| 2161 | |
| 2162 | if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME)) |
| 2163 | return -EBUSY; |
| 2164 | |
| 2165 | return 0; |
| 2166 | } |
| 2167 | |
| 2168 | static void smc_release_attrib(struct platform_device *pdev, |
| 2169 | struct net_device *ndev) |
| 2170 | { |
| 2171 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); |
| 2172 | struct smc_local *lp __maybe_unused = netdev_priv(ndev); |
| 2173 | |
| 2174 | if (res) |
| 2175 | release_mem_region(res->start, ATTRIB_SIZE); |
| 2176 | } |
| 2177 | |
| 2178 | static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev) |
| 2179 | { |
| 2180 | if (SMC_CAN_USE_DATACS) { |
| 2181 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); |
| 2182 | struct smc_local *lp = netdev_priv(ndev); |
| 2183 | |
| 2184 | if (!res) |
| 2185 | return; |
| 2186 | |
| 2187 | if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) { |
| 2188 | printk(KERN_INFO "%s: failed to request datacs memory region.\n", CARDNAME); |
| 2189 | return; |
| 2190 | } |
| 2191 | |
| 2192 | lp->datacs = ioremap(res->start, SMC_DATA_EXTENT); |
| 2193 | } |
| 2194 | } |
| 2195 | |
| 2196 | static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev) |
| 2197 | { |
| 2198 | if (SMC_CAN_USE_DATACS) { |
| 2199 | struct smc_local *lp = netdev_priv(ndev); |
| 2200 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); |
| 2201 | |
| 2202 | if (lp->datacs) |
| 2203 | iounmap(lp->datacs); |
| 2204 | |
| 2205 | lp->datacs = NULL; |
| 2206 | |
| 2207 | if (res) |
| 2208 | release_mem_region(res->start, SMC_DATA_EXTENT); |
| 2209 | } |
| 2210 | } |
| 2211 | |
| 2212 | /* |
| 2213 | * smc_init(void) |
| 2214 | * Input parameters: |
| 2215 | * dev->base_addr == 0, try to find all possible locations |
| 2216 | * dev->base_addr > 0x1ff, this is the address to check |
| 2217 | * dev->base_addr == <anything else>, return failure code |
| 2218 | * |
| 2219 | * Output: |
| 2220 | * 0 --> there is a device |
| 2221 | * anything else, error |
| 2222 | */ |
| 2223 | static int __devinit smc_drv_probe(struct platform_device *pdev) |
| 2224 | { |
| 2225 | struct smc91x_platdata *pd = pdev->dev.platform_data; |
| 2226 | struct smc_local *lp; |
| 2227 | struct net_device *ndev; |
| 2228 | struct resource *res, *ires; |
| 2229 | unsigned int __iomem *addr; |
| 2230 | unsigned long irq_flags = SMC_IRQ_FLAGS; |
| 2231 | int ret; |
| 2232 | |
| 2233 | ndev = alloc_etherdev(sizeof(struct smc_local)); |
| 2234 | if (!ndev) { |
| 2235 | printk("%s: could not allocate device.\n", CARDNAME); |
| 2236 | ret = -ENOMEM; |
| 2237 | goto out; |
| 2238 | } |
| 2239 | SET_NETDEV_DEV(ndev, &pdev->dev); |
| 2240 | |
| 2241 | /* get configuration from platform data, only allow use of |
| 2242 | * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set. |
| 2243 | */ |
| 2244 | |
| 2245 | lp = netdev_priv(ndev); |
| 2246 | |
| 2247 | if (pd) { |
| 2248 | memcpy(&lp->cfg, pd, sizeof(lp->cfg)); |
| 2249 | lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags); |
| 2250 | } else { |
| 2251 | lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0; |
| 2252 | lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0; |
| 2253 | lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0; |
| 2254 | lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0; |
| 2255 | } |
| 2256 | |
| 2257 | if (!lp->cfg.leda && !lp->cfg.ledb) { |
| 2258 | lp->cfg.leda = RPC_LSA_DEFAULT; |
| 2259 | lp->cfg.ledb = RPC_LSB_DEFAULT; |
| 2260 | } |
| 2261 | |
| 2262 | ndev->dma = (unsigned char)-1; |
| 2263 | |
| 2264 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); |
| 2265 | if (!res) |
| 2266 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2267 | if (!res) { |
| 2268 | ret = -ENODEV; |
| 2269 | goto out_free_netdev; |
| 2270 | } |
| 2271 | |
| 2272 | |
| 2273 | if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) { |
| 2274 | ret = -EBUSY; |
| 2275 | goto out_free_netdev; |
| 2276 | } |
| 2277 | |
| 2278 | ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 2279 | if (!ires) { |
| 2280 | ret = -ENODEV; |
| 2281 | goto out_release_io; |
| 2282 | } |
| 2283 | |
| 2284 | ndev->irq = ires->start; |
| 2285 | |
| 2286 | if (ires->flags & IRQF_TRIGGER_MASK) |
| 2287 | irq_flags = ires->flags & IRQF_TRIGGER_MASK; |
| 2288 | |
| 2289 | ret = smc_request_attrib(pdev, ndev); |
| 2290 | if (ret) |
| 2291 | goto out_release_io; |
| 2292 | #if defined(CONFIG_SA1100_ASSABET) |
| 2293 | NCR_0 |= NCR_ENET_OSC_EN; |
| 2294 | #endif |
| 2295 | platform_set_drvdata(pdev, ndev); |
| 2296 | ret = smc_enable_device(pdev); |
| 2297 | if (ret) |
| 2298 | goto out_release_attrib; |
| 2299 | |
| 2300 | addr = ioremap(res->start, SMC_IO_EXTENT); |
| 2301 | if (!addr) { |
| 2302 | ret = -ENOMEM; |
| 2303 | goto out_release_attrib; |
| 2304 | } |
| 2305 | |
| 2306 | #ifdef CONFIG_ARCH_PXA |
| 2307 | { |
| 2308 | struct smc_local *lp = netdev_priv(ndev); |
| 2309 | lp->device = &pdev->dev; |
| 2310 | lp->physaddr = res->start; |
| 2311 | } |
| 2312 | #endif |
| 2313 | |
| 2314 | ret = smc_probe(ndev, addr, irq_flags); |
| 2315 | if (ret != 0) |
| 2316 | goto out_iounmap; |
| 2317 | |
| 2318 | smc_request_datacs(pdev, ndev); |
| 2319 | |
| 2320 | return 0; |
| 2321 | |
| 2322 | out_iounmap: |
| 2323 | platform_set_drvdata(pdev, NULL); |
| 2324 | iounmap(addr); |
| 2325 | out_release_attrib: |
| 2326 | smc_release_attrib(pdev, ndev); |
| 2327 | out_release_io: |
| 2328 | release_mem_region(res->start, SMC_IO_EXTENT); |
| 2329 | out_free_netdev: |
| 2330 | free_netdev(ndev); |
| 2331 | out: |
| 2332 | printk("%s: not found (%d).\n", CARDNAME, ret); |
| 2333 | |
| 2334 | return ret; |
| 2335 | } |
| 2336 | |
| 2337 | static int __devexit smc_drv_remove(struct platform_device *pdev) |
| 2338 | { |
| 2339 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 2340 | struct smc_local *lp = netdev_priv(ndev); |
| 2341 | struct resource *res; |
| 2342 | |
| 2343 | platform_set_drvdata(pdev, NULL); |
| 2344 | |
| 2345 | unregister_netdev(ndev); |
| 2346 | |
| 2347 | free_irq(ndev->irq, ndev); |
| 2348 | |
| 2349 | #ifdef CONFIG_ARCH_PXA |
| 2350 | if (ndev->dma != (unsigned char)-1) |
| 2351 | pxa_free_dma(ndev->dma); |
| 2352 | #endif |
| 2353 | iounmap(lp->base); |
| 2354 | |
| 2355 | smc_release_datacs(pdev,ndev); |
| 2356 | smc_release_attrib(pdev,ndev); |
| 2357 | |
| 2358 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); |
| 2359 | if (!res) |
| 2360 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2361 | release_mem_region(res->start, SMC_IO_EXTENT); |
| 2362 | |
| 2363 | free_netdev(ndev); |
| 2364 | |
| 2365 | return 0; |
| 2366 | } |
| 2367 | |
| 2368 | static int smc_drv_suspend(struct platform_device *dev, pm_message_t state) |
| 2369 | { |
| 2370 | struct net_device *ndev = platform_get_drvdata(dev); |
| 2371 | |
| 2372 | if (ndev) { |
| 2373 | if (netif_running(ndev)) { |
| 2374 | netif_device_detach(ndev); |
| 2375 | smc_shutdown(ndev); |
| 2376 | smc_phy_powerdown(ndev); |
| 2377 | } |
| 2378 | } |
| 2379 | return 0; |
| 2380 | } |
| 2381 | |
| 2382 | static int smc_drv_resume(struct platform_device *dev) |
| 2383 | { |
| 2384 | struct net_device *ndev = platform_get_drvdata(dev); |
| 2385 | |
| 2386 | if (ndev) { |
| 2387 | struct smc_local *lp = netdev_priv(ndev); |
| 2388 | smc_enable_device(dev); |
| 2389 | if (netif_running(ndev)) { |
| 2390 | smc_reset(ndev); |
| 2391 | smc_enable(ndev); |
| 2392 | if (lp->phy_type != 0) |
| 2393 | smc_phy_configure(&lp->phy_configure); |
| 2394 | netif_device_attach(ndev); |
| 2395 | } |
| 2396 | } |
| 2397 | return 0; |
| 2398 | } |
| 2399 | |
| 2400 | static struct platform_driver smc_driver = { |
| 2401 | .probe = smc_drv_probe, |
| 2402 | .remove = __devexit_p(smc_drv_remove), |
| 2403 | .suspend = smc_drv_suspend, |
| 2404 | .resume = smc_drv_resume, |
| 2405 | .driver = { |
| 2406 | .name = CARDNAME, |
| 2407 | .owner = THIS_MODULE, |
| 2408 | }, |
| 2409 | }; |
| 2410 | |
| 2411 | static int __init smc_init(void) |
| 2412 | { |
| 2413 | return platform_driver_register(&smc_driver); |
| 2414 | } |
| 2415 | |
| 2416 | static void __exit smc_cleanup(void) |
| 2417 | { |
| 2418 | platform_driver_unregister(&smc_driver); |
| 2419 | } |
| 2420 | |
| 2421 | module_init(smc_init); |
| 2422 | module_exit(smc_cleanup); |