| 1 | /* |
| 2 | * Definitions for the new Marvell Yukon 2 driver. |
| 3 | */ |
| 4 | #ifndef _SKY2_H |
| 5 | #define _SKY2_H |
| 6 | |
| 7 | #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */ |
| 8 | |
| 9 | /* PCI config registers */ |
| 10 | enum { |
| 11 | PCI_DEV_REG1 = 0x40, |
| 12 | PCI_DEV_REG2 = 0x44, |
| 13 | PCI_DEV_STATUS = 0x7c, |
| 14 | PCI_DEV_REG3 = 0x80, |
| 15 | PCI_DEV_REG4 = 0x84, |
| 16 | PCI_DEV_REG5 = 0x88, |
| 17 | PCI_CFG_REG_0 = 0x90, |
| 18 | PCI_CFG_REG_1 = 0x94, |
| 19 | }; |
| 20 | |
| 21 | /* Yukon-2 */ |
| 22 | enum pci_dev_reg_1 { |
| 23 | PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ |
| 24 | PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ |
| 25 | PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */ |
| 26 | PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ |
| 27 | PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ |
| 28 | PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ |
| 29 | PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ |
| 30 | PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */ |
| 31 | |
| 32 | PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */ |
| 33 | PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */ |
| 34 | PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */ |
| 35 | PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */ |
| 36 | }; |
| 37 | |
| 38 | enum pci_dev_reg_2 { |
| 39 | PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */ |
| 40 | PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */ |
| 41 | PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */ |
| 42 | |
| 43 | PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */ |
| 44 | PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */ |
| 45 | PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */ |
| 46 | PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */ |
| 47 | |
| 48 | PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */ |
| 49 | }; |
| 50 | |
| 51 | /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ |
| 52 | enum pci_dev_reg_4 { |
| 53 | /* (Link Training & Status State Machine) */ |
| 54 | P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */ |
| 55 | #define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK) |
| 56 | P_PEX_LTSSM_L1_STAT = 0x34, |
| 57 | P_PEX_LTSSM_DET_STAT = 0x01, |
| 58 | P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */ |
| 59 | /* (Active State Power Management) */ |
| 60 | P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */ |
| 61 | P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */ |
| 62 | P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */ |
| 63 | P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */ |
| 64 | |
| 65 | P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */ |
| 66 | P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */ |
| 67 | P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */ |
| 68 | P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */ |
| 69 | P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */ |
| 70 | P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN |
| 71 | | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY, |
| 72 | }; |
| 73 | |
| 74 | /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ |
| 75 | enum pci_dev_reg_5 { |
| 76 | /* Bit 31..27: for A3 & later */ |
| 77 | P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */ |
| 78 | P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */ |
| 79 | P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */ |
| 80 | P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */ |
| 81 | /* Bit 26..16: Release Clock on Event */ |
| 82 | P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */ |
| 83 | P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */ |
| 84 | P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */ |
| 85 | P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */ |
| 86 | P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */ |
| 87 | P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */ |
| 88 | P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */ |
| 89 | P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */ |
| 90 | P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */ |
| 91 | P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */ |
| 92 | P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */ |
| 93 | |
| 94 | /* Bit 10.. 0: Mask for Gate Clock */ |
| 95 | P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */ |
| 96 | P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */ |
| 97 | P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */ |
| 98 | P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */ |
| 99 | P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */ |
| 100 | P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */ |
| 101 | P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */ |
| 102 | P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */ |
| 103 | P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */ |
| 104 | P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */ |
| 105 | P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */ |
| 106 | |
| 107 | PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET | |
| 108 | P_REL_INT_FIFO_N_EMPTY | |
| 109 | P_REL_PCIE_EXIT_L1_ST | |
| 110 | P_REL_PCIE_RX_EX_IDLE | |
| 111 | P_GAT_GPHY_N_REC_PACKET | |
| 112 | P_GAT_INT_FIFO_EMPTY | |
| 113 | P_GAT_PCIE_ENTER_L1_ST | |
| 114 | P_GAT_PCIE_RX_EL_IDLE, |
| 115 | }; |
| 116 | |
| 117 | #/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */ |
| 118 | enum pci_cfg_reg1 { |
| 119 | P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */ |
| 120 | /* Bit 23..21: Release Clock on Event */ |
| 121 | P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */ |
| 122 | P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */ |
| 123 | P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */ |
| 124 | /* Bit 20..18: Gate Clock on Event */ |
| 125 | P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */ |
| 126 | P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */ |
| 127 | P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */ |
| 128 | P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ |
| 129 | P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */ |
| 130 | |
| 131 | P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */ |
| 132 | |
| 133 | P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */ |
| 134 | P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */ |
| 135 | |
| 136 | PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST | |
| 137 | P_CF1_REL_LDR_NOT_FIN | |
| 138 | P_CF1_REL_VMAIN_AVLBL | |
| 139 | P_CF1_REL_PCIE_RESET | |
| 140 | P_CF1_GAT_LDR_NOT_FIN | |
| 141 | P_CF1_GAT_PCIE_RESET | |
| 142 | P_CF1_PRST_PHY_CLKREQ | |
| 143 | P_CF1_ENA_CFG_LDR_DONE | |
| 144 | P_CF1_ENA_TXBMU_RD_IDLE | |
| 145 | P_CF1_ENA_TXBMU_WR_IDLE, |
| 146 | }; |
| 147 | |
| 148 | |
| 149 | #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ |
| 150 | PCI_STATUS_SIG_SYSTEM_ERROR | \ |
| 151 | PCI_STATUS_REC_MASTER_ABORT | \ |
| 152 | PCI_STATUS_REC_TARGET_ABORT | \ |
| 153 | PCI_STATUS_PARITY) |
| 154 | |
| 155 | enum csr_regs { |
| 156 | B0_RAP = 0x0000, |
| 157 | B0_CTST = 0x0004, |
| 158 | |
| 159 | B0_POWER_CTRL = 0x0007, |
| 160 | B0_ISRC = 0x0008, |
| 161 | B0_IMSK = 0x000c, |
| 162 | B0_HWE_ISRC = 0x0010, |
| 163 | B0_HWE_IMSK = 0x0014, |
| 164 | |
| 165 | /* Special ISR registers (Yukon-2 only) */ |
| 166 | B0_Y2_SP_ISRC2 = 0x001c, |
| 167 | B0_Y2_SP_ISRC3 = 0x0020, |
| 168 | B0_Y2_SP_EISR = 0x0024, |
| 169 | B0_Y2_SP_LISR = 0x0028, |
| 170 | B0_Y2_SP_ICR = 0x002c, |
| 171 | |
| 172 | B2_MAC_1 = 0x0100, |
| 173 | B2_MAC_2 = 0x0108, |
| 174 | B2_MAC_3 = 0x0110, |
| 175 | B2_CONN_TYP = 0x0118, |
| 176 | B2_PMD_TYP = 0x0119, |
| 177 | B2_MAC_CFG = 0x011a, |
| 178 | B2_CHIP_ID = 0x011b, |
| 179 | B2_E_0 = 0x011c, |
| 180 | |
| 181 | B2_Y2_CLK_GATE = 0x011d, |
| 182 | B2_Y2_HW_RES = 0x011e, |
| 183 | B2_E_3 = 0x011f, |
| 184 | B2_Y2_CLK_CTRL = 0x0120, |
| 185 | |
| 186 | B2_TI_INI = 0x0130, |
| 187 | B2_TI_VAL = 0x0134, |
| 188 | B2_TI_CTRL = 0x0138, |
| 189 | B2_TI_TEST = 0x0139, |
| 190 | |
| 191 | B2_TST_CTRL1 = 0x0158, |
| 192 | B2_TST_CTRL2 = 0x0159, |
| 193 | B2_GP_IO = 0x015c, |
| 194 | |
| 195 | B2_I2C_CTRL = 0x0160, |
| 196 | B2_I2C_DATA = 0x0164, |
| 197 | B2_I2C_IRQ = 0x0168, |
| 198 | B2_I2C_SW = 0x016c, |
| 199 | |
| 200 | B3_RAM_ADDR = 0x0180, |
| 201 | B3_RAM_DATA_LO = 0x0184, |
| 202 | B3_RAM_DATA_HI = 0x0188, |
| 203 | |
| 204 | /* RAM Interface Registers */ |
| 205 | /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */ |
| 206 | /* |
| 207 | * The HW-Spec. calls this registers Timeout Value 0..11. But this names are |
| 208 | * not usable in SW. Please notice these are NOT real timeouts, these are |
| 209 | * the number of qWords transferred continuously. |
| 210 | */ |
| 211 | #define RAM_BUFFER(port, reg) (reg | (port <<6)) |
| 212 | |
| 213 | B3_RI_WTO_R1 = 0x0190, |
| 214 | B3_RI_WTO_XA1 = 0x0191, |
| 215 | B3_RI_WTO_XS1 = 0x0192, |
| 216 | B3_RI_RTO_R1 = 0x0193, |
| 217 | B3_RI_RTO_XA1 = 0x0194, |
| 218 | B3_RI_RTO_XS1 = 0x0195, |
| 219 | B3_RI_WTO_R2 = 0x0196, |
| 220 | B3_RI_WTO_XA2 = 0x0197, |
| 221 | B3_RI_WTO_XS2 = 0x0198, |
| 222 | B3_RI_RTO_R2 = 0x0199, |
| 223 | B3_RI_RTO_XA2 = 0x019a, |
| 224 | B3_RI_RTO_XS2 = 0x019b, |
| 225 | B3_RI_TO_VAL = 0x019c, |
| 226 | B3_RI_CTRL = 0x01a0, |
| 227 | B3_RI_TEST = 0x01a2, |
| 228 | B3_MA_TOINI_RX1 = 0x01b0, |
| 229 | B3_MA_TOINI_RX2 = 0x01b1, |
| 230 | B3_MA_TOINI_TX1 = 0x01b2, |
| 231 | B3_MA_TOINI_TX2 = 0x01b3, |
| 232 | B3_MA_TOVAL_RX1 = 0x01b4, |
| 233 | B3_MA_TOVAL_RX2 = 0x01b5, |
| 234 | B3_MA_TOVAL_TX1 = 0x01b6, |
| 235 | B3_MA_TOVAL_TX2 = 0x01b7, |
| 236 | B3_MA_TO_CTRL = 0x01b8, |
| 237 | B3_MA_TO_TEST = 0x01ba, |
| 238 | B3_MA_RCINI_RX1 = 0x01c0, |
| 239 | B3_MA_RCINI_RX2 = 0x01c1, |
| 240 | B3_MA_RCINI_TX1 = 0x01c2, |
| 241 | B3_MA_RCINI_TX2 = 0x01c3, |
| 242 | B3_MA_RCVAL_RX1 = 0x01c4, |
| 243 | B3_MA_RCVAL_RX2 = 0x01c5, |
| 244 | B3_MA_RCVAL_TX1 = 0x01c6, |
| 245 | B3_MA_RCVAL_TX2 = 0x01c7, |
| 246 | B3_MA_RC_CTRL = 0x01c8, |
| 247 | B3_MA_RC_TEST = 0x01ca, |
| 248 | B3_PA_TOINI_RX1 = 0x01d0, |
| 249 | B3_PA_TOINI_RX2 = 0x01d4, |
| 250 | B3_PA_TOINI_TX1 = 0x01d8, |
| 251 | B3_PA_TOINI_TX2 = 0x01dc, |
| 252 | B3_PA_TOVAL_RX1 = 0x01e0, |
| 253 | B3_PA_TOVAL_RX2 = 0x01e4, |
| 254 | B3_PA_TOVAL_TX1 = 0x01e8, |
| 255 | B3_PA_TOVAL_TX2 = 0x01ec, |
| 256 | B3_PA_CTRL = 0x01f0, |
| 257 | B3_PA_TEST = 0x01f2, |
| 258 | |
| 259 | Y2_CFG_SPC = 0x1c00, /* PCI config space region */ |
| 260 | Y2_CFG_AER = 0x1d00, /* PCI Advanced Error Report region */ |
| 261 | }; |
| 262 | |
| 263 | /* B0_CTST 24 bit Control/Status register */ |
| 264 | enum { |
| 265 | Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */ |
| 266 | Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */ |
| 267 | Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */ |
| 268 | Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */ |
| 269 | Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */ |
| 270 | Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */ |
| 271 | Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */ |
| 272 | Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */ |
| 273 | Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */ |
| 274 | Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */ |
| 275 | |
| 276 | CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */ |
| 277 | CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */ |
| 278 | CS_STOP_DONE = 1<<5, /* Stop Master is finished */ |
| 279 | CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ |
| 280 | CS_MRST_CLR = 1<<3, /* Clear Master reset */ |
| 281 | CS_MRST_SET = 1<<2, /* Set Master reset */ |
| 282 | CS_RST_CLR = 1<<1, /* Clear Software reset */ |
| 283 | CS_RST_SET = 1, /* Set Software reset */ |
| 284 | }; |
| 285 | |
| 286 | /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ |
| 287 | enum { |
| 288 | PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */ |
| 289 | PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */ |
| 290 | PC_VCC_ENA = 1<<5, /* Switch VCC Enable */ |
| 291 | PC_VCC_DIS = 1<<4, /* Switch VCC Disable */ |
| 292 | PC_VAUX_ON = 1<<3, /* Switch VAUX On */ |
| 293 | PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */ |
| 294 | PC_VCC_ON = 1<<1, /* Switch VCC On */ |
| 295 | PC_VCC_OFF = 1<<0, /* Switch VCC Off */ |
| 296 | }; |
| 297 | |
| 298 | /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ |
| 299 | |
| 300 | /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ |
| 301 | /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ |
| 302 | /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ |
| 303 | /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ |
| 304 | enum { |
| 305 | Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */ |
| 306 | Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */ |
| 307 | Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */ |
| 308 | |
| 309 | Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */ |
| 310 | Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */ |
| 311 | Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */ |
| 312 | Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */ |
| 313 | |
| 314 | Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */ |
| 315 | Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */ |
| 316 | Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */ |
| 317 | Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */ |
| 318 | Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */ |
| 319 | |
| 320 | Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */ |
| 321 | Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */ |
| 322 | Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */ |
| 323 | Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */ |
| 324 | Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */ |
| 325 | |
| 326 | Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU, |
| 327 | Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
| 328 | | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1, |
| 329 | Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
| 330 | | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, |
| 331 | Y2_IS_ERROR = Y2_IS_HW_ERR | |
| 332 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 | |
| 333 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, |
| 334 | }; |
| 335 | |
| 336 | /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ |
| 337 | enum { |
| 338 | IS_ERR_MSK = 0x00003fff,/* All Error bits */ |
| 339 | |
| 340 | IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */ |
| 341 | IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */ |
| 342 | IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */ |
| 343 | IS_IRQ_STAT = 1<<10, /* IRQ status exception */ |
| 344 | IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */ |
| 345 | IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */ |
| 346 | IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */ |
| 347 | IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */ |
| 348 | IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */ |
| 349 | IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */ |
| 350 | IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */ |
| 351 | IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */ |
| 352 | IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */ |
| 353 | IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */ |
| 354 | }; |
| 355 | |
| 356 | /* Hardware error interrupt mask for Yukon 2 */ |
| 357 | enum { |
| 358 | Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */ |
| 359 | Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */ |
| 360 | Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */ |
| 361 | Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */ |
| 362 | Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */ |
| 363 | Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */ |
| 364 | /* Link 2 */ |
| 365 | Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */ |
| 366 | Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */ |
| 367 | Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */ |
| 368 | Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */ |
| 369 | Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */ |
| 370 | Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */ |
| 371 | /* Link 1 */ |
| 372 | Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */ |
| 373 | Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */ |
| 374 | Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */ |
| 375 | Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */ |
| 376 | Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */ |
| 377 | Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */ |
| 378 | |
| 379 | Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 | |
| 380 | Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1, |
| 381 | Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 | |
| 382 | Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2, |
| 383 | |
| 384 | Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | |
| 385 | Y2_HWE_L1_MASK | Y2_HWE_L2_MASK, |
| 386 | }; |
| 387 | |
| 388 | /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ |
| 389 | enum { |
| 390 | DPT_START = 1<<1, |
| 391 | DPT_STOP = 1<<0, |
| 392 | }; |
| 393 | |
| 394 | /* B2_TST_CTRL1 8 bit Test Control Register 1 */ |
| 395 | enum { |
| 396 | TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */ |
| 397 | TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */ |
| 398 | TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */ |
| 399 | TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */ |
| 400 | TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */ |
| 401 | TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */ |
| 402 | TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ |
| 403 | TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */ |
| 404 | }; |
| 405 | |
| 406 | /* B2_GPIO */ |
| 407 | enum { |
| 408 | GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */ |
| 409 | GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */ |
| 410 | |
| 411 | GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */ |
| 412 | GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */ |
| 413 | GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */ |
| 414 | GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */ |
| 415 | GLB_GPIO_TEST_SEL_BASE = 1<<11, |
| 416 | GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */ |
| 417 | GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */ |
| 418 | }; |
| 419 | |
| 420 | /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ |
| 421 | enum { |
| 422 | CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ |
| 423 | /* Bit 3.. 2: reserved */ |
| 424 | CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */ |
| 425 | CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/ |
| 426 | }; |
| 427 | |
| 428 | /* B2_CHIP_ID 8 bit Chip Identification Number */ |
| 429 | enum { |
| 430 | CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */ |
| 431 | CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */ |
| 432 | CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */ |
| 433 | CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */ |
| 434 | CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */ |
| 435 | CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */ |
| 436 | CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */ |
| 437 | CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */ |
| 438 | }; |
| 439 | enum yukon_ec_rev { |
| 440 | CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ |
| 441 | CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ |
| 442 | CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ |
| 443 | }; |
| 444 | enum yukon_ec_u_rev { |
| 445 | CHIP_REV_YU_EC_U_A0 = 1, |
| 446 | CHIP_REV_YU_EC_U_A1 = 2, |
| 447 | CHIP_REV_YU_EC_U_B0 = 3, |
| 448 | }; |
| 449 | enum yukon_fe_rev { |
| 450 | CHIP_REV_YU_FE_A1 = 1, |
| 451 | CHIP_REV_YU_FE_A2 = 2, |
| 452 | }; |
| 453 | enum yukon_fe_p_rev { |
| 454 | CHIP_REV_YU_FE2_A0 = 0, |
| 455 | }; |
| 456 | enum yukon_ex_rev { |
| 457 | CHIP_REV_YU_EX_A0 = 1, |
| 458 | CHIP_REV_YU_EX_B0 = 2, |
| 459 | }; |
| 460 | enum yukon_supr_rev { |
| 461 | CHIP_REV_YU_SU_A0 = 0, |
| 462 | }; |
| 463 | |
| 464 | |
| 465 | /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ |
| 466 | enum { |
| 467 | Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */ |
| 468 | Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */ |
| 469 | Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */ |
| 470 | Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */ |
| 471 | Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */ |
| 472 | Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */ |
| 473 | Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */ |
| 474 | Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */ |
| 475 | }; |
| 476 | |
| 477 | /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ |
| 478 | enum { |
| 479 | CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */ |
| 480 | CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */ |
| 481 | CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */ |
| 482 | }; |
| 483 | #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) |
| 484 | #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) |
| 485 | |
| 486 | |
| 487 | /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */ |
| 488 | enum { |
| 489 | Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */ |
| 490 | #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK) |
| 491 | Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */ |
| 492 | Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */ |
| 493 | #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK) |
| 494 | #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK) |
| 495 | Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */ |
| 496 | Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */ |
| 497 | }; |
| 498 | |
| 499 | /* B2_TI_CTRL 8 bit Timer control */ |
| 500 | /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ |
| 501 | enum { |
| 502 | TIM_START = 1<<2, /* Start Timer */ |
| 503 | TIM_STOP = 1<<1, /* Stop Timer */ |
| 504 | TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */ |
| 505 | }; |
| 506 | |
| 507 | /* B2_TI_TEST 8 Bit Timer Test */ |
| 508 | /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ |
| 509 | /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ |
| 510 | enum { |
| 511 | TIM_T_ON = 1<<2, /* Test mode on */ |
| 512 | TIM_T_OFF = 1<<1, /* Test mode off */ |
| 513 | TIM_T_STEP = 1<<0, /* Test step */ |
| 514 | }; |
| 515 | |
| 516 | /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ |
| 517 | /* Bit 31..19: reserved */ |
| 518 | #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ |
| 519 | /* RAM Interface Registers */ |
| 520 | |
| 521 | /* B3_RI_CTRL 16 bit RAM Interface Control Register */ |
| 522 | enum { |
| 523 | RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ |
| 524 | RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ |
| 525 | |
| 526 | RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ |
| 527 | RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ |
| 528 | }; |
| 529 | |
| 530 | #define SK_RI_TO_53 36 /* RAM interface timeout */ |
| 531 | |
| 532 | |
| 533 | /* Port related registers FIFO, and Arbiter */ |
| 534 | #define SK_REG(port,reg) (((port)<<7)+(reg)) |
| 535 | |
| 536 | /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ |
| 537 | /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ |
| 538 | /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ |
| 539 | /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ |
| 540 | /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ |
| 541 | |
| 542 | #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ |
| 543 | |
| 544 | /* TXA_CTRL 8 bit Tx Arbiter Control Register */ |
| 545 | enum { |
| 546 | TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */ |
| 547 | TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */ |
| 548 | TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */ |
| 549 | TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */ |
| 550 | TXA_START_RC = 1<<3, /* Start sync Rate Control */ |
| 551 | TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */ |
| 552 | TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */ |
| 553 | TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */ |
| 554 | }; |
| 555 | |
| 556 | /* |
| 557 | * Bank 4 - 5 |
| 558 | */ |
| 559 | /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ |
| 560 | enum { |
| 561 | TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ |
| 562 | TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ |
| 563 | TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */ |
| 564 | TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */ |
| 565 | TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ |
| 566 | TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ |
| 567 | TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ |
| 568 | }; |
| 569 | |
| 570 | |
| 571 | enum { |
| 572 | B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ |
| 573 | B7_CFG_SPC = 0x0380,/* copy of the Configuration register */ |
| 574 | B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */ |
| 575 | B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */ |
| 576 | B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */ |
| 577 | B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */ |
| 578 | B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */ |
| 579 | B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */ |
| 580 | B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */ |
| 581 | }; |
| 582 | |
| 583 | /* Queue Register Offsets, use Q_ADDR() to access */ |
| 584 | enum { |
| 585 | B8_Q_REGS = 0x0400, /* base of Queue registers */ |
| 586 | Q_D = 0x00, /* 8*32 bit Current Descriptor */ |
| 587 | Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */ |
| 588 | Q_DONE = 0x24, /* 16 bit Done Index */ |
| 589 | Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ |
| 590 | Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ |
| 591 | Q_BC = 0x30, /* 32 bit Current Byte Counter */ |
| 592 | Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ |
| 593 | Q_TEST = 0x38, /* 32 bit Test/Control Register */ |
| 594 | |
| 595 | /* Yukon-2 */ |
| 596 | Q_WM = 0x40, /* 16 bit FIFO Watermark */ |
| 597 | Q_AL = 0x42, /* 8 bit FIFO Alignment */ |
| 598 | Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ |
| 599 | Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */ |
| 600 | Q_RP = 0x48, /* 8 bit FIFO Read Pointer */ |
| 601 | Q_RL = 0x4a, /* 8 bit FIFO Read Level */ |
| 602 | Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */ |
| 603 | Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */ |
| 604 | Q_WL = 0x4e, /* 8 bit FIFO Write Level */ |
| 605 | Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */ |
| 606 | }; |
| 607 | #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) |
| 608 | |
| 609 | /* Q_TEST 32 bit Test Register */ |
| 610 | enum { |
| 611 | /* Transmit */ |
| 612 | F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */ |
| 613 | F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */ |
| 614 | |
| 615 | /* Receive */ |
| 616 | F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ |
| 617 | |
| 618 | /* Hardware testbits not used */ |
| 619 | }; |
| 620 | |
| 621 | /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ |
| 622 | enum { |
| 623 | Y2_B8_PREF_REGS = 0x0450, |
| 624 | |
| 625 | PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */ |
| 626 | PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */ |
| 627 | PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */ |
| 628 | PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/ |
| 629 | PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */ |
| 630 | PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */ |
| 631 | PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */ |
| 632 | PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */ |
| 633 | PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */ |
| 634 | PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */ |
| 635 | |
| 636 | PREF_UNIT_MASK_IDX = 0x0fff, |
| 637 | }; |
| 638 | #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg)) |
| 639 | |
| 640 | /* RAM Buffer Register Offsets */ |
| 641 | enum { |
| 642 | |
| 643 | RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ |
| 644 | RB_END = 0x04,/* 32 bit RAM Buffer End Address */ |
| 645 | RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ |
| 646 | RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ |
| 647 | RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ |
| 648 | RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ |
| 649 | RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ |
| 650 | RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ |
| 651 | /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ |
| 652 | RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ |
| 653 | RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ |
| 654 | RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ |
| 655 | RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */ |
| 656 | RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */ |
| 657 | }; |
| 658 | |
| 659 | /* Receive and Transmit Queues */ |
| 660 | enum { |
| 661 | Q_R1 = 0x0000, /* Receive Queue 1 */ |
| 662 | Q_R2 = 0x0080, /* Receive Queue 2 */ |
| 663 | Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */ |
| 664 | Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */ |
| 665 | Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */ |
| 666 | Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */ |
| 667 | }; |
| 668 | |
| 669 | /* Different PHY Types */ |
| 670 | enum { |
| 671 | PHY_ADDR_MARV = 0, |
| 672 | }; |
| 673 | |
| 674 | #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs)) |
| 675 | |
| 676 | |
| 677 | enum { |
| 678 | LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */ |
| 679 | LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */ |
| 680 | LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */ |
| 681 | LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */ |
| 682 | |
| 683 | LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */ |
| 684 | |
| 685 | /* Receive GMAC FIFO (YUKON and Yukon-2) */ |
| 686 | |
| 687 | RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ |
| 688 | RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ |
| 689 | RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ |
| 690 | RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ |
| 691 | RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ |
| 692 | RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ |
| 693 | RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ |
| 694 | RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ |
| 695 | RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ |
| 696 | RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ |
| 697 | |
| 698 | RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ |
| 699 | |
| 700 | RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ |
| 701 | |
| 702 | RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ |
| 703 | }; |
| 704 | |
| 705 | |
| 706 | /* Q_BC 32 bit Current Byte Counter */ |
| 707 | |
| 708 | /* BMU Control Status Registers */ |
| 709 | /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ |
| 710 | /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ |
| 711 | /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ |
| 712 | /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ |
| 713 | /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ |
| 714 | /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ |
| 715 | /* Q_CSR 32 bit BMU Control/Status Register */ |
| 716 | |
| 717 | /* Rx BMU Control / Status Registers (Yukon-2) */ |
| 718 | enum { |
| 719 | BMU_IDLE = 1<<31, /* BMU Idle State */ |
| 720 | BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */ |
| 721 | BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */ |
| 722 | |
| 723 | BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */ |
| 724 | BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */ |
| 725 | BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */ |
| 726 | BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */ |
| 727 | BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */ |
| 728 | BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */ |
| 729 | BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */ |
| 730 | BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */ |
| 731 | BMU_START = 1<<8, /* Start Rx/Tx Queue */ |
| 732 | BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */ |
| 733 | BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */ |
| 734 | BMU_FIFO_ENA = 1<<5, /* Enable FIFO */ |
| 735 | BMU_FIFO_RST = 1<<4, /* Reset FIFO */ |
| 736 | BMU_OP_ON = 1<<3, /* BMU Operational On */ |
| 737 | BMU_OP_OFF = 1<<2, /* BMU Operational Off */ |
| 738 | BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */ |
| 739 | BMU_RST_SET = 1<<0, /* Set BMU Reset */ |
| 740 | |
| 741 | BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, |
| 742 | BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | |
| 743 | BMU_FIFO_ENA | BMU_OP_ON, |
| 744 | |
| 745 | BMU_WM_DEFAULT = 0x600, |
| 746 | BMU_WM_PEX = 0x80, |
| 747 | }; |
| 748 | |
| 749 | /* Tx BMU Control / Status Registers (Yukon-2) */ |
| 750 | /* Bit 31: same as for Rx */ |
| 751 | enum { |
| 752 | BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */ |
| 753 | BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */ |
| 754 | BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */ |
| 755 | }; |
| 756 | |
| 757 | /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ |
| 758 | /* PREF_UNIT_CTRL 32 bit Prefetch Control register */ |
| 759 | enum { |
| 760 | PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */ |
| 761 | PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */ |
| 762 | PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */ |
| 763 | PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */ |
| 764 | }; |
| 765 | |
| 766 | /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ |
| 767 | /* RB_START 32 bit RAM Buffer Start Address */ |
| 768 | /* RB_END 32 bit RAM Buffer End Address */ |
| 769 | /* RB_WP 32 bit RAM Buffer Write Pointer */ |
| 770 | /* RB_RP 32 bit RAM Buffer Read Pointer */ |
| 771 | /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ |
| 772 | /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ |
| 773 | /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ |
| 774 | /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ |
| 775 | /* RB_PC 32 bit RAM Buffer Packet Counter */ |
| 776 | /* RB_LEV 32 bit RAM Buffer Level Register */ |
| 777 | |
| 778 | #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ |
| 779 | /* RB_TST2 8 bit RAM Buffer Test Register 2 */ |
| 780 | /* RB_TST1 8 bit RAM Buffer Test Register 1 */ |
| 781 | |
| 782 | /* RB_CTRL 8 bit RAM Buffer Control Register */ |
| 783 | enum { |
| 784 | RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */ |
| 785 | RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */ |
| 786 | RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ |
| 787 | RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ |
| 788 | RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ |
| 789 | RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ |
| 790 | }; |
| 791 | |
| 792 | |
| 793 | /* Transmit GMAC FIFO (YUKON only) */ |
| 794 | enum { |
| 795 | TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */ |
| 796 | TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ |
| 797 | TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */ |
| 798 | |
| 799 | TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */ |
| 800 | TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ |
| 801 | TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */ |
| 802 | |
| 803 | TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ |
| 804 | TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ |
| 805 | TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ |
| 806 | |
| 807 | /* Threshold values for Yukon-EC Ultra and Extreme */ |
| 808 | ECU_AE_THR = 0x0070, /* Almost Empty Threshold */ |
| 809 | ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */ |
| 810 | ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */ |
| 811 | }; |
| 812 | |
| 813 | /* Descriptor Poll Timer Registers */ |
| 814 | enum { |
| 815 | B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */ |
| 816 | B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */ |
| 817 | B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */ |
| 818 | |
| 819 | B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */ |
| 820 | }; |
| 821 | |
| 822 | /* Time Stamp Timer Registers (YUKON only) */ |
| 823 | enum { |
| 824 | GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */ |
| 825 | GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */ |
| 826 | GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ |
| 827 | }; |
| 828 | |
| 829 | /* Polling Unit Registers (Yukon-2 only) */ |
| 830 | enum { |
| 831 | POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */ |
| 832 | POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */ |
| 833 | |
| 834 | POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */ |
| 835 | POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */ |
| 836 | }; |
| 837 | |
| 838 | enum { |
| 839 | SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */ |
| 840 | SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */ |
| 841 | }; |
| 842 | |
| 843 | enum { |
| 844 | CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */ |
| 845 | CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */ |
| 846 | CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */ |
| 847 | CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */ |
| 848 | CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */ |
| 849 | CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */ |
| 850 | HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */ |
| 851 | CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */ |
| 852 | HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */ |
| 853 | HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */ |
| 854 | }; |
| 855 | |
| 856 | /* ASF Subsystem Registers (Yukon-2 only) */ |
| 857 | enum { |
| 858 | B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */ |
| 859 | B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */ |
| 860 | B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */ |
| 861 | |
| 862 | B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */ |
| 863 | B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */ |
| 864 | B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */ |
| 865 | B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */ |
| 866 | B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */ |
| 867 | B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */ |
| 868 | }; |
| 869 | |
| 870 | /* Status BMU Registers (Yukon-2 only)*/ |
| 871 | enum { |
| 872 | STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */ |
| 873 | STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */ |
| 874 | |
| 875 | STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */ |
| 876 | STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */ |
| 877 | STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */ |
| 878 | STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */ |
| 879 | STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */ |
| 880 | STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */ |
| 881 | STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */ |
| 882 | STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */ |
| 883 | |
| 884 | /* FIFO Control/Status Registers (Yukon-2 only)*/ |
| 885 | STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */ |
| 886 | STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */ |
| 887 | STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */ |
| 888 | STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */ |
| 889 | STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */ |
| 890 | STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */ |
| 891 | STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */ |
| 892 | |
| 893 | /* Level and ISR Timer Registers (Yukon-2 only)*/ |
| 894 | STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */ |
| 895 | STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */ |
| 896 | STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */ |
| 897 | STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */ |
| 898 | STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */ |
| 899 | STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */ |
| 900 | STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */ |
| 901 | STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */ |
| 902 | STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */ |
| 903 | STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */ |
| 904 | STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */ |
| 905 | STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */ |
| 906 | }; |
| 907 | |
| 908 | enum { |
| 909 | LINKLED_OFF = 0x01, |
| 910 | LINKLED_ON = 0x02, |
| 911 | LINKLED_LINKSYNC_OFF = 0x04, |
| 912 | LINKLED_LINKSYNC_ON = 0x08, |
| 913 | LINKLED_BLINK_OFF = 0x10, |
| 914 | LINKLED_BLINK_ON = 0x20, |
| 915 | }; |
| 916 | |
| 917 | /* GMAC and GPHY Control Registers (YUKON only) */ |
| 918 | enum { |
| 919 | GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ |
| 920 | GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */ |
| 921 | GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */ |
| 922 | GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */ |
| 923 | GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */ |
| 924 | |
| 925 | /* Wake-up Frame Pattern Match Control Registers (YUKON only) */ |
| 926 | WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */ |
| 927 | WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ |
| 928 | WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ |
| 929 | WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ |
| 930 | WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ |
| 931 | |
| 932 | /* WOL Pattern Length Registers (YUKON only) */ |
| 933 | WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */ |
| 934 | WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */ |
| 935 | |
| 936 | /* WOL Pattern Counter Registers (YUKON only) */ |
| 937 | WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */ |
| 938 | WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */ |
| 939 | }; |
| 940 | #define WOL_REGS(port, x) (x + (port)*0x80) |
| 941 | |
| 942 | enum { |
| 943 | WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */ |
| 944 | WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */ |
| 945 | }; |
| 946 | #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400) |
| 947 | |
| 948 | enum { |
| 949 | BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */ |
| 950 | BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */ |
| 951 | }; |
| 952 | |
| 953 | /* |
| 954 | * Marvel-PHY Registers, indirect addressed over GMAC |
| 955 | */ |
| 956 | enum { |
| 957 | PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ |
| 958 | PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */ |
| 959 | PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ |
| 960 | PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ |
| 961 | PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ |
| 962 | PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ |
| 963 | PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ |
| 964 | PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */ |
| 965 | PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ |
| 966 | /* Marvel-specific registers */ |
| 967 | PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ |
| 968 | PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ |
| 969 | PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ |
| 970 | PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */ |
| 971 | PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */ |
| 972 | PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */ |
| 973 | PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */ |
| 974 | PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */ |
| 975 | PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */ |
| 976 | PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */ |
| 977 | PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */ |
| 978 | PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */ |
| 979 | PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */ |
| 980 | PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */ |
| 981 | PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */ |
| 982 | PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */ |
| 983 | PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */ |
| 984 | PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */ |
| 985 | |
| 986 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 987 | PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */ |
| 988 | PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */ |
| 989 | PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */ |
| 990 | PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */ |
| 991 | PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ |
| 992 | }; |
| 993 | |
| 994 | enum { |
| 995 | PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ |
| 996 | PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ |
| 997 | PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */ |
| 998 | PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */ |
| 999 | PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */ |
| 1000 | PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */ |
| 1001 | PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */ |
| 1002 | PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */ |
| 1003 | PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */ |
| 1004 | PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */ |
| 1005 | }; |
| 1006 | |
| 1007 | enum { |
| 1008 | PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */ |
| 1009 | PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */ |
| 1010 | PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */ |
| 1011 | }; |
| 1012 | |
| 1013 | enum { |
| 1014 | PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */ |
| 1015 | |
| 1016 | PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */ |
| 1017 | PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */ |
| 1018 | PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */ |
| 1019 | PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */ |
| 1020 | PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */ |
| 1021 | PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */ |
| 1022 | PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */ |
| 1023 | }; |
| 1024 | |
| 1025 | enum { |
| 1026 | PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */ |
| 1027 | PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */ |
| 1028 | PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */ |
| 1029 | }; |
| 1030 | |
| 1031 | /* different Marvell PHY Ids */ |
| 1032 | enum { |
| 1033 | PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */ |
| 1034 | |
| 1035 | PHY_BCOM_ID1_A1 = 0x6041, |
| 1036 | PHY_BCOM_ID1_B2 = 0x6043, |
| 1037 | PHY_BCOM_ID1_C0 = 0x6044, |
| 1038 | PHY_BCOM_ID1_C5 = 0x6047, |
| 1039 | |
| 1040 | PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ |
| 1041 | PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ |
| 1042 | PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ |
| 1043 | PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ |
| 1044 | PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */ |
| 1045 | PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */ |
| 1046 | }; |
| 1047 | |
| 1048 | /* Advertisement register bits */ |
| 1049 | enum { |
| 1050 | PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ |
| 1051 | PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ |
| 1052 | PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */ |
| 1053 | |
| 1054 | PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */ |
| 1055 | PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */ |
| 1056 | PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */ |
| 1057 | PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */ |
| 1058 | PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */ |
| 1059 | PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */ |
| 1060 | PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */ |
| 1061 | PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */ |
| 1062 | PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/ |
| 1063 | PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, |
| 1064 | PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL | |
| 1065 | PHY_AN_100HALF | PHY_AN_100FULL, |
| 1066 | }; |
| 1067 | |
| 1068 | /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ |
| 1069 | /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ |
| 1070 | enum { |
| 1071 | PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */ |
| 1072 | PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */ |
| 1073 | PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */ |
| 1074 | PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */ |
| 1075 | PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */ |
| 1076 | PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */ |
| 1077 | /* Bit 9..8: reserved */ |
| 1078 | PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */ |
| 1079 | }; |
| 1080 | |
| 1081 | /** Marvell-Specific */ |
| 1082 | enum { |
| 1083 | PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */ |
| 1084 | PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */ |
| 1085 | PHY_M_AN_RF = 1<<13, /* Remote Fault */ |
| 1086 | |
| 1087 | PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */ |
| 1088 | PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */ |
| 1089 | PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */ |
| 1090 | PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */ |
| 1091 | PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */ |
| 1092 | PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */ |
| 1093 | PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */ |
| 1094 | PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */ |
| 1095 | }; |
| 1096 | |
| 1097 | /* special defines for FIBER (88E1011S only) */ |
| 1098 | enum { |
| 1099 | PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */ |
| 1100 | PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */ |
| 1101 | PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */ |
| 1102 | PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */ |
| 1103 | }; |
| 1104 | |
| 1105 | /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ |
| 1106 | enum { |
| 1107 | PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */ |
| 1108 | PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */ |
| 1109 | PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */ |
| 1110 | PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */ |
| 1111 | }; |
| 1112 | |
| 1113 | /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ |
| 1114 | enum { |
| 1115 | PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ |
| 1116 | PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */ |
| 1117 | PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */ |
| 1118 | PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */ |
| 1119 | PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */ |
| 1120 | PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */ |
| 1121 | }; |
| 1122 | |
| 1123 | /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ |
| 1124 | enum { |
| 1125 | PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */ |
| 1126 | PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */ |
| 1127 | PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */ |
| 1128 | PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */ |
| 1129 | PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */ |
| 1130 | PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */ |
| 1131 | PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */ |
| 1132 | PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */ |
| 1133 | PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */ |
| 1134 | PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */ |
| 1135 | PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */ |
| 1136 | PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */ |
| 1137 | }; |
| 1138 | |
| 1139 | enum { |
| 1140 | PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */ |
| 1141 | PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ |
| 1142 | }; |
| 1143 | |
| 1144 | #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK) |
| 1145 | |
| 1146 | enum { |
| 1147 | PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ |
| 1148 | PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */ |
| 1149 | PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ |
| 1150 | }; |
| 1151 | |
| 1152 | /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */ |
| 1153 | enum { |
| 1154 | PHY_M_PC_COP_TX_DIS = 1<<3, /* Copper Transmitter Disable */ |
| 1155 | PHY_M_PC_POW_D_ENA = 1<<2, /* Power Down Enable */ |
| 1156 | }; |
| 1157 | |
| 1158 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1159 | enum { |
| 1160 | PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ |
| 1161 | PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */ |
| 1162 | PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */ |
| 1163 | PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */ |
| 1164 | PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */ |
| 1165 | |
| 1166 | PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */ |
| 1167 | PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */ |
| 1168 | |
| 1169 | PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */ |
| 1170 | PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */ |
| 1171 | }; |
| 1172 | |
| 1173 | /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ |
| 1174 | enum { |
| 1175 | PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */ |
| 1176 | PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */ |
| 1177 | PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */ |
| 1178 | PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */ |
| 1179 | PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */ |
| 1180 | PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */ |
| 1181 | PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */ |
| 1182 | PHY_M_PS_LINK_UP = 1<<10, /* Link Up */ |
| 1183 | PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */ |
| 1184 | PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */ |
| 1185 | PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */ |
| 1186 | PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */ |
| 1187 | PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */ |
| 1188 | PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */ |
| 1189 | PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */ |
| 1190 | PHY_M_PS_JABBER = 1<<0, /* Jabber */ |
| 1191 | }; |
| 1192 | |
| 1193 | #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) |
| 1194 | |
| 1195 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1196 | enum { |
| 1197 | PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */ |
| 1198 | PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ |
| 1199 | }; |
| 1200 | |
| 1201 | enum { |
| 1202 | PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */ |
| 1203 | PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */ |
| 1204 | PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */ |
| 1205 | PHY_M_IS_AN_PR = 1<<12, /* Page Received */ |
| 1206 | PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */ |
| 1207 | PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */ |
| 1208 | PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */ |
| 1209 | PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */ |
| 1210 | PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */ |
| 1211 | PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */ |
| 1212 | PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */ |
| 1213 | PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */ |
| 1214 | |
| 1215 | PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */ |
| 1216 | PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */ |
| 1217 | PHY_M_IS_JABBER = 1<<0, /* Jabber */ |
| 1218 | |
| 1219 | PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE |
| 1220 | | PHY_M_IS_DUP_CHANGE, |
| 1221 | PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL, |
| 1222 | }; |
| 1223 | |
| 1224 | |
| 1225 | /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ |
| 1226 | enum { |
| 1227 | PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */ |
| 1228 | PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */ |
| 1229 | |
| 1230 | PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */ |
| 1231 | PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */ |
| 1232 | /* (88E1011 only) */ |
| 1233 | PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */ |
| 1234 | /* (88E1011 only) */ |
| 1235 | PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */ |
| 1236 | /* (88E1111 only) */ |
| 1237 | PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */ |
| 1238 | /* !!! Errata in spec. (1 = disable) */ |
| 1239 | PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/ |
| 1240 | PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */ |
| 1241 | PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */ |
| 1242 | PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */ |
| 1243 | PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */ |
| 1244 | PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */}; |
| 1245 | |
| 1246 | #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK) |
| 1247 | /* 00=1x; 01=2x; 10=3x; 11=4x */ |
| 1248 | #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK) |
| 1249 | /* 00=dis; 01=1x; 10=2x; 11=3x */ |
| 1250 | #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2) |
| 1251 | /* 000=1x; 001=2x; 010=3x; 011=4x */ |
| 1252 | #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK) |
| 1253 | /* 01X=0; 110=2.5; 111=25 (MHz) */ |
| 1254 | |
| 1255 | /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ |
| 1256 | enum { |
| 1257 | PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */ |
| 1258 | PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */ |
| 1259 | PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */ |
| 1260 | }; |
| 1261 | /* !!! Errata in spec. (1 = disable) */ |
| 1262 | |
| 1263 | #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK) |
| 1264 | /* 100=5x; 101=6x; 110=7x; 111=8x */ |
| 1265 | enum { |
| 1266 | MAC_TX_CLK_0_MHZ = 2, |
| 1267 | MAC_TX_CLK_2_5_MHZ = 6, |
| 1268 | MAC_TX_CLK_25_MHZ = 7, |
| 1269 | }; |
| 1270 | |
| 1271 | /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ |
| 1272 | enum { |
| 1273 | PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */ |
| 1274 | PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */ |
| 1275 | PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */ |
| 1276 | PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */ |
| 1277 | PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */ |
| 1278 | PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */ |
| 1279 | PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */ |
| 1280 | /* (88E1111 only) */ |
| 1281 | }; |
| 1282 | |
| 1283 | enum { |
| 1284 | PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */ |
| 1285 | /* (88E1011 only) */ |
| 1286 | PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */ |
| 1287 | PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */ |
| 1288 | PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */ |
| 1289 | PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */ |
| 1290 | PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ |
| 1291 | }; |
| 1292 | |
| 1293 | #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK) |
| 1294 | |
| 1295 | /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/ |
| 1296 | enum { |
| 1297 | PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */ |
| 1298 | PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ |
| 1299 | PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ |
| 1300 | PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ |
| 1301 | PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ |
| 1302 | PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ |
| 1303 | }; |
| 1304 | |
| 1305 | #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK) |
| 1306 | #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK) |
| 1307 | #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK) |
| 1308 | #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK) |
| 1309 | #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK) |
| 1310 | #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK) |
| 1311 | |
| 1312 | enum { |
| 1313 | PULS_NO_STR = 0,/* no pulse stretching */ |
| 1314 | PULS_21MS = 1,/* 21 ms to 42 ms */ |
| 1315 | PULS_42MS = 2,/* 42 ms to 84 ms */ |
| 1316 | PULS_84MS = 3,/* 84 ms to 170 ms */ |
| 1317 | PULS_170MS = 4,/* 170 ms to 340 ms */ |
| 1318 | PULS_340MS = 5,/* 340 ms to 670 ms */ |
| 1319 | PULS_670MS = 6,/* 670 ms to 1.3 s */ |
| 1320 | PULS_1300MS = 7,/* 1.3 s to 2.7 s */ |
| 1321 | }; |
| 1322 | |
| 1323 | #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK) |
| 1324 | |
| 1325 | enum { |
| 1326 | BLINK_42MS = 0,/* 42 ms */ |
| 1327 | BLINK_84MS = 1,/* 84 ms */ |
| 1328 | BLINK_170MS = 2,/* 170 ms */ |
| 1329 | BLINK_340MS = 3,/* 340 ms */ |
| 1330 | BLINK_670MS = 4,/* 670 ms */ |
| 1331 | }; |
| 1332 | |
| 1333 | /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ |
| 1334 | #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */ |
| 1335 | |
| 1336 | #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */ |
| 1337 | #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */ |
| 1338 | #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */ |
| 1339 | #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */ |
| 1340 | #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */ |
| 1341 | #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */ |
| 1342 | |
| 1343 | enum led_mode { |
| 1344 | MO_LED_NORM = 0, |
| 1345 | MO_LED_BLINK = 1, |
| 1346 | MO_LED_OFF = 2, |
| 1347 | MO_LED_ON = 3, |
| 1348 | }; |
| 1349 | |
| 1350 | /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ |
| 1351 | enum { |
| 1352 | PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */ |
| 1353 | PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */ |
| 1354 | PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */ |
| 1355 | PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */ |
| 1356 | PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */ |
| 1357 | }; |
| 1358 | |
| 1359 | /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ |
| 1360 | enum { |
| 1361 | PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */ |
| 1362 | PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */ |
| 1363 | PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */ |
| 1364 | PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */ |
| 1365 | PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */ |
| 1366 | PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */ |
| 1367 | PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */ |
| 1368 | /* (88E1111 only) */ |
| 1369 | |
| 1370 | PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */ |
| 1371 | PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */ |
| 1372 | PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ |
| 1373 | }; |
| 1374 | |
| 1375 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1376 | /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ |
| 1377 | /* Bit 15..12: reserved (used internally) */ |
| 1378 | enum { |
| 1379 | PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */ |
| 1380 | PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */ |
| 1381 | PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ |
| 1382 | }; |
| 1383 | |
| 1384 | #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK) |
| 1385 | #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK) |
| 1386 | #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK) |
| 1387 | |
| 1388 | enum { |
| 1389 | LED_PAR_CTRL_COLX = 0x00, |
| 1390 | LED_PAR_CTRL_ERROR = 0x01, |
| 1391 | LED_PAR_CTRL_DUPLEX = 0x02, |
| 1392 | LED_PAR_CTRL_DP_COL = 0x03, |
| 1393 | LED_PAR_CTRL_SPEED = 0x04, |
| 1394 | LED_PAR_CTRL_LINK = 0x05, |
| 1395 | LED_PAR_CTRL_TX = 0x06, |
| 1396 | LED_PAR_CTRL_RX = 0x07, |
| 1397 | LED_PAR_CTRL_ACT = 0x08, |
| 1398 | LED_PAR_CTRL_LNK_RX = 0x09, |
| 1399 | LED_PAR_CTRL_LNK_AC = 0x0a, |
| 1400 | LED_PAR_CTRL_ACT_BL = 0x0b, |
| 1401 | LED_PAR_CTRL_TX_BL = 0x0c, |
| 1402 | LED_PAR_CTRL_RX_BL = 0x0d, |
| 1403 | LED_PAR_CTRL_COL_BL = 0x0e, |
| 1404 | LED_PAR_CTRL_INACT = 0x0f |
| 1405 | }; |
| 1406 | |
| 1407 | /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ |
| 1408 | enum { |
| 1409 | PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */ |
| 1410 | PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */ |
| 1411 | PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */ |
| 1412 | }; |
| 1413 | |
| 1414 | /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ |
| 1415 | /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ |
| 1416 | enum { |
| 1417 | PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */ |
| 1418 | PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */ |
| 1419 | PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */ |
| 1420 | }; |
| 1421 | |
| 1422 | /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ |
| 1423 | /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ |
| 1424 | enum { |
| 1425 | PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ |
| 1426 | PHY_M_MAC_GMIF_PUP = 1<<3, /* GMII Power Up (88E1149 only) */ |
| 1427 | PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ |
| 1428 | PHY_M_MAC_MD_COPPER = 5,/* Copper only */ |
| 1429 | PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ |
| 1430 | }; |
| 1431 | #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK) |
| 1432 | |
| 1433 | /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ |
| 1434 | enum { |
| 1435 | PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */ |
| 1436 | PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */ |
| 1437 | PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */ |
| 1438 | PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ |
| 1439 | }; |
| 1440 | |
| 1441 | #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK) |
| 1442 | #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK) |
| 1443 | #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK) |
| 1444 | #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK) |
| 1445 | |
| 1446 | /* GMAC registers */ |
| 1447 | /* Port Registers */ |
| 1448 | enum { |
| 1449 | GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */ |
| 1450 | GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */ |
| 1451 | GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */ |
| 1452 | GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */ |
| 1453 | GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */ |
| 1454 | GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */ |
| 1455 | GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */ |
| 1456 | /* Source Address Registers */ |
| 1457 | GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */ |
| 1458 | GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */ |
| 1459 | GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */ |
| 1460 | GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */ |
| 1461 | GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */ |
| 1462 | GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */ |
| 1463 | |
| 1464 | /* Multicast Address Hash Registers */ |
| 1465 | GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */ |
| 1466 | GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */ |
| 1467 | GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */ |
| 1468 | GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */ |
| 1469 | |
| 1470 | /* Interrupt Source Registers */ |
| 1471 | GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */ |
| 1472 | GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */ |
| 1473 | GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */ |
| 1474 | |
| 1475 | /* Interrupt Mask Registers */ |
| 1476 | GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */ |
| 1477 | GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */ |
| 1478 | GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */ |
| 1479 | |
| 1480 | /* Serial Management Interface (SMI) Registers */ |
| 1481 | GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */ |
| 1482 | GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */ |
| 1483 | GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ |
| 1484 | /* MIB Counters */ |
| 1485 | GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */ |
| 1486 | GM_MIB_CNT_END = 0x025C, /* Last MIB counter */ |
| 1487 | }; |
| 1488 | |
| 1489 | |
| 1490 | /* |
| 1491 | * MIB Counters base address definitions (low word) - |
| 1492 | * use offset 4 for access to high word (32 bit r/o) |
| 1493 | */ |
| 1494 | enum { |
| 1495 | GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */ |
| 1496 | GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */ |
| 1497 | GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */ |
| 1498 | GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */ |
| 1499 | GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */ |
| 1500 | |
| 1501 | GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */ |
| 1502 | GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */ |
| 1503 | GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */ |
| 1504 | GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */ |
| 1505 | GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */ |
| 1506 | GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */ |
| 1507 | GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */ |
| 1508 | GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */ |
| 1509 | GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */ |
| 1510 | GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */ |
| 1511 | GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */ |
| 1512 | GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */ |
| 1513 | GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */ |
| 1514 | GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */ |
| 1515 | GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */ |
| 1516 | |
| 1517 | GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */ |
| 1518 | GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */ |
| 1519 | GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */ |
| 1520 | GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */ |
| 1521 | GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */ |
| 1522 | GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */ |
| 1523 | GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */ |
| 1524 | GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */ |
| 1525 | GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */ |
| 1526 | GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */ |
| 1527 | GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */ |
| 1528 | GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */ |
| 1529 | GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */ |
| 1530 | GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */ |
| 1531 | |
| 1532 | GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */ |
| 1533 | GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */ |
| 1534 | GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */ |
| 1535 | GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */ |
| 1536 | GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */ |
| 1537 | GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */ |
| 1538 | }; |
| 1539 | |
| 1540 | /* GMAC Bit Definitions */ |
| 1541 | /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ |
| 1542 | enum { |
| 1543 | GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */ |
| 1544 | GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */ |
| 1545 | GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */ |
| 1546 | GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */ |
| 1547 | GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */ |
| 1548 | GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */ |
| 1549 | GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */ |
| 1550 | GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */ |
| 1551 | |
| 1552 | GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */ |
| 1553 | GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ |
| 1554 | GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */ |
| 1555 | GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ |
| 1556 | GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ |
| 1557 | }; |
| 1558 | |
| 1559 | /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ |
| 1560 | enum { |
| 1561 | GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ |
| 1562 | GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */ |
| 1563 | GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */ |
| 1564 | GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */ |
| 1565 | GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */ |
| 1566 | GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */ |
| 1567 | GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */ |
| 1568 | GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */ |
| 1569 | GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */ |
| 1570 | GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */ |
| 1571 | GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */ |
| 1572 | GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */ |
| 1573 | GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */ |
| 1574 | GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */ |
| 1575 | GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */ |
| 1576 | }; |
| 1577 | |
| 1578 | #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) |
| 1579 | |
| 1580 | /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ |
| 1581 | enum { |
| 1582 | GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ |
| 1583 | GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ |
| 1584 | GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ |
| 1585 | GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */ |
| 1586 | }; |
| 1587 | |
| 1588 | #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) |
| 1589 | #define TX_COL_DEF 0x04 |
| 1590 | |
| 1591 | /* GM_RX_CTRL 16 bit r/w Receive Control Register */ |
| 1592 | enum { |
| 1593 | GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ |
| 1594 | GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */ |
| 1595 | GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ |
| 1596 | GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ |
| 1597 | }; |
| 1598 | |
| 1599 | /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ |
| 1600 | enum { |
| 1601 | GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ |
| 1602 | GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */ |
| 1603 | GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */ |
| 1604 | GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */ |
| 1605 | |
| 1606 | TX_JAM_LEN_DEF = 0x03, |
| 1607 | TX_JAM_IPG_DEF = 0x0b, |
| 1608 | TX_IPG_JAM_DEF = 0x1c, |
| 1609 | TX_BOF_LIM_DEF = 0x04, |
| 1610 | }; |
| 1611 | |
| 1612 | #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK) |
| 1613 | #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK) |
| 1614 | #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK) |
| 1615 | #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) |
| 1616 | |
| 1617 | |
| 1618 | /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ |
| 1619 | enum { |
| 1620 | GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */ |
| 1621 | GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */ |
| 1622 | GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */ |
| 1623 | GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ |
| 1624 | GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ |
| 1625 | }; |
| 1626 | |
| 1627 | #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) |
| 1628 | #define DATA_BLIND_DEF 0x04 |
| 1629 | |
| 1630 | #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) |
| 1631 | #define IPG_DATA_DEF 0x1e |
| 1632 | |
| 1633 | /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ |
| 1634 | enum { |
| 1635 | GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */ |
| 1636 | GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */ |
| 1637 | GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/ |
| 1638 | GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ |
| 1639 | GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ |
| 1640 | }; |
| 1641 | |
| 1642 | #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK) |
| 1643 | #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK) |
| 1644 | |
| 1645 | /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ |
| 1646 | enum { |
| 1647 | GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ |
| 1648 | GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ |
| 1649 | }; |
| 1650 | |
| 1651 | /* Receive Frame Status Encoding */ |
| 1652 | enum { |
| 1653 | GMR_FS_LEN = 0x7fff<<16, /* Bit 30..16: Rx Frame Length */ |
| 1654 | GMR_FS_VLAN = 1<<13, /* VLAN Packet */ |
| 1655 | GMR_FS_JABBER = 1<<12, /* Jabber Packet */ |
| 1656 | GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */ |
| 1657 | GMR_FS_MC = 1<<10, /* Multicast Packet */ |
| 1658 | GMR_FS_BC = 1<<9, /* Broadcast Packet */ |
| 1659 | GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */ |
| 1660 | GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */ |
| 1661 | GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */ |
| 1662 | GMR_FS_MII_ERR = 1<<5, /* MII Error */ |
| 1663 | GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */ |
| 1664 | GMR_FS_FRAGMENT = 1<<3, /* Fragment */ |
| 1665 | |
| 1666 | GMR_FS_CRC_ERR = 1<<1, /* CRC Error */ |
| 1667 | GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */ |
| 1668 | |
| 1669 | GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR | |
| 1670 | GMR_FS_FRAGMENT | GMR_FS_LONG_ERR | |
| 1671 | GMR_FS_MII_ERR | GMR_FS_BAD_FC | |
| 1672 | GMR_FS_UN_SIZE | GMR_FS_JABBER, |
| 1673 | }; |
| 1674 | |
| 1675 | /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ |
| 1676 | enum { |
| 1677 | RX_TRUNC_ON = 1<<27, /* enable packet truncation */ |
| 1678 | RX_TRUNC_OFF = 1<<26, /* disable packet truncation */ |
| 1679 | RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */ |
| 1680 | RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */ |
| 1681 | |
| 1682 | RX_MACSEC_FLUSH_ON = 1<<23, |
| 1683 | RX_MACSEC_FLUSH_OFF = 1<<22, |
| 1684 | RX_MACSEC_ASF_FLUSH_ON = 1<<21, |
| 1685 | RX_MACSEC_ASF_FLUSH_OFF = 1<<20, |
| 1686 | |
| 1687 | GMF_RX_OVER_ON = 1<<19, /* enable flushing on receive overrun */ |
| 1688 | GMF_RX_OVER_OFF = 1<<18, /* disable flushing on receive overrun */ |
| 1689 | GMF_ASF_RX_OVER_ON = 1<<17, /* enable flushing of ASF when overrun */ |
| 1690 | GMF_ASF_RX_OVER_OFF = 1<<16, /* disable flushing of ASF when overrun */ |
| 1691 | |
| 1692 | GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */ |
| 1693 | GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */ |
| 1694 | GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */ |
| 1695 | |
| 1696 | GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */ |
| 1697 | GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */ |
| 1698 | GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */ |
| 1699 | GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */ |
| 1700 | GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */ |
| 1701 | GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */ |
| 1702 | GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */ |
| 1703 | |
| 1704 | GMF_OPER_ON = 1<<3, /* Operational Mode On */ |
| 1705 | GMF_OPER_OFF = 1<<2, /* Operational Mode Off */ |
| 1706 | GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */ |
| 1707 | GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */ |
| 1708 | |
| 1709 | RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */ |
| 1710 | |
| 1711 | GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON, |
| 1712 | }; |
| 1713 | |
| 1714 | /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ |
| 1715 | enum { |
| 1716 | TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */ |
| 1717 | }; |
| 1718 | |
| 1719 | /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ |
| 1720 | enum { |
| 1721 | TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */ |
| 1722 | TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */ |
| 1723 | |
| 1724 | TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */ |
| 1725 | TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */ |
| 1726 | |
| 1727 | TX_JUMBO_ENA = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */ |
| 1728 | TX_JUMBO_DIS = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */ |
| 1729 | |
| 1730 | GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */ |
| 1731 | GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */ |
| 1732 | GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */ |
| 1733 | |
| 1734 | GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */ |
| 1735 | GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */ |
| 1736 | GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */ |
| 1737 | }; |
| 1738 | |
| 1739 | /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ |
| 1740 | enum { |
| 1741 | GMT_ST_START = 1<<2, /* Start Time Stamp Timer */ |
| 1742 | GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */ |
| 1743 | GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */ |
| 1744 | }; |
| 1745 | |
| 1746 | /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ |
| 1747 | enum { |
| 1748 | Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */ |
| 1749 | Y2_ASF_RESET = 1<<3, /* ASF system in reset state */ |
| 1750 | Y2_ASF_RUNNING = 1<<2, /* ASF system operational */ |
| 1751 | Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */ |
| 1752 | Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */ |
| 1753 | |
| 1754 | Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */ |
| 1755 | Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */ |
| 1756 | }; |
| 1757 | |
| 1758 | /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ |
| 1759 | enum { |
| 1760 | Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */ |
| 1761 | Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */ |
| 1762 | }; |
| 1763 | /* HCU_CCSR CPU Control and Status Register */ |
| 1764 | enum { |
| 1765 | HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */ |
| 1766 | HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */ |
| 1767 | /* Clock Stretching Timeout */ |
| 1768 | HCU_CCSR_CS_TO = 1<<25, |
| 1769 | HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */ |
| 1770 | |
| 1771 | HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */ |
| 1772 | HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */ |
| 1773 | |
| 1774 | HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */ |
| 1775 | HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */ |
| 1776 | |
| 1777 | HCU_CCSR_SET_SYNC_CPU = 1<<5, |
| 1778 | HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */ |
| 1779 | HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3, |
| 1780 | HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */ |
| 1781 | /* Microcontroller State */ |
| 1782 | HCU_CCSR_UC_STATE_MSK = 3, |
| 1783 | HCU_CCSR_UC_STATE_BASE = 1<<0, |
| 1784 | HCU_CCSR_ASF_RESET = 0, |
| 1785 | HCU_CCSR_ASF_HALTED = 1<<1, |
| 1786 | HCU_CCSR_ASF_RUNNING = 1<<0, |
| 1787 | }; |
| 1788 | |
| 1789 | /* HCU_HCSR Host Control and Status Register */ |
| 1790 | enum { |
| 1791 | HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */ |
| 1792 | |
| 1793 | HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */ |
| 1794 | HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */ |
| 1795 | }; |
| 1796 | |
| 1797 | /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ |
| 1798 | enum { |
| 1799 | SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */ |
| 1800 | SC_STAT_OP_ON = 1<<3, /* Operational Mode On */ |
| 1801 | SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */ |
| 1802 | SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */ |
| 1803 | SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */ |
| 1804 | }; |
| 1805 | |
| 1806 | /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ |
| 1807 | enum { |
| 1808 | GMC_SET_RST = 1<<15,/* MAC SEC RST */ |
| 1809 | GMC_SEC_RST_OFF = 1<<14,/* MAC SEC RSt OFF */ |
| 1810 | GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */ |
| 1811 | GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */ |
| 1812 | GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */ |
| 1813 | GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX off*/ |
| 1814 | GMC_BYP_RETR_ON = 1<<9, /* Bypass retransmit FIFO On */ |
| 1815 | GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */ |
| 1816 | |
| 1817 | GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */ |
| 1818 | GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */ |
| 1819 | GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */ |
| 1820 | GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */ |
| 1821 | GMC_PAUSE_ON = 1<<3, /* Pause On */ |
| 1822 | GMC_PAUSE_OFF = 1<<2, /* Pause Off */ |
| 1823 | GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */ |
| 1824 | GMC_RST_SET = 1<<0, /* Set GMAC Reset */ |
| 1825 | }; |
| 1826 | |
| 1827 | /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ |
| 1828 | enum { |
| 1829 | GPC_TX_PAUSE = 1<<30, /* Tx pause enabled (ro) */ |
| 1830 | GPC_RX_PAUSE = 1<<29, /* Rx pause enabled (ro) */ |
| 1831 | GPC_SPEED = 3<<27, /* PHY speed (ro) */ |
| 1832 | GPC_LINK = 1<<26, /* Link up (ro) */ |
| 1833 | GPC_DUPLEX = 1<<25, /* Duplex (ro) */ |
| 1834 | GPC_CLOCK = 1<<24, /* 125Mhz clock stable (ro) */ |
| 1835 | |
| 1836 | GPC_PDOWN = 1<<23, /* Internal regulator 2.5 power down */ |
| 1837 | GPC_TSTMODE = 1<<22, /* Test mode */ |
| 1838 | GPC_REG18 = 1<<21, /* Reg18 Power down */ |
| 1839 | GPC_REG12SEL = 3<<19, /* Reg12 power setting */ |
| 1840 | GPC_REG18SEL = 3<<17, /* Reg18 power setting */ |
| 1841 | GPC_SPILOCK = 1<<16, /* SPI lock (ASF) */ |
| 1842 | |
| 1843 | GPC_LEDMUX = 3<<14, /* LED Mux */ |
| 1844 | GPC_INTPOL = 1<<13, /* Interrupt polarity */ |
| 1845 | GPC_DETECT = 1<<12, /* Energy detect */ |
| 1846 | GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */ |
| 1847 | GPC_SLAVE = 1<<10, /* Slave mode */ |
| 1848 | GPC_PAUSE = 1<<9, /* Pause enable */ |
| 1849 | GPC_LEDCTL = 3<<6, /* GPHY Leds */ |
| 1850 | |
| 1851 | GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ |
| 1852 | GPC_RST_SET = 1<<0, /* Set GPHY Reset */ |
| 1853 | }; |
| 1854 | |
| 1855 | /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ |
| 1856 | /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ |
| 1857 | enum { |
| 1858 | GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */ |
| 1859 | GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */ |
| 1860 | GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */ |
| 1861 | GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */ |
| 1862 | GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ |
| 1863 | GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ |
| 1864 | |
| 1865 | #define GMAC_DEF_MSK GM_IS_TX_FF_UR |
| 1866 | }; |
| 1867 | |
| 1868 | /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ |
| 1869 | enum { /* Bits 15.. 2: reserved */ |
| 1870 | GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */ |
| 1871 | GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */ |
| 1872 | }; |
| 1873 | |
| 1874 | |
| 1875 | /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ |
| 1876 | enum { |
| 1877 | WOL_CTL_LINK_CHG_OCC = 1<<15, |
| 1878 | WOL_CTL_MAGIC_PKT_OCC = 1<<14, |
| 1879 | WOL_CTL_PATTERN_OCC = 1<<13, |
| 1880 | WOL_CTL_CLEAR_RESULT = 1<<12, |
| 1881 | WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11, |
| 1882 | WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10, |
| 1883 | WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9, |
| 1884 | WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8, |
| 1885 | WOL_CTL_ENA_PME_ON_PATTERN = 1<<7, |
| 1886 | WOL_CTL_DIS_PME_ON_PATTERN = 1<<6, |
| 1887 | WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5, |
| 1888 | WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4, |
| 1889 | WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3, |
| 1890 | WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2, |
| 1891 | WOL_CTL_ENA_PATTERN_UNIT = 1<<1, |
| 1892 | WOL_CTL_DIS_PATTERN_UNIT = 1<<0, |
| 1893 | }; |
| 1894 | |
| 1895 | |
| 1896 | /* Control flags */ |
| 1897 | enum { |
| 1898 | UDPTCP = 1<<0, |
| 1899 | CALSUM = 1<<1, |
| 1900 | WR_SUM = 1<<2, |
| 1901 | INIT_SUM= 1<<3, |
| 1902 | LOCK_SUM= 1<<4, |
| 1903 | INS_VLAN= 1<<5, |
| 1904 | EOP = 1<<7, |
| 1905 | }; |
| 1906 | |
| 1907 | enum { |
| 1908 | HW_OWNER = 1<<7, |
| 1909 | OP_TCPWRITE = 0x11, |
| 1910 | OP_TCPSTART = 0x12, |
| 1911 | OP_TCPINIT = 0x14, |
| 1912 | OP_TCPLCK = 0x18, |
| 1913 | OP_TCPCHKSUM = OP_TCPSTART, |
| 1914 | OP_TCPIS = OP_TCPINIT | OP_TCPSTART, |
| 1915 | OP_TCPLW = OP_TCPLCK | OP_TCPWRITE, |
| 1916 | OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE, |
| 1917 | OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE, |
| 1918 | |
| 1919 | OP_ADDR64 = 0x21, |
| 1920 | OP_VLAN = 0x22, |
| 1921 | OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN, |
| 1922 | OP_LRGLEN = 0x24, |
| 1923 | OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN, |
| 1924 | OP_MSS = 0x28, |
| 1925 | OP_MSSVLAN = OP_MSS | OP_VLAN, |
| 1926 | |
| 1927 | OP_BUFFER = 0x40, |
| 1928 | OP_PACKET = 0x41, |
| 1929 | OP_LARGESEND = 0x43, |
| 1930 | OP_LSOV2 = 0x45, |
| 1931 | |
| 1932 | /* YUKON-2 STATUS opcodes defines */ |
| 1933 | OP_RXSTAT = 0x60, |
| 1934 | OP_RXTIMESTAMP = 0x61, |
| 1935 | OP_RXVLAN = 0x62, |
| 1936 | OP_RXCHKS = 0x64, |
| 1937 | OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN, |
| 1938 | OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN, |
| 1939 | OP_RSS_HASH = 0x65, |
| 1940 | OP_TXINDEXLE = 0x68, |
| 1941 | OP_MACSEC = 0x6c, |
| 1942 | OP_PUTIDX = 0x70, |
| 1943 | }; |
| 1944 | |
| 1945 | enum status_css { |
| 1946 | CSS_TCPUDPCSOK = 1<<7, /* TCP / UDP checksum is ok */ |
| 1947 | CSS_ISUDP = 1<<6, /* packet is a UDP packet */ |
| 1948 | CSS_ISTCP = 1<<5, /* packet is a TCP packet */ |
| 1949 | CSS_ISIPFRAG = 1<<4, /* packet is a TCP/UDP frag, CS calc not done */ |
| 1950 | CSS_ISIPV6 = 1<<3, /* packet is a IPv6 packet */ |
| 1951 | CSS_IPV4CSUMOK = 1<<2, /* IP v4: TCP header checksum is ok */ |
| 1952 | CSS_ISIPV4 = 1<<1, /* packet is a IPv4 packet */ |
| 1953 | CSS_LINK_BIT = 1<<0, /* port number (legacy) */ |
| 1954 | }; |
| 1955 | |
| 1956 | /* Yukon 2 hardware interface */ |
| 1957 | struct sky2_tx_le { |
| 1958 | __le32 addr; |
| 1959 | __le16 length; /* also vlan tag or checksum start */ |
| 1960 | u8 ctrl; |
| 1961 | u8 opcode; |
| 1962 | } __attribute((packed)); |
| 1963 | |
| 1964 | struct sky2_rx_le { |
| 1965 | __le32 addr; |
| 1966 | __le16 length; |
| 1967 | u8 ctrl; |
| 1968 | u8 opcode; |
| 1969 | } __attribute((packed)); |
| 1970 | |
| 1971 | struct sky2_status_le { |
| 1972 | __le32 status; /* also checksum */ |
| 1973 | __le16 length; /* also vlan tag */ |
| 1974 | u8 css; |
| 1975 | u8 opcode; |
| 1976 | } __attribute((packed)); |
| 1977 | |
| 1978 | struct tx_ring_info { |
| 1979 | struct sk_buff *skb; |
| 1980 | unsigned long flags; |
| 1981 | #define TX_MAP_SINGLE 0x0001 |
| 1982 | #define TX_MAP_PAGE 000002 |
| 1983 | DECLARE_PCI_UNMAP_ADDR(mapaddr); |
| 1984 | DECLARE_PCI_UNMAP_LEN(maplen); |
| 1985 | }; |
| 1986 | |
| 1987 | struct rx_ring_info { |
| 1988 | struct sk_buff *skb; |
| 1989 | dma_addr_t data_addr; |
| 1990 | DECLARE_PCI_UNMAP_LEN(data_size); |
| 1991 | dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT]; |
| 1992 | }; |
| 1993 | |
| 1994 | enum flow_control { |
| 1995 | FC_NONE = 0, |
| 1996 | FC_TX = 1, |
| 1997 | FC_RX = 2, |
| 1998 | FC_BOTH = 3, |
| 1999 | }; |
| 2000 | |
| 2001 | struct sky2_port { |
| 2002 | struct sky2_hw *hw; |
| 2003 | struct net_device *netdev; |
| 2004 | unsigned port; |
| 2005 | u32 msg_enable; |
| 2006 | spinlock_t phy_lock; |
| 2007 | |
| 2008 | struct tx_ring_info *tx_ring; |
| 2009 | struct sky2_tx_le *tx_le; |
| 2010 | u16 tx_ring_size; |
| 2011 | u16 tx_cons; /* next le to check */ |
| 2012 | u16 tx_prod; /* next le to use */ |
| 2013 | u16 tx_next; /* debug only */ |
| 2014 | |
| 2015 | u16 tx_pending; |
| 2016 | u16 tx_last_mss; |
| 2017 | u32 tx_last_upper; |
| 2018 | u32 tx_tcpsum; |
| 2019 | |
| 2020 | struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp; |
| 2021 | struct sky2_rx_le *rx_le; |
| 2022 | |
| 2023 | u16 rx_next; /* next re to check */ |
| 2024 | u16 rx_put; /* next le index to use */ |
| 2025 | u16 rx_pending; |
| 2026 | u16 rx_data_size; |
| 2027 | u16 rx_nfrags; |
| 2028 | |
| 2029 | #ifdef SKY2_VLAN_TAG_USED |
| 2030 | u16 rx_tag; |
| 2031 | struct vlan_group *vlgrp; |
| 2032 | #endif |
| 2033 | struct { |
| 2034 | unsigned long last; |
| 2035 | u32 mac_rp; |
| 2036 | u8 mac_lev; |
| 2037 | u8 fifo_rp; |
| 2038 | u8 fifo_lev; |
| 2039 | } check; |
| 2040 | |
| 2041 | dma_addr_t rx_le_map; |
| 2042 | dma_addr_t tx_le_map; |
| 2043 | |
| 2044 | u16 advertising; /* ADVERTISED_ bits */ |
| 2045 | u16 speed; /* SPEED_1000, SPEED_100, ... */ |
| 2046 | u8 wol; /* WAKE_ bits */ |
| 2047 | u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */ |
| 2048 | u16 flags; |
| 2049 | #define SKY2_FLAG_RX_CHECKSUM 0x0001 |
| 2050 | #define SKY2_FLAG_AUTO_SPEED 0x0002 |
| 2051 | #define SKY2_FLAG_AUTO_PAUSE 0x0004 |
| 2052 | |
| 2053 | enum flow_control flow_mode; |
| 2054 | enum flow_control flow_status; |
| 2055 | |
| 2056 | #ifdef CONFIG_SKY2_DEBUG |
| 2057 | struct dentry *debugfs; |
| 2058 | #endif |
| 2059 | }; |
| 2060 | |
| 2061 | struct sky2_hw { |
| 2062 | void __iomem *regs; |
| 2063 | struct pci_dev *pdev; |
| 2064 | struct napi_struct napi; |
| 2065 | struct net_device *dev[2]; |
| 2066 | unsigned long flags; |
| 2067 | #define SKY2_HW_USE_MSI 0x00000001 |
| 2068 | #define SKY2_HW_FIBRE_PHY 0x00000002 |
| 2069 | #define SKY2_HW_GIGABIT 0x00000004 |
| 2070 | #define SKY2_HW_NEWER_PHY 0x00000008 |
| 2071 | #define SKY2_HW_RAM_BUFFER 0x00000010 |
| 2072 | #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */ |
| 2073 | #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */ |
| 2074 | #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */ |
| 2075 | |
| 2076 | u8 chip_id; |
| 2077 | u8 chip_rev; |
| 2078 | u8 pmd_type; |
| 2079 | u8 ports; |
| 2080 | |
| 2081 | struct sky2_status_le *st_le; |
| 2082 | u32 st_idx; |
| 2083 | dma_addr_t st_dma; |
| 2084 | |
| 2085 | struct timer_list watchdog_timer; |
| 2086 | struct work_struct restart_work; |
| 2087 | wait_queue_head_t msi_wait; |
| 2088 | }; |
| 2089 | |
| 2090 | static inline int sky2_is_copper(const struct sky2_hw *hw) |
| 2091 | { |
| 2092 | return !(hw->flags & SKY2_HW_FIBRE_PHY); |
| 2093 | } |
| 2094 | |
| 2095 | /* Register accessor for memory mapped device */ |
| 2096 | static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) |
| 2097 | { |
| 2098 | return readl(hw->regs + reg); |
| 2099 | } |
| 2100 | |
| 2101 | static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg) |
| 2102 | { |
| 2103 | return readw(hw->regs + reg); |
| 2104 | } |
| 2105 | |
| 2106 | static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg) |
| 2107 | { |
| 2108 | return readb(hw->regs + reg); |
| 2109 | } |
| 2110 | |
| 2111 | static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) |
| 2112 | { |
| 2113 | writel(val, hw->regs + reg); |
| 2114 | } |
| 2115 | |
| 2116 | static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) |
| 2117 | { |
| 2118 | writew(val, hw->regs + reg); |
| 2119 | } |
| 2120 | |
| 2121 | static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) |
| 2122 | { |
| 2123 | writeb(val, hw->regs + reg); |
| 2124 | } |
| 2125 | |
| 2126 | /* Yukon PHY related registers */ |
| 2127 | #define SK_GMAC_REG(port,reg) \ |
| 2128 | (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) |
| 2129 | #define GM_PHY_RETRIES 100 |
| 2130 | |
| 2131 | static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg) |
| 2132 | { |
| 2133 | return sky2_read16(hw, SK_GMAC_REG(port,reg)); |
| 2134 | } |
| 2135 | |
| 2136 | static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg) |
| 2137 | { |
| 2138 | unsigned base = SK_GMAC_REG(port, reg); |
| 2139 | return (u32) sky2_read16(hw, base) |
| 2140 | | (u32) sky2_read16(hw, base+4) << 16; |
| 2141 | } |
| 2142 | |
| 2143 | static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v) |
| 2144 | { |
| 2145 | sky2_write16(hw, SK_GMAC_REG(port,r), v); |
| 2146 | } |
| 2147 | |
| 2148 | static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, |
| 2149 | const u8 *addr) |
| 2150 | { |
| 2151 | gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); |
| 2152 | gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); |
| 2153 | gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); |
| 2154 | } |
| 2155 | |
| 2156 | /* PCI config space access */ |
| 2157 | static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) |
| 2158 | { |
| 2159 | return sky2_read32(hw, Y2_CFG_SPC + reg); |
| 2160 | } |
| 2161 | |
| 2162 | static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) |
| 2163 | { |
| 2164 | return sky2_read16(hw, Y2_CFG_SPC + reg); |
| 2165 | } |
| 2166 | |
| 2167 | static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) |
| 2168 | { |
| 2169 | sky2_write32(hw, Y2_CFG_SPC + reg, val); |
| 2170 | } |
| 2171 | |
| 2172 | static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) |
| 2173 | { |
| 2174 | sky2_write16(hw, Y2_CFG_SPC + reg, val); |
| 2175 | } |
| 2176 | #endif |