| 1 | /* |
| 2 | * New driver for Marvell Yukon 2 chipset. |
| 3 | * Based on earlier sk98lin, and skge driver. |
| 4 | * |
| 5 | * This driver intentionally does not support all the features |
| 6 | * of the original driver such as link fail-over and link management because |
| 7 | * those should be done at higher levels. |
| 8 | * |
| 9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 23 | */ |
| 24 | |
| 25 | #include <linux/crc32.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/netdevice.h> |
| 29 | #include <linux/dma-mapping.h> |
| 30 | #include <linux/etherdevice.h> |
| 31 | #include <linux/ethtool.h> |
| 32 | #include <linux/pci.h> |
| 33 | #include <linux/ip.h> |
| 34 | #include <net/ip.h> |
| 35 | #include <linux/tcp.h> |
| 36 | #include <linux/in.h> |
| 37 | #include <linux/delay.h> |
| 38 | #include <linux/workqueue.h> |
| 39 | #include <linux/if_vlan.h> |
| 40 | #include <linux/prefetch.h> |
| 41 | #include <linux/debugfs.h> |
| 42 | #include <linux/mii.h> |
| 43 | |
| 44 | #include <asm/irq.h> |
| 45 | |
| 46 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
| 47 | #define SKY2_VLAN_TAG_USED 1 |
| 48 | #endif |
| 49 | |
| 50 | #include "sky2.h" |
| 51 | |
| 52 | #define DRV_NAME "sky2" |
| 53 | #define DRV_VERSION "1.25" |
| 54 | #define PFX DRV_NAME " " |
| 55 | |
| 56 | /* |
| 57 | * The Yukon II chipset takes 64 bit command blocks (called list elements) |
| 58 | * that are organized into three (receive, transmit, status) different rings |
| 59 | * similar to Tigon3. |
| 60 | */ |
| 61 | |
| 62 | #define RX_LE_SIZE 1024 |
| 63 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
| 64 | #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) |
| 65 | #define RX_DEF_PENDING RX_MAX_PENDING |
| 66 | |
| 67 | /* This is the worst case number of transmit list elements for a single skb: |
| 68 | VLAN + TSO + CKSUM + Data + skb_frags * DMA */ |
| 69 | #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS) |
| 70 | #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) |
| 71 | #define TX_MAX_PENDING 4096 |
| 72 | #define TX_DEF_PENDING 127 |
| 73 | |
| 74 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
| 75 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
| 76 | #define TX_WATCHDOG (5 * HZ) |
| 77 | #define NAPI_WEIGHT 64 |
| 78 | #define PHY_RETRIES 1000 |
| 79 | |
| 80 | #define SKY2_EEPROM_MAGIC 0x9955aabb |
| 81 | |
| 82 | |
| 83 | #define RING_NEXT(x,s) (((x)+1) & ((s)-1)) |
| 84 | |
| 85 | static const u32 default_msg = |
| 86 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
| 87 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR |
| 88 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
| 89 | |
| 90 | static int debug = -1; /* defaults above */ |
| 91 | module_param(debug, int, 0); |
| 92 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); |
| 93 | |
| 94 | static int copybreak __read_mostly = 128; |
| 95 | module_param(copybreak, int, 0); |
| 96 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); |
| 97 | |
| 98 | static int disable_msi = 0; |
| 99 | module_param(disable_msi, int, 0); |
| 100 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); |
| 101 | |
| 102 | static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = { |
| 103 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ |
| 104 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ |
| 105 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ |
| 106 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ |
| 107 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ |
| 108 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ |
| 109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ |
| 110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ |
| 111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ |
| 112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ |
| 113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ |
| 114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ |
| 115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ |
| 116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ |
| 117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ |
| 118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ |
| 119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ |
| 120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ |
| 121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ |
| 122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ |
| 123 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ |
| 124 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ |
| 125 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ |
| 126 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ |
| 127 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ |
| 128 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ |
| 129 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ |
| 130 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ |
| 131 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ |
| 132 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ |
| 133 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ |
| 134 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ |
| 135 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ |
| 136 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ |
| 137 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ |
| 138 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ |
| 139 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ |
| 140 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ |
| 141 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ |
| 142 | { 0 } |
| 143 | }; |
| 144 | |
| 145 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
| 146 | |
| 147 | /* Avoid conditionals by using array */ |
| 148 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; |
| 149 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; |
| 150 | static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; |
| 151 | |
| 152 | static void sky2_set_multicast(struct net_device *dev); |
| 153 | |
| 154 | /* Access to PHY via serial interconnect */ |
| 155 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
| 156 | { |
| 157 | int i; |
| 158 | |
| 159 | gma_write16(hw, port, GM_SMI_DATA, val); |
| 160 | gma_write16(hw, port, GM_SMI_CTRL, |
| 161 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); |
| 162 | |
| 163 | for (i = 0; i < PHY_RETRIES; i++) { |
| 164 | u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); |
| 165 | if (ctrl == 0xffff) |
| 166 | goto io_error; |
| 167 | |
| 168 | if (!(ctrl & GM_SMI_CT_BUSY)) |
| 169 | return 0; |
| 170 | |
| 171 | udelay(10); |
| 172 | } |
| 173 | |
| 174 | dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name); |
| 175 | return -ETIMEDOUT; |
| 176 | |
| 177 | io_error: |
| 178 | dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); |
| 179 | return -EIO; |
| 180 | } |
| 181 | |
| 182 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
| 183 | { |
| 184 | int i; |
| 185 | |
| 186 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
| 187 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
| 188 | |
| 189 | for (i = 0; i < PHY_RETRIES; i++) { |
| 190 | u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); |
| 191 | if (ctrl == 0xffff) |
| 192 | goto io_error; |
| 193 | |
| 194 | if (ctrl & GM_SMI_CT_RD_VAL) { |
| 195 | *val = gma_read16(hw, port, GM_SMI_DATA); |
| 196 | return 0; |
| 197 | } |
| 198 | |
| 199 | udelay(10); |
| 200 | } |
| 201 | |
| 202 | dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); |
| 203 | return -ETIMEDOUT; |
| 204 | io_error: |
| 205 | dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); |
| 206 | return -EIO; |
| 207 | } |
| 208 | |
| 209 | static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) |
| 210 | { |
| 211 | u16 v; |
| 212 | __gm_phy_read(hw, port, reg, &v); |
| 213 | return v; |
| 214 | } |
| 215 | |
| 216 | |
| 217 | static void sky2_power_on(struct sky2_hw *hw) |
| 218 | { |
| 219 | /* switch power to VCC (WA for VAUX problem) */ |
| 220 | sky2_write8(hw, B0_POWER_CTRL, |
| 221 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); |
| 222 | |
| 223 | /* disable Core Clock Division, */ |
| 224 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); |
| 225 | |
| 226 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
| 227 | /* enable bits are inverted */ |
| 228 | sky2_write8(hw, B2_Y2_CLK_GATE, |
| 229 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | |
| 230 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | |
| 231 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); |
| 232 | else |
| 233 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
| 234 | |
| 235 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { |
| 236 | u32 reg; |
| 237 | |
| 238 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
| 239 | |
| 240 | reg = sky2_pci_read32(hw, PCI_DEV_REG4); |
| 241 | /* set all bits to 0 except bits 15..12 and 8 */ |
| 242 | reg &= P_ASPM_CONTROL_MSK; |
| 243 | sky2_pci_write32(hw, PCI_DEV_REG4, reg); |
| 244 | |
| 245 | reg = sky2_pci_read32(hw, PCI_DEV_REG5); |
| 246 | /* set all bits to 0 except bits 28 & 27 */ |
| 247 | reg &= P_CTL_TIM_VMAIN_AV_MSK; |
| 248 | sky2_pci_write32(hw, PCI_DEV_REG5, reg); |
| 249 | |
| 250 | sky2_pci_write32(hw, PCI_CFG_REG_1, 0); |
| 251 | |
| 252 | /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ |
| 253 | reg = sky2_read32(hw, B2_GP_IO); |
| 254 | reg |= GLB_GPIO_STAT_RACE_DIS; |
| 255 | sky2_write32(hw, B2_GP_IO, reg); |
| 256 | |
| 257 | sky2_read32(hw, B2_GP_IO); |
| 258 | } |
| 259 | |
| 260 | /* Turn on "driver loaded" LED */ |
| 261 | sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); |
| 262 | } |
| 263 | |
| 264 | static void sky2_power_aux(struct sky2_hw *hw) |
| 265 | { |
| 266 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
| 267 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
| 268 | else |
| 269 | /* enable bits are inverted */ |
| 270 | sky2_write8(hw, B2_Y2_CLK_GATE, |
| 271 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | |
| 272 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | |
| 273 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); |
| 274 | |
| 275 | /* switch power to VAUX if supported and PME from D3cold */ |
| 276 | if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && |
| 277 | pci_pme_capable(hw->pdev, PCI_D3cold)) |
| 278 | sky2_write8(hw, B0_POWER_CTRL, |
| 279 | (PC_VAUX_ENA | PC_VCC_ENA | |
| 280 | PC_VAUX_ON | PC_VCC_OFF)); |
| 281 | |
| 282 | /* turn off "driver loaded LED" */ |
| 283 | sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); |
| 284 | } |
| 285 | |
| 286 | static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) |
| 287 | { |
| 288 | u16 reg; |
| 289 | |
| 290 | /* disable all GMAC IRQ's */ |
| 291 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
| 292 | |
| 293 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
| 294 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); |
| 295 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); |
| 296 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); |
| 297 | |
| 298 | reg = gma_read16(hw, port, GM_RX_CTRL); |
| 299 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; |
| 300 | gma_write16(hw, port, GM_RX_CTRL, reg); |
| 301 | } |
| 302 | |
| 303 | /* flow control to advertise bits */ |
| 304 | static const u16 copper_fc_adv[] = { |
| 305 | [FC_NONE] = 0, |
| 306 | [FC_TX] = PHY_M_AN_ASP, |
| 307 | [FC_RX] = PHY_M_AN_PC, |
| 308 | [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, |
| 309 | }; |
| 310 | |
| 311 | /* flow control to advertise bits when using 1000BaseX */ |
| 312 | static const u16 fiber_fc_adv[] = { |
| 313 | [FC_NONE] = PHY_M_P_NO_PAUSE_X, |
| 314 | [FC_TX] = PHY_M_P_ASYM_MD_X, |
| 315 | [FC_RX] = PHY_M_P_SYM_MD_X, |
| 316 | [FC_BOTH] = PHY_M_P_BOTH_MD_X, |
| 317 | }; |
| 318 | |
| 319 | /* flow control to GMA disable bits */ |
| 320 | static const u16 gm_fc_disable[] = { |
| 321 | [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, |
| 322 | [FC_TX] = GM_GPCR_FC_RX_DIS, |
| 323 | [FC_RX] = GM_GPCR_FC_TX_DIS, |
| 324 | [FC_BOTH] = 0, |
| 325 | }; |
| 326 | |
| 327 | |
| 328 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) |
| 329 | { |
| 330 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); |
| 331 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; |
| 332 | |
| 333 | if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && |
| 334 | !(hw->flags & SKY2_HW_NEWER_PHY)) { |
| 335 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
| 336 | |
| 337 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | |
| 338 | PHY_M_EC_MAC_S_MSK); |
| 339 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
| 340 | |
| 341 | /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ |
| 342 | if (hw->chip_id == CHIP_ID_YUKON_EC) |
| 343 | /* set downshift counter to 3x and enable downshift */ |
| 344 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; |
| 345 | else |
| 346 | /* set master & slave downshift counter to 1x */ |
| 347 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); |
| 348 | |
| 349 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); |
| 350 | } |
| 351 | |
| 352 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
| 353 | if (sky2_is_copper(hw)) { |
| 354 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
| 355 | /* enable automatic crossover */ |
| 356 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; |
| 357 | |
| 358 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
| 359 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { |
| 360 | u16 spec; |
| 361 | |
| 362 | /* Enable Class A driver for FE+ A0 */ |
| 363 | spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); |
| 364 | spec |= PHY_M_FESC_SEL_CL_A; |
| 365 | gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); |
| 366 | } |
| 367 | } else { |
| 368 | /* disable energy detect */ |
| 369 | ctrl &= ~PHY_M_PC_EN_DET_MSK; |
| 370 | |
| 371 | /* enable automatic crossover */ |
| 372 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); |
| 373 | |
| 374 | /* downshift on PHY 88E1112 and 88E1149 is changed */ |
| 375 | if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) |
| 376 | && (hw->flags & SKY2_HW_NEWER_PHY)) { |
| 377 | /* set downshift counter to 3x and enable downshift */ |
| 378 | ctrl &= ~PHY_M_PC_DSC_MSK; |
| 379 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; |
| 380 | } |
| 381 | } |
| 382 | } else { |
| 383 | /* workaround for deviation #4.88 (CRC errors) */ |
| 384 | /* disable Automatic Crossover */ |
| 385 | |
| 386 | ctrl &= ~PHY_M_PC_MDIX_MSK; |
| 387 | } |
| 388 | |
| 389 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
| 390 | |
| 391 | /* special setup for PHY 88E1112 Fiber */ |
| 392 | if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { |
| 393 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
| 394 | |
| 395 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ |
| 396 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); |
| 397 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
| 398 | ctrl &= ~PHY_M_MAC_MD_MSK; |
| 399 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); |
| 400 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
| 401 | |
| 402 | if (hw->pmd_type == 'P') { |
| 403 | /* select page 1 to access Fiber registers */ |
| 404 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); |
| 405 | |
| 406 | /* for SFP-module set SIGDET polarity to low */ |
| 407 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
| 408 | ctrl |= PHY_M_FIB_SIGD_POL; |
| 409 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
| 410 | } |
| 411 | |
| 412 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
| 413 | } |
| 414 | |
| 415 | ctrl = PHY_CT_RESET; |
| 416 | ct1000 = 0; |
| 417 | adv = PHY_AN_CSMA; |
| 418 | reg = 0; |
| 419 | |
| 420 | if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { |
| 421 | if (sky2_is_copper(hw)) { |
| 422 | if (sky2->advertising & ADVERTISED_1000baseT_Full) |
| 423 | ct1000 |= PHY_M_1000C_AFD; |
| 424 | if (sky2->advertising & ADVERTISED_1000baseT_Half) |
| 425 | ct1000 |= PHY_M_1000C_AHD; |
| 426 | if (sky2->advertising & ADVERTISED_100baseT_Full) |
| 427 | adv |= PHY_M_AN_100_FD; |
| 428 | if (sky2->advertising & ADVERTISED_100baseT_Half) |
| 429 | adv |= PHY_M_AN_100_HD; |
| 430 | if (sky2->advertising & ADVERTISED_10baseT_Full) |
| 431 | adv |= PHY_M_AN_10_FD; |
| 432 | if (sky2->advertising & ADVERTISED_10baseT_Half) |
| 433 | adv |= PHY_M_AN_10_HD; |
| 434 | |
| 435 | } else { /* special defines for FIBER (88E1040S only) */ |
| 436 | if (sky2->advertising & ADVERTISED_1000baseT_Full) |
| 437 | adv |= PHY_M_AN_1000X_AFD; |
| 438 | if (sky2->advertising & ADVERTISED_1000baseT_Half) |
| 439 | adv |= PHY_M_AN_1000X_AHD; |
| 440 | } |
| 441 | |
| 442 | /* Restart Auto-negotiation */ |
| 443 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; |
| 444 | } else { |
| 445 | /* forced speed/duplex settings */ |
| 446 | ct1000 = PHY_M_1000C_MSE; |
| 447 | |
| 448 | /* Disable auto update for duplex flow control and duplex */ |
| 449 | reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; |
| 450 | |
| 451 | switch (sky2->speed) { |
| 452 | case SPEED_1000: |
| 453 | ctrl |= PHY_CT_SP1000; |
| 454 | reg |= GM_GPCR_SPEED_1000; |
| 455 | break; |
| 456 | case SPEED_100: |
| 457 | ctrl |= PHY_CT_SP100; |
| 458 | reg |= GM_GPCR_SPEED_100; |
| 459 | break; |
| 460 | } |
| 461 | |
| 462 | if (sky2->duplex == DUPLEX_FULL) { |
| 463 | reg |= GM_GPCR_DUP_FULL; |
| 464 | ctrl |= PHY_CT_DUP_MD; |
| 465 | } else if (sky2->speed < SPEED_1000) |
| 466 | sky2->flow_mode = FC_NONE; |
| 467 | } |
| 468 | |
| 469 | if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { |
| 470 | if (sky2_is_copper(hw)) |
| 471 | adv |= copper_fc_adv[sky2->flow_mode]; |
| 472 | else |
| 473 | adv |= fiber_fc_adv[sky2->flow_mode]; |
| 474 | } else { |
| 475 | reg |= GM_GPCR_AU_FCT_DIS; |
| 476 | reg |= gm_fc_disable[sky2->flow_mode]; |
| 477 | |
| 478 | /* Forward pause packets to GMAC? */ |
| 479 | if (sky2->flow_mode & FC_RX) |
| 480 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
| 481 | else |
| 482 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
| 483 | } |
| 484 | |
| 485 | gma_write16(hw, port, GM_GP_CTRL, reg); |
| 486 | |
| 487 | if (hw->flags & SKY2_HW_GIGABIT) |
| 488 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
| 489 | |
| 490 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); |
| 491 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); |
| 492 | |
| 493 | /* Setup Phy LED's */ |
| 494 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); |
| 495 | ledover = 0; |
| 496 | |
| 497 | switch (hw->chip_id) { |
| 498 | case CHIP_ID_YUKON_FE: |
| 499 | /* on 88E3082 these bits are at 11..9 (shifted left) */ |
| 500 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; |
| 501 | |
| 502 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); |
| 503 | |
| 504 | /* delete ACT LED control bits */ |
| 505 | ctrl &= ~PHY_M_FELP_LED1_MSK; |
| 506 | /* change ACT LED control to blink mode */ |
| 507 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); |
| 508 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); |
| 509 | break; |
| 510 | |
| 511 | case CHIP_ID_YUKON_FE_P: |
| 512 | /* Enable Link Partner Next Page */ |
| 513 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
| 514 | ctrl |= PHY_M_PC_ENA_LIP_NP; |
| 515 | |
| 516 | /* disable Energy Detect and enable scrambler */ |
| 517 | ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); |
| 518 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
| 519 | |
| 520 | /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ |
| 521 | ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | |
| 522 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | |
| 523 | PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); |
| 524 | |
| 525 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); |
| 526 | break; |
| 527 | |
| 528 | case CHIP_ID_YUKON_XL: |
| 529 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
| 530 | |
| 531 | /* select page 3 to access LED control register */ |
| 532 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); |
| 533 | |
| 534 | /* set LED Function Control register */ |
| 535 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
| 536 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ |
| 537 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ |
| 538 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ |
| 539 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ |
| 540 | |
| 541 | /* set Polarity Control register */ |
| 542 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, |
| 543 | (PHY_M_POLC_LS1_P_MIX(4) | |
| 544 | PHY_M_POLC_IS0_P_MIX(4) | |
| 545 | PHY_M_POLC_LOS_CTRL(2) | |
| 546 | PHY_M_POLC_INIT_CTRL(2) | |
| 547 | PHY_M_POLC_STA1_CTRL(2) | |
| 548 | PHY_M_POLC_STA0_CTRL(2))); |
| 549 | |
| 550 | /* restore page register */ |
| 551 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
| 552 | break; |
| 553 | |
| 554 | case CHIP_ID_YUKON_EC_U: |
| 555 | case CHIP_ID_YUKON_EX: |
| 556 | case CHIP_ID_YUKON_SUPR: |
| 557 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
| 558 | |
| 559 | /* select page 3 to access LED control register */ |
| 560 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); |
| 561 | |
| 562 | /* set LED Function Control register */ |
| 563 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
| 564 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ |
| 565 | PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ |
| 566 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ |
| 567 | PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ |
| 568 | |
| 569 | /* set Blink Rate in LED Timer Control Register */ |
| 570 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, |
| 571 | ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); |
| 572 | /* restore page register */ |
| 573 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
| 574 | break; |
| 575 | |
| 576 | default: |
| 577 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ |
| 578 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; |
| 579 | |
| 580 | /* turn off the Rx LED (LED_RX) */ |
| 581 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); |
| 582 | } |
| 583 | |
| 584 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { |
| 585 | /* apply fixes in PHY AFE */ |
| 586 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); |
| 587 | |
| 588 | /* increase differential signal amplitude in 10BASE-T */ |
| 589 | gm_phy_write(hw, port, 0x18, 0xaa99); |
| 590 | gm_phy_write(hw, port, 0x17, 0x2011); |
| 591 | |
| 592 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { |
| 593 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ |
| 594 | gm_phy_write(hw, port, 0x18, 0xa204); |
| 595 | gm_phy_write(hw, port, 0x17, 0x2002); |
| 596 | } |
| 597 | |
| 598 | /* set page register to 0 */ |
| 599 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); |
| 600 | } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
| 601 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { |
| 602 | /* apply workaround for integrated resistors calibration */ |
| 603 | gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); |
| 604 | gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); |
| 605 | } else if (hw->chip_id != CHIP_ID_YUKON_EX && |
| 606 | hw->chip_id < CHIP_ID_YUKON_SUPR) { |
| 607 | /* no effect on Yukon-XL */ |
| 608 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); |
| 609 | |
| 610 | if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED) |
| 611 | || sky2->speed == SPEED_100) { |
| 612 | /* turn on 100 Mbps LED (LED_LINK100) */ |
| 613 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); |
| 614 | } |
| 615 | |
| 616 | if (ledover) |
| 617 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); |
| 618 | |
| 619 | } |
| 620 | |
| 621 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
| 622 | if (sky2->flags & SKY2_FLAG_AUTO_SPEED) |
| 623 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); |
| 624 | else |
| 625 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); |
| 626 | } |
| 627 | |
| 628 | static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; |
| 629 | static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; |
| 630 | |
| 631 | static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) |
| 632 | { |
| 633 | u32 reg1; |
| 634 | |
| 635 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
| 636 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
| 637 | reg1 &= ~phy_power[port]; |
| 638 | |
| 639 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
| 640 | reg1 |= coma_mode[port]; |
| 641 | |
| 642 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
| 643 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
| 644 | sky2_pci_read32(hw, PCI_DEV_REG1); |
| 645 | |
| 646 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
| 647 | gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); |
| 648 | else if (hw->flags & SKY2_HW_ADV_POWER_CTL) |
| 649 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); |
| 650 | } |
| 651 | |
| 652 | static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) |
| 653 | { |
| 654 | u32 reg1; |
| 655 | u16 ctrl; |
| 656 | |
| 657 | /* release GPHY Control reset */ |
| 658 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); |
| 659 | |
| 660 | /* release GMAC reset */ |
| 661 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); |
| 662 | |
| 663 | if (hw->flags & SKY2_HW_NEWER_PHY) { |
| 664 | /* select page 2 to access MAC control register */ |
| 665 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); |
| 666 | |
| 667 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
| 668 | /* allow GMII Power Down */ |
| 669 | ctrl &= ~PHY_M_MAC_GMIF_PUP; |
| 670 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
| 671 | |
| 672 | /* set page register back to 0 */ |
| 673 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); |
| 674 | } |
| 675 | |
| 676 | /* setup General Purpose Control Register */ |
| 677 | gma_write16(hw, port, GM_GP_CTRL, |
| 678 | GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | |
| 679 | GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | |
| 680 | GM_GPCR_AU_SPD_DIS); |
| 681 | |
| 682 | if (hw->chip_id != CHIP_ID_YUKON_EC) { |
| 683 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { |
| 684 | /* select page 2 to access MAC control register */ |
| 685 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); |
| 686 | |
| 687 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
| 688 | /* enable Power Down */ |
| 689 | ctrl |= PHY_M_PC_POW_D_ENA; |
| 690 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
| 691 | |
| 692 | /* set page register back to 0 */ |
| 693 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); |
| 694 | } |
| 695 | |
| 696 | /* set IEEE compatible Power Down Mode (dev. #4.99) */ |
| 697 | gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); |
| 698 | } |
| 699 | |
| 700 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
| 701 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
| 702 | reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ |
| 703 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
| 704 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
| 705 | } |
| 706 | |
| 707 | /* Force a renegotiation */ |
| 708 | static void sky2_phy_reinit(struct sky2_port *sky2) |
| 709 | { |
| 710 | spin_lock_bh(&sky2->phy_lock); |
| 711 | sky2_phy_init(sky2->hw, sky2->port); |
| 712 | spin_unlock_bh(&sky2->phy_lock); |
| 713 | } |
| 714 | |
| 715 | /* Put device in state to listen for Wake On Lan */ |
| 716 | static void sky2_wol_init(struct sky2_port *sky2) |
| 717 | { |
| 718 | struct sky2_hw *hw = sky2->hw; |
| 719 | unsigned port = sky2->port; |
| 720 | enum flow_control save_mode; |
| 721 | u16 ctrl; |
| 722 | u32 reg1; |
| 723 | |
| 724 | /* Bring hardware out of reset */ |
| 725 | sky2_write16(hw, B0_CTST, CS_RST_CLR); |
| 726 | sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); |
| 727 | |
| 728 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); |
| 729 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); |
| 730 | |
| 731 | /* Force to 10/100 |
| 732 | * sky2_reset will re-enable on resume |
| 733 | */ |
| 734 | save_mode = sky2->flow_mode; |
| 735 | ctrl = sky2->advertising; |
| 736 | |
| 737 | sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); |
| 738 | sky2->flow_mode = FC_NONE; |
| 739 | |
| 740 | spin_lock_bh(&sky2->phy_lock); |
| 741 | sky2_phy_power_up(hw, port); |
| 742 | sky2_phy_init(hw, port); |
| 743 | spin_unlock_bh(&sky2->phy_lock); |
| 744 | |
| 745 | sky2->flow_mode = save_mode; |
| 746 | sky2->advertising = ctrl; |
| 747 | |
| 748 | /* Set GMAC to no flow control and auto update for speed/duplex */ |
| 749 | gma_write16(hw, port, GM_GP_CTRL, |
| 750 | GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| |
| 751 | GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); |
| 752 | |
| 753 | /* Set WOL address */ |
| 754 | memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), |
| 755 | sky2->netdev->dev_addr, ETH_ALEN); |
| 756 | |
| 757 | /* Turn on appropriate WOL control bits */ |
| 758 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); |
| 759 | ctrl = 0; |
| 760 | if (sky2->wol & WAKE_PHY) |
| 761 | ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; |
| 762 | else |
| 763 | ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; |
| 764 | |
| 765 | if (sky2->wol & WAKE_MAGIC) |
| 766 | ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; |
| 767 | else |
| 768 | ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;; |
| 769 | |
| 770 | ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; |
| 771 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); |
| 772 | |
| 773 | /* Turn on legacy PCI-Express PME mode */ |
| 774 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
| 775 | reg1 |= PCI_Y2_PME_LEGACY; |
| 776 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
| 777 | |
| 778 | /* block receiver */ |
| 779 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
| 780 | |
| 781 | } |
| 782 | |
| 783 | static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) |
| 784 | { |
| 785 | struct net_device *dev = hw->dev[port]; |
| 786 | |
| 787 | if ( (hw->chip_id == CHIP_ID_YUKON_EX && |
| 788 | hw->chip_rev != CHIP_REV_YU_EX_A0) || |
| 789 | hw->chip_id == CHIP_ID_YUKON_FE_P || |
| 790 | hw->chip_id == CHIP_ID_YUKON_SUPR) { |
| 791 | /* Yukon-Extreme B0 and further Extreme devices */ |
| 792 | /* enable Store & Forward mode for TX */ |
| 793 | |
| 794 | if (dev->mtu <= ETH_DATA_LEN) |
| 795 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
| 796 | TX_JUMBO_DIS | TX_STFW_ENA); |
| 797 | |
| 798 | else |
| 799 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
| 800 | TX_JUMBO_ENA| TX_STFW_ENA); |
| 801 | } else { |
| 802 | if (dev->mtu <= ETH_DATA_LEN) |
| 803 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); |
| 804 | else { |
| 805 | /* set Tx GMAC FIFO Almost Empty Threshold */ |
| 806 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), |
| 807 | (ECU_JUMBO_WM << 16) | ECU_AE_THR); |
| 808 | |
| 809 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); |
| 810 | |
| 811 | /* Can't do offload because of lack of store/forward */ |
| 812 | dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM); |
| 813 | } |
| 814 | } |
| 815 | } |
| 816 | |
| 817 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
| 818 | { |
| 819 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); |
| 820 | u16 reg; |
| 821 | u32 rx_reg; |
| 822 | int i; |
| 823 | const u8 *addr = hw->dev[port]->dev_addr; |
| 824 | |
| 825 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
| 826 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); |
| 827 | |
| 828 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); |
| 829 | |
| 830 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
| 831 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
| 832 | /* clear GMAC 1 Control reset */ |
| 833 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); |
| 834 | do { |
| 835 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); |
| 836 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); |
| 837 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || |
| 838 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || |
| 839 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); |
| 840 | } |
| 841 | |
| 842 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
| 843 | |
| 844 | /* Enable Transmit FIFO Underrun */ |
| 845 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
| 846 | |
| 847 | spin_lock_bh(&sky2->phy_lock); |
| 848 | sky2_phy_power_up(hw, port); |
| 849 | sky2_phy_init(hw, port); |
| 850 | spin_unlock_bh(&sky2->phy_lock); |
| 851 | |
| 852 | /* MIB clear */ |
| 853 | reg = gma_read16(hw, port, GM_PHY_ADDR); |
| 854 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); |
| 855 | |
| 856 | for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) |
| 857 | gma_read16(hw, port, i); |
| 858 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
| 859 | |
| 860 | /* transmit control */ |
| 861 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); |
| 862 | |
| 863 | /* receive control reg: unicast + multicast + no FCS */ |
| 864 | gma_write16(hw, port, GM_RX_CTRL, |
| 865 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
| 866 | |
| 867 | /* transmit flow control */ |
| 868 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); |
| 869 | |
| 870 | /* transmit parameter */ |
| 871 | gma_write16(hw, port, GM_TX_PARAM, |
| 872 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | |
| 873 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | |
| 874 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | |
| 875 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); |
| 876 | |
| 877 | /* serial mode register */ |
| 878 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
| 879 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
| 880 | |
| 881 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
| 882 | reg |= GM_SMOD_JUMBO_ENA; |
| 883 | |
| 884 | gma_write16(hw, port, GM_SERIAL_MODE, reg); |
| 885 | |
| 886 | /* virtual address for data */ |
| 887 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); |
| 888 | |
| 889 | /* physical address: used for pause frames */ |
| 890 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); |
| 891 | |
| 892 | /* ignore counter overflows */ |
| 893 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
| 894 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); |
| 895 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); |
| 896 | |
| 897 | /* Configure Rx MAC FIFO */ |
| 898 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); |
| 899 | rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; |
| 900 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
| 901 | hw->chip_id == CHIP_ID_YUKON_FE_P) |
| 902 | rx_reg |= GMF_RX_OVER_ON; |
| 903 | |
| 904 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); |
| 905 | |
| 906 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
| 907 | /* Hardware errata - clear flush mask */ |
| 908 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); |
| 909 | } else { |
| 910 | /* Flush Rx MAC FIFO on any flow control or error */ |
| 911 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
| 912 | } |
| 913 | |
| 914 | /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ |
| 915 | reg = RX_GMF_FL_THR_DEF + 1; |
| 916 | /* Another magic mystery workaround from sk98lin */ |
| 917 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
| 918 | hw->chip_rev == CHIP_REV_YU_FE2_A0) |
| 919 | reg = 0x178; |
| 920 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); |
| 921 | |
| 922 | /* Configure Tx MAC FIFO */ |
| 923 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); |
| 924 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); |
| 925 | |
| 926 | /* On chips without ram buffer, pause is controled by MAC level */ |
| 927 | if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { |
| 928 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); |
| 929 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); |
| 930 | |
| 931 | sky2_set_tx_stfwd(hw, port); |
| 932 | } |
| 933 | |
| 934 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
| 935 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { |
| 936 | /* disable dynamic watermark */ |
| 937 | reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); |
| 938 | reg &= ~TX_DYN_WM_ENA; |
| 939 | sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); |
| 940 | } |
| 941 | } |
| 942 | |
| 943 | /* Assign Ram Buffer allocation to queue */ |
| 944 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) |
| 945 | { |
| 946 | u32 end; |
| 947 | |
| 948 | /* convert from K bytes to qwords used for hw register */ |
| 949 | start *= 1024/8; |
| 950 | space *= 1024/8; |
| 951 | end = start + space - 1; |
| 952 | |
| 953 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
| 954 | sky2_write32(hw, RB_ADDR(q, RB_START), start); |
| 955 | sky2_write32(hw, RB_ADDR(q, RB_END), end); |
| 956 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); |
| 957 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); |
| 958 | |
| 959 | if (q == Q_R1 || q == Q_R2) { |
| 960 | u32 tp = space - space/4; |
| 961 | |
| 962 | /* On receive queue's set the thresholds |
| 963 | * give receiver priority when > 3/4 full |
| 964 | * send pause when down to 2K |
| 965 | */ |
| 966 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); |
| 967 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); |
| 968 | |
| 969 | tp = space - 2048/8; |
| 970 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); |
| 971 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); |
| 972 | } else { |
| 973 | /* Enable store & forward on Tx queue's because |
| 974 | * Tx FIFO is only 1K on Yukon |
| 975 | */ |
| 976 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); |
| 977 | } |
| 978 | |
| 979 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); |
| 980 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
| 981 | } |
| 982 | |
| 983 | /* Setup Bus Memory Interface */ |
| 984 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
| 985 | { |
| 986 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); |
| 987 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); |
| 988 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); |
| 989 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
| 990 | } |
| 991 | |
| 992 | /* Setup prefetch unit registers. This is the interface between |
| 993 | * hardware and driver list elements |
| 994 | */ |
| 995 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
| 996 | dma_addr_t addr, u32 last) |
| 997 | { |
| 998 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
| 999 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); |
| 1000 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); |
| 1001 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); |
| 1002 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); |
| 1003 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); |
| 1004 | |
| 1005 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); |
| 1006 | } |
| 1007 | |
| 1008 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) |
| 1009 | { |
| 1010 | struct sky2_tx_le *le = sky2->tx_le + *slot; |
| 1011 | struct tx_ring_info *re = sky2->tx_ring + *slot; |
| 1012 | |
| 1013 | *slot = RING_NEXT(*slot, sky2->tx_ring_size); |
| 1014 | re->flags = 0; |
| 1015 | re->skb = NULL; |
| 1016 | le->ctrl = 0; |
| 1017 | return le; |
| 1018 | } |
| 1019 | |
| 1020 | static void tx_init(struct sky2_port *sky2) |
| 1021 | { |
| 1022 | struct sky2_tx_le *le; |
| 1023 | |
| 1024 | sky2->tx_prod = sky2->tx_cons = 0; |
| 1025 | sky2->tx_tcpsum = 0; |
| 1026 | sky2->tx_last_mss = 0; |
| 1027 | |
| 1028 | le = get_tx_le(sky2, &sky2->tx_prod); |
| 1029 | le->addr = 0; |
| 1030 | le->opcode = OP_ADDR64 | HW_OWNER; |
| 1031 | sky2->tx_last_upper = 0; |
| 1032 | } |
| 1033 | |
| 1034 | /* Update chip's next pointer */ |
| 1035 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) |
| 1036 | { |
| 1037 | /* Make sure write' to descriptors are complete before we tell hardware */ |
| 1038 | wmb(); |
| 1039 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
| 1040 | |
| 1041 | /* Synchronize I/O on since next processor may write to tail */ |
| 1042 | mmiowb(); |
| 1043 | } |
| 1044 | |
| 1045 | |
| 1046 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
| 1047 | { |
| 1048 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; |
| 1049 | sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); |
| 1050 | le->ctrl = 0; |
| 1051 | return le; |
| 1052 | } |
| 1053 | |
| 1054 | /* Build description to hardware for one receive segment */ |
| 1055 | static void sky2_rx_add(struct sky2_port *sky2, u8 op, |
| 1056 | dma_addr_t map, unsigned len) |
| 1057 | { |
| 1058 | struct sky2_rx_le *le; |
| 1059 | |
| 1060 | if (sizeof(dma_addr_t) > sizeof(u32)) { |
| 1061 | le = sky2_next_rx(sky2); |
| 1062 | le->addr = cpu_to_le32(upper_32_bits(map)); |
| 1063 | le->opcode = OP_ADDR64 | HW_OWNER; |
| 1064 | } |
| 1065 | |
| 1066 | le = sky2_next_rx(sky2); |
| 1067 | le->addr = cpu_to_le32(lower_32_bits(map)); |
| 1068 | le->length = cpu_to_le16(len); |
| 1069 | le->opcode = op | HW_OWNER; |
| 1070 | } |
| 1071 | |
| 1072 | /* Build description to hardware for one possibly fragmented skb */ |
| 1073 | static void sky2_rx_submit(struct sky2_port *sky2, |
| 1074 | const struct rx_ring_info *re) |
| 1075 | { |
| 1076 | int i; |
| 1077 | |
| 1078 | sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); |
| 1079 | |
| 1080 | for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) |
| 1081 | sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); |
| 1082 | } |
| 1083 | |
| 1084 | |
| 1085 | static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, |
| 1086 | unsigned size) |
| 1087 | { |
| 1088 | struct sk_buff *skb = re->skb; |
| 1089 | int i; |
| 1090 | |
| 1091 | re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); |
| 1092 | if (unlikely(pci_dma_mapping_error(pdev, re->data_addr))) |
| 1093 | return -EIO; |
| 1094 | |
| 1095 | pci_unmap_len_set(re, data_size, size); |
| 1096 | |
| 1097 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) |
| 1098 | re->frag_addr[i] = pci_map_page(pdev, |
| 1099 | skb_shinfo(skb)->frags[i].page, |
| 1100 | skb_shinfo(skb)->frags[i].page_offset, |
| 1101 | skb_shinfo(skb)->frags[i].size, |
| 1102 | PCI_DMA_FROMDEVICE); |
| 1103 | return 0; |
| 1104 | } |
| 1105 | |
| 1106 | static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) |
| 1107 | { |
| 1108 | struct sk_buff *skb = re->skb; |
| 1109 | int i; |
| 1110 | |
| 1111 | pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size), |
| 1112 | PCI_DMA_FROMDEVICE); |
| 1113 | |
| 1114 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) |
| 1115 | pci_unmap_page(pdev, re->frag_addr[i], |
| 1116 | skb_shinfo(skb)->frags[i].size, |
| 1117 | PCI_DMA_FROMDEVICE); |
| 1118 | } |
| 1119 | |
| 1120 | /* Tell chip where to start receive checksum. |
| 1121 | * Actually has two checksums, but set both same to avoid possible byte |
| 1122 | * order problems. |
| 1123 | */ |
| 1124 | static void rx_set_checksum(struct sky2_port *sky2) |
| 1125 | { |
| 1126 | struct sky2_rx_le *le = sky2_next_rx(sky2); |
| 1127 | |
| 1128 | le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); |
| 1129 | le->ctrl = 0; |
| 1130 | le->opcode = OP_TCPSTART | HW_OWNER; |
| 1131 | |
| 1132 | sky2_write32(sky2->hw, |
| 1133 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
| 1134 | (sky2->flags & SKY2_FLAG_RX_CHECKSUM) |
| 1135 | ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); |
| 1136 | } |
| 1137 | |
| 1138 | /* |
| 1139 | * The RX Stop command will not work for Yukon-2 if the BMU does not |
| 1140 | * reach the end of packet and since we can't make sure that we have |
| 1141 | * incoming data, we must reset the BMU while it is not doing a DMA |
| 1142 | * transfer. Since it is possible that the RX path is still active, |
| 1143 | * the RX RAM buffer will be stopped first, so any possible incoming |
| 1144 | * data will not trigger a DMA. After the RAM buffer is stopped, the |
| 1145 | * BMU is polled until any DMA in progress is ended and only then it |
| 1146 | * will be reset. |
| 1147 | */ |
| 1148 | static void sky2_rx_stop(struct sky2_port *sky2) |
| 1149 | { |
| 1150 | struct sky2_hw *hw = sky2->hw; |
| 1151 | unsigned rxq = rxqaddr[sky2->port]; |
| 1152 | int i; |
| 1153 | |
| 1154 | /* disable the RAM Buffer receive queue */ |
| 1155 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); |
| 1156 | |
| 1157 | for (i = 0; i < 0xffff; i++) |
| 1158 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) |
| 1159 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) |
| 1160 | goto stopped; |
| 1161 | |
| 1162 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", |
| 1163 | sky2->netdev->name); |
| 1164 | stopped: |
| 1165 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); |
| 1166 | |
| 1167 | /* reset the Rx prefetch unit */ |
| 1168 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
| 1169 | mmiowb(); |
| 1170 | } |
| 1171 | |
| 1172 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
| 1173 | static void sky2_rx_clean(struct sky2_port *sky2) |
| 1174 | { |
| 1175 | unsigned i; |
| 1176 | |
| 1177 | memset(sky2->rx_le, 0, RX_LE_BYTES); |
| 1178 | for (i = 0; i < sky2->rx_pending; i++) { |
| 1179 | struct rx_ring_info *re = sky2->rx_ring + i; |
| 1180 | |
| 1181 | if (re->skb) { |
| 1182 | sky2_rx_unmap_skb(sky2->hw->pdev, re); |
| 1183 | kfree_skb(re->skb); |
| 1184 | re->skb = NULL; |
| 1185 | } |
| 1186 | } |
| 1187 | } |
| 1188 | |
| 1189 | /* Basic MII support */ |
| 1190 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 1191 | { |
| 1192 | struct mii_ioctl_data *data = if_mii(ifr); |
| 1193 | struct sky2_port *sky2 = netdev_priv(dev); |
| 1194 | struct sky2_hw *hw = sky2->hw; |
| 1195 | int err = -EOPNOTSUPP; |
| 1196 | |
| 1197 | if (!netif_running(dev)) |
| 1198 | return -ENODEV; /* Phy still in reset */ |
| 1199 | |
| 1200 | switch (cmd) { |
| 1201 | case SIOCGMIIPHY: |
| 1202 | data->phy_id = PHY_ADDR_MARV; |
| 1203 | |
| 1204 | /* fallthru */ |
| 1205 | case SIOCGMIIREG: { |
| 1206 | u16 val = 0; |
| 1207 | |
| 1208 | spin_lock_bh(&sky2->phy_lock); |
| 1209 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
| 1210 | spin_unlock_bh(&sky2->phy_lock); |
| 1211 | |
| 1212 | data->val_out = val; |
| 1213 | break; |
| 1214 | } |
| 1215 | |
| 1216 | case SIOCSMIIREG: |
| 1217 | spin_lock_bh(&sky2->phy_lock); |
| 1218 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
| 1219 | data->val_in); |
| 1220 | spin_unlock_bh(&sky2->phy_lock); |
| 1221 | break; |
| 1222 | } |
| 1223 | return err; |
| 1224 | } |
| 1225 | |
| 1226 | #ifdef SKY2_VLAN_TAG_USED |
| 1227 | static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff) |
| 1228 | { |
| 1229 | if (onoff) { |
| 1230 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), |
| 1231 | RX_VLAN_STRIP_ON); |
| 1232 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
| 1233 | TX_VLAN_TAG_ON); |
| 1234 | } else { |
| 1235 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), |
| 1236 | RX_VLAN_STRIP_OFF); |
| 1237 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
| 1238 | TX_VLAN_TAG_OFF); |
| 1239 | } |
| 1240 | } |
| 1241 | |
| 1242 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
| 1243 | { |
| 1244 | struct sky2_port *sky2 = netdev_priv(dev); |
| 1245 | struct sky2_hw *hw = sky2->hw; |
| 1246 | u16 port = sky2->port; |
| 1247 | |
| 1248 | netif_tx_lock_bh(dev); |
| 1249 | napi_disable(&hw->napi); |
| 1250 | |
| 1251 | sky2->vlgrp = grp; |
| 1252 | sky2_set_vlan_mode(hw, port, grp != NULL); |
| 1253 | |
| 1254 | sky2_read32(hw, B0_Y2_SP_LISR); |
| 1255 | napi_enable(&hw->napi); |
| 1256 | netif_tx_unlock_bh(dev); |
| 1257 | } |
| 1258 | #endif |
| 1259 | |
| 1260 | /* Amount of required worst case padding in rx buffer */ |
| 1261 | static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) |
| 1262 | { |
| 1263 | return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; |
| 1264 | } |
| 1265 | |
| 1266 | /* |
| 1267 | * Allocate an skb for receiving. If the MTU is large enough |
| 1268 | * make the skb non-linear with a fragment list of pages. |
| 1269 | */ |
| 1270 | static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2) |
| 1271 | { |
| 1272 | struct sk_buff *skb; |
| 1273 | int i; |
| 1274 | |
| 1275 | skb = netdev_alloc_skb(sky2->netdev, |
| 1276 | sky2->rx_data_size + sky2_rx_pad(sky2->hw)); |
| 1277 | if (!skb) |
| 1278 | goto nomem; |
| 1279 | |
| 1280 | if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { |
| 1281 | unsigned char *start; |
| 1282 | /* |
| 1283 | * Workaround for a bug in FIFO that cause hang |
| 1284 | * if the FIFO if the receive buffer is not 64 byte aligned. |
| 1285 | * The buffer returned from netdev_alloc_skb is |
| 1286 | * aligned except if slab debugging is enabled. |
| 1287 | */ |
| 1288 | start = PTR_ALIGN(skb->data, 8); |
| 1289 | skb_reserve(skb, start - skb->data); |
| 1290 | } else |
| 1291 | skb_reserve(skb, NET_IP_ALIGN); |
| 1292 | |
| 1293 | for (i = 0; i < sky2->rx_nfrags; i++) { |
| 1294 | struct page *page = alloc_page(GFP_ATOMIC); |
| 1295 | |
| 1296 | if (!page) |
| 1297 | goto free_partial; |
| 1298 | skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); |
| 1299 | } |
| 1300 | |
| 1301 | return skb; |
| 1302 | free_partial: |
| 1303 | kfree_skb(skb); |
| 1304 | nomem: |
| 1305 | return NULL; |
| 1306 | } |
| 1307 | |
| 1308 | static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) |
| 1309 | { |
| 1310 | sky2_put_idx(sky2->hw, rxq, sky2->rx_put); |
| 1311 | } |
| 1312 | |
| 1313 | /* |
| 1314 | * Allocate and setup receiver buffer pool. |
| 1315 | * Normal case this ends up creating one list element for skb |
| 1316 | * in the receive ring. Worst case if using large MTU and each |
| 1317 | * allocation falls on a different 64 bit region, that results |
| 1318 | * in 6 list elements per ring entry. |
| 1319 | * One element is used for checksum enable/disable, and one |
| 1320 | * extra to avoid wrap. |
| 1321 | */ |
| 1322 | static int sky2_rx_start(struct sky2_port *sky2) |
| 1323 | { |
| 1324 | struct sky2_hw *hw = sky2->hw; |
| 1325 | struct rx_ring_info *re; |
| 1326 | unsigned rxq = rxqaddr[sky2->port]; |
| 1327 | unsigned i, size, thresh; |
| 1328 | |
| 1329 | sky2->rx_put = sky2->rx_next = 0; |
| 1330 | sky2_qset(hw, rxq); |
| 1331 | |
| 1332 | /* On PCI express lowering the watermark gives better performance */ |
| 1333 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) |
| 1334 | sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); |
| 1335 | |
| 1336 | /* These chips have no ram buffer? |
| 1337 | * MAC Rx RAM Read is controlled by hardware */ |
| 1338 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
| 1339 | (hw->chip_rev == CHIP_REV_YU_EC_U_A1 |
| 1340 | || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) |
| 1341 | sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); |
| 1342 | |
| 1343 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
| 1344 | |
| 1345 | if (!(hw->flags & SKY2_HW_NEW_LE)) |
| 1346 | rx_set_checksum(sky2); |
| 1347 | |
| 1348 | /* Space needed for frame data + headers rounded up */ |
| 1349 | size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); |
| 1350 | |
| 1351 | /* Stopping point for hardware truncation */ |
| 1352 | thresh = (size - 8) / sizeof(u32); |
| 1353 | |
| 1354 | sky2->rx_nfrags = size >> PAGE_SHIFT; |
| 1355 | BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); |
| 1356 | |
| 1357 | /* Compute residue after pages */ |
| 1358 | size -= sky2->rx_nfrags << PAGE_SHIFT; |
| 1359 | |
| 1360 | /* Optimize to handle small packets and headers */ |
| 1361 | if (size < copybreak) |
| 1362 | size = copybreak; |
| 1363 | if (size < ETH_HLEN) |
| 1364 | size = ETH_HLEN; |
| 1365 | |
| 1366 | sky2->rx_data_size = size; |
| 1367 | |
| 1368 | /* Fill Rx ring */ |
| 1369 | for (i = 0; i < sky2->rx_pending; i++) { |
| 1370 | re = sky2->rx_ring + i; |
| 1371 | |
| 1372 | re->skb = sky2_rx_alloc(sky2); |
| 1373 | if (!re->skb) |
| 1374 | goto nomem; |
| 1375 | |
| 1376 | if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { |
| 1377 | dev_kfree_skb(re->skb); |
| 1378 | re->skb = NULL; |
| 1379 | goto nomem; |
| 1380 | } |
| 1381 | |
| 1382 | sky2_rx_submit(sky2, re); |
| 1383 | } |
| 1384 | |
| 1385 | /* |
| 1386 | * The receiver hangs if it receives frames larger than the |
| 1387 | * packet buffer. As a workaround, truncate oversize frames, but |
| 1388 | * the register is limited to 9 bits, so if you do frames > 2052 |
| 1389 | * you better get the MTU right! |
| 1390 | */ |
| 1391 | if (thresh > 0x1ff) |
| 1392 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); |
| 1393 | else { |
| 1394 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); |
| 1395 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); |
| 1396 | } |
| 1397 | |
| 1398 | /* Tell chip about available buffers */ |
| 1399 | sky2_rx_update(sky2, rxq); |
| 1400 | return 0; |
| 1401 | nomem: |
| 1402 | sky2_rx_clean(sky2); |
| 1403 | return -ENOMEM; |
| 1404 | } |
| 1405 | |
| 1406 | static int sky2_alloc_buffers(struct sky2_port *sky2) |
| 1407 | { |
| 1408 | struct sky2_hw *hw = sky2->hw; |
| 1409 | |
| 1410 | /* must be power of 2 */ |
| 1411 | sky2->tx_le = pci_alloc_consistent(hw->pdev, |
| 1412 | sky2->tx_ring_size * |
| 1413 | sizeof(struct sky2_tx_le), |
| 1414 | &sky2->tx_le_map); |
| 1415 | if (!sky2->tx_le) |
| 1416 | goto nomem; |
| 1417 | |
| 1418 | sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), |
| 1419 | GFP_KERNEL); |
| 1420 | if (!sky2->tx_ring) |
| 1421 | goto nomem; |
| 1422 | |
| 1423 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, |
| 1424 | &sky2->rx_le_map); |
| 1425 | if (!sky2->rx_le) |
| 1426 | goto nomem; |
| 1427 | memset(sky2->rx_le, 0, RX_LE_BYTES); |
| 1428 | |
| 1429 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), |
| 1430 | GFP_KERNEL); |
| 1431 | if (!sky2->rx_ring) |
| 1432 | goto nomem; |
| 1433 | |
| 1434 | return 0; |
| 1435 | nomem: |
| 1436 | return -ENOMEM; |
| 1437 | } |
| 1438 | |
| 1439 | static void sky2_free_buffers(struct sky2_port *sky2) |
| 1440 | { |
| 1441 | struct sky2_hw *hw = sky2->hw; |
| 1442 | |
| 1443 | if (sky2->rx_le) { |
| 1444 | pci_free_consistent(hw->pdev, RX_LE_BYTES, |
| 1445 | sky2->rx_le, sky2->rx_le_map); |
| 1446 | sky2->rx_le = NULL; |
| 1447 | } |
| 1448 | if (sky2->tx_le) { |
| 1449 | pci_free_consistent(hw->pdev, |
| 1450 | sky2->tx_ring_size * sizeof(struct sky2_tx_le), |
| 1451 | sky2->tx_le, sky2->tx_le_map); |
| 1452 | sky2->tx_le = NULL; |
| 1453 | } |
| 1454 | kfree(sky2->tx_ring); |
| 1455 | kfree(sky2->rx_ring); |
| 1456 | |
| 1457 | sky2->tx_ring = NULL; |
| 1458 | sky2->rx_ring = NULL; |
| 1459 | } |
| 1460 | |
| 1461 | /* Bring up network interface. */ |
| 1462 | static int sky2_up(struct net_device *dev) |
| 1463 | { |
| 1464 | struct sky2_port *sky2 = netdev_priv(dev); |
| 1465 | struct sky2_hw *hw = sky2->hw; |
| 1466 | unsigned port = sky2->port; |
| 1467 | u32 imask, ramsize; |
| 1468 | int cap, err; |
| 1469 | struct net_device *otherdev = hw->dev[sky2->port^1]; |
| 1470 | |
| 1471 | /* |
| 1472 | * On dual port PCI-X card, there is an problem where status |
| 1473 | * can be received out of order due to split transactions |
| 1474 | */ |
| 1475 | if (otherdev && netif_running(otherdev) && |
| 1476 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { |
| 1477 | u16 cmd; |
| 1478 | |
| 1479 | cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); |
| 1480 | cmd &= ~PCI_X_CMD_MAX_SPLIT; |
| 1481 | sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); |
| 1482 | |
| 1483 | } |
| 1484 | |
| 1485 | netif_carrier_off(dev); |
| 1486 | |
| 1487 | err = sky2_alloc_buffers(sky2); |
| 1488 | if (err) |
| 1489 | goto err_out; |
| 1490 | |
| 1491 | tx_init(sky2); |
| 1492 | |
| 1493 | sky2_mac_init(hw, port); |
| 1494 | |
| 1495 | /* Register is number of 4K blocks on internal RAM buffer. */ |
| 1496 | ramsize = sky2_read8(hw, B2_E_0) * 4; |
| 1497 | if (ramsize > 0) { |
| 1498 | u32 rxspace; |
| 1499 | |
| 1500 | hw->flags |= SKY2_HW_RAM_BUFFER; |
| 1501 | pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize); |
| 1502 | if (ramsize < 16) |
| 1503 | rxspace = ramsize / 2; |
| 1504 | else |
| 1505 | rxspace = 8 + (2*(ramsize - 16))/3; |
| 1506 | |
| 1507 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
| 1508 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); |
| 1509 | |
| 1510 | /* Make sure SyncQ is disabled */ |
| 1511 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), |
| 1512 | RB_RST_SET); |
| 1513 | } |
| 1514 | |
| 1515 | sky2_qset(hw, txqaddr[port]); |
| 1516 | |
| 1517 | /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ |
| 1518 | if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) |
| 1519 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); |
| 1520 | |
| 1521 | /* Set almost empty threshold */ |
| 1522 | if (hw->chip_id == CHIP_ID_YUKON_EC_U |
| 1523 | && hw->chip_rev == CHIP_REV_YU_EC_U_A0) |
| 1524 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); |
| 1525 | |
| 1526 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
| 1527 | sky2->tx_ring_size - 1); |
| 1528 | |
| 1529 | #ifdef SKY2_VLAN_TAG_USED |
| 1530 | sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL); |
| 1531 | #endif |
| 1532 | |
| 1533 | err = sky2_rx_start(sky2); |
| 1534 | if (err) |
| 1535 | goto err_out; |
| 1536 | |
| 1537 | /* Enable interrupts from phy/mac for port */ |
| 1538 | imask = sky2_read32(hw, B0_IMSK); |
| 1539 | imask |= portirq_msk[port]; |
| 1540 | sky2_write32(hw, B0_IMSK, imask); |
| 1541 | sky2_read32(hw, B0_IMSK); |
| 1542 | |
| 1543 | if (netif_msg_ifup(sky2)) |
| 1544 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); |
| 1545 | |
| 1546 | return 0; |
| 1547 | |
| 1548 | err_out: |
| 1549 | sky2_free_buffers(sky2); |
| 1550 | return err; |
| 1551 | } |
| 1552 | |
| 1553 | /* Modular subtraction in ring */ |
| 1554 | static inline int tx_inuse(const struct sky2_port *sky2) |
| 1555 | { |
| 1556 | return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); |
| 1557 | } |
| 1558 | |
| 1559 | /* Number of list elements available for next tx */ |
| 1560 | static inline int tx_avail(const struct sky2_port *sky2) |
| 1561 | { |
| 1562 | return sky2->tx_pending - tx_inuse(sky2); |
| 1563 | } |
| 1564 | |
| 1565 | /* Estimate of number of transmit list elements required */ |
| 1566 | static unsigned tx_le_req(const struct sk_buff *skb) |
| 1567 | { |
| 1568 | unsigned count; |
| 1569 | |
| 1570 | count = sizeof(dma_addr_t) / sizeof(u32); |
| 1571 | count += skb_shinfo(skb)->nr_frags * count; |
| 1572 | |
| 1573 | if (skb_is_gso(skb)) |
| 1574 | ++count; |
| 1575 | |
| 1576 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
| 1577 | ++count; |
| 1578 | |
| 1579 | return count; |
| 1580 | } |
| 1581 | |
| 1582 | static void sky2_tx_unmap(struct pci_dev *pdev, |
| 1583 | const struct tx_ring_info *re) |
| 1584 | { |
| 1585 | if (re->flags & TX_MAP_SINGLE) |
| 1586 | pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), |
| 1587 | pci_unmap_len(re, maplen), |
| 1588 | PCI_DMA_TODEVICE); |
| 1589 | else if (re->flags & TX_MAP_PAGE) |
| 1590 | pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr), |
| 1591 | pci_unmap_len(re, maplen), |
| 1592 | PCI_DMA_TODEVICE); |
| 1593 | } |
| 1594 | |
| 1595 | /* |
| 1596 | * Put one packet in ring for transmit. |
| 1597 | * A single packet can generate multiple list elements, and |
| 1598 | * the number of ring elements will probably be less than the number |
| 1599 | * of list elements used. |
| 1600 | */ |
| 1601 | static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, |
| 1602 | struct net_device *dev) |
| 1603 | { |
| 1604 | struct sky2_port *sky2 = netdev_priv(dev); |
| 1605 | struct sky2_hw *hw = sky2->hw; |
| 1606 | struct sky2_tx_le *le = NULL; |
| 1607 | struct tx_ring_info *re; |
| 1608 | unsigned i, len; |
| 1609 | dma_addr_t mapping; |
| 1610 | u32 upper; |
| 1611 | u16 slot; |
| 1612 | u16 mss; |
| 1613 | u8 ctrl; |
| 1614 | |
| 1615 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) |
| 1616 | return NETDEV_TX_BUSY; |
| 1617 | |
| 1618 | len = skb_headlen(skb); |
| 1619 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); |
| 1620 | |
| 1621 | if (pci_dma_mapping_error(hw->pdev, mapping)) |
| 1622 | goto mapping_error; |
| 1623 | |
| 1624 | slot = sky2->tx_prod; |
| 1625 | if (unlikely(netif_msg_tx_queued(sky2))) |
| 1626 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
| 1627 | dev->name, slot, skb->len); |
| 1628 | |
| 1629 | /* Send high bits if needed */ |
| 1630 | upper = upper_32_bits(mapping); |
| 1631 | if (upper != sky2->tx_last_upper) { |
| 1632 | le = get_tx_le(sky2, &slot); |
| 1633 | le->addr = cpu_to_le32(upper); |
| 1634 | sky2->tx_last_upper = upper; |
| 1635 | le->opcode = OP_ADDR64 | HW_OWNER; |
| 1636 | } |
| 1637 | |
| 1638 | /* Check for TCP Segmentation Offload */ |
| 1639 | mss = skb_shinfo(skb)->gso_size; |
| 1640 | if (mss != 0) { |
| 1641 | |
| 1642 | if (!(hw->flags & SKY2_HW_NEW_LE)) |
| 1643 | mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); |
| 1644 | |
| 1645 | if (mss != sky2->tx_last_mss) { |
| 1646 | le = get_tx_le(sky2, &slot); |
| 1647 | le->addr = cpu_to_le32(mss); |
| 1648 | |
| 1649 | if (hw->flags & SKY2_HW_NEW_LE) |
| 1650 | le->opcode = OP_MSS | HW_OWNER; |
| 1651 | else |
| 1652 | le->opcode = OP_LRGLEN | HW_OWNER; |
| 1653 | sky2->tx_last_mss = mss; |
| 1654 | } |
| 1655 | } |
| 1656 | |
| 1657 | ctrl = 0; |
| 1658 | #ifdef SKY2_VLAN_TAG_USED |
| 1659 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ |
| 1660 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { |
| 1661 | if (!le) { |
| 1662 | le = get_tx_le(sky2, &slot); |
| 1663 | le->addr = 0; |
| 1664 | le->opcode = OP_VLAN|HW_OWNER; |
| 1665 | } else |
| 1666 | le->opcode |= OP_VLAN; |
| 1667 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); |
| 1668 | ctrl |= INS_VLAN; |
| 1669 | } |
| 1670 | #endif |
| 1671 | |
| 1672 | /* Handle TCP checksum offload */ |
| 1673 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
| 1674 | /* On Yukon EX (some versions) encoding change. */ |
| 1675 | if (hw->flags & SKY2_HW_AUTO_TX_SUM) |
| 1676 | ctrl |= CALSUM; /* auto checksum */ |
| 1677 | else { |
| 1678 | const unsigned offset = skb_transport_offset(skb); |
| 1679 | u32 tcpsum; |
| 1680 | |
| 1681 | tcpsum = offset << 16; /* sum start */ |
| 1682 | tcpsum |= offset + skb->csum_offset; /* sum write */ |
| 1683 | |
| 1684 | ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; |
| 1685 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) |
| 1686 | ctrl |= UDPTCP; |
| 1687 | |
| 1688 | if (tcpsum != sky2->tx_tcpsum) { |
| 1689 | sky2->tx_tcpsum = tcpsum; |
| 1690 | |
| 1691 | le = get_tx_le(sky2, &slot); |
| 1692 | le->addr = cpu_to_le32(tcpsum); |
| 1693 | le->length = 0; /* initial checksum value */ |
| 1694 | le->ctrl = 1; /* one packet */ |
| 1695 | le->opcode = OP_TCPLISW | HW_OWNER; |
| 1696 | } |
| 1697 | } |
| 1698 | } |
| 1699 | |
| 1700 | re = sky2->tx_ring + slot; |
| 1701 | re->flags = TX_MAP_SINGLE; |
| 1702 | pci_unmap_addr_set(re, mapaddr, mapping); |
| 1703 | pci_unmap_len_set(re, maplen, len); |
| 1704 | |
| 1705 | le = get_tx_le(sky2, &slot); |
| 1706 | le->addr = cpu_to_le32(lower_32_bits(mapping)); |
| 1707 | le->length = cpu_to_le16(len); |
| 1708 | le->ctrl = ctrl; |
| 1709 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
| 1710 | |
| 1711 | |
| 1712 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
| 1713 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 1714 | |
| 1715 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, |
| 1716 | frag->size, PCI_DMA_TODEVICE); |
| 1717 | |
| 1718 | if (pci_dma_mapping_error(hw->pdev, mapping)) |
| 1719 | goto mapping_unwind; |
| 1720 | |
| 1721 | upper = upper_32_bits(mapping); |
| 1722 | if (upper != sky2->tx_last_upper) { |
| 1723 | le = get_tx_le(sky2, &slot); |
| 1724 | le->addr = cpu_to_le32(upper); |
| 1725 | sky2->tx_last_upper = upper; |
| 1726 | le->opcode = OP_ADDR64 | HW_OWNER; |
| 1727 | } |
| 1728 | |
| 1729 | re = sky2->tx_ring + slot; |
| 1730 | re->flags = TX_MAP_PAGE; |
| 1731 | pci_unmap_addr_set(re, mapaddr, mapping); |
| 1732 | pci_unmap_len_set(re, maplen, frag->size); |
| 1733 | |
| 1734 | le = get_tx_le(sky2, &slot); |
| 1735 | le->addr = cpu_to_le32(lower_32_bits(mapping)); |
| 1736 | le->length = cpu_to_le16(frag->size); |
| 1737 | le->ctrl = ctrl; |
| 1738 | le->opcode = OP_BUFFER | HW_OWNER; |
| 1739 | } |
| 1740 | |
| 1741 | re->skb = skb; |
| 1742 | le->ctrl |= EOP; |
| 1743 | |
| 1744 | sky2->tx_prod = slot; |
| 1745 | |
| 1746 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
| 1747 | netif_stop_queue(dev); |
| 1748 | |
| 1749 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); |
| 1750 | |
| 1751 | return NETDEV_TX_OK; |
| 1752 | |
| 1753 | mapping_unwind: |
| 1754 | for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { |
| 1755 | re = sky2->tx_ring + i; |
| 1756 | |
| 1757 | sky2_tx_unmap(hw->pdev, re); |
| 1758 | } |
| 1759 | |
| 1760 | mapping_error: |
| 1761 | if (net_ratelimit()) |
| 1762 | dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); |
| 1763 | dev_kfree_skb(skb); |
| 1764 | return NETDEV_TX_OK; |
| 1765 | } |
| 1766 | |
| 1767 | /* |
| 1768 | * Free ring elements from starting at tx_cons until "done" |
| 1769 | * |
| 1770 | * NB: |
| 1771 | * 1. The hardware will tell us about partial completion of multi-part |
| 1772 | * buffers so make sure not to free skb to early. |
| 1773 | * 2. This may run in parallel start_xmit because the it only |
| 1774 | * looks at the tail of the queue of FIFO (tx_cons), not |
| 1775 | * the head (tx_prod) |
| 1776 | */ |
| 1777 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
| 1778 | { |
| 1779 | struct net_device *dev = sky2->netdev; |
| 1780 | unsigned idx; |
| 1781 | |
| 1782 | BUG_ON(done >= sky2->tx_ring_size); |
| 1783 | |
| 1784 | for (idx = sky2->tx_cons; idx != done; |
| 1785 | idx = RING_NEXT(idx, sky2->tx_ring_size)) { |
| 1786 | struct tx_ring_info *re = sky2->tx_ring + idx; |
| 1787 | struct sk_buff *skb = re->skb; |
| 1788 | |
| 1789 | sky2_tx_unmap(sky2->hw->pdev, re); |
| 1790 | |
| 1791 | if (skb) { |
| 1792 | if (unlikely(netif_msg_tx_done(sky2))) |
| 1793 | printk(KERN_DEBUG "%s: tx done %u\n", |
| 1794 | dev->name, idx); |
| 1795 | |
| 1796 | dev->stats.tx_packets++; |
| 1797 | dev->stats.tx_bytes += skb->len; |
| 1798 | |
| 1799 | dev_kfree_skb_any(skb); |
| 1800 | |
| 1801 | sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); |
| 1802 | } |
| 1803 | } |
| 1804 | |
| 1805 | sky2->tx_cons = idx; |
| 1806 | smp_mb(); |
| 1807 | |
| 1808 | if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) |
| 1809 | netif_wake_queue(dev); |
| 1810 | } |
| 1811 | |
| 1812 | static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) |
| 1813 | { |
| 1814 | /* Disable Force Sync bit and Enable Alloc bit */ |
| 1815 | sky2_write8(hw, SK_REG(port, TXA_CTRL), |
| 1816 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); |
| 1817 | |
| 1818 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ |
| 1819 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); |
| 1820 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); |
| 1821 | |
| 1822 | /* Reset the PCI FIFO of the async Tx queue */ |
| 1823 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
| 1824 | BMU_RST_SET | BMU_FIFO_RST); |
| 1825 | |
| 1826 | /* Reset the Tx prefetch units */ |
| 1827 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), |
| 1828 | PREF_UNIT_RST_SET); |
| 1829 | |
| 1830 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); |
| 1831 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); |
| 1832 | } |
| 1833 | |
| 1834 | /* Network shutdown */ |
| 1835 | static int sky2_down(struct net_device *dev) |
| 1836 | { |
| 1837 | struct sky2_port *sky2 = netdev_priv(dev); |
| 1838 | struct sky2_hw *hw = sky2->hw; |
| 1839 | unsigned port = sky2->port; |
| 1840 | u16 ctrl; |
| 1841 | u32 imask; |
| 1842 | |
| 1843 | /* Never really got started! */ |
| 1844 | if (!sky2->tx_le) |
| 1845 | return 0; |
| 1846 | |
| 1847 | if (netif_msg_ifdown(sky2)) |
| 1848 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); |
| 1849 | |
| 1850 | /* Force flow control off */ |
| 1851 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
| 1852 | |
| 1853 | /* Stop transmitter */ |
| 1854 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); |
| 1855 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); |
| 1856 | |
| 1857 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), |
| 1858 | RB_RST_SET | RB_DIS_OP_MD); |
| 1859 | |
| 1860 | ctrl = gma_read16(hw, port, GM_GP_CTRL); |
| 1861 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
| 1862 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
| 1863 | |
| 1864 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
| 1865 | |
| 1866 | /* Workaround shared GMAC reset */ |
| 1867 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
| 1868 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) |
| 1869 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
| 1870 | |
| 1871 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
| 1872 | |
| 1873 | /* Force any delayed status interrrupt and NAPI */ |
| 1874 | sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); |
| 1875 | sky2_write32(hw, STAT_TX_TIMER_CNT, 0); |
| 1876 | sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); |
| 1877 | sky2_read8(hw, STAT_ISR_TIMER_CTRL); |
| 1878 | |
| 1879 | sky2_rx_stop(sky2); |
| 1880 | |
| 1881 | /* Disable port IRQ */ |
| 1882 | imask = sky2_read32(hw, B0_IMSK); |
| 1883 | imask &= ~portirq_msk[port]; |
| 1884 | sky2_write32(hw, B0_IMSK, imask); |
| 1885 | sky2_read32(hw, B0_IMSK); |
| 1886 | |
| 1887 | synchronize_irq(hw->pdev->irq); |
| 1888 | napi_synchronize(&hw->napi); |
| 1889 | |
| 1890 | spin_lock_bh(&sky2->phy_lock); |
| 1891 | sky2_phy_power_down(hw, port); |
| 1892 | spin_unlock_bh(&sky2->phy_lock); |
| 1893 | |
| 1894 | sky2_tx_reset(hw, port); |
| 1895 | |
| 1896 | /* Free any pending frames stuck in HW queue */ |
| 1897 | sky2_tx_complete(sky2, sky2->tx_prod); |
| 1898 | |
| 1899 | sky2_rx_clean(sky2); |
| 1900 | |
| 1901 | sky2_free_buffers(sky2); |
| 1902 | |
| 1903 | return 0; |
| 1904 | } |
| 1905 | |
| 1906 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) |
| 1907 | { |
| 1908 | if (hw->flags & SKY2_HW_FIBRE_PHY) |
| 1909 | return SPEED_1000; |
| 1910 | |
| 1911 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
| 1912 | if (aux & PHY_M_PS_SPEED_100) |
| 1913 | return SPEED_100; |
| 1914 | else |
| 1915 | return SPEED_10; |
| 1916 | } |
| 1917 | |
| 1918 | switch (aux & PHY_M_PS_SPEED_MSK) { |
| 1919 | case PHY_M_PS_SPEED_1000: |
| 1920 | return SPEED_1000; |
| 1921 | case PHY_M_PS_SPEED_100: |
| 1922 | return SPEED_100; |
| 1923 | default: |
| 1924 | return SPEED_10; |
| 1925 | } |
| 1926 | } |
| 1927 | |
| 1928 | static void sky2_link_up(struct sky2_port *sky2) |
| 1929 | { |
| 1930 | struct sky2_hw *hw = sky2->hw; |
| 1931 | unsigned port = sky2->port; |
| 1932 | u16 reg; |
| 1933 | static const char *fc_name[] = { |
| 1934 | [FC_NONE] = "none", |
| 1935 | [FC_TX] = "tx", |
| 1936 | [FC_RX] = "rx", |
| 1937 | [FC_BOTH] = "both", |
| 1938 | }; |
| 1939 | |
| 1940 | /* enable Rx/Tx */ |
| 1941 | reg = gma_read16(hw, port, GM_GP_CTRL); |
| 1942 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; |
| 1943 | gma_write16(hw, port, GM_GP_CTRL, reg); |
| 1944 | |
| 1945 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); |
| 1946 | |
| 1947 | netif_carrier_on(sky2->netdev); |
| 1948 | |
| 1949 | mod_timer(&hw->watchdog_timer, jiffies + 1); |
| 1950 | |
| 1951 | /* Turn on link LED */ |
| 1952 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
| 1953 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
| 1954 | |
| 1955 | if (netif_msg_link(sky2)) |
| 1956 | printk(KERN_INFO PFX |
| 1957 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
| 1958 | sky2->netdev->name, sky2->speed, |
| 1959 | sky2->duplex == DUPLEX_FULL ? "full" : "half", |
| 1960 | fc_name[sky2->flow_status]); |
| 1961 | } |
| 1962 | |
| 1963 | static void sky2_link_down(struct sky2_port *sky2) |
| 1964 | { |
| 1965 | struct sky2_hw *hw = sky2->hw; |
| 1966 | unsigned port = sky2->port; |
| 1967 | u16 reg; |
| 1968 | |
| 1969 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); |
| 1970 | |
| 1971 | reg = gma_read16(hw, port, GM_GP_CTRL); |
| 1972 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); |
| 1973 | gma_write16(hw, port, GM_GP_CTRL, reg); |
| 1974 | |
| 1975 | netif_carrier_off(sky2->netdev); |
| 1976 | |
| 1977 | /* Turn on link LED */ |
| 1978 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); |
| 1979 | |
| 1980 | if (netif_msg_link(sky2)) |
| 1981 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); |
| 1982 | |
| 1983 | sky2_phy_init(hw, port); |
| 1984 | } |
| 1985 | |
| 1986 | static enum flow_control sky2_flow(int rx, int tx) |
| 1987 | { |
| 1988 | if (rx) |
| 1989 | return tx ? FC_BOTH : FC_RX; |
| 1990 | else |
| 1991 | return tx ? FC_TX : FC_NONE; |
| 1992 | } |
| 1993 | |
| 1994 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
| 1995 | { |
| 1996 | struct sky2_hw *hw = sky2->hw; |
| 1997 | unsigned port = sky2->port; |
| 1998 | u16 advert, lpa; |
| 1999 | |
| 2000 | advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); |
| 2001 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); |
| 2002 | if (lpa & PHY_M_AN_RF) { |
| 2003 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); |
| 2004 | return -1; |
| 2005 | } |
| 2006 | |
| 2007 | if (!(aux & PHY_M_PS_SPDUP_RES)) { |
| 2008 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", |
| 2009 | sky2->netdev->name); |
| 2010 | return -1; |
| 2011 | } |
| 2012 | |
| 2013 | sky2->speed = sky2_phy_speed(hw, aux); |
| 2014 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; |
| 2015 | |
| 2016 | /* Since the pause result bits seem to in different positions on |
| 2017 | * different chips. look at registers. |
| 2018 | */ |
| 2019 | if (hw->flags & SKY2_HW_FIBRE_PHY) { |
| 2020 | /* Shift for bits in fiber PHY */ |
| 2021 | advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); |
| 2022 | lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); |
| 2023 | |
| 2024 | if (advert & ADVERTISE_1000XPAUSE) |
| 2025 | advert |= ADVERTISE_PAUSE_CAP; |
| 2026 | if (advert & ADVERTISE_1000XPSE_ASYM) |
| 2027 | advert |= ADVERTISE_PAUSE_ASYM; |
| 2028 | if (lpa & LPA_1000XPAUSE) |
| 2029 | lpa |= LPA_PAUSE_CAP; |
| 2030 | if (lpa & LPA_1000XPAUSE_ASYM) |
| 2031 | lpa |= LPA_PAUSE_ASYM; |
| 2032 | } |
| 2033 | |
| 2034 | sky2->flow_status = FC_NONE; |
| 2035 | if (advert & ADVERTISE_PAUSE_CAP) { |
| 2036 | if (lpa & LPA_PAUSE_CAP) |
| 2037 | sky2->flow_status = FC_BOTH; |
| 2038 | else if (advert & ADVERTISE_PAUSE_ASYM) |
| 2039 | sky2->flow_status = FC_RX; |
| 2040 | } else if (advert & ADVERTISE_PAUSE_ASYM) { |
| 2041 | if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) |
| 2042 | sky2->flow_status = FC_TX; |
| 2043 | } |
| 2044 | |
| 2045 | if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 |
| 2046 | && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) |
| 2047 | sky2->flow_status = FC_NONE; |
| 2048 | |
| 2049 | if (sky2->flow_status & FC_TX) |
| 2050 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
| 2051 | else |
| 2052 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
| 2053 | |
| 2054 | return 0; |
| 2055 | } |
| 2056 | |
| 2057 | /* Interrupt from PHY */ |
| 2058 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) |
| 2059 | { |
| 2060 | struct net_device *dev = hw->dev[port]; |
| 2061 | struct sky2_port *sky2 = netdev_priv(dev); |
| 2062 | u16 istatus, phystat; |
| 2063 | |
| 2064 | if (!netif_running(dev)) |
| 2065 | return; |
| 2066 | |
| 2067 | spin_lock(&sky2->phy_lock); |
| 2068 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); |
| 2069 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); |
| 2070 | |
| 2071 | if (netif_msg_intr(sky2)) |
| 2072 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", |
| 2073 | sky2->netdev->name, istatus, phystat); |
| 2074 | |
| 2075 | if (istatus & PHY_M_IS_AN_COMPL) { |
| 2076 | if (sky2_autoneg_done(sky2, phystat) == 0) |
| 2077 | sky2_link_up(sky2); |
| 2078 | goto out; |
| 2079 | } |
| 2080 | |
| 2081 | if (istatus & PHY_M_IS_LSP_CHANGE) |
| 2082 | sky2->speed = sky2_phy_speed(hw, phystat); |
| 2083 | |
| 2084 | if (istatus & PHY_M_IS_DUP_CHANGE) |
| 2085 | sky2->duplex = |
| 2086 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; |
| 2087 | |
| 2088 | if (istatus & PHY_M_IS_LST_CHANGE) { |
| 2089 | if (phystat & PHY_M_PS_LINK_UP) |
| 2090 | sky2_link_up(sky2); |
| 2091 | else |
| 2092 | sky2_link_down(sky2); |
| 2093 | } |
| 2094 | out: |
| 2095 | spin_unlock(&sky2->phy_lock); |
| 2096 | } |
| 2097 | |
| 2098 | /* Transmit timeout is only called if we are running, carrier is up |
| 2099 | * and tx queue is full (stopped). |
| 2100 | */ |
| 2101 | static void sky2_tx_timeout(struct net_device *dev) |
| 2102 | { |
| 2103 | struct sky2_port *sky2 = netdev_priv(dev); |
| 2104 | struct sky2_hw *hw = sky2->hw; |
| 2105 | |
| 2106 | if (netif_msg_timer(sky2)) |
| 2107 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); |
| 2108 | |
| 2109 | printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n", |
| 2110 | dev->name, sky2->tx_cons, sky2->tx_prod, |
| 2111 | sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), |
| 2112 | sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); |
| 2113 | |
| 2114 | /* can't restart safely under softirq */ |
| 2115 | schedule_work(&hw->restart_work); |
| 2116 | } |
| 2117 | |
| 2118 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) |
| 2119 | { |
| 2120 | struct sky2_port *sky2 = netdev_priv(dev); |
| 2121 | struct sky2_hw *hw = sky2->hw; |
| 2122 | unsigned port = sky2->port; |
| 2123 | int err; |
| 2124 | u16 ctl, mode; |
| 2125 | u32 imask; |
| 2126 | |
| 2127 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) |
| 2128 | return -EINVAL; |
| 2129 | |
| 2130 | if (new_mtu > ETH_DATA_LEN && |
| 2131 | (hw->chip_id == CHIP_ID_YUKON_FE || |
| 2132 | hw->chip_id == CHIP_ID_YUKON_FE_P)) |
| 2133 | return -EINVAL; |
| 2134 | |
| 2135 | if (!netif_running(dev)) { |
| 2136 | dev->mtu = new_mtu; |
| 2137 | return 0; |
| 2138 | } |
| 2139 | |
| 2140 | imask = sky2_read32(hw, B0_IMSK); |
| 2141 | sky2_write32(hw, B0_IMSK, 0); |
| 2142 | |
| 2143 | dev->trans_start = jiffies; /* prevent tx timeout */ |
| 2144 | netif_stop_queue(dev); |
| 2145 | napi_disable(&hw->napi); |
| 2146 | |
| 2147 | synchronize_irq(hw->pdev->irq); |
| 2148 | |
| 2149 | if (!(hw->flags & SKY2_HW_RAM_BUFFER)) |
| 2150 | sky2_set_tx_stfwd(hw, port); |
| 2151 | |
| 2152 | ctl = gma_read16(hw, port, GM_GP_CTRL); |
| 2153 | gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); |
| 2154 | sky2_rx_stop(sky2); |
| 2155 | sky2_rx_clean(sky2); |
| 2156 | |
| 2157 | dev->mtu = new_mtu; |
| 2158 | |
| 2159 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
| 2160 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
| 2161 | |
| 2162 | if (dev->mtu > ETH_DATA_LEN) |
| 2163 | mode |= GM_SMOD_JUMBO_ENA; |
| 2164 | |
| 2165 | gma_write16(hw, port, GM_SERIAL_MODE, mode); |
| 2166 | |
| 2167 | sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); |
| 2168 | |
| 2169 | err = sky2_rx_start(sky2); |
| 2170 | sky2_write32(hw, B0_IMSK, imask); |
| 2171 | |
| 2172 | sky2_read32(hw, B0_Y2_SP_LISR); |
| 2173 | napi_enable(&hw->napi); |
| 2174 | |
| 2175 | if (err) |
| 2176 | dev_close(dev); |
| 2177 | else { |
| 2178 | gma_write16(hw, port, GM_GP_CTRL, ctl); |
| 2179 | |
| 2180 | netif_wake_queue(dev); |
| 2181 | } |
| 2182 | |
| 2183 | return err; |
| 2184 | } |
| 2185 | |
| 2186 | /* For small just reuse existing skb for next receive */ |
| 2187 | static struct sk_buff *receive_copy(struct sky2_port *sky2, |
| 2188 | const struct rx_ring_info *re, |
| 2189 | unsigned length) |
| 2190 | { |
| 2191 | struct sk_buff *skb; |
| 2192 | |
| 2193 | skb = netdev_alloc_skb(sky2->netdev, length + 2); |
| 2194 | if (likely(skb)) { |
| 2195 | skb_reserve(skb, 2); |
| 2196 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, |
| 2197 | length, PCI_DMA_FROMDEVICE); |
| 2198 | skb_copy_from_linear_data(re->skb, skb->data, length); |
| 2199 | skb->ip_summed = re->skb->ip_summed; |
| 2200 | skb->csum = re->skb->csum; |
| 2201 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, |
| 2202 | length, PCI_DMA_FROMDEVICE); |
| 2203 | re->skb->ip_summed = CHECKSUM_NONE; |
| 2204 | skb_put(skb, length); |
| 2205 | } |
| 2206 | return skb; |
| 2207 | } |
| 2208 | |
| 2209 | /* Adjust length of skb with fragments to match received data */ |
| 2210 | static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, |
| 2211 | unsigned int length) |
| 2212 | { |
| 2213 | int i, num_frags; |
| 2214 | unsigned int size; |
| 2215 | |
| 2216 | /* put header into skb */ |
| 2217 | size = min(length, hdr_space); |
| 2218 | skb->tail += size; |
| 2219 | skb->len += size; |
| 2220 | length -= size; |
| 2221 | |
| 2222 | num_frags = skb_shinfo(skb)->nr_frags; |
| 2223 | for (i = 0; i < num_frags; i++) { |
| 2224 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 2225 | |
| 2226 | if (length == 0) { |
| 2227 | /* don't need this page */ |
| 2228 | __free_page(frag->page); |
| 2229 | --skb_shinfo(skb)->nr_frags; |
| 2230 | } else { |
| 2231 | size = min(length, (unsigned) PAGE_SIZE); |
| 2232 | |
| 2233 | frag->size = size; |
| 2234 | skb->data_len += size; |
| 2235 | skb->truesize += size; |
| 2236 | skb->len += size; |
| 2237 | length -= size; |
| 2238 | } |
| 2239 | } |
| 2240 | } |
| 2241 | |
| 2242 | /* Normal packet - take skb from ring element and put in a new one */ |
| 2243 | static struct sk_buff *receive_new(struct sky2_port *sky2, |
| 2244 | struct rx_ring_info *re, |
| 2245 | unsigned int length) |
| 2246 | { |
| 2247 | struct sk_buff *skb, *nskb; |
| 2248 | unsigned hdr_space = sky2->rx_data_size; |
| 2249 | |
| 2250 | /* Don't be tricky about reusing pages (yet) */ |
| 2251 | nskb = sky2_rx_alloc(sky2); |
| 2252 | if (unlikely(!nskb)) |
| 2253 | return NULL; |
| 2254 | |
| 2255 | skb = re->skb; |
| 2256 | sky2_rx_unmap_skb(sky2->hw->pdev, re); |
| 2257 | |
| 2258 | prefetch(skb->data); |
| 2259 | re->skb = nskb; |
| 2260 | if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) { |
| 2261 | dev_kfree_skb(nskb); |
| 2262 | re->skb = skb; |
| 2263 | return NULL; |
| 2264 | } |
| 2265 | |
| 2266 | if (skb_shinfo(skb)->nr_frags) |
| 2267 | skb_put_frags(skb, hdr_space, length); |
| 2268 | else |
| 2269 | skb_put(skb, length); |
| 2270 | return skb; |
| 2271 | } |
| 2272 | |
| 2273 | /* |
| 2274 | * Receive one packet. |
| 2275 | * For larger packets, get new buffer. |
| 2276 | */ |
| 2277 | static struct sk_buff *sky2_receive(struct net_device *dev, |
| 2278 | u16 length, u32 status) |
| 2279 | { |
| 2280 | struct sky2_port *sky2 = netdev_priv(dev); |
| 2281 | struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; |
| 2282 | struct sk_buff *skb = NULL; |
| 2283 | u16 count = (status & GMR_FS_LEN) >> 16; |
| 2284 | |
| 2285 | #ifdef SKY2_VLAN_TAG_USED |
| 2286 | /* Account for vlan tag */ |
| 2287 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) |
| 2288 | count -= VLAN_HLEN; |
| 2289 | #endif |
| 2290 | |
| 2291 | if (unlikely(netif_msg_rx_status(sky2))) |
| 2292 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", |
| 2293 | dev->name, sky2->rx_next, status, length); |
| 2294 | |
| 2295 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
| 2296 | prefetch(sky2->rx_ring + sky2->rx_next); |
| 2297 | |
| 2298 | /* This chip has hardware problems that generates bogus status. |
| 2299 | * So do only marginal checking and expect higher level protocols |
| 2300 | * to handle crap frames. |
| 2301 | */ |
| 2302 | if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && |
| 2303 | sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && |
| 2304 | length != count) |
| 2305 | goto okay; |
| 2306 | |
| 2307 | if (status & GMR_FS_ANY_ERR) |
| 2308 | goto error; |
| 2309 | |
| 2310 | if (!(status & GMR_FS_RX_OK)) |
| 2311 | goto resubmit; |
| 2312 | |
| 2313 | /* if length reported by DMA does not match PHY, packet was truncated */ |
| 2314 | if (length != count) |
| 2315 | goto len_error; |
| 2316 | |
| 2317 | okay: |
| 2318 | if (length < copybreak) |
| 2319 | skb = receive_copy(sky2, re, length); |
| 2320 | else |
| 2321 | skb = receive_new(sky2, re, length); |
| 2322 | resubmit: |
| 2323 | sky2_rx_submit(sky2, re); |
| 2324 | |
| 2325 | return skb; |
| 2326 | |
| 2327 | len_error: |
| 2328 | /* Truncation of overlength packets |
| 2329 | causes PHY length to not match MAC length */ |
| 2330 | ++dev->stats.rx_length_errors; |
| 2331 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
| 2332 | pr_info(PFX "%s: rx length error: status %#x length %d\n", |
| 2333 | dev->name, status, length); |
| 2334 | goto resubmit; |
| 2335 | |
| 2336 | error: |
| 2337 | ++dev->stats.rx_errors; |
| 2338 | if (status & GMR_FS_RX_FF_OV) { |
| 2339 | dev->stats.rx_over_errors++; |
| 2340 | goto resubmit; |
| 2341 | } |
| 2342 | |
| 2343 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
| 2344 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", |
| 2345 | dev->name, status, length); |
| 2346 | |
| 2347 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) |
| 2348 | dev->stats.rx_length_errors++; |
| 2349 | if (status & GMR_FS_FRAGMENT) |
| 2350 | dev->stats.rx_frame_errors++; |
| 2351 | if (status & GMR_FS_CRC_ERR) |
| 2352 | dev->stats.rx_crc_errors++; |
| 2353 | |
| 2354 | goto resubmit; |
| 2355 | } |
| 2356 | |
| 2357 | /* Transmit complete */ |
| 2358 | static inline void sky2_tx_done(struct net_device *dev, u16 last) |
| 2359 | { |
| 2360 | struct sky2_port *sky2 = netdev_priv(dev); |
| 2361 | |
| 2362 | if (netif_running(dev)) |
| 2363 | sky2_tx_complete(sky2, last); |
| 2364 | } |
| 2365 | |
| 2366 | static inline void sky2_skb_rx(const struct sky2_port *sky2, |
| 2367 | u32 status, struct sk_buff *skb) |
| 2368 | { |
| 2369 | #ifdef SKY2_VLAN_TAG_USED |
| 2370 | u16 vlan_tag = be16_to_cpu(sky2->rx_tag); |
| 2371 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { |
| 2372 | if (skb->ip_summed == CHECKSUM_NONE) |
| 2373 | vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag); |
| 2374 | else |
| 2375 | vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp, |
| 2376 | vlan_tag, skb); |
| 2377 | return; |
| 2378 | } |
| 2379 | #endif |
| 2380 | if (skb->ip_summed == CHECKSUM_NONE) |
| 2381 | netif_receive_skb(skb); |
| 2382 | else |
| 2383 | napi_gro_receive(&sky2->hw->napi, skb); |
| 2384 | } |
| 2385 | |
| 2386 | static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, |
| 2387 | unsigned packets, unsigned bytes) |
| 2388 | { |
| 2389 | if (packets) { |
| 2390 | struct net_device *dev = hw->dev[port]; |
| 2391 | |
| 2392 | dev->stats.rx_packets += packets; |
| 2393 | dev->stats.rx_bytes += bytes; |
| 2394 | dev->last_rx = jiffies; |
| 2395 | sky2_rx_update(netdev_priv(dev), rxqaddr[port]); |
| 2396 | } |
| 2397 | } |
| 2398 | |
| 2399 | /* Process status response ring */ |
| 2400 | static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) |
| 2401 | { |
| 2402 | int work_done = 0; |
| 2403 | unsigned int total_bytes[2] = { 0 }; |
| 2404 | unsigned int total_packets[2] = { 0 }; |
| 2405 | |
| 2406 | rmb(); |
| 2407 | do { |
| 2408 | struct sky2_port *sky2; |
| 2409 | struct sky2_status_le *le = hw->st_le + hw->st_idx; |
| 2410 | unsigned port; |
| 2411 | struct net_device *dev; |
| 2412 | struct sk_buff *skb; |
| 2413 | u32 status; |
| 2414 | u16 length; |
| 2415 | u8 opcode = le->opcode; |
| 2416 | |
| 2417 | if (!(opcode & HW_OWNER)) |
| 2418 | break; |
| 2419 | |
| 2420 | hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE); |
| 2421 | |
| 2422 | port = le->css & CSS_LINK_BIT; |
| 2423 | dev = hw->dev[port]; |
| 2424 | sky2 = netdev_priv(dev); |
| 2425 | length = le16_to_cpu(le->length); |
| 2426 | status = le32_to_cpu(le->status); |
| 2427 | |
| 2428 | le->opcode = 0; |
| 2429 | switch (opcode & ~HW_OWNER) { |
| 2430 | case OP_RXSTAT: |
| 2431 | total_packets[port]++; |
| 2432 | total_bytes[port] += length; |
| 2433 | skb = sky2_receive(dev, length, status); |
| 2434 | if (unlikely(!skb)) { |
| 2435 | dev->stats.rx_dropped++; |
| 2436 | break; |
| 2437 | } |
| 2438 | |
| 2439 | /* This chip reports checksum status differently */ |
| 2440 | if (hw->flags & SKY2_HW_NEW_LE) { |
| 2441 | if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) && |
| 2442 | (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && |
| 2443 | (le->css & CSS_TCPUDPCSOK)) |
| 2444 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 2445 | else |
| 2446 | skb->ip_summed = CHECKSUM_NONE; |
| 2447 | } |
| 2448 | |
| 2449 | skb->protocol = eth_type_trans(skb, dev); |
| 2450 | |
| 2451 | sky2_skb_rx(sky2, status, skb); |
| 2452 | |
| 2453 | /* Stop after net poll weight */ |
| 2454 | if (++work_done >= to_do) |
| 2455 | goto exit_loop; |
| 2456 | break; |
| 2457 | |
| 2458 | #ifdef SKY2_VLAN_TAG_USED |
| 2459 | case OP_RXVLAN: |
| 2460 | sky2->rx_tag = length; |
| 2461 | break; |
| 2462 | |
| 2463 | case OP_RXCHKSVLAN: |
| 2464 | sky2->rx_tag = length; |
| 2465 | /* fall through */ |
| 2466 | #endif |
| 2467 | case OP_RXCHKS: |
| 2468 | if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM)) |
| 2469 | break; |
| 2470 | |
| 2471 | /* If this happens then driver assuming wrong format */ |
| 2472 | if (unlikely(hw->flags & SKY2_HW_NEW_LE)) { |
| 2473 | if (net_ratelimit()) |
| 2474 | printk(KERN_NOTICE "%s: unexpected" |
| 2475 | " checksum status\n", |
| 2476 | dev->name); |
| 2477 | break; |
| 2478 | } |
| 2479 | |
| 2480 | /* Both checksum counters are programmed to start at |
| 2481 | * the same offset, so unless there is a problem they |
| 2482 | * should match. This failure is an early indication that |
| 2483 | * hardware receive checksumming won't work. |
| 2484 | */ |
| 2485 | if (likely(status >> 16 == (status & 0xffff))) { |
| 2486 | skb = sky2->rx_ring[sky2->rx_next].skb; |
| 2487 | skb->ip_summed = CHECKSUM_COMPLETE; |
| 2488 | skb->csum = le16_to_cpu(status); |
| 2489 | } else { |
| 2490 | printk(KERN_NOTICE PFX "%s: hardware receive " |
| 2491 | "checksum problem (status = %#x)\n", |
| 2492 | dev->name, status); |
| 2493 | sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM; |
| 2494 | |
| 2495 | sky2_write32(sky2->hw, |
| 2496 | Q_ADDR(rxqaddr[port], Q_CSR), |
| 2497 | BMU_DIS_RX_CHKSUM); |
| 2498 | } |
| 2499 | break; |
| 2500 | |
| 2501 | case OP_TXINDEXLE: |
| 2502 | /* TX index reports status for both ports */ |
| 2503 | sky2_tx_done(hw->dev[0], status & 0xfff); |
| 2504 | if (hw->dev[1]) |
| 2505 | sky2_tx_done(hw->dev[1], |
| 2506 | ((status >> 24) & 0xff) |
| 2507 | | (u16)(length & 0xf) << 8); |
| 2508 | break; |
| 2509 | |
| 2510 | default: |
| 2511 | if (net_ratelimit()) |
| 2512 | printk(KERN_WARNING PFX |
| 2513 | "unknown status opcode 0x%x\n", opcode); |
| 2514 | } |
| 2515 | } while (hw->st_idx != idx); |
| 2516 | |
| 2517 | /* Fully processed status ring so clear irq */ |
| 2518 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); |
| 2519 | |
| 2520 | exit_loop: |
| 2521 | sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); |
| 2522 | sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); |
| 2523 | |
| 2524 | return work_done; |
| 2525 | } |
| 2526 | |
| 2527 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) |
| 2528 | { |
| 2529 | struct net_device *dev = hw->dev[port]; |
| 2530 | |
| 2531 | if (net_ratelimit()) |
| 2532 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", |
| 2533 | dev->name, status); |
| 2534 | |
| 2535 | if (status & Y2_IS_PAR_RD1) { |
| 2536 | if (net_ratelimit()) |
| 2537 | printk(KERN_ERR PFX "%s: ram data read parity error\n", |
| 2538 | dev->name); |
| 2539 | /* Clear IRQ */ |
| 2540 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); |
| 2541 | } |
| 2542 | |
| 2543 | if (status & Y2_IS_PAR_WR1) { |
| 2544 | if (net_ratelimit()) |
| 2545 | printk(KERN_ERR PFX "%s: ram data write parity error\n", |
| 2546 | dev->name); |
| 2547 | |
| 2548 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); |
| 2549 | } |
| 2550 | |
| 2551 | if (status & Y2_IS_PAR_MAC1) { |
| 2552 | if (net_ratelimit()) |
| 2553 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); |
| 2554 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
| 2555 | } |
| 2556 | |
| 2557 | if (status & Y2_IS_PAR_RX1) { |
| 2558 | if (net_ratelimit()) |
| 2559 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); |
| 2560 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
| 2561 | } |
| 2562 | |
| 2563 | if (status & Y2_IS_TCP_TXA1) { |
| 2564 | if (net_ratelimit()) |
| 2565 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", |
| 2566 | dev->name); |
| 2567 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
| 2568 | } |
| 2569 | } |
| 2570 | |
| 2571 | static void sky2_hw_intr(struct sky2_hw *hw) |
| 2572 | { |
| 2573 | struct pci_dev *pdev = hw->pdev; |
| 2574 | u32 status = sky2_read32(hw, B0_HWE_ISRC); |
| 2575 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); |
| 2576 | |
| 2577 | status &= hwmsk; |
| 2578 | |
| 2579 | if (status & Y2_IS_TIST_OV) |
| 2580 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
| 2581 | |
| 2582 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { |
| 2583 | u16 pci_err; |
| 2584 | |
| 2585 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
| 2586 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
| 2587 | if (net_ratelimit()) |
| 2588 | dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", |
| 2589 | pci_err); |
| 2590 | |
| 2591 | sky2_pci_write16(hw, PCI_STATUS, |
| 2592 | pci_err | PCI_STATUS_ERROR_BITS); |
| 2593 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
| 2594 | } |
| 2595 | |
| 2596 | if (status & Y2_IS_PCI_EXP) { |
| 2597 | /* PCI-Express uncorrectable Error occurred */ |
| 2598 | u32 err; |
| 2599 | |
| 2600 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
| 2601 | err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); |
| 2602 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, |
| 2603 | 0xfffffffful); |
| 2604 | if (net_ratelimit()) |
| 2605 | dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); |
| 2606 | |
| 2607 | sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); |
| 2608 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
| 2609 | } |
| 2610 | |
| 2611 | if (status & Y2_HWE_L1_MASK) |
| 2612 | sky2_hw_error(hw, 0, status); |
| 2613 | status >>= 8; |
| 2614 | if (status & Y2_HWE_L1_MASK) |
| 2615 | sky2_hw_error(hw, 1, status); |
| 2616 | } |
| 2617 | |
| 2618 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) |
| 2619 | { |
| 2620 | struct net_device *dev = hw->dev[port]; |
| 2621 | struct sky2_port *sky2 = netdev_priv(dev); |
| 2622 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); |
| 2623 | |
| 2624 | if (netif_msg_intr(sky2)) |
| 2625 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", |
| 2626 | dev->name, status); |
| 2627 | |
| 2628 | if (status & GM_IS_RX_CO_OV) |
| 2629 | gma_read16(hw, port, GM_RX_IRQ_SRC); |
| 2630 | |
| 2631 | if (status & GM_IS_TX_CO_OV) |
| 2632 | gma_read16(hw, port, GM_TX_IRQ_SRC); |
| 2633 | |
| 2634 | if (status & GM_IS_RX_FF_OR) { |
| 2635 | ++dev->stats.rx_fifo_errors; |
| 2636 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); |
| 2637 | } |
| 2638 | |
| 2639 | if (status & GM_IS_TX_FF_UR) { |
| 2640 | ++dev->stats.tx_fifo_errors; |
| 2641 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); |
| 2642 | } |
| 2643 | } |
| 2644 | |
| 2645 | /* This should never happen it is a bug. */ |
| 2646 | static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) |
| 2647 | { |
| 2648 | struct net_device *dev = hw->dev[port]; |
| 2649 | u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); |
| 2650 | |
| 2651 | dev_err(&hw->pdev->dev, PFX |
| 2652 | "%s: descriptor error q=%#x get=%u put=%u\n", |
| 2653 | dev->name, (unsigned) q, (unsigned) idx, |
| 2654 | (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); |
| 2655 | |
| 2656 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); |
| 2657 | } |
| 2658 | |
| 2659 | static int sky2_rx_hung(struct net_device *dev) |
| 2660 | { |
| 2661 | struct sky2_port *sky2 = netdev_priv(dev); |
| 2662 | struct sky2_hw *hw = sky2->hw; |
| 2663 | unsigned port = sky2->port; |
| 2664 | unsigned rxq = rxqaddr[port]; |
| 2665 | u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); |
| 2666 | u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); |
| 2667 | u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); |
| 2668 | u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); |
| 2669 | |
| 2670 | /* If idle and MAC or PCI is stuck */ |
| 2671 | if (sky2->check.last == dev->last_rx && |
| 2672 | ((mac_rp == sky2->check.mac_rp && |
| 2673 | mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || |
| 2674 | /* Check if the PCI RX hang */ |
| 2675 | (fifo_rp == sky2->check.fifo_rp && |
| 2676 | fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { |
| 2677 | printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n", |
| 2678 | dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp, |
| 2679 | sky2_read8(hw, Q_ADDR(rxq, Q_WP))); |
| 2680 | return 1; |
| 2681 | } else { |
| 2682 | sky2->check.last = dev->last_rx; |
| 2683 | sky2->check.mac_rp = mac_rp; |
| 2684 | sky2->check.mac_lev = mac_lev; |
| 2685 | sky2->check.fifo_rp = fifo_rp; |
| 2686 | sky2->check.fifo_lev = fifo_lev; |
| 2687 | return 0; |
| 2688 | } |
| 2689 | } |
| 2690 | |
| 2691 | static void sky2_watchdog(unsigned long arg) |
| 2692 | { |
| 2693 | struct sky2_hw *hw = (struct sky2_hw *) arg; |
| 2694 | |
| 2695 | /* Check for lost IRQ once a second */ |
| 2696 | if (sky2_read32(hw, B0_ISRC)) { |
| 2697 | napi_schedule(&hw->napi); |
| 2698 | } else { |
| 2699 | int i, active = 0; |
| 2700 | |
| 2701 | for (i = 0; i < hw->ports; i++) { |
| 2702 | struct net_device *dev = hw->dev[i]; |
| 2703 | if (!netif_running(dev)) |
| 2704 | continue; |
| 2705 | ++active; |
| 2706 | |
| 2707 | /* For chips with Rx FIFO, check if stuck */ |
| 2708 | if ((hw->flags & SKY2_HW_RAM_BUFFER) && |
| 2709 | sky2_rx_hung(dev)) { |
| 2710 | pr_info(PFX "%s: receiver hang detected\n", |
| 2711 | dev->name); |
| 2712 | schedule_work(&hw->restart_work); |
| 2713 | return; |
| 2714 | } |
| 2715 | } |
| 2716 | |
| 2717 | if (active == 0) |
| 2718 | return; |
| 2719 | } |
| 2720 | |
| 2721 | mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); |
| 2722 | } |
| 2723 | |
| 2724 | /* Hardware/software error handling */ |
| 2725 | static void sky2_err_intr(struct sky2_hw *hw, u32 status) |
| 2726 | { |
| 2727 | if (net_ratelimit()) |
| 2728 | dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); |
| 2729 | |
| 2730 | if (status & Y2_IS_HW_ERR) |
| 2731 | sky2_hw_intr(hw); |
| 2732 | |
| 2733 | if (status & Y2_IS_IRQ_MAC1) |
| 2734 | sky2_mac_intr(hw, 0); |
| 2735 | |
| 2736 | if (status & Y2_IS_IRQ_MAC2) |
| 2737 | sky2_mac_intr(hw, 1); |
| 2738 | |
| 2739 | if (status & Y2_IS_CHK_RX1) |
| 2740 | sky2_le_error(hw, 0, Q_R1); |
| 2741 | |
| 2742 | if (status & Y2_IS_CHK_RX2) |
| 2743 | sky2_le_error(hw, 1, Q_R2); |
| 2744 | |
| 2745 | if (status & Y2_IS_CHK_TXA1) |
| 2746 | sky2_le_error(hw, 0, Q_XA1); |
| 2747 | |
| 2748 | if (status & Y2_IS_CHK_TXA2) |
| 2749 | sky2_le_error(hw, 1, Q_XA2); |
| 2750 | } |
| 2751 | |
| 2752 | static int sky2_poll(struct napi_struct *napi, int work_limit) |
| 2753 | { |
| 2754 | struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); |
| 2755 | u32 status = sky2_read32(hw, B0_Y2_SP_EISR); |
| 2756 | int work_done = 0; |
| 2757 | u16 idx; |
| 2758 | |
| 2759 | if (unlikely(status & Y2_IS_ERROR)) |
| 2760 | sky2_err_intr(hw, status); |
| 2761 | |
| 2762 | if (status & Y2_IS_IRQ_PHY1) |
| 2763 | sky2_phy_intr(hw, 0); |
| 2764 | |
| 2765 | if (status & Y2_IS_IRQ_PHY2) |
| 2766 | sky2_phy_intr(hw, 1); |
| 2767 | |
| 2768 | while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { |
| 2769 | work_done += sky2_status_intr(hw, work_limit - work_done, idx); |
| 2770 | |
| 2771 | if (work_done >= work_limit) |
| 2772 | goto done; |
| 2773 | } |
| 2774 | |
| 2775 | napi_complete(napi); |
| 2776 | sky2_read32(hw, B0_Y2_SP_LISR); |
| 2777 | done: |
| 2778 | |
| 2779 | return work_done; |
| 2780 | } |
| 2781 | |
| 2782 | static irqreturn_t sky2_intr(int irq, void *dev_id) |
| 2783 | { |
| 2784 | struct sky2_hw *hw = dev_id; |
| 2785 | u32 status; |
| 2786 | |
| 2787 | /* Reading this mask interrupts as side effect */ |
| 2788 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); |
| 2789 | if (status == 0 || status == ~0) |
| 2790 | return IRQ_NONE; |
| 2791 | |
| 2792 | prefetch(&hw->st_le[hw->st_idx]); |
| 2793 | |
| 2794 | napi_schedule(&hw->napi); |
| 2795 | |
| 2796 | return IRQ_HANDLED; |
| 2797 | } |
| 2798 | |
| 2799 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 2800 | static void sky2_netpoll(struct net_device *dev) |
| 2801 | { |
| 2802 | struct sky2_port *sky2 = netdev_priv(dev); |
| 2803 | |
| 2804 | napi_schedule(&sky2->hw->napi); |
| 2805 | } |
| 2806 | #endif |
| 2807 | |
| 2808 | /* Chip internal frequency for clock calculations */ |
| 2809 | static u32 sky2_mhz(const struct sky2_hw *hw) |
| 2810 | { |
| 2811 | switch (hw->chip_id) { |
| 2812 | case CHIP_ID_YUKON_EC: |
| 2813 | case CHIP_ID_YUKON_EC_U: |
| 2814 | case CHIP_ID_YUKON_EX: |
| 2815 | case CHIP_ID_YUKON_SUPR: |
| 2816 | case CHIP_ID_YUKON_UL_2: |
| 2817 | return 125; |
| 2818 | |
| 2819 | case CHIP_ID_YUKON_FE: |
| 2820 | return 100; |
| 2821 | |
| 2822 | case CHIP_ID_YUKON_FE_P: |
| 2823 | return 50; |
| 2824 | |
| 2825 | case CHIP_ID_YUKON_XL: |
| 2826 | return 156; |
| 2827 | |
| 2828 | default: |
| 2829 | BUG(); |
| 2830 | } |
| 2831 | } |
| 2832 | |
| 2833 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
| 2834 | { |
| 2835 | return sky2_mhz(hw) * us; |
| 2836 | } |
| 2837 | |
| 2838 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
| 2839 | { |
| 2840 | return clk / sky2_mhz(hw); |
| 2841 | } |
| 2842 | |
| 2843 | |
| 2844 | static int __devinit sky2_init(struct sky2_hw *hw) |
| 2845 | { |
| 2846 | u8 t8; |
| 2847 | |
| 2848 | /* Enable all clocks and check for bad PCI access */ |
| 2849 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
| 2850 | |
| 2851 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
| 2852 | |
| 2853 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
| 2854 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; |
| 2855 | |
| 2856 | switch(hw->chip_id) { |
| 2857 | case CHIP_ID_YUKON_XL: |
| 2858 | hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; |
| 2859 | break; |
| 2860 | |
| 2861 | case CHIP_ID_YUKON_EC_U: |
| 2862 | hw->flags = SKY2_HW_GIGABIT |
| 2863 | | SKY2_HW_NEWER_PHY |
| 2864 | | SKY2_HW_ADV_POWER_CTL; |
| 2865 | break; |
| 2866 | |
| 2867 | case CHIP_ID_YUKON_EX: |
| 2868 | hw->flags = SKY2_HW_GIGABIT |
| 2869 | | SKY2_HW_NEWER_PHY |
| 2870 | | SKY2_HW_NEW_LE |
| 2871 | | SKY2_HW_ADV_POWER_CTL; |
| 2872 | |
| 2873 | /* New transmit checksum */ |
| 2874 | if (hw->chip_rev != CHIP_REV_YU_EX_B0) |
| 2875 | hw->flags |= SKY2_HW_AUTO_TX_SUM; |
| 2876 | break; |
| 2877 | |
| 2878 | case CHIP_ID_YUKON_EC: |
| 2879 | /* This rev is really old, and requires untested workarounds */ |
| 2880 | if (hw->chip_rev == CHIP_REV_YU_EC_A1) { |
| 2881 | dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); |
| 2882 | return -EOPNOTSUPP; |
| 2883 | } |
| 2884 | hw->flags = SKY2_HW_GIGABIT; |
| 2885 | break; |
| 2886 | |
| 2887 | case CHIP_ID_YUKON_FE: |
| 2888 | break; |
| 2889 | |
| 2890 | case CHIP_ID_YUKON_FE_P: |
| 2891 | hw->flags = SKY2_HW_NEWER_PHY |
| 2892 | | SKY2_HW_NEW_LE |
| 2893 | | SKY2_HW_AUTO_TX_SUM |
| 2894 | | SKY2_HW_ADV_POWER_CTL; |
| 2895 | break; |
| 2896 | |
| 2897 | case CHIP_ID_YUKON_SUPR: |
| 2898 | hw->flags = SKY2_HW_GIGABIT |
| 2899 | | SKY2_HW_NEWER_PHY |
| 2900 | | SKY2_HW_NEW_LE |
| 2901 | | SKY2_HW_AUTO_TX_SUM |
| 2902 | | SKY2_HW_ADV_POWER_CTL; |
| 2903 | break; |
| 2904 | |
| 2905 | case CHIP_ID_YUKON_UL_2: |
| 2906 | hw->flags = SKY2_HW_GIGABIT |
| 2907 | | SKY2_HW_ADV_POWER_CTL; |
| 2908 | break; |
| 2909 | |
| 2910 | default: |
| 2911 | dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", |
| 2912 | hw->chip_id); |
| 2913 | return -EOPNOTSUPP; |
| 2914 | } |
| 2915 | |
| 2916 | hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); |
| 2917 | if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') |
| 2918 | hw->flags |= SKY2_HW_FIBRE_PHY; |
| 2919 | |
| 2920 | hw->ports = 1; |
| 2921 | t8 = sky2_read8(hw, B2_Y2_HW_RES); |
| 2922 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { |
| 2923 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) |
| 2924 | ++hw->ports; |
| 2925 | } |
| 2926 | |
| 2927 | return 0; |
| 2928 | } |
| 2929 | |
| 2930 | static void sky2_reset(struct sky2_hw *hw) |
| 2931 | { |
| 2932 | struct pci_dev *pdev = hw->pdev; |
| 2933 | u16 status; |
| 2934 | int i, cap; |
| 2935 | u32 hwe_mask = Y2_HWE_ALL_MASK; |
| 2936 | |
| 2937 | /* disable ASF */ |
| 2938 | if (hw->chip_id == CHIP_ID_YUKON_EX) { |
| 2939 | status = sky2_read16(hw, HCU_CCSR); |
| 2940 | status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | |
| 2941 | HCU_CCSR_UC_STATE_MSK); |
| 2942 | sky2_write16(hw, HCU_CCSR, status); |
| 2943 | } else |
| 2944 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); |
| 2945 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); |
| 2946 | |
| 2947 | /* do a SW reset */ |
| 2948 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
| 2949 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
| 2950 | |
| 2951 | /* allow writes to PCI config */ |
| 2952 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
| 2953 | |
| 2954 | /* clear PCI errors, if any */ |
| 2955 | status = sky2_pci_read16(hw, PCI_STATUS); |
| 2956 | status |= PCI_STATUS_ERROR_BITS; |
| 2957 | sky2_pci_write16(hw, PCI_STATUS, status); |
| 2958 | |
| 2959 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); |
| 2960 | |
| 2961 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
| 2962 | if (cap) { |
| 2963 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, |
| 2964 | 0xfffffffful); |
| 2965 | |
| 2966 | /* If error bit is stuck on ignore it */ |
| 2967 | if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) |
| 2968 | dev_info(&pdev->dev, "ignoring stuck error report bit\n"); |
| 2969 | else |
| 2970 | hwe_mask |= Y2_IS_PCI_EXP; |
| 2971 | } |
| 2972 | |
| 2973 | sky2_power_on(hw); |
| 2974 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
| 2975 | |
| 2976 | for (i = 0; i < hw->ports; i++) { |
| 2977 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); |
| 2978 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); |
| 2979 | |
| 2980 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
| 2981 | hw->chip_id == CHIP_ID_YUKON_SUPR) |
| 2982 | sky2_write16(hw, SK_REG(i, GMAC_CTRL), |
| 2983 | GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
| 2984 | | GMC_BYP_RETR_ON); |
| 2985 | } |
| 2986 | |
| 2987 | /* Clear I2C IRQ noise */ |
| 2988 | sky2_write32(hw, B2_I2C_IRQ, 1); |
| 2989 | |
| 2990 | /* turn off hardware timer (unused) */ |
| 2991 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); |
| 2992 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); |
| 2993 | |
| 2994 | /* Turn off descriptor polling */ |
| 2995 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); |
| 2996 | |
| 2997 | /* Turn off receive timestamp */ |
| 2998 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); |
| 2999 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
| 3000 | |
| 3001 | /* enable the Tx Arbiters */ |
| 3002 | for (i = 0; i < hw->ports; i++) |
| 3003 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); |
| 3004 | |
| 3005 | /* Initialize ram interface */ |
| 3006 | for (i = 0; i < hw->ports; i++) { |
| 3007 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
| 3008 | |
| 3009 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); |
| 3010 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); |
| 3011 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); |
| 3012 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); |
| 3013 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); |
| 3014 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); |
| 3015 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); |
| 3016 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); |
| 3017 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); |
| 3018 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); |
| 3019 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); |
| 3020 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); |
| 3021 | } |
| 3022 | |
| 3023 | sky2_write32(hw, B0_HWE_IMSK, hwe_mask); |
| 3024 | |
| 3025 | for (i = 0; i < hw->ports; i++) |
| 3026 | sky2_gmac_reset(hw, i); |
| 3027 | |
| 3028 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
| 3029 | hw->st_idx = 0; |
| 3030 | |
| 3031 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); |
| 3032 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); |
| 3033 | |
| 3034 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); |
| 3035 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
| 3036 | |
| 3037 | /* Set the list last index */ |
| 3038 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
| 3039 | |
| 3040 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
| 3041 | sky2_write8(hw, STAT_FIFO_WM, 16); |
| 3042 | |
| 3043 | /* set Status-FIFO ISR watermark */ |
| 3044 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) |
| 3045 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); |
| 3046 | else |
| 3047 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); |
| 3048 | |
| 3049 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
| 3050 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); |
| 3051 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); |
| 3052 | |
| 3053 | /* enable status unit */ |
| 3054 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
| 3055 | |
| 3056 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); |
| 3057 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); |
| 3058 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); |
| 3059 | } |
| 3060 | |
| 3061 | /* Take device down (offline). |
| 3062 | * Equivalent to doing dev_stop() but this does not |
| 3063 | * inform upper layers of the transistion. |
| 3064 | */ |
| 3065 | static void sky2_detach(struct net_device *dev) |
| 3066 | { |
| 3067 | if (netif_running(dev)) { |
| 3068 | netif_device_detach(dev); /* stop txq */ |
| 3069 | sky2_down(dev); |
| 3070 | } |
| 3071 | } |
| 3072 | |
| 3073 | /* Bring device back after doing sky2_detach */ |
| 3074 | static int sky2_reattach(struct net_device *dev) |
| 3075 | { |
| 3076 | int err = 0; |
| 3077 | |
| 3078 | if (netif_running(dev)) { |
| 3079 | err = sky2_up(dev); |
| 3080 | if (err) { |
| 3081 | printk(KERN_INFO PFX "%s: could not restart %d\n", |
| 3082 | dev->name, err); |
| 3083 | dev_close(dev); |
| 3084 | } else { |
| 3085 | netif_device_attach(dev); |
| 3086 | sky2_set_multicast(dev); |
| 3087 | } |
| 3088 | } |
| 3089 | |
| 3090 | return err; |
| 3091 | } |
| 3092 | |
| 3093 | static void sky2_restart(struct work_struct *work) |
| 3094 | { |
| 3095 | struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); |
| 3096 | int i; |
| 3097 | |
| 3098 | rtnl_lock(); |
| 3099 | for (i = 0; i < hw->ports; i++) |
| 3100 | sky2_detach(hw->dev[i]); |
| 3101 | |
| 3102 | napi_disable(&hw->napi); |
| 3103 | sky2_write32(hw, B0_IMSK, 0); |
| 3104 | sky2_reset(hw); |
| 3105 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |
| 3106 | napi_enable(&hw->napi); |
| 3107 | |
| 3108 | for (i = 0; i < hw->ports; i++) |
| 3109 | sky2_reattach(hw->dev[i]); |
| 3110 | |
| 3111 | rtnl_unlock(); |
| 3112 | } |
| 3113 | |
| 3114 | static inline u8 sky2_wol_supported(const struct sky2_hw *hw) |
| 3115 | { |
| 3116 | return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; |
| 3117 | } |
| 3118 | |
| 3119 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
| 3120 | { |
| 3121 | const struct sky2_port *sky2 = netdev_priv(dev); |
| 3122 | |
| 3123 | wol->supported = sky2_wol_supported(sky2->hw); |
| 3124 | wol->wolopts = sky2->wol; |
| 3125 | } |
| 3126 | |
| 3127 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
| 3128 | { |
| 3129 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3130 | struct sky2_hw *hw = sky2->hw; |
| 3131 | |
| 3132 | if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) |
| 3133 | || !device_can_wakeup(&hw->pdev->dev)) |
| 3134 | return -EOPNOTSUPP; |
| 3135 | |
| 3136 | sky2->wol = wol->wolopts; |
| 3137 | |
| 3138 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || |
| 3139 | hw->chip_id == CHIP_ID_YUKON_EX || |
| 3140 | hw->chip_id == CHIP_ID_YUKON_FE_P) |
| 3141 | sky2_write32(hw, B0_CTST, sky2->wol |
| 3142 | ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF); |
| 3143 | |
| 3144 | device_set_wakeup_enable(&hw->pdev->dev, sky2->wol); |
| 3145 | |
| 3146 | if (!netif_running(dev)) |
| 3147 | sky2_wol_init(sky2); |
| 3148 | return 0; |
| 3149 | } |
| 3150 | |
| 3151 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
| 3152 | { |
| 3153 | if (sky2_is_copper(hw)) { |
| 3154 | u32 modes = SUPPORTED_10baseT_Half |
| 3155 | | SUPPORTED_10baseT_Full |
| 3156 | | SUPPORTED_100baseT_Half |
| 3157 | | SUPPORTED_100baseT_Full |
| 3158 | | SUPPORTED_Autoneg | SUPPORTED_TP; |
| 3159 | |
| 3160 | if (hw->flags & SKY2_HW_GIGABIT) |
| 3161 | modes |= SUPPORTED_1000baseT_Half |
| 3162 | | SUPPORTED_1000baseT_Full; |
| 3163 | return modes; |
| 3164 | } else |
| 3165 | return SUPPORTED_1000baseT_Half |
| 3166 | | SUPPORTED_1000baseT_Full |
| 3167 | | SUPPORTED_Autoneg |
| 3168 | | SUPPORTED_FIBRE; |
| 3169 | } |
| 3170 | |
| 3171 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
| 3172 | { |
| 3173 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3174 | struct sky2_hw *hw = sky2->hw; |
| 3175 | |
| 3176 | ecmd->transceiver = XCVR_INTERNAL; |
| 3177 | ecmd->supported = sky2_supported_modes(hw); |
| 3178 | ecmd->phy_address = PHY_ADDR_MARV; |
| 3179 | if (sky2_is_copper(hw)) { |
| 3180 | ecmd->port = PORT_TP; |
| 3181 | ecmd->speed = sky2->speed; |
| 3182 | } else { |
| 3183 | ecmd->speed = SPEED_1000; |
| 3184 | ecmd->port = PORT_FIBRE; |
| 3185 | } |
| 3186 | |
| 3187 | ecmd->advertising = sky2->advertising; |
| 3188 | ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) |
| 3189 | ? AUTONEG_ENABLE : AUTONEG_DISABLE; |
| 3190 | ecmd->duplex = sky2->duplex; |
| 3191 | return 0; |
| 3192 | } |
| 3193 | |
| 3194 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
| 3195 | { |
| 3196 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3197 | const struct sky2_hw *hw = sky2->hw; |
| 3198 | u32 supported = sky2_supported_modes(hw); |
| 3199 | |
| 3200 | if (ecmd->autoneg == AUTONEG_ENABLE) { |
| 3201 | sky2->flags |= SKY2_FLAG_AUTO_SPEED; |
| 3202 | ecmd->advertising = supported; |
| 3203 | sky2->duplex = -1; |
| 3204 | sky2->speed = -1; |
| 3205 | } else { |
| 3206 | u32 setting; |
| 3207 | |
| 3208 | switch (ecmd->speed) { |
| 3209 | case SPEED_1000: |
| 3210 | if (ecmd->duplex == DUPLEX_FULL) |
| 3211 | setting = SUPPORTED_1000baseT_Full; |
| 3212 | else if (ecmd->duplex == DUPLEX_HALF) |
| 3213 | setting = SUPPORTED_1000baseT_Half; |
| 3214 | else |
| 3215 | return -EINVAL; |
| 3216 | break; |
| 3217 | case SPEED_100: |
| 3218 | if (ecmd->duplex == DUPLEX_FULL) |
| 3219 | setting = SUPPORTED_100baseT_Full; |
| 3220 | else if (ecmd->duplex == DUPLEX_HALF) |
| 3221 | setting = SUPPORTED_100baseT_Half; |
| 3222 | else |
| 3223 | return -EINVAL; |
| 3224 | break; |
| 3225 | |
| 3226 | case SPEED_10: |
| 3227 | if (ecmd->duplex == DUPLEX_FULL) |
| 3228 | setting = SUPPORTED_10baseT_Full; |
| 3229 | else if (ecmd->duplex == DUPLEX_HALF) |
| 3230 | setting = SUPPORTED_10baseT_Half; |
| 3231 | else |
| 3232 | return -EINVAL; |
| 3233 | break; |
| 3234 | default: |
| 3235 | return -EINVAL; |
| 3236 | } |
| 3237 | |
| 3238 | if ((setting & supported) == 0) |
| 3239 | return -EINVAL; |
| 3240 | |
| 3241 | sky2->speed = ecmd->speed; |
| 3242 | sky2->duplex = ecmd->duplex; |
| 3243 | sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; |
| 3244 | } |
| 3245 | |
| 3246 | sky2->advertising = ecmd->advertising; |
| 3247 | |
| 3248 | if (netif_running(dev)) { |
| 3249 | sky2_phy_reinit(sky2); |
| 3250 | sky2_set_multicast(dev); |
| 3251 | } |
| 3252 | |
| 3253 | return 0; |
| 3254 | } |
| 3255 | |
| 3256 | static void sky2_get_drvinfo(struct net_device *dev, |
| 3257 | struct ethtool_drvinfo *info) |
| 3258 | { |
| 3259 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3260 | |
| 3261 | strcpy(info->driver, DRV_NAME); |
| 3262 | strcpy(info->version, DRV_VERSION); |
| 3263 | strcpy(info->fw_version, "N/A"); |
| 3264 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); |
| 3265 | } |
| 3266 | |
| 3267 | static const struct sky2_stat { |
| 3268 | char name[ETH_GSTRING_LEN]; |
| 3269 | u16 offset; |
| 3270 | } sky2_stats[] = { |
| 3271 | { "tx_bytes", GM_TXO_OK_HI }, |
| 3272 | { "rx_bytes", GM_RXO_OK_HI }, |
| 3273 | { "tx_broadcast", GM_TXF_BC_OK }, |
| 3274 | { "rx_broadcast", GM_RXF_BC_OK }, |
| 3275 | { "tx_multicast", GM_TXF_MC_OK }, |
| 3276 | { "rx_multicast", GM_RXF_MC_OK }, |
| 3277 | { "tx_unicast", GM_TXF_UC_OK }, |
| 3278 | { "rx_unicast", GM_RXF_UC_OK }, |
| 3279 | { "tx_mac_pause", GM_TXF_MPAUSE }, |
| 3280 | { "rx_mac_pause", GM_RXF_MPAUSE }, |
| 3281 | { "collisions", GM_TXF_COL }, |
| 3282 | { "late_collision",GM_TXF_LAT_COL }, |
| 3283 | { "aborted", GM_TXF_ABO_COL }, |
| 3284 | { "single_collisions", GM_TXF_SNG_COL }, |
| 3285 | { "multi_collisions", GM_TXF_MUL_COL }, |
| 3286 | |
| 3287 | { "rx_short", GM_RXF_SHT }, |
| 3288 | { "rx_runt", GM_RXE_FRAG }, |
| 3289 | { "rx_64_byte_packets", GM_RXF_64B }, |
| 3290 | { "rx_65_to_127_byte_packets", GM_RXF_127B }, |
| 3291 | { "rx_128_to_255_byte_packets", GM_RXF_255B }, |
| 3292 | { "rx_256_to_511_byte_packets", GM_RXF_511B }, |
| 3293 | { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, |
| 3294 | { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, |
| 3295 | { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, |
| 3296 | { "rx_too_long", GM_RXF_LNG_ERR }, |
| 3297 | { "rx_fifo_overflow", GM_RXE_FIFO_OV }, |
| 3298 | { "rx_jabber", GM_RXF_JAB_PKT }, |
| 3299 | { "rx_fcs_error", GM_RXF_FCS_ERR }, |
| 3300 | |
| 3301 | { "tx_64_byte_packets", GM_TXF_64B }, |
| 3302 | { "tx_65_to_127_byte_packets", GM_TXF_127B }, |
| 3303 | { "tx_128_to_255_byte_packets", GM_TXF_255B }, |
| 3304 | { "tx_256_to_511_byte_packets", GM_TXF_511B }, |
| 3305 | { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, |
| 3306 | { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, |
| 3307 | { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, |
| 3308 | { "tx_fifo_underrun", GM_TXE_FIFO_UR }, |
| 3309 | }; |
| 3310 | |
| 3311 | static u32 sky2_get_rx_csum(struct net_device *dev) |
| 3312 | { |
| 3313 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3314 | |
| 3315 | return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM); |
| 3316 | } |
| 3317 | |
| 3318 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) |
| 3319 | { |
| 3320 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3321 | |
| 3322 | if (data) |
| 3323 | sky2->flags |= SKY2_FLAG_RX_CHECKSUM; |
| 3324 | else |
| 3325 | sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM; |
| 3326 | |
| 3327 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
| 3328 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); |
| 3329 | |
| 3330 | return 0; |
| 3331 | } |
| 3332 | |
| 3333 | static u32 sky2_get_msglevel(struct net_device *netdev) |
| 3334 | { |
| 3335 | struct sky2_port *sky2 = netdev_priv(netdev); |
| 3336 | return sky2->msg_enable; |
| 3337 | } |
| 3338 | |
| 3339 | static int sky2_nway_reset(struct net_device *dev) |
| 3340 | { |
| 3341 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3342 | |
| 3343 | if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) |
| 3344 | return -EINVAL; |
| 3345 | |
| 3346 | sky2_phy_reinit(sky2); |
| 3347 | sky2_set_multicast(dev); |
| 3348 | |
| 3349 | return 0; |
| 3350 | } |
| 3351 | |
| 3352 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
| 3353 | { |
| 3354 | struct sky2_hw *hw = sky2->hw; |
| 3355 | unsigned port = sky2->port; |
| 3356 | int i; |
| 3357 | |
| 3358 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 |
| 3359 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
| 3360 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
| 3361 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
| 3362 | |
| 3363 | for (i = 2; i < count; i++) |
| 3364 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
| 3365 | } |
| 3366 | |
| 3367 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
| 3368 | { |
| 3369 | struct sky2_port *sky2 = netdev_priv(netdev); |
| 3370 | sky2->msg_enable = value; |
| 3371 | } |
| 3372 | |
| 3373 | static int sky2_get_sset_count(struct net_device *dev, int sset) |
| 3374 | { |
| 3375 | switch (sset) { |
| 3376 | case ETH_SS_STATS: |
| 3377 | return ARRAY_SIZE(sky2_stats); |
| 3378 | default: |
| 3379 | return -EOPNOTSUPP; |
| 3380 | } |
| 3381 | } |
| 3382 | |
| 3383 | static void sky2_get_ethtool_stats(struct net_device *dev, |
| 3384 | struct ethtool_stats *stats, u64 * data) |
| 3385 | { |
| 3386 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3387 | |
| 3388 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
| 3389 | } |
| 3390 | |
| 3391 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
| 3392 | { |
| 3393 | int i; |
| 3394 | |
| 3395 | switch (stringset) { |
| 3396 | case ETH_SS_STATS: |
| 3397 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) |
| 3398 | memcpy(data + i * ETH_GSTRING_LEN, |
| 3399 | sky2_stats[i].name, ETH_GSTRING_LEN); |
| 3400 | break; |
| 3401 | } |
| 3402 | } |
| 3403 | |
| 3404 | static int sky2_set_mac_address(struct net_device *dev, void *p) |
| 3405 | { |
| 3406 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3407 | struct sky2_hw *hw = sky2->hw; |
| 3408 | unsigned port = sky2->port; |
| 3409 | const struct sockaddr *addr = p; |
| 3410 | |
| 3411 | if (!is_valid_ether_addr(addr->sa_data)) |
| 3412 | return -EADDRNOTAVAIL; |
| 3413 | |
| 3414 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
| 3415 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
| 3416 | dev->dev_addr, ETH_ALEN); |
| 3417 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
| 3418 | dev->dev_addr, ETH_ALEN); |
| 3419 | |
| 3420 | /* virtual address for data */ |
| 3421 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); |
| 3422 | |
| 3423 | /* physical address: used for pause frames */ |
| 3424 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); |
| 3425 | |
| 3426 | return 0; |
| 3427 | } |
| 3428 | |
| 3429 | static void inline sky2_add_filter(u8 filter[8], const u8 *addr) |
| 3430 | { |
| 3431 | u32 bit; |
| 3432 | |
| 3433 | bit = ether_crc(ETH_ALEN, addr) & 63; |
| 3434 | filter[bit >> 3] |= 1 << (bit & 7); |
| 3435 | } |
| 3436 | |
| 3437 | static void sky2_set_multicast(struct net_device *dev) |
| 3438 | { |
| 3439 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3440 | struct sky2_hw *hw = sky2->hw; |
| 3441 | unsigned port = sky2->port; |
| 3442 | struct dev_mc_list *list = dev->mc_list; |
| 3443 | u16 reg; |
| 3444 | u8 filter[8]; |
| 3445 | int rx_pause; |
| 3446 | static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; |
| 3447 | |
| 3448 | rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); |
| 3449 | memset(filter, 0, sizeof(filter)); |
| 3450 | |
| 3451 | reg = gma_read16(hw, port, GM_RX_CTRL); |
| 3452 | reg |= GM_RXCR_UCF_ENA; |
| 3453 | |
| 3454 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
| 3455 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
| 3456 | else if (dev->flags & IFF_ALLMULTI) |
| 3457 | memset(filter, 0xff, sizeof(filter)); |
| 3458 | else if (dev->mc_count == 0 && !rx_pause) |
| 3459 | reg &= ~GM_RXCR_MCF_ENA; |
| 3460 | else { |
| 3461 | int i; |
| 3462 | reg |= GM_RXCR_MCF_ENA; |
| 3463 | |
| 3464 | if (rx_pause) |
| 3465 | sky2_add_filter(filter, pause_mc_addr); |
| 3466 | |
| 3467 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) |
| 3468 | sky2_add_filter(filter, list->dmi_addr); |
| 3469 | } |
| 3470 | |
| 3471 | gma_write16(hw, port, GM_MC_ADDR_H1, |
| 3472 | (u16) filter[0] | ((u16) filter[1] << 8)); |
| 3473 | gma_write16(hw, port, GM_MC_ADDR_H2, |
| 3474 | (u16) filter[2] | ((u16) filter[3] << 8)); |
| 3475 | gma_write16(hw, port, GM_MC_ADDR_H3, |
| 3476 | (u16) filter[4] | ((u16) filter[5] << 8)); |
| 3477 | gma_write16(hw, port, GM_MC_ADDR_H4, |
| 3478 | (u16) filter[6] | ((u16) filter[7] << 8)); |
| 3479 | |
| 3480 | gma_write16(hw, port, GM_RX_CTRL, reg); |
| 3481 | } |
| 3482 | |
| 3483 | /* Can have one global because blinking is controlled by |
| 3484 | * ethtool and that is always under RTNL mutex |
| 3485 | */ |
| 3486 | static void sky2_led(struct sky2_port *sky2, enum led_mode mode) |
| 3487 | { |
| 3488 | struct sky2_hw *hw = sky2->hw; |
| 3489 | unsigned port = sky2->port; |
| 3490 | |
| 3491 | spin_lock_bh(&sky2->phy_lock); |
| 3492 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || |
| 3493 | hw->chip_id == CHIP_ID_YUKON_EX || |
| 3494 | hw->chip_id == CHIP_ID_YUKON_SUPR) { |
| 3495 | u16 pg; |
| 3496 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
| 3497 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); |
| 3498 | |
| 3499 | switch (mode) { |
| 3500 | case MO_LED_OFF: |
| 3501 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
| 3502 | PHY_M_LEDC_LOS_CTRL(8) | |
| 3503 | PHY_M_LEDC_INIT_CTRL(8) | |
| 3504 | PHY_M_LEDC_STA1_CTRL(8) | |
| 3505 | PHY_M_LEDC_STA0_CTRL(8)); |
| 3506 | break; |
| 3507 | case MO_LED_ON: |
| 3508 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
| 3509 | PHY_M_LEDC_LOS_CTRL(9) | |
| 3510 | PHY_M_LEDC_INIT_CTRL(9) | |
| 3511 | PHY_M_LEDC_STA1_CTRL(9) | |
| 3512 | PHY_M_LEDC_STA0_CTRL(9)); |
| 3513 | break; |
| 3514 | case MO_LED_BLINK: |
| 3515 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
| 3516 | PHY_M_LEDC_LOS_CTRL(0xa) | |
| 3517 | PHY_M_LEDC_INIT_CTRL(0xa) | |
| 3518 | PHY_M_LEDC_STA1_CTRL(0xa) | |
| 3519 | PHY_M_LEDC_STA0_CTRL(0xa)); |
| 3520 | break; |
| 3521 | case MO_LED_NORM: |
| 3522 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
| 3523 | PHY_M_LEDC_LOS_CTRL(1) | |
| 3524 | PHY_M_LEDC_INIT_CTRL(8) | |
| 3525 | PHY_M_LEDC_STA1_CTRL(7) | |
| 3526 | PHY_M_LEDC_STA0_CTRL(7)); |
| 3527 | } |
| 3528 | |
| 3529 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
| 3530 | } else |
| 3531 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
| 3532 | PHY_M_LED_MO_DUP(mode) | |
| 3533 | PHY_M_LED_MO_10(mode) | |
| 3534 | PHY_M_LED_MO_100(mode) | |
| 3535 | PHY_M_LED_MO_1000(mode) | |
| 3536 | PHY_M_LED_MO_RX(mode) | |
| 3537 | PHY_M_LED_MO_TX(mode)); |
| 3538 | |
| 3539 | spin_unlock_bh(&sky2->phy_lock); |
| 3540 | } |
| 3541 | |
| 3542 | /* blink LED's for finding board */ |
| 3543 | static int sky2_phys_id(struct net_device *dev, u32 data) |
| 3544 | { |
| 3545 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3546 | unsigned int i; |
| 3547 | |
| 3548 | if (data == 0) |
| 3549 | data = UINT_MAX; |
| 3550 | |
| 3551 | for (i = 0; i < data; i++) { |
| 3552 | sky2_led(sky2, MO_LED_ON); |
| 3553 | if (msleep_interruptible(500)) |
| 3554 | break; |
| 3555 | sky2_led(sky2, MO_LED_OFF); |
| 3556 | if (msleep_interruptible(500)) |
| 3557 | break; |
| 3558 | } |
| 3559 | sky2_led(sky2, MO_LED_NORM); |
| 3560 | |
| 3561 | return 0; |
| 3562 | } |
| 3563 | |
| 3564 | static void sky2_get_pauseparam(struct net_device *dev, |
| 3565 | struct ethtool_pauseparam *ecmd) |
| 3566 | { |
| 3567 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3568 | |
| 3569 | switch (sky2->flow_mode) { |
| 3570 | case FC_NONE: |
| 3571 | ecmd->tx_pause = ecmd->rx_pause = 0; |
| 3572 | break; |
| 3573 | case FC_TX: |
| 3574 | ecmd->tx_pause = 1, ecmd->rx_pause = 0; |
| 3575 | break; |
| 3576 | case FC_RX: |
| 3577 | ecmd->tx_pause = 0, ecmd->rx_pause = 1; |
| 3578 | break; |
| 3579 | case FC_BOTH: |
| 3580 | ecmd->tx_pause = ecmd->rx_pause = 1; |
| 3581 | } |
| 3582 | |
| 3583 | ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) |
| 3584 | ? AUTONEG_ENABLE : AUTONEG_DISABLE; |
| 3585 | } |
| 3586 | |
| 3587 | static int sky2_set_pauseparam(struct net_device *dev, |
| 3588 | struct ethtool_pauseparam *ecmd) |
| 3589 | { |
| 3590 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3591 | |
| 3592 | if (ecmd->autoneg == AUTONEG_ENABLE) |
| 3593 | sky2->flags |= SKY2_FLAG_AUTO_PAUSE; |
| 3594 | else |
| 3595 | sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; |
| 3596 | |
| 3597 | sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); |
| 3598 | |
| 3599 | if (netif_running(dev)) |
| 3600 | sky2_phy_reinit(sky2); |
| 3601 | |
| 3602 | return 0; |
| 3603 | } |
| 3604 | |
| 3605 | static int sky2_get_coalesce(struct net_device *dev, |
| 3606 | struct ethtool_coalesce *ecmd) |
| 3607 | { |
| 3608 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3609 | struct sky2_hw *hw = sky2->hw; |
| 3610 | |
| 3611 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) |
| 3612 | ecmd->tx_coalesce_usecs = 0; |
| 3613 | else { |
| 3614 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); |
| 3615 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); |
| 3616 | } |
| 3617 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); |
| 3618 | |
| 3619 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) |
| 3620 | ecmd->rx_coalesce_usecs = 0; |
| 3621 | else { |
| 3622 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); |
| 3623 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); |
| 3624 | } |
| 3625 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); |
| 3626 | |
| 3627 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) |
| 3628 | ecmd->rx_coalesce_usecs_irq = 0; |
| 3629 | else { |
| 3630 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); |
| 3631 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); |
| 3632 | } |
| 3633 | |
| 3634 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); |
| 3635 | |
| 3636 | return 0; |
| 3637 | } |
| 3638 | |
| 3639 | /* Note: this affect both ports */ |
| 3640 | static int sky2_set_coalesce(struct net_device *dev, |
| 3641 | struct ethtool_coalesce *ecmd) |
| 3642 | { |
| 3643 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3644 | struct sky2_hw *hw = sky2->hw; |
| 3645 | const u32 tmax = sky2_clk2us(hw, 0x0ffffff); |
| 3646 | |
| 3647 | if (ecmd->tx_coalesce_usecs > tmax || |
| 3648 | ecmd->rx_coalesce_usecs > tmax || |
| 3649 | ecmd->rx_coalesce_usecs_irq > tmax) |
| 3650 | return -EINVAL; |
| 3651 | |
| 3652 | if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) |
| 3653 | return -EINVAL; |
| 3654 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
| 3655 | return -EINVAL; |
| 3656 | if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING) |
| 3657 | return -EINVAL; |
| 3658 | |
| 3659 | if (ecmd->tx_coalesce_usecs == 0) |
| 3660 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); |
| 3661 | else { |
| 3662 | sky2_write32(hw, STAT_TX_TIMER_INI, |
| 3663 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); |
| 3664 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); |
| 3665 | } |
| 3666 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); |
| 3667 | |
| 3668 | if (ecmd->rx_coalesce_usecs == 0) |
| 3669 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); |
| 3670 | else { |
| 3671 | sky2_write32(hw, STAT_LEV_TIMER_INI, |
| 3672 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); |
| 3673 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); |
| 3674 | } |
| 3675 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); |
| 3676 | |
| 3677 | if (ecmd->rx_coalesce_usecs_irq == 0) |
| 3678 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); |
| 3679 | else { |
| 3680 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
| 3681 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
| 3682 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); |
| 3683 | } |
| 3684 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); |
| 3685 | return 0; |
| 3686 | } |
| 3687 | |
| 3688 | static void sky2_get_ringparam(struct net_device *dev, |
| 3689 | struct ethtool_ringparam *ering) |
| 3690 | { |
| 3691 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3692 | |
| 3693 | ering->rx_max_pending = RX_MAX_PENDING; |
| 3694 | ering->rx_mini_max_pending = 0; |
| 3695 | ering->rx_jumbo_max_pending = 0; |
| 3696 | ering->tx_max_pending = TX_MAX_PENDING; |
| 3697 | |
| 3698 | ering->rx_pending = sky2->rx_pending; |
| 3699 | ering->rx_mini_pending = 0; |
| 3700 | ering->rx_jumbo_pending = 0; |
| 3701 | ering->tx_pending = sky2->tx_pending; |
| 3702 | } |
| 3703 | |
| 3704 | static int sky2_set_ringparam(struct net_device *dev, |
| 3705 | struct ethtool_ringparam *ering) |
| 3706 | { |
| 3707 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3708 | |
| 3709 | if (ering->rx_pending > RX_MAX_PENDING || |
| 3710 | ering->rx_pending < 8 || |
| 3711 | ering->tx_pending < TX_MIN_PENDING || |
| 3712 | ering->tx_pending > TX_MAX_PENDING) |
| 3713 | return -EINVAL; |
| 3714 | |
| 3715 | sky2_detach(dev); |
| 3716 | |
| 3717 | sky2->rx_pending = ering->rx_pending; |
| 3718 | sky2->tx_pending = ering->tx_pending; |
| 3719 | sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1); |
| 3720 | |
| 3721 | return sky2_reattach(dev); |
| 3722 | } |
| 3723 | |
| 3724 | static int sky2_get_regs_len(struct net_device *dev) |
| 3725 | { |
| 3726 | return 0x4000; |
| 3727 | } |
| 3728 | |
| 3729 | /* |
| 3730 | * Returns copy of control register region |
| 3731 | * Note: ethtool_get_regs always provides full size (16k) buffer |
| 3732 | */ |
| 3733 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
| 3734 | void *p) |
| 3735 | { |
| 3736 | const struct sky2_port *sky2 = netdev_priv(dev); |
| 3737 | const void __iomem *io = sky2->hw->regs; |
| 3738 | unsigned int b; |
| 3739 | |
| 3740 | regs->version = 1; |
| 3741 | |
| 3742 | for (b = 0; b < 128; b++) { |
| 3743 | /* This complicated switch statement is to make sure and |
| 3744 | * only access regions that are unreserved. |
| 3745 | * Some blocks are only valid on dual port cards. |
| 3746 | * and block 3 has some special diagnostic registers that |
| 3747 | * are poison. |
| 3748 | */ |
| 3749 | switch (b) { |
| 3750 | case 3: |
| 3751 | /* skip diagnostic ram region */ |
| 3752 | memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); |
| 3753 | break; |
| 3754 | |
| 3755 | /* dual port cards only */ |
| 3756 | case 5: /* Tx Arbiter 2 */ |
| 3757 | case 9: /* RX2 */ |
| 3758 | case 14 ... 15: /* TX2 */ |
| 3759 | case 17: case 19: /* Ram Buffer 2 */ |
| 3760 | case 22 ... 23: /* Tx Ram Buffer 2 */ |
| 3761 | case 25: /* Rx MAC Fifo 1 */ |
| 3762 | case 27: /* Tx MAC Fifo 2 */ |
| 3763 | case 31: /* GPHY 2 */ |
| 3764 | case 40 ... 47: /* Pattern Ram 2 */ |
| 3765 | case 52: case 54: /* TCP Segmentation 2 */ |
| 3766 | case 112 ... 116: /* GMAC 2 */ |
| 3767 | if (sky2->hw->ports == 1) |
| 3768 | goto reserved; |
| 3769 | /* fall through */ |
| 3770 | case 0: /* Control */ |
| 3771 | case 2: /* Mac address */ |
| 3772 | case 4: /* Tx Arbiter 1 */ |
| 3773 | case 7: /* PCI express reg */ |
| 3774 | case 8: /* RX1 */ |
| 3775 | case 12 ... 13: /* TX1 */ |
| 3776 | case 16: case 18:/* Rx Ram Buffer 1 */ |
| 3777 | case 20 ... 21: /* Tx Ram Buffer 1 */ |
| 3778 | case 24: /* Rx MAC Fifo 1 */ |
| 3779 | case 26: /* Tx MAC Fifo 1 */ |
| 3780 | case 28 ... 29: /* Descriptor and status unit */ |
| 3781 | case 30: /* GPHY 1*/ |
| 3782 | case 32 ... 39: /* Pattern Ram 1 */ |
| 3783 | case 48: case 50: /* TCP Segmentation 1 */ |
| 3784 | case 56 ... 60: /* PCI space */ |
| 3785 | case 80 ... 84: /* GMAC 1 */ |
| 3786 | memcpy_fromio(p, io, 128); |
| 3787 | break; |
| 3788 | default: |
| 3789 | reserved: |
| 3790 | memset(p, 0, 128); |
| 3791 | } |
| 3792 | |
| 3793 | p += 128; |
| 3794 | io += 128; |
| 3795 | } |
| 3796 | } |
| 3797 | |
| 3798 | /* In order to do Jumbo packets on these chips, need to turn off the |
| 3799 | * transmit store/forward. Therefore checksum offload won't work. |
| 3800 | */ |
| 3801 | static int no_tx_offload(struct net_device *dev) |
| 3802 | { |
| 3803 | const struct sky2_port *sky2 = netdev_priv(dev); |
| 3804 | const struct sky2_hw *hw = sky2->hw; |
| 3805 | |
| 3806 | return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U; |
| 3807 | } |
| 3808 | |
| 3809 | static int sky2_set_tx_csum(struct net_device *dev, u32 data) |
| 3810 | { |
| 3811 | if (data && no_tx_offload(dev)) |
| 3812 | return -EINVAL; |
| 3813 | |
| 3814 | return ethtool_op_set_tx_csum(dev, data); |
| 3815 | } |
| 3816 | |
| 3817 | |
| 3818 | static int sky2_set_tso(struct net_device *dev, u32 data) |
| 3819 | { |
| 3820 | if (data && no_tx_offload(dev)) |
| 3821 | return -EINVAL; |
| 3822 | |
| 3823 | return ethtool_op_set_tso(dev, data); |
| 3824 | } |
| 3825 | |
| 3826 | static int sky2_get_eeprom_len(struct net_device *dev) |
| 3827 | { |
| 3828 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3829 | struct sky2_hw *hw = sky2->hw; |
| 3830 | u16 reg2; |
| 3831 | |
| 3832 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); |
| 3833 | return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); |
| 3834 | } |
| 3835 | |
| 3836 | static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) |
| 3837 | { |
| 3838 | unsigned long start = jiffies; |
| 3839 | |
| 3840 | while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { |
| 3841 | /* Can take up to 10.6 ms for write */ |
| 3842 | if (time_after(jiffies, start + HZ/4)) { |
| 3843 | dev_err(&hw->pdev->dev, PFX "VPD cycle timed out"); |
| 3844 | return -ETIMEDOUT; |
| 3845 | } |
| 3846 | mdelay(1); |
| 3847 | } |
| 3848 | |
| 3849 | return 0; |
| 3850 | } |
| 3851 | |
| 3852 | static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, |
| 3853 | u16 offset, size_t length) |
| 3854 | { |
| 3855 | int rc = 0; |
| 3856 | |
| 3857 | while (length > 0) { |
| 3858 | u32 val; |
| 3859 | |
| 3860 | sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); |
| 3861 | rc = sky2_vpd_wait(hw, cap, 0); |
| 3862 | if (rc) |
| 3863 | break; |
| 3864 | |
| 3865 | val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); |
| 3866 | |
| 3867 | memcpy(data, &val, min(sizeof(val), length)); |
| 3868 | offset += sizeof(u32); |
| 3869 | data += sizeof(u32); |
| 3870 | length -= sizeof(u32); |
| 3871 | } |
| 3872 | |
| 3873 | return rc; |
| 3874 | } |
| 3875 | |
| 3876 | static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, |
| 3877 | u16 offset, unsigned int length) |
| 3878 | { |
| 3879 | unsigned int i; |
| 3880 | int rc = 0; |
| 3881 | |
| 3882 | for (i = 0; i < length; i += sizeof(u32)) { |
| 3883 | u32 val = *(u32 *)(data + i); |
| 3884 | |
| 3885 | sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); |
| 3886 | sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); |
| 3887 | |
| 3888 | rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); |
| 3889 | if (rc) |
| 3890 | break; |
| 3891 | } |
| 3892 | return rc; |
| 3893 | } |
| 3894 | |
| 3895 | static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, |
| 3896 | u8 *data) |
| 3897 | { |
| 3898 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3899 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); |
| 3900 | |
| 3901 | if (!cap) |
| 3902 | return -EINVAL; |
| 3903 | |
| 3904 | eeprom->magic = SKY2_EEPROM_MAGIC; |
| 3905 | |
| 3906 | return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); |
| 3907 | } |
| 3908 | |
| 3909 | static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, |
| 3910 | u8 *data) |
| 3911 | { |
| 3912 | struct sky2_port *sky2 = netdev_priv(dev); |
| 3913 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); |
| 3914 | |
| 3915 | if (!cap) |
| 3916 | return -EINVAL; |
| 3917 | |
| 3918 | if (eeprom->magic != SKY2_EEPROM_MAGIC) |
| 3919 | return -EINVAL; |
| 3920 | |
| 3921 | /* Partial writes not supported */ |
| 3922 | if ((eeprom->offset & 3) || (eeprom->len & 3)) |
| 3923 | return -EINVAL; |
| 3924 | |
| 3925 | return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); |
| 3926 | } |
| 3927 | |
| 3928 | |
| 3929 | static const struct ethtool_ops sky2_ethtool_ops = { |
| 3930 | .get_settings = sky2_get_settings, |
| 3931 | .set_settings = sky2_set_settings, |
| 3932 | .get_drvinfo = sky2_get_drvinfo, |
| 3933 | .get_wol = sky2_get_wol, |
| 3934 | .set_wol = sky2_set_wol, |
| 3935 | .get_msglevel = sky2_get_msglevel, |
| 3936 | .set_msglevel = sky2_set_msglevel, |
| 3937 | .nway_reset = sky2_nway_reset, |
| 3938 | .get_regs_len = sky2_get_regs_len, |
| 3939 | .get_regs = sky2_get_regs, |
| 3940 | .get_link = ethtool_op_get_link, |
| 3941 | .get_eeprom_len = sky2_get_eeprom_len, |
| 3942 | .get_eeprom = sky2_get_eeprom, |
| 3943 | .set_eeprom = sky2_set_eeprom, |
| 3944 | .set_sg = ethtool_op_set_sg, |
| 3945 | .set_tx_csum = sky2_set_tx_csum, |
| 3946 | .set_tso = sky2_set_tso, |
| 3947 | .get_rx_csum = sky2_get_rx_csum, |
| 3948 | .set_rx_csum = sky2_set_rx_csum, |
| 3949 | .get_strings = sky2_get_strings, |
| 3950 | .get_coalesce = sky2_get_coalesce, |
| 3951 | .set_coalesce = sky2_set_coalesce, |
| 3952 | .get_ringparam = sky2_get_ringparam, |
| 3953 | .set_ringparam = sky2_set_ringparam, |
| 3954 | .get_pauseparam = sky2_get_pauseparam, |
| 3955 | .set_pauseparam = sky2_set_pauseparam, |
| 3956 | .phys_id = sky2_phys_id, |
| 3957 | .get_sset_count = sky2_get_sset_count, |
| 3958 | .get_ethtool_stats = sky2_get_ethtool_stats, |
| 3959 | }; |
| 3960 | |
| 3961 | #ifdef CONFIG_SKY2_DEBUG |
| 3962 | |
| 3963 | static struct dentry *sky2_debug; |
| 3964 | |
| 3965 | |
| 3966 | /* |
| 3967 | * Read and parse the first part of Vital Product Data |
| 3968 | */ |
| 3969 | #define VPD_SIZE 128 |
| 3970 | #define VPD_MAGIC 0x82 |
| 3971 | |
| 3972 | static const struct vpd_tag { |
| 3973 | char tag[2]; |
| 3974 | char *label; |
| 3975 | } vpd_tags[] = { |
| 3976 | { "PN", "Part Number" }, |
| 3977 | { "EC", "Engineering Level" }, |
| 3978 | { "MN", "Manufacturer" }, |
| 3979 | { "SN", "Serial Number" }, |
| 3980 | { "YA", "Asset Tag" }, |
| 3981 | { "VL", "First Error Log Message" }, |
| 3982 | { "VF", "Second Error Log Message" }, |
| 3983 | { "VB", "Boot Agent ROM Configuration" }, |
| 3984 | { "VE", "EFI UNDI Configuration" }, |
| 3985 | }; |
| 3986 | |
| 3987 | static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) |
| 3988 | { |
| 3989 | size_t vpd_size; |
| 3990 | loff_t offs; |
| 3991 | u8 len; |
| 3992 | unsigned char *buf; |
| 3993 | u16 reg2; |
| 3994 | |
| 3995 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); |
| 3996 | vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); |
| 3997 | |
| 3998 | seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); |
| 3999 | buf = kmalloc(vpd_size, GFP_KERNEL); |
| 4000 | if (!buf) { |
| 4001 | seq_puts(seq, "no memory!\n"); |
| 4002 | return; |
| 4003 | } |
| 4004 | |
| 4005 | if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { |
| 4006 | seq_puts(seq, "VPD read failed\n"); |
| 4007 | goto out; |
| 4008 | } |
| 4009 | |
| 4010 | if (buf[0] != VPD_MAGIC) { |
| 4011 | seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); |
| 4012 | goto out; |
| 4013 | } |
| 4014 | len = buf[1]; |
| 4015 | if (len == 0 || len > vpd_size - 4) { |
| 4016 | seq_printf(seq, "Invalid id length: %d\n", len); |
| 4017 | goto out; |
| 4018 | } |
| 4019 | |
| 4020 | seq_printf(seq, "%.*s\n", len, buf + 3); |
| 4021 | offs = len + 3; |
| 4022 | |
| 4023 | while (offs < vpd_size - 4) { |
| 4024 | int i; |
| 4025 | |
| 4026 | if (!memcmp("RW", buf + offs, 2)) /* end marker */ |
| 4027 | break; |
| 4028 | len = buf[offs + 2]; |
| 4029 | if (offs + len + 3 >= vpd_size) |
| 4030 | break; |
| 4031 | |
| 4032 | for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { |
| 4033 | if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { |
| 4034 | seq_printf(seq, " %s: %.*s\n", |
| 4035 | vpd_tags[i].label, len, buf + offs + 3); |
| 4036 | break; |
| 4037 | } |
| 4038 | } |
| 4039 | offs += len + 3; |
| 4040 | } |
| 4041 | out: |
| 4042 | kfree(buf); |
| 4043 | } |
| 4044 | |
| 4045 | static int sky2_debug_show(struct seq_file *seq, void *v) |
| 4046 | { |
| 4047 | struct net_device *dev = seq->private; |
| 4048 | const struct sky2_port *sky2 = netdev_priv(dev); |
| 4049 | struct sky2_hw *hw = sky2->hw; |
| 4050 | unsigned port = sky2->port; |
| 4051 | unsigned idx, last; |
| 4052 | int sop; |
| 4053 | |
| 4054 | sky2_show_vpd(seq, hw); |
| 4055 | |
| 4056 | seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", |
| 4057 | sky2_read32(hw, B0_ISRC), |
| 4058 | sky2_read32(hw, B0_IMSK), |
| 4059 | sky2_read32(hw, B0_Y2_SP_ICR)); |
| 4060 | |
| 4061 | if (!netif_running(dev)) { |
| 4062 | seq_printf(seq, "network not running\n"); |
| 4063 | return 0; |
| 4064 | } |
| 4065 | |
| 4066 | napi_disable(&hw->napi); |
| 4067 | last = sky2_read16(hw, STAT_PUT_IDX); |
| 4068 | |
| 4069 | if (hw->st_idx == last) |
| 4070 | seq_puts(seq, "Status ring (empty)\n"); |
| 4071 | else { |
| 4072 | seq_puts(seq, "Status ring\n"); |
| 4073 | for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE; |
| 4074 | idx = RING_NEXT(idx, STATUS_RING_SIZE)) { |
| 4075 | const struct sky2_status_le *le = hw->st_le + idx; |
| 4076 | seq_printf(seq, "[%d] %#x %d %#x\n", |
| 4077 | idx, le->opcode, le->length, le->status); |
| 4078 | } |
| 4079 | seq_puts(seq, "\n"); |
| 4080 | } |
| 4081 | |
| 4082 | seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", |
| 4083 | sky2->tx_cons, sky2->tx_prod, |
| 4084 | sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), |
| 4085 | sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); |
| 4086 | |
| 4087 | /* Dump contents of tx ring */ |
| 4088 | sop = 1; |
| 4089 | for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; |
| 4090 | idx = RING_NEXT(idx, sky2->tx_ring_size)) { |
| 4091 | const struct sky2_tx_le *le = sky2->tx_le + idx; |
| 4092 | u32 a = le32_to_cpu(le->addr); |
| 4093 | |
| 4094 | if (sop) |
| 4095 | seq_printf(seq, "%u:", idx); |
| 4096 | sop = 0; |
| 4097 | |
| 4098 | switch(le->opcode & ~HW_OWNER) { |
| 4099 | case OP_ADDR64: |
| 4100 | seq_printf(seq, " %#x:", a); |
| 4101 | break; |
| 4102 | case OP_LRGLEN: |
| 4103 | seq_printf(seq, " mtu=%d", a); |
| 4104 | break; |
| 4105 | case OP_VLAN: |
| 4106 | seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); |
| 4107 | break; |
| 4108 | case OP_TCPLISW: |
| 4109 | seq_printf(seq, " csum=%#x", a); |
| 4110 | break; |
| 4111 | case OP_LARGESEND: |
| 4112 | seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); |
| 4113 | break; |
| 4114 | case OP_PACKET: |
| 4115 | seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); |
| 4116 | break; |
| 4117 | case OP_BUFFER: |
| 4118 | seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); |
| 4119 | break; |
| 4120 | default: |
| 4121 | seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, |
| 4122 | a, le16_to_cpu(le->length)); |
| 4123 | } |
| 4124 | |
| 4125 | if (le->ctrl & EOP) { |
| 4126 | seq_putc(seq, '\n'); |
| 4127 | sop = 1; |
| 4128 | } |
| 4129 | } |
| 4130 | |
| 4131 | seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", |
| 4132 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), |
| 4133 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), |
| 4134 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); |
| 4135 | |
| 4136 | sky2_read32(hw, B0_Y2_SP_LISR); |
| 4137 | napi_enable(&hw->napi); |
| 4138 | return 0; |
| 4139 | } |
| 4140 | |
| 4141 | static int sky2_debug_open(struct inode *inode, struct file *file) |
| 4142 | { |
| 4143 | return single_open(file, sky2_debug_show, inode->i_private); |
| 4144 | } |
| 4145 | |
| 4146 | static const struct file_operations sky2_debug_fops = { |
| 4147 | .owner = THIS_MODULE, |
| 4148 | .open = sky2_debug_open, |
| 4149 | .read = seq_read, |
| 4150 | .llseek = seq_lseek, |
| 4151 | .release = single_release, |
| 4152 | }; |
| 4153 | |
| 4154 | /* |
| 4155 | * Use network device events to create/remove/rename |
| 4156 | * debugfs file entries |
| 4157 | */ |
| 4158 | static int sky2_device_event(struct notifier_block *unused, |
| 4159 | unsigned long event, void *ptr) |
| 4160 | { |
| 4161 | struct net_device *dev = ptr; |
| 4162 | struct sky2_port *sky2 = netdev_priv(dev); |
| 4163 | |
| 4164 | if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug) |
| 4165 | return NOTIFY_DONE; |
| 4166 | |
| 4167 | switch(event) { |
| 4168 | case NETDEV_CHANGENAME: |
| 4169 | if (sky2->debugfs) { |
| 4170 | sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, |
| 4171 | sky2_debug, dev->name); |
| 4172 | } |
| 4173 | break; |
| 4174 | |
| 4175 | case NETDEV_GOING_DOWN: |
| 4176 | if (sky2->debugfs) { |
| 4177 | printk(KERN_DEBUG PFX "%s: remove debugfs\n", |
| 4178 | dev->name); |
| 4179 | debugfs_remove(sky2->debugfs); |
| 4180 | sky2->debugfs = NULL; |
| 4181 | } |
| 4182 | break; |
| 4183 | |
| 4184 | case NETDEV_UP: |
| 4185 | sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, |
| 4186 | sky2_debug, dev, |
| 4187 | &sky2_debug_fops); |
| 4188 | if (IS_ERR(sky2->debugfs)) |
| 4189 | sky2->debugfs = NULL; |
| 4190 | } |
| 4191 | |
| 4192 | return NOTIFY_DONE; |
| 4193 | } |
| 4194 | |
| 4195 | static struct notifier_block sky2_notifier = { |
| 4196 | .notifier_call = sky2_device_event, |
| 4197 | }; |
| 4198 | |
| 4199 | |
| 4200 | static __init void sky2_debug_init(void) |
| 4201 | { |
| 4202 | struct dentry *ent; |
| 4203 | |
| 4204 | ent = debugfs_create_dir("sky2", NULL); |
| 4205 | if (!ent || IS_ERR(ent)) |
| 4206 | return; |
| 4207 | |
| 4208 | sky2_debug = ent; |
| 4209 | register_netdevice_notifier(&sky2_notifier); |
| 4210 | } |
| 4211 | |
| 4212 | static __exit void sky2_debug_cleanup(void) |
| 4213 | { |
| 4214 | if (sky2_debug) { |
| 4215 | unregister_netdevice_notifier(&sky2_notifier); |
| 4216 | debugfs_remove(sky2_debug); |
| 4217 | sky2_debug = NULL; |
| 4218 | } |
| 4219 | } |
| 4220 | |
| 4221 | #else |
| 4222 | #define sky2_debug_init() |
| 4223 | #define sky2_debug_cleanup() |
| 4224 | #endif |
| 4225 | |
| 4226 | /* Two copies of network device operations to handle special case of |
| 4227 | not allowing netpoll on second port */ |
| 4228 | static const struct net_device_ops sky2_netdev_ops[2] = { |
| 4229 | { |
| 4230 | .ndo_open = sky2_up, |
| 4231 | .ndo_stop = sky2_down, |
| 4232 | .ndo_start_xmit = sky2_xmit_frame, |
| 4233 | .ndo_do_ioctl = sky2_ioctl, |
| 4234 | .ndo_validate_addr = eth_validate_addr, |
| 4235 | .ndo_set_mac_address = sky2_set_mac_address, |
| 4236 | .ndo_set_multicast_list = sky2_set_multicast, |
| 4237 | .ndo_change_mtu = sky2_change_mtu, |
| 4238 | .ndo_tx_timeout = sky2_tx_timeout, |
| 4239 | #ifdef SKY2_VLAN_TAG_USED |
| 4240 | .ndo_vlan_rx_register = sky2_vlan_rx_register, |
| 4241 | #endif |
| 4242 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 4243 | .ndo_poll_controller = sky2_netpoll, |
| 4244 | #endif |
| 4245 | }, |
| 4246 | { |
| 4247 | .ndo_open = sky2_up, |
| 4248 | .ndo_stop = sky2_down, |
| 4249 | .ndo_start_xmit = sky2_xmit_frame, |
| 4250 | .ndo_do_ioctl = sky2_ioctl, |
| 4251 | .ndo_validate_addr = eth_validate_addr, |
| 4252 | .ndo_set_mac_address = sky2_set_mac_address, |
| 4253 | .ndo_set_multicast_list = sky2_set_multicast, |
| 4254 | .ndo_change_mtu = sky2_change_mtu, |
| 4255 | .ndo_tx_timeout = sky2_tx_timeout, |
| 4256 | #ifdef SKY2_VLAN_TAG_USED |
| 4257 | .ndo_vlan_rx_register = sky2_vlan_rx_register, |
| 4258 | #endif |
| 4259 | }, |
| 4260 | }; |
| 4261 | |
| 4262 | /* Initialize network device */ |
| 4263 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, |
| 4264 | unsigned port, |
| 4265 | int highmem, int wol) |
| 4266 | { |
| 4267 | struct sky2_port *sky2; |
| 4268 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); |
| 4269 | |
| 4270 | if (!dev) { |
| 4271 | dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); |
| 4272 | return NULL; |
| 4273 | } |
| 4274 | |
| 4275 | SET_NETDEV_DEV(dev, &hw->pdev->dev); |
| 4276 | dev->irq = hw->pdev->irq; |
| 4277 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); |
| 4278 | dev->watchdog_timeo = TX_WATCHDOG; |
| 4279 | dev->netdev_ops = &sky2_netdev_ops[port]; |
| 4280 | |
| 4281 | sky2 = netdev_priv(dev); |
| 4282 | sky2->netdev = dev; |
| 4283 | sky2->hw = hw; |
| 4284 | sky2->msg_enable = netif_msg_init(debug, default_msg); |
| 4285 | |
| 4286 | /* Auto speed and flow control */ |
| 4287 | sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; |
| 4288 | if (hw->chip_id != CHIP_ID_YUKON_XL) |
| 4289 | sky2->flags |= SKY2_FLAG_RX_CHECKSUM; |
| 4290 | |
| 4291 | sky2->flow_mode = FC_BOTH; |
| 4292 | |
| 4293 | sky2->duplex = -1; |
| 4294 | sky2->speed = -1; |
| 4295 | sky2->advertising = sky2_supported_modes(hw); |
| 4296 | sky2->wol = wol; |
| 4297 | |
| 4298 | spin_lock_init(&sky2->phy_lock); |
| 4299 | |
| 4300 | sky2->tx_pending = TX_DEF_PENDING; |
| 4301 | sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1); |
| 4302 | sky2->rx_pending = RX_DEF_PENDING; |
| 4303 | |
| 4304 | hw->dev[port] = dev; |
| 4305 | |
| 4306 | sky2->port = port; |
| 4307 | |
| 4308 | dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG; |
| 4309 | if (highmem) |
| 4310 | dev->features |= NETIF_F_HIGHDMA; |
| 4311 | |
| 4312 | #ifdef SKY2_VLAN_TAG_USED |
| 4313 | /* The workaround for FE+ status conflicts with VLAN tag detection. */ |
| 4314 | if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && |
| 4315 | sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) { |
| 4316 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
| 4317 | } |
| 4318 | #endif |
| 4319 | |
| 4320 | /* read the mac address */ |
| 4321 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
| 4322 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
| 4323 | |
| 4324 | return dev; |
| 4325 | } |
| 4326 | |
| 4327 | static void __devinit sky2_show_addr(struct net_device *dev) |
| 4328 | { |
| 4329 | const struct sky2_port *sky2 = netdev_priv(dev); |
| 4330 | |
| 4331 | if (netif_msg_probe(sky2)) |
| 4332 | printk(KERN_INFO PFX "%s: addr %pM\n", |
| 4333 | dev->name, dev->dev_addr); |
| 4334 | } |
| 4335 | |
| 4336 | /* Handle software interrupt used during MSI test */ |
| 4337 | static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id) |
| 4338 | { |
| 4339 | struct sky2_hw *hw = dev_id; |
| 4340 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); |
| 4341 | |
| 4342 | if (status == 0) |
| 4343 | return IRQ_NONE; |
| 4344 | |
| 4345 | if (status & Y2_IS_IRQ_SW) { |
| 4346 | hw->flags |= SKY2_HW_USE_MSI; |
| 4347 | wake_up(&hw->msi_wait); |
| 4348 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); |
| 4349 | } |
| 4350 | sky2_write32(hw, B0_Y2_SP_ICR, 2); |
| 4351 | |
| 4352 | return IRQ_HANDLED; |
| 4353 | } |
| 4354 | |
| 4355 | /* Test interrupt path by forcing a a software IRQ */ |
| 4356 | static int __devinit sky2_test_msi(struct sky2_hw *hw) |
| 4357 | { |
| 4358 | struct pci_dev *pdev = hw->pdev; |
| 4359 | int err; |
| 4360 | |
| 4361 | init_waitqueue_head (&hw->msi_wait); |
| 4362 | |
| 4363 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); |
| 4364 | |
| 4365 | err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); |
| 4366 | if (err) { |
| 4367 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); |
| 4368 | return err; |
| 4369 | } |
| 4370 | |
| 4371 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); |
| 4372 | sky2_read8(hw, B0_CTST); |
| 4373 | |
| 4374 | wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); |
| 4375 | |
| 4376 | if (!(hw->flags & SKY2_HW_USE_MSI)) { |
| 4377 | /* MSI test failed, go back to INTx mode */ |
| 4378 | dev_info(&pdev->dev, "No interrupt generated using MSI, " |
| 4379 | "switching to INTx mode.\n"); |
| 4380 | |
| 4381 | err = -EOPNOTSUPP; |
| 4382 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); |
| 4383 | } |
| 4384 | |
| 4385 | sky2_write32(hw, B0_IMSK, 0); |
| 4386 | sky2_read32(hw, B0_IMSK); |
| 4387 | |
| 4388 | free_irq(pdev->irq, hw); |
| 4389 | |
| 4390 | return err; |
| 4391 | } |
| 4392 | |
| 4393 | /* This driver supports yukon2 chipset only */ |
| 4394 | static const char *sky2_name(u8 chipid, char *buf, int sz) |
| 4395 | { |
| 4396 | const char *name[] = { |
| 4397 | "XL", /* 0xb3 */ |
| 4398 | "EC Ultra", /* 0xb4 */ |
| 4399 | "Extreme", /* 0xb5 */ |
| 4400 | "EC", /* 0xb6 */ |
| 4401 | "FE", /* 0xb7 */ |
| 4402 | "FE+", /* 0xb8 */ |
| 4403 | "Supreme", /* 0xb9 */ |
| 4404 | "UL 2", /* 0xba */ |
| 4405 | }; |
| 4406 | |
| 4407 | if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2) |
| 4408 | strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); |
| 4409 | else |
| 4410 | snprintf(buf, sz, "(chip %#x)", chipid); |
| 4411 | return buf; |
| 4412 | } |
| 4413 | |
| 4414 | static int __devinit sky2_probe(struct pci_dev *pdev, |
| 4415 | const struct pci_device_id *ent) |
| 4416 | { |
| 4417 | struct net_device *dev; |
| 4418 | struct sky2_hw *hw; |
| 4419 | int err, using_dac = 0, wol_default; |
| 4420 | u32 reg; |
| 4421 | char buf1[16]; |
| 4422 | |
| 4423 | err = pci_enable_device(pdev); |
| 4424 | if (err) { |
| 4425 | dev_err(&pdev->dev, "cannot enable PCI device\n"); |
| 4426 | goto err_out; |
| 4427 | } |
| 4428 | |
| 4429 | /* Get configuration information |
| 4430 | * Note: only regular PCI config access once to test for HW issues |
| 4431 | * other PCI access through shared memory for speed and to |
| 4432 | * avoid MMCONFIG problems. |
| 4433 | */ |
| 4434 | err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); |
| 4435 | if (err) { |
| 4436 | dev_err(&pdev->dev, "PCI read config failed\n"); |
| 4437 | goto err_out; |
| 4438 | } |
| 4439 | |
| 4440 | if (~reg == 0) { |
| 4441 | dev_err(&pdev->dev, "PCI configuration read error\n"); |
| 4442 | goto err_out; |
| 4443 | } |
| 4444 | |
| 4445 | err = pci_request_regions(pdev, DRV_NAME); |
| 4446 | if (err) { |
| 4447 | dev_err(&pdev->dev, "cannot obtain PCI resources\n"); |
| 4448 | goto err_out_disable; |
| 4449 | } |
| 4450 | |
| 4451 | pci_set_master(pdev); |
| 4452 | |
| 4453 | if (sizeof(dma_addr_t) > sizeof(u32) && |
| 4454 | !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { |
| 4455 | using_dac = 1; |
| 4456 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
| 4457 | if (err < 0) { |
| 4458 | dev_err(&pdev->dev, "unable to obtain 64 bit DMA " |
| 4459 | "for consistent allocations\n"); |
| 4460 | goto err_out_free_regions; |
| 4461 | } |
| 4462 | } else { |
| 4463 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
| 4464 | if (err) { |
| 4465 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
| 4466 | goto err_out_free_regions; |
| 4467 | } |
| 4468 | } |
| 4469 | |
| 4470 | |
| 4471 | #ifdef __BIG_ENDIAN |
| 4472 | /* The sk98lin vendor driver uses hardware byte swapping but |
| 4473 | * this driver uses software swapping. |
| 4474 | */ |
| 4475 | reg &= ~PCI_REV_DESC; |
| 4476 | err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg); |
| 4477 | if (err) { |
| 4478 | dev_err(&pdev->dev, "PCI write config failed\n"); |
| 4479 | goto err_out_free_regions; |
| 4480 | } |
| 4481 | #endif |
| 4482 | |
| 4483 | wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; |
| 4484 | |
| 4485 | err = -ENOMEM; |
| 4486 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
| 4487 | if (!hw) { |
| 4488 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); |
| 4489 | goto err_out_free_regions; |
| 4490 | } |
| 4491 | |
| 4492 | hw->pdev = pdev; |
| 4493 | |
| 4494 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); |
| 4495 | if (!hw->regs) { |
| 4496 | dev_err(&pdev->dev, "cannot map device registers\n"); |
| 4497 | goto err_out_free_hw; |
| 4498 | } |
| 4499 | |
| 4500 | /* ring for status responses */ |
| 4501 | hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma); |
| 4502 | if (!hw->st_le) |
| 4503 | goto err_out_iounmap; |
| 4504 | |
| 4505 | err = sky2_init(hw); |
| 4506 | if (err) |
| 4507 | goto err_out_iounmap; |
| 4508 | |
| 4509 | dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", |
| 4510 | sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); |
| 4511 | |
| 4512 | sky2_reset(hw); |
| 4513 | |
| 4514 | dev = sky2_init_netdev(hw, 0, using_dac, wol_default); |
| 4515 | if (!dev) { |
| 4516 | err = -ENOMEM; |
| 4517 | goto err_out_free_pci; |
| 4518 | } |
| 4519 | |
| 4520 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
| 4521 | err = sky2_test_msi(hw); |
| 4522 | if (err == -EOPNOTSUPP) |
| 4523 | pci_disable_msi(pdev); |
| 4524 | else if (err) |
| 4525 | goto err_out_free_netdev; |
| 4526 | } |
| 4527 | |
| 4528 | err = register_netdev(dev); |
| 4529 | if (err) { |
| 4530 | dev_err(&pdev->dev, "cannot register net device\n"); |
| 4531 | goto err_out_free_netdev; |
| 4532 | } |
| 4533 | |
| 4534 | netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); |
| 4535 | |
| 4536 | err = request_irq(pdev->irq, sky2_intr, |
| 4537 | (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, |
| 4538 | dev->name, hw); |
| 4539 | if (err) { |
| 4540 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); |
| 4541 | goto err_out_unregister; |
| 4542 | } |
| 4543 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |
| 4544 | napi_enable(&hw->napi); |
| 4545 | |
| 4546 | sky2_show_addr(dev); |
| 4547 | |
| 4548 | if (hw->ports > 1) { |
| 4549 | struct net_device *dev1; |
| 4550 | |
| 4551 | dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); |
| 4552 | if (!dev1) |
| 4553 | dev_warn(&pdev->dev, "allocation for second device failed\n"); |
| 4554 | else if ((err = register_netdev(dev1))) { |
| 4555 | dev_warn(&pdev->dev, |
| 4556 | "register of second port failed (%d)\n", err); |
| 4557 | hw->dev[1] = NULL; |
| 4558 | free_netdev(dev1); |
| 4559 | } else |
| 4560 | sky2_show_addr(dev1); |
| 4561 | } |
| 4562 | |
| 4563 | setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); |
| 4564 | INIT_WORK(&hw->restart_work, sky2_restart); |
| 4565 | |
| 4566 | pci_set_drvdata(pdev, hw); |
| 4567 | |
| 4568 | return 0; |
| 4569 | |
| 4570 | err_out_unregister: |
| 4571 | if (hw->flags & SKY2_HW_USE_MSI) |
| 4572 | pci_disable_msi(pdev); |
| 4573 | unregister_netdev(dev); |
| 4574 | err_out_free_netdev: |
| 4575 | free_netdev(dev); |
| 4576 | err_out_free_pci: |
| 4577 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
| 4578 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
| 4579 | err_out_iounmap: |
| 4580 | iounmap(hw->regs); |
| 4581 | err_out_free_hw: |
| 4582 | kfree(hw); |
| 4583 | err_out_free_regions: |
| 4584 | pci_release_regions(pdev); |
| 4585 | err_out_disable: |
| 4586 | pci_disable_device(pdev); |
| 4587 | err_out: |
| 4588 | pci_set_drvdata(pdev, NULL); |
| 4589 | return err; |
| 4590 | } |
| 4591 | |
| 4592 | static void __devexit sky2_remove(struct pci_dev *pdev) |
| 4593 | { |
| 4594 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
| 4595 | int i; |
| 4596 | |
| 4597 | if (!hw) |
| 4598 | return; |
| 4599 | |
| 4600 | del_timer_sync(&hw->watchdog_timer); |
| 4601 | cancel_work_sync(&hw->restart_work); |
| 4602 | |
| 4603 | for (i = hw->ports-1; i >= 0; --i) |
| 4604 | unregister_netdev(hw->dev[i]); |
| 4605 | |
| 4606 | sky2_write32(hw, B0_IMSK, 0); |
| 4607 | |
| 4608 | sky2_power_aux(hw); |
| 4609 | |
| 4610 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
| 4611 | sky2_read8(hw, B0_CTST); |
| 4612 | |
| 4613 | free_irq(pdev->irq, hw); |
| 4614 | if (hw->flags & SKY2_HW_USE_MSI) |
| 4615 | pci_disable_msi(pdev); |
| 4616 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
| 4617 | pci_release_regions(pdev); |
| 4618 | pci_disable_device(pdev); |
| 4619 | |
| 4620 | for (i = hw->ports-1; i >= 0; --i) |
| 4621 | free_netdev(hw->dev[i]); |
| 4622 | |
| 4623 | iounmap(hw->regs); |
| 4624 | kfree(hw); |
| 4625 | |
| 4626 | pci_set_drvdata(pdev, NULL); |
| 4627 | } |
| 4628 | |
| 4629 | #ifdef CONFIG_PM |
| 4630 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) |
| 4631 | { |
| 4632 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
| 4633 | int i, wol = 0; |
| 4634 | |
| 4635 | if (!hw) |
| 4636 | return 0; |
| 4637 | |
| 4638 | del_timer_sync(&hw->watchdog_timer); |
| 4639 | cancel_work_sync(&hw->restart_work); |
| 4640 | |
| 4641 | rtnl_lock(); |
| 4642 | for (i = 0; i < hw->ports; i++) { |
| 4643 | struct net_device *dev = hw->dev[i]; |
| 4644 | struct sky2_port *sky2 = netdev_priv(dev); |
| 4645 | |
| 4646 | sky2_detach(dev); |
| 4647 | |
| 4648 | if (sky2->wol) |
| 4649 | sky2_wol_init(sky2); |
| 4650 | |
| 4651 | wol |= sky2->wol; |
| 4652 | } |
| 4653 | |
| 4654 | sky2_write32(hw, B0_IMSK, 0); |
| 4655 | napi_disable(&hw->napi); |
| 4656 | sky2_power_aux(hw); |
| 4657 | rtnl_unlock(); |
| 4658 | |
| 4659 | pci_save_state(pdev); |
| 4660 | pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); |
| 4661 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
| 4662 | |
| 4663 | return 0; |
| 4664 | } |
| 4665 | |
| 4666 | static int sky2_resume(struct pci_dev *pdev) |
| 4667 | { |
| 4668 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
| 4669 | int i, err; |
| 4670 | |
| 4671 | if (!hw) |
| 4672 | return 0; |
| 4673 | |
| 4674 | err = pci_set_power_state(pdev, PCI_D0); |
| 4675 | if (err) |
| 4676 | goto out; |
| 4677 | |
| 4678 | err = pci_restore_state(pdev); |
| 4679 | if (err) |
| 4680 | goto out; |
| 4681 | |
| 4682 | pci_enable_wake(pdev, PCI_D0, 0); |
| 4683 | |
| 4684 | /* Re-enable all clocks */ |
| 4685 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
| 4686 | hw->chip_id == CHIP_ID_YUKON_EC_U || |
| 4687 | hw->chip_id == CHIP_ID_YUKON_FE_P) |
| 4688 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
| 4689 | |
| 4690 | sky2_reset(hw); |
| 4691 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |
| 4692 | napi_enable(&hw->napi); |
| 4693 | |
| 4694 | rtnl_lock(); |
| 4695 | for (i = 0; i < hw->ports; i++) { |
| 4696 | err = sky2_reattach(hw->dev[i]); |
| 4697 | if (err) |
| 4698 | goto out; |
| 4699 | } |
| 4700 | rtnl_unlock(); |
| 4701 | |
| 4702 | return 0; |
| 4703 | out: |
| 4704 | rtnl_unlock(); |
| 4705 | |
| 4706 | dev_err(&pdev->dev, "resume failed (%d)\n", err); |
| 4707 | pci_disable_device(pdev); |
| 4708 | return err; |
| 4709 | } |
| 4710 | #endif |
| 4711 | |
| 4712 | static void sky2_shutdown(struct pci_dev *pdev) |
| 4713 | { |
| 4714 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
| 4715 | int i, wol = 0; |
| 4716 | |
| 4717 | if (!hw) |
| 4718 | return; |
| 4719 | |
| 4720 | rtnl_lock(); |
| 4721 | del_timer_sync(&hw->watchdog_timer); |
| 4722 | |
| 4723 | for (i = 0; i < hw->ports; i++) { |
| 4724 | struct net_device *dev = hw->dev[i]; |
| 4725 | struct sky2_port *sky2 = netdev_priv(dev); |
| 4726 | |
| 4727 | if (sky2->wol) { |
| 4728 | wol = 1; |
| 4729 | sky2_wol_init(sky2); |
| 4730 | } |
| 4731 | } |
| 4732 | |
| 4733 | if (wol) |
| 4734 | sky2_power_aux(hw); |
| 4735 | rtnl_unlock(); |
| 4736 | |
| 4737 | pci_enable_wake(pdev, PCI_D3hot, wol); |
| 4738 | pci_enable_wake(pdev, PCI_D3cold, wol); |
| 4739 | |
| 4740 | pci_disable_device(pdev); |
| 4741 | pci_set_power_state(pdev, PCI_D3hot); |
| 4742 | } |
| 4743 | |
| 4744 | static struct pci_driver sky2_driver = { |
| 4745 | .name = DRV_NAME, |
| 4746 | .id_table = sky2_id_table, |
| 4747 | .probe = sky2_probe, |
| 4748 | .remove = __devexit_p(sky2_remove), |
| 4749 | #ifdef CONFIG_PM |
| 4750 | .suspend = sky2_suspend, |
| 4751 | .resume = sky2_resume, |
| 4752 | #endif |
| 4753 | .shutdown = sky2_shutdown, |
| 4754 | }; |
| 4755 | |
| 4756 | static int __init sky2_init_module(void) |
| 4757 | { |
| 4758 | pr_info(PFX "driver version " DRV_VERSION "\n"); |
| 4759 | |
| 4760 | sky2_debug_init(); |
| 4761 | return pci_register_driver(&sky2_driver); |
| 4762 | } |
| 4763 | |
| 4764 | static void __exit sky2_cleanup_module(void) |
| 4765 | { |
| 4766 | pci_unregister_driver(&sky2_driver); |
| 4767 | sky2_debug_cleanup(); |
| 4768 | } |
| 4769 | |
| 4770 | module_init(sky2_init_module); |
| 4771 | module_exit(sky2_cleanup_module); |
| 4772 | |
| 4773 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); |
| 4774 | MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); |
| 4775 | MODULE_LICENSE("GPL"); |
| 4776 | MODULE_VERSION(DRV_VERSION); |