projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
sfc: Fix return value from efx_ethtool_set_rx_ntuple()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sfc / efx.c
... / ...
CommitLineData
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2011 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
20#include <linux/crc32.h>
21#include <linux/ethtool.h>
22#include <linux/topology.h>
23#include <linux/gfp.h>
24#include <linux/cpu_rmap.h>
25#include "net_driver.h"
26#include "efx.h"
27#include "nic.h"
28
29#include "mcdi.h"
30#include "workarounds.h"
31
32/**************************************************************************
33 *
34 * Type name strings
35 *
36 **************************************************************************
37 */
38
39/* Loopback mode names (see LOOPBACK_MODE()) */
40const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
41const char *efx_loopback_mode_names[] = {
42 [LOOPBACK_NONE] = "NONE",
43 [LOOPBACK_DATA] = "DATAPATH",
44 [LOOPBACK_GMAC] = "GMAC",
45 [LOOPBACK_XGMII] = "XGMII",
46 [LOOPBACK_XGXS] = "XGXS",
47 [LOOPBACK_XAUI] = "XAUI",
48 [LOOPBACK_GMII] = "GMII",
49 [LOOPBACK_SGMII] = "SGMII",
50 [LOOPBACK_XGBR] = "XGBR",
51 [LOOPBACK_XFI] = "XFI",
52 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
53 [LOOPBACK_GMII_FAR] = "GMII_FAR",
54 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
55 [LOOPBACK_XFI_FAR] = "XFI_FAR",
56 [LOOPBACK_GPHY] = "GPHY",
57 [LOOPBACK_PHYXS] = "PHYXS",
58 [LOOPBACK_PCS] = "PCS",
59 [LOOPBACK_PMAPMD] = "PMA/PMD",
60 [LOOPBACK_XPORT] = "XPORT",
61 [LOOPBACK_XGMII_WS] = "XGMII_WS",
62 [LOOPBACK_XAUI_WS] = "XAUI_WS",
63 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
64 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
65 [LOOPBACK_GMII_WS] = "GMII_WS",
66 [LOOPBACK_XFI_WS] = "XFI_WS",
67 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
68 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
69};
70
71const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
72const char *efx_reset_type_names[] = {
73 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
74 [RESET_TYPE_ALL] = "ALL",
75 [RESET_TYPE_WORLD] = "WORLD",
76 [RESET_TYPE_DISABLE] = "DISABLE",
77 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
78 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
79 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
80 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH",
81 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH",
82 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
83 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
84};
85
86#define EFX_MAX_MTU (9 * 1024)
87
88/* Reset workqueue. If any NIC has a hardware failure then a reset will be
89 * queued onto this work queue. This is not a per-nic work queue, because
90 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
91 */
92static struct workqueue_struct *reset_workqueue;
93
94/**************************************************************************
95 *
96 * Configurable values
97 *
98 *************************************************************************/
99
100/*
101 * Use separate channels for TX and RX events
102 *
103 * Set this to 1 to use separate channels for TX and RX. It allows us
104 * to control interrupt affinity separately for TX and RX.
105 *
106 * This is only used in MSI-X interrupt mode
107 */
108static unsigned int separate_tx_channels;
109module_param(separate_tx_channels, uint, 0444);
110MODULE_PARM_DESC(separate_tx_channels,
111 "Use separate channels for TX and RX");
112
113/* This is the weight assigned to each of the (per-channel) virtual
114 * NAPI devices.
115 */
116static int napi_weight = 64;
117
118/* This is the time (in jiffies) between invocations of the hardware
119 * monitor. On Falcon-based NICs, this will:
120 * - Check the on-board hardware monitor;
121 * - Poll the link state and reconfigure the hardware as necessary.
122 */
123static unsigned int efx_monitor_interval = 1 * HZ;
124
125/* This controls whether or not the driver will initialise devices
126 * with invalid MAC addresses stored in the EEPROM or flash. If true,
127 * such devices will be initialised with a random locally-generated
128 * MAC address. This allows for loading the sfc_mtd driver to
129 * reprogram the flash, even if the flash contents (including the MAC
130 * address) have previously been erased.
131 */
132static unsigned int allow_bad_hwaddr;
133
134/* Initial interrupt moderation settings. They can be modified after
135 * module load with ethtool.
136 *
137 * The default for RX should strike a balance between increasing the
138 * round-trip latency and reducing overhead.
139 */
140static unsigned int rx_irq_mod_usec = 60;
141
142/* Initial interrupt moderation settings. They can be modified after
143 * module load with ethtool.
144 *
145 * This default is chosen to ensure that a 10G link does not go idle
146 * while a TX queue is stopped after it has become full. A queue is
147 * restarted when it drops below half full. The time this takes (assuming
148 * worst case 3 descriptors per packet and 1024 descriptors) is
149 * 512 / 3 * 1.2 = 205 usec.
150 */
151static unsigned int tx_irq_mod_usec = 150;
152
153/* This is the first interrupt mode to try out of:
154 * 0 => MSI-X
155 * 1 => MSI
156 * 2 => legacy
157 */
158static unsigned int interrupt_mode;
159
160/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
161 * i.e. the number of CPUs among which we may distribute simultaneous
162 * interrupt handling.
163 *
164 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
165 * The default (0) means to assign an interrupt to each package (level II cache)
166 */
167static unsigned int rss_cpus;
168module_param(rss_cpus, uint, 0444);
169MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
170
171static int phy_flash_cfg;
172module_param(phy_flash_cfg, int, 0644);
173MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
174
175static unsigned irq_adapt_low_thresh = 10000;
176module_param(irq_adapt_low_thresh, uint, 0644);
177MODULE_PARM_DESC(irq_adapt_low_thresh,
178 "Threshold score for reducing IRQ moderation");
179
180static unsigned irq_adapt_high_thresh = 20000;
181module_param(irq_adapt_high_thresh, uint, 0644);
182MODULE_PARM_DESC(irq_adapt_high_thresh,
183 "Threshold score for increasing IRQ moderation");
184
185static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
186 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
187 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
188 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
189module_param(debug, uint, 0);
190MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
191
192/**************************************************************************
193 *
194 * Utility functions and prototypes
195 *
196 *************************************************************************/
197
198static void efx_remove_channels(struct efx_nic *efx);
199static void efx_remove_port(struct efx_nic *efx);
200static void efx_init_napi(struct efx_nic *efx);
201static void efx_fini_napi(struct efx_nic *efx);
202static void efx_fini_napi_channel(struct efx_channel *channel);
203static void efx_fini_struct(struct efx_nic *efx);
204static void efx_start_all(struct efx_nic *efx);
205static void efx_stop_all(struct efx_nic *efx);
206
207#define EFX_ASSERT_RESET_SERIALISED(efx) \
208 do { \
209 if ((efx->state == STATE_RUNNING) || \
210 (efx->state == STATE_DISABLED)) \
211 ASSERT_RTNL(); \
212 } while (0)
213
214/**************************************************************************
215 *
216 * Event queue processing
217 *
218 *************************************************************************/
219
220/* Process channel's event queue
221 *
222 * This function is responsible for processing the event queue of a
223 * single channel. The caller must guarantee that this function will
224 * never be concurrently called more than once on the same channel,
225 * though different channels may be being processed concurrently.
226 */
227static int efx_process_channel(struct efx_channel *channel, int budget)
228{
229 struct efx_nic *efx = channel->efx;
230 int spent;
231
232 if (unlikely(efx->reset_pending != RESET_TYPE_NONE ||
233 !channel->enabled))
234 return 0;
235
236 spent = efx_nic_process_eventq(channel, budget);
237 if (spent == 0)
238 return 0;
239
240 /* Deliver last RX packet. */
241 if (channel->rx_pkt) {
242 __efx_rx_packet(channel, channel->rx_pkt,
243 channel->rx_pkt_csummed);
244 channel->rx_pkt = NULL;
245 }
246
247 efx_rx_strategy(channel);
248
249 efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel));
250
251 return spent;
252}
253
254/* Mark channel as finished processing
255 *
256 * Note that since we will not receive further interrupts for this
257 * channel before we finish processing and call the eventq_read_ack()
258 * method, there is no need to use the interrupt hold-off timers.
259 */
260static inline void efx_channel_processed(struct efx_channel *channel)
261{
262 /* The interrupt handler for this channel may set work_pending
263 * as soon as we acknowledge the events we've seen. Make sure
264 * it's cleared before then. */
265 channel->work_pending = false;
266 smp_wmb();
267
268 efx_nic_eventq_read_ack(channel);
269}
270
271/* NAPI poll handler
272 *
273 * NAPI guarantees serialisation of polls of the same device, which
274 * provides the guarantee required by efx_process_channel().
275 */
276static int efx_poll(struct napi_struct *napi, int budget)
277{
278 struct efx_channel *channel =
279 container_of(napi, struct efx_channel, napi_str);
280 struct efx_nic *efx = channel->efx;
281 int spent;
282
283 netif_vdbg(efx, intr, efx->net_dev,
284 "channel %d NAPI poll executing on CPU %d\n",
285 channel->channel, raw_smp_processor_id());
286
287 spent = efx_process_channel(channel, budget);
288
289 if (spent < budget) {
290 if (channel->channel < efx->n_rx_channels &&
291 efx->irq_rx_adaptive &&
292 unlikely(++channel->irq_count == 1000)) {
293 if (unlikely(channel->irq_mod_score <
294 irq_adapt_low_thresh)) {
295 if (channel->irq_moderation > 1) {
296 channel->irq_moderation -= 1;
297 efx->type->push_irq_moderation(channel);
298 }
299 } else if (unlikely(channel->irq_mod_score >
300 irq_adapt_high_thresh)) {
301 if (channel->irq_moderation <
302 efx->irq_rx_moderation) {
303 channel->irq_moderation += 1;
304 efx->type->push_irq_moderation(channel);
305 }
306 }
307 channel->irq_count = 0;
308 channel->irq_mod_score = 0;
309 }
310
311 efx_filter_rfs_expire(channel);
312
313 /* There is no race here; although napi_disable() will
314 * only wait for napi_complete(), this isn't a problem
315 * since efx_channel_processed() will have no effect if
316 * interrupts have already been disabled.
317 */
318 napi_complete(napi);
319 efx_channel_processed(channel);
320 }
321
322 return spent;
323}
324
325/* Process the eventq of the specified channel immediately on this CPU
326 *
327 * Disable hardware generated interrupts, wait for any existing
328 * processing to finish, then directly poll (and ack ) the eventq.
329 * Finally reenable NAPI and interrupts.
330 *
331 * This is for use only during a loopback self-test. It must not
332 * deliver any packets up the stack as this can result in deadlock.
333 */
334void efx_process_channel_now(struct efx_channel *channel)
335{
336 struct efx_nic *efx = channel->efx;
337
338 BUG_ON(channel->channel >= efx->n_channels);
339 BUG_ON(!channel->enabled);
340 BUG_ON(!efx->loopback_selftest);
341
342 /* Disable interrupts and wait for ISRs to complete */
343 efx_nic_disable_interrupts(efx);
344 if (efx->legacy_irq) {
345 synchronize_irq(efx->legacy_irq);
346 efx->legacy_irq_enabled = false;
347 }
348 if (channel->irq)
349 synchronize_irq(channel->irq);
350
351 /* Wait for any NAPI processing to complete */
352 napi_disable(&channel->napi_str);
353
354 /* Poll the channel */
355 efx_process_channel(channel, channel->eventq_mask + 1);
356
357 /* Ack the eventq. This may cause an interrupt to be generated
358 * when they are reenabled */
359 efx_channel_processed(channel);
360
361 napi_enable(&channel->napi_str);
362 if (efx->legacy_irq)
363 efx->legacy_irq_enabled = true;
364 efx_nic_enable_interrupts(efx);
365}
366
367/* Create event queue
368 * Event queue memory allocations are done only once. If the channel
369 * is reset, the memory buffer will be reused; this guards against
370 * errors during channel reset and also simplifies interrupt handling.
371 */
372static int efx_probe_eventq(struct efx_channel *channel)
373{
374 struct efx_nic *efx = channel->efx;
375 unsigned long entries;
376
377 netif_dbg(channel->efx, probe, channel->efx->net_dev,
378 "chan %d create event queue\n", channel->channel);
379
380 /* Build an event queue with room for one event per tx and rx buffer,
381 * plus some extra for link state events and MCDI completions. */
382 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
383 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
384 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
385
386 return efx_nic_probe_eventq(channel);
387}
388
389/* Prepare channel's event queue */
390static void efx_init_eventq(struct efx_channel *channel)
391{
392 netif_dbg(channel->efx, drv, channel->efx->net_dev,
393 "chan %d init event queue\n", channel->channel);
394
395 channel->eventq_read_ptr = 0;
396
397 efx_nic_init_eventq(channel);
398}
399
400static void efx_fini_eventq(struct efx_channel *channel)
401{
402 netif_dbg(channel->efx, drv, channel->efx->net_dev,
403 "chan %d fini event queue\n", channel->channel);
404
405 efx_nic_fini_eventq(channel);
406}
407
408static void efx_remove_eventq(struct efx_channel *channel)
409{
410 netif_dbg(channel->efx, drv, channel->efx->net_dev,
411 "chan %d remove event queue\n", channel->channel);
412
413 efx_nic_remove_eventq(channel);
414}
415
416/**************************************************************************
417 *
418 * Channel handling
419 *
420 *************************************************************************/
421
422/* Allocate and initialise a channel structure, optionally copying
423 * parameters (but not resources) from an old channel structure. */
424static struct efx_channel *
425efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
426{
427 struct efx_channel *channel;
428 struct efx_rx_queue *rx_queue;
429 struct efx_tx_queue *tx_queue;
430 int j;
431
432 if (old_channel) {
433 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
434 if (!channel)
435 return NULL;
436
437 *channel = *old_channel;
438
439 channel->napi_dev = NULL;
440 memset(&channel->eventq, 0, sizeof(channel->eventq));
441
442 rx_queue = &channel->rx_queue;
443 rx_queue->buffer = NULL;
444 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
445
446 for (j = 0; j < EFX_TXQ_TYPES; j++) {
447 tx_queue = &channel->tx_queue[j];
448 if (tx_queue->channel)
449 tx_queue->channel = channel;
450 tx_queue->buffer = NULL;
451 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
452 }
453 } else {
454 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
455 if (!channel)
456 return NULL;
457
458 channel->efx = efx;
459 channel->channel = i;
460
461 for (j = 0; j < EFX_TXQ_TYPES; j++) {
462 tx_queue = &channel->tx_queue[j];
463 tx_queue->efx = efx;
464 tx_queue->queue = i * EFX_TXQ_TYPES + j;
465 tx_queue->channel = channel;
466 }
467 }
468
469 rx_queue = &channel->rx_queue;
470 rx_queue->efx = efx;
471 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
472 (unsigned long)rx_queue);
473
474 return channel;
475}
476
477static int efx_probe_channel(struct efx_channel *channel)
478{
479 struct efx_tx_queue *tx_queue;
480 struct efx_rx_queue *rx_queue;
481 int rc;
482
483 netif_dbg(channel->efx, probe, channel->efx->net_dev,
484 "creating channel %d\n", channel->channel);
485
486 rc = efx_probe_eventq(channel);
487 if (rc)
488 goto fail1;
489
490 efx_for_each_channel_tx_queue(tx_queue, channel) {
491 rc = efx_probe_tx_queue(tx_queue);
492 if (rc)
493 goto fail2;
494 }
495
496 efx_for_each_channel_rx_queue(rx_queue, channel) {
497 rc = efx_probe_rx_queue(rx_queue);
498 if (rc)
499 goto fail3;
500 }
501
502 channel->n_rx_frm_trunc = 0;
503
504 return 0;
505
506 fail3:
507 efx_for_each_channel_rx_queue(rx_queue, channel)
508 efx_remove_rx_queue(rx_queue);
509 fail2:
510 efx_for_each_channel_tx_queue(tx_queue, channel)
511 efx_remove_tx_queue(tx_queue);
512 fail1:
513 return rc;
514}
515
516
517static void efx_set_channel_names(struct efx_nic *efx)
518{
519 struct efx_channel *channel;
520 const char *type = "";
521 int number;
522
523 efx_for_each_channel(channel, efx) {
524 number = channel->channel;
525 if (efx->n_channels > efx->n_rx_channels) {
526 if (channel->channel < efx->n_rx_channels) {
527 type = "-rx";
528 } else {
529 type = "-tx";
530 number -= efx->n_rx_channels;
531 }
532 }
533 snprintf(efx->channel_name[channel->channel],
534 sizeof(efx->channel_name[0]),
535 "%s%s-%d", efx->name, type, number);
536 }
537}
538
539static int efx_probe_channels(struct efx_nic *efx)
540{
541 struct efx_channel *channel;
542 int rc;
543
544 /* Restart special buffer allocation */
545 efx->next_buffer_table = 0;
546
547 efx_for_each_channel(channel, efx) {
548 rc = efx_probe_channel(channel);
549 if (rc) {
550 netif_err(efx, probe, efx->net_dev,
551 "failed to create channel %d\n",
552 channel->channel);
553 goto fail;
554 }
555 }
556 efx_set_channel_names(efx);
557
558 return 0;
559
560fail:
561 efx_remove_channels(efx);
562 return rc;
563}
564
565/* Channels are shutdown and reinitialised whilst the NIC is running
566 * to propagate configuration changes (mtu, checksum offload), or
567 * to clear hardware error conditions
568 */
569static void efx_init_channels(struct efx_nic *efx)
570{
571 struct efx_tx_queue *tx_queue;
572 struct efx_rx_queue *rx_queue;
573 struct efx_channel *channel;
574
575 /* Calculate the rx buffer allocation parameters required to
576 * support the current MTU, including padding for header
577 * alignment and overruns.
578 */
579 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
580 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
581 efx->type->rx_buffer_hash_size +
582 efx->type->rx_buffer_padding);
583 efx->rx_buffer_order = get_order(efx->rx_buffer_len +
584 sizeof(struct efx_rx_page_state));
585
586 /* Initialise the channels */
587 efx_for_each_channel(channel, efx) {
588 netif_dbg(channel->efx, drv, channel->efx->net_dev,
589 "init chan %d\n", channel->channel);
590
591 efx_init_eventq(channel);
592
593 efx_for_each_channel_tx_queue(tx_queue, channel)
594 efx_init_tx_queue(tx_queue);
595
596 /* The rx buffer allocation strategy is MTU dependent */
597 efx_rx_strategy(channel);
598
599 efx_for_each_channel_rx_queue(rx_queue, channel)
600 efx_init_rx_queue(rx_queue);
601
602 WARN_ON(channel->rx_pkt != NULL);
603 efx_rx_strategy(channel);
604 }
605}
606
607/* This enables event queue processing and packet transmission.
608 *
609 * Note that this function is not allowed to fail, since that would
610 * introduce too much complexity into the suspend/resume path.
611 */
612static void efx_start_channel(struct efx_channel *channel)
613{
614 struct efx_rx_queue *rx_queue;
615
616 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
617 "starting chan %d\n", channel->channel);
618
619 /* The interrupt handler for this channel may set work_pending
620 * as soon as we enable it. Make sure it's cleared before
621 * then. Similarly, make sure it sees the enabled flag set. */
622 channel->work_pending = false;
623 channel->enabled = true;
624 smp_wmb();
625
626 /* Fill the queues before enabling NAPI */
627 efx_for_each_channel_rx_queue(rx_queue, channel)
628 efx_fast_push_rx_descriptors(rx_queue);
629
630 napi_enable(&channel->napi_str);
631}
632
633/* This disables event queue processing and packet transmission.
634 * This function does not guarantee that all queue processing
635 * (e.g. RX refill) is complete.
636 */
637static void efx_stop_channel(struct efx_channel *channel)
638{
639 if (!channel->enabled)
640 return;
641
642 netif_dbg(channel->efx, ifdown, channel->efx->net_dev,
643 "stop chan %d\n", channel->channel);
644
645 channel->enabled = false;
646 napi_disable(&channel->napi_str);
647}
648
649static void efx_fini_channels(struct efx_nic *efx)
650{
651 struct efx_channel *channel;
652 struct efx_tx_queue *tx_queue;
653 struct efx_rx_queue *rx_queue;
654 int rc;
655
656 EFX_ASSERT_RESET_SERIALISED(efx);
657 BUG_ON(efx->port_enabled);
658
659 rc = efx_nic_flush_queues(efx);
660 if (rc && EFX_WORKAROUND_7803(efx)) {
661 /* Schedule a reset to recover from the flush failure. The
662 * descriptor caches reference memory we're about to free,
663 * but falcon_reconfigure_mac_wrapper() won't reconnect
664 * the MACs because of the pending reset. */
665 netif_err(efx, drv, efx->net_dev,
666 "Resetting to recover from flush failure\n");
667 efx_schedule_reset(efx, RESET_TYPE_ALL);
668 } else if (rc) {
669 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
670 } else {
671 netif_dbg(efx, drv, efx->net_dev,
672 "successfully flushed all queues\n");
673 }
674
675 efx_for_each_channel(channel, efx) {
676 netif_dbg(channel->efx, drv, channel->efx->net_dev,
677 "shut down chan %d\n", channel->channel);
678
679 efx_for_each_channel_rx_queue(rx_queue, channel)
680 efx_fini_rx_queue(rx_queue);
681 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
682 efx_fini_tx_queue(tx_queue);
683 efx_fini_eventq(channel);
684 }
685}
686
687static void efx_remove_channel(struct efx_channel *channel)
688{
689 struct efx_tx_queue *tx_queue;
690 struct efx_rx_queue *rx_queue;
691
692 netif_dbg(channel->efx, drv, channel->efx->net_dev,
693 "destroy chan %d\n", channel->channel);
694
695 efx_for_each_channel_rx_queue(rx_queue, channel)
696 efx_remove_rx_queue(rx_queue);
697 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
698 efx_remove_tx_queue(tx_queue);
699 efx_remove_eventq(channel);
700}
701
702static void efx_remove_channels(struct efx_nic *efx)
703{
704 struct efx_channel *channel;
705
706 efx_for_each_channel(channel, efx)
707 efx_remove_channel(channel);
708}
709
710int
711efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
712{
713 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
714 u32 old_rxq_entries, old_txq_entries;
715 unsigned i;
716 int rc;
717
718 efx_stop_all(efx);
719 efx_fini_channels(efx);
720
721 /* Clone channels */
722 memset(other_channel, 0, sizeof(other_channel));
723 for (i = 0; i < efx->n_channels; i++) {
724 channel = efx_alloc_channel(efx, i, efx->channel[i]);
725 if (!channel) {
726 rc = -ENOMEM;
727 goto out;
728 }
729 other_channel[i] = channel;
730 }
731
732 /* Swap entry counts and channel pointers */
733 old_rxq_entries = efx->rxq_entries;
734 old_txq_entries = efx->txq_entries;
735 efx->rxq_entries = rxq_entries;
736 efx->txq_entries = txq_entries;
737 for (i = 0; i < efx->n_channels; i++) {
738 channel = efx->channel[i];
739 efx->channel[i] = other_channel[i];
740 other_channel[i] = channel;
741 }
742
743 rc = efx_probe_channels(efx);
744 if (rc)
745 goto rollback;
746
747 efx_init_napi(efx);
748
749 /* Destroy old channels */
750 for (i = 0; i < efx->n_channels; i++) {
751 efx_fini_napi_channel(other_channel[i]);
752 efx_remove_channel(other_channel[i]);
753 }
754out:
755 /* Free unused channel structures */
756 for (i = 0; i < efx->n_channels; i++)
757 kfree(other_channel[i]);
758
759 efx_init_channels(efx);
760 efx_start_all(efx);
761 return rc;
762
763rollback:
764 /* Swap back */
765 efx->rxq_entries = old_rxq_entries;
766 efx->txq_entries = old_txq_entries;
767 for (i = 0; i < efx->n_channels; i++) {
768 channel = efx->channel[i];
769 efx->channel[i] = other_channel[i];
770 other_channel[i] = channel;
771 }
772 goto out;
773}
774
775void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
776{
777 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
778}
779
780/**************************************************************************
781 *
782 * Port handling
783 *
784 **************************************************************************/
785
786/* This ensures that the kernel is kept informed (via
787 * netif_carrier_on/off) of the link status, and also maintains the
788 * link status's stop on the port's TX queue.
789 */
790void efx_link_status_changed(struct efx_nic *efx)
791{
792 struct efx_link_state *link_state = &efx->link_state;
793
794 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
795 * that no events are triggered between unregister_netdev() and the
796 * driver unloading. A more general condition is that NETDEV_CHANGE
797 * can only be generated between NETDEV_UP and NETDEV_DOWN */
798 if (!netif_running(efx->net_dev))
799 return;
800
801 if (efx->port_inhibited) {
802 netif_carrier_off(efx->net_dev);
803 return;
804 }
805
806 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
807 efx->n_link_state_changes++;
808
809 if (link_state->up)
810 netif_carrier_on(efx->net_dev);
811 else
812 netif_carrier_off(efx->net_dev);
813 }
814
815 /* Status message for kernel log */
816 if (link_state->up) {
817 netif_info(efx, link, efx->net_dev,
818 "link up at %uMbps %s-duplex (MTU %d)%s\n",
819 link_state->speed, link_state->fd ? "full" : "half",
820 efx->net_dev->mtu,
821 (efx->promiscuous ? " [PROMISC]" : ""));
822 } else {
823 netif_info(efx, link, efx->net_dev, "link down\n");
824 }
825
826}
827
828void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
829{
830 efx->link_advertising = advertising;
831 if (advertising) {
832 if (advertising & ADVERTISED_Pause)
833 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
834 else
835 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
836 if (advertising & ADVERTISED_Asym_Pause)
837 efx->wanted_fc ^= EFX_FC_TX;
838 }
839}
840
841void efx_link_set_wanted_fc(struct efx_nic *efx, enum efx_fc_type wanted_fc)
842{
843 efx->wanted_fc = wanted_fc;
844 if (efx->link_advertising) {
845 if (wanted_fc & EFX_FC_RX)
846 efx->link_advertising |= (ADVERTISED_Pause |
847 ADVERTISED_Asym_Pause);
848 else
849 efx->link_advertising &= ~(ADVERTISED_Pause |
850 ADVERTISED_Asym_Pause);
851 if (wanted_fc & EFX_FC_TX)
852 efx->link_advertising ^= ADVERTISED_Asym_Pause;
853 }
854}
855
856static void efx_fini_port(struct efx_nic *efx);
857
858/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
859 * the MAC appropriately. All other PHY configuration changes are pushed
860 * through phy_op->set_settings(), and pushed asynchronously to the MAC
861 * through efx_monitor().
862 *
863 * Callers must hold the mac_lock
864 */
865int __efx_reconfigure_port(struct efx_nic *efx)
866{
867 enum efx_phy_mode phy_mode;
868 int rc;
869
870 WARN_ON(!mutex_is_locked(&efx->mac_lock));
871
872 /* Serialise the promiscuous flag with efx_set_multicast_list. */
873 if (efx_dev_registered(efx)) {
874 netif_addr_lock_bh(efx->net_dev);
875 netif_addr_unlock_bh(efx->net_dev);
876 }
877
878 /* Disable PHY transmit in mac level loopbacks */
879 phy_mode = efx->phy_mode;
880 if (LOOPBACK_INTERNAL(efx))
881 efx->phy_mode |= PHY_MODE_TX_DISABLED;
882 else
883 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
884
885 rc = efx->type->reconfigure_port(efx);
886
887 if (rc)
888 efx->phy_mode = phy_mode;
889
890 return rc;
891}
892
893/* Reinitialise the MAC to pick up new PHY settings, even if the port is
894 * disabled. */
895int efx_reconfigure_port(struct efx_nic *efx)
896{
897 int rc;
898
899 EFX_ASSERT_RESET_SERIALISED(efx);
900
901 mutex_lock(&efx->mac_lock);
902 rc = __efx_reconfigure_port(efx);
903 mutex_unlock(&efx->mac_lock);
904
905 return rc;
906}
907
908/* Asynchronous work item for changing MAC promiscuity and multicast
909 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
910 * MAC directly. */
911static void efx_mac_work(struct work_struct *data)
912{
913 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
914
915 mutex_lock(&efx->mac_lock);
916 if (efx->port_enabled) {
917 efx->type->push_multicast_hash(efx);
918 efx->mac_op->reconfigure(efx);
919 }
920 mutex_unlock(&efx->mac_lock);
921}
922
923static int efx_probe_port(struct efx_nic *efx)
924{
925 unsigned char *perm_addr;
926 int rc;
927
928 netif_dbg(efx, probe, efx->net_dev, "create port\n");
929
930 if (phy_flash_cfg)
931 efx->phy_mode = PHY_MODE_SPECIAL;
932
933 /* Connect up MAC/PHY operations table */
934 rc = efx->type->probe_port(efx);
935 if (rc)
936 return rc;
937
938 /* Sanity check MAC address */
939 perm_addr = efx->net_dev->perm_addr;
940 if (is_valid_ether_addr(perm_addr)) {
941 memcpy(efx->net_dev->dev_addr, perm_addr, ETH_ALEN);
942 } else {
943 netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n",
944 perm_addr);
945 if (!allow_bad_hwaddr) {
946 rc = -EINVAL;
947 goto err;
948 }
949 random_ether_addr(efx->net_dev->dev_addr);
950 netif_info(efx, probe, efx->net_dev,
951 "using locally-generated MAC %pM\n",
952 efx->net_dev->dev_addr);
953 }
954
955 return 0;
956
957 err:
958 efx->type->remove_port(efx);
959 return rc;
960}
961
962static int efx_init_port(struct efx_nic *efx)
963{
964 int rc;
965
966 netif_dbg(efx, drv, efx->net_dev, "init port\n");
967
968 mutex_lock(&efx->mac_lock);
969
970 rc = efx->phy_op->init(efx);
971 if (rc)
972 goto fail1;
973
974 efx->port_initialized = true;
975
976 /* Reconfigure the MAC before creating dma queues (required for
977 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
978 efx->mac_op->reconfigure(efx);
979
980 /* Ensure the PHY advertises the correct flow control settings */
981 rc = efx->phy_op->reconfigure(efx);
982 if (rc)
983 goto fail2;
984
985 mutex_unlock(&efx->mac_lock);
986 return 0;
987
988fail2:
989 efx->phy_op->fini(efx);
990fail1:
991 mutex_unlock(&efx->mac_lock);
992 return rc;
993}
994
995static void efx_start_port(struct efx_nic *efx)
996{
997 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
998 BUG_ON(efx->port_enabled);
999
1000 mutex_lock(&efx->mac_lock);
1001 efx->port_enabled = true;
1002
1003 /* efx_mac_work() might have been scheduled after efx_stop_port(),
1004 * and then cancelled by efx_flush_all() */
1005 efx->type->push_multicast_hash(efx);
1006 efx->mac_op->reconfigure(efx);
1007
1008 mutex_unlock(&efx->mac_lock);
1009}
1010
1011/* Prevent efx_mac_work() and efx_monitor() from working */
1012static void efx_stop_port(struct efx_nic *efx)
1013{
1014 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
1015
1016 mutex_lock(&efx->mac_lock);
1017 efx->port_enabled = false;
1018 mutex_unlock(&efx->mac_lock);
1019
1020 /* Serialise against efx_set_multicast_list() */
1021 if (efx_dev_registered(efx)) {
1022 netif_addr_lock_bh(efx->net_dev);
1023 netif_addr_unlock_bh(efx->net_dev);
1024 }
1025}
1026
1027static void efx_fini_port(struct efx_nic *efx)
1028{
1029 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
1030
1031 if (!efx->port_initialized)
1032 return;
1033
1034 efx->phy_op->fini(efx);
1035 efx->port_initialized = false;
1036
1037 efx->link_state.up = false;
1038 efx_link_status_changed(efx);
1039}
1040
1041static void efx_remove_port(struct efx_nic *efx)
1042{
1043 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
1044
1045 efx->type->remove_port(efx);
1046}
1047
1048/**************************************************************************
1049 *
1050 * NIC handling
1051 *
1052 **************************************************************************/
1053
1054/* This configures the PCI device to enable I/O and DMA. */
1055static int efx_init_io(struct efx_nic *efx)
1056{
1057 struct pci_dev *pci_dev = efx->pci_dev;
1058 dma_addr_t dma_mask = efx->type->max_dma_mask;
1059 bool use_wc;
1060 int rc;
1061
1062 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
1063
1064 rc = pci_enable_device(pci_dev);
1065 if (rc) {
1066 netif_err(efx, probe, efx->net_dev,
1067 "failed to enable PCI device\n");
1068 goto fail1;
1069 }
1070
1071 pci_set_master(pci_dev);
1072
1073 /* Set the PCI DMA mask. Try all possibilities from our
1074 * genuine mask down to 32 bits, because some architectures
1075 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1076 * masks event though they reject 46 bit masks.
1077 */
1078 while (dma_mask > 0x7fffffffUL) {
1079 if (pci_dma_supported(pci_dev, dma_mask) &&
1080 ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0))
1081 break;
1082 dma_mask >>= 1;
1083 }
1084 if (rc) {
1085 netif_err(efx, probe, efx->net_dev,
1086 "could not find a suitable DMA mask\n");
1087 goto fail2;
1088 }
1089 netif_dbg(efx, probe, efx->net_dev,
1090 "using DMA mask %llx\n", (unsigned long long) dma_mask);
1091 rc = pci_set_consistent_dma_mask(pci_dev, dma_mask);
1092 if (rc) {
1093 /* pci_set_consistent_dma_mask() is not *allowed* to
1094 * fail with a mask that pci_set_dma_mask() accepted,
1095 * but just in case...
1096 */
1097 netif_err(efx, probe, efx->net_dev,
1098 "failed to set consistent DMA mask\n");
1099 goto fail2;
1100 }
1101
1102 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1103 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
1104 if (rc) {
1105 netif_err(efx, probe, efx->net_dev,
1106 "request for memory BAR failed\n");
1107 rc = -EIO;
1108 goto fail3;
1109 }
1110
1111 /* bug22643: If SR-IOV is enabled then tx push over a write combined
1112 * mapping is unsafe. We need to disable write combining in this case.
1113 * MSI is unsupported when SR-IOV is enabled, and the firmware will
1114 * have removed the MSI capability. So write combining is safe if
1115 * there is an MSI capability.
1116 */
1117 use_wc = (!EFX_WORKAROUND_22643(efx) ||
1118 pci_find_capability(pci_dev, PCI_CAP_ID_MSI));
1119 if (use_wc)
1120 efx->membase = ioremap_wc(efx->membase_phys,
1121 efx->type->mem_map_size);
1122 else
1123 efx->membase = ioremap_nocache(efx->membase_phys,
1124 efx->type->mem_map_size);
1125 if (!efx->membase) {
1126 netif_err(efx, probe, efx->net_dev,
1127 "could not map memory BAR at %llx+%x\n",
1128 (unsigned long long)efx->membase_phys,
1129 efx->type->mem_map_size);
1130 rc = -ENOMEM;
1131 goto fail4;
1132 }
1133 netif_dbg(efx, probe, efx->net_dev,
1134 "memory BAR at %llx+%x (virtual %p)\n",
1135 (unsigned long long)efx->membase_phys,
1136 efx->type->mem_map_size, efx->membase);
1137
1138 return 0;
1139
1140 fail4:
1141 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
1142 fail3:
1143 efx->membase_phys = 0;
1144 fail2:
1145 pci_disable_device(efx->pci_dev);
1146 fail1:
1147 return rc;
1148}
1149
1150static void efx_fini_io(struct efx_nic *efx)
1151{
1152 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
1153
1154 if (efx->membase) {
1155 iounmap(efx->membase);
1156 efx->membase = NULL;
1157 }
1158
1159 if (efx->membase_phys) {
1160 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
1161 efx->membase_phys = 0;
1162 }
1163
1164 pci_disable_device(efx->pci_dev);
1165}
1166
1167/* Get number of channels wanted. Each channel will have its own IRQ,
1168 * 1 RX queue and/or 2 TX queues. */
1169static int efx_wanted_channels(void)
1170{
1171 cpumask_var_t core_mask;
1172 int count;
1173 int cpu;
1174
1175 if (rss_cpus)
1176 return rss_cpus;
1177
1178 if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) {
1179 printk(KERN_WARNING
1180 "sfc: RSS disabled due to allocation failure\n");
1181 return 1;
1182 }
1183
1184 count = 0;
1185 for_each_online_cpu(cpu) {
1186 if (!cpumask_test_cpu(cpu, core_mask)) {
1187 ++count;
1188 cpumask_or(core_mask, core_mask,
1189 topology_core_cpumask(cpu));
1190 }
1191 }
1192
1193 free_cpumask_var(core_mask);
1194 return count;
1195}
1196
1197static int
1198efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries)
1199{
1200#ifdef CONFIG_RFS_ACCEL
1201 int i, rc;
1202
1203 efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels);
1204 if (!efx->net_dev->rx_cpu_rmap)
1205 return -ENOMEM;
1206 for (i = 0; i < efx->n_rx_channels; i++) {
1207 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
1208 xentries[i].vector);
1209 if (rc) {
1210 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
1211 efx->net_dev->rx_cpu_rmap = NULL;
1212 return rc;
1213 }
1214 }
1215#endif
1216 return 0;
1217}
1218
1219/* Probe the number and type of interrupts we are able to obtain, and
1220 * the resulting numbers of channels and RX queues.
1221 */
1222static int efx_probe_interrupts(struct efx_nic *efx)
1223{
1224 int max_channels =
1225 min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
1226 int rc, i;
1227
1228 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
1229 struct msix_entry xentries[EFX_MAX_CHANNELS];
1230 int n_channels;
1231
1232 n_channels = efx_wanted_channels();
1233 if (separate_tx_channels)
1234 n_channels *= 2;
1235 n_channels = min(n_channels, max_channels);
1236
1237 for (i = 0; i < n_channels; i++)
1238 xentries[i].entry = i;
1239 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
1240 if (rc > 0) {
1241 netif_err(efx, drv, efx->net_dev,
1242 "WARNING: Insufficient MSI-X vectors"
1243 " available (%d < %d).\n", rc, n_channels);
1244 netif_err(efx, drv, efx->net_dev,
1245 "WARNING: Performance may be reduced.\n");
1246 EFX_BUG_ON_PARANOID(rc >= n_channels);
1247 n_channels = rc;
1248 rc = pci_enable_msix(efx->pci_dev, xentries,
1249 n_channels);
1250 }
1251
1252 if (rc == 0) {
1253 efx->n_channels = n_channels;
1254 if (separate_tx_channels) {
1255 efx->n_tx_channels =
1256 max(efx->n_channels / 2, 1U);
1257 efx->n_rx_channels =
1258 max(efx->n_channels -
1259 efx->n_tx_channels, 1U);
1260 } else {
1261 efx->n_tx_channels = efx->n_channels;
1262 efx->n_rx_channels = efx->n_channels;
1263 }
1264 rc = efx_init_rx_cpu_rmap(efx, xentries);
1265 if (rc) {
1266 pci_disable_msix(efx->pci_dev);
1267 return rc;
1268 }
1269 for (i = 0; i < n_channels; i++)
1270 efx_get_channel(efx, i)->irq =
1271 xentries[i].vector;
1272 } else {
1273 /* Fall back to single channel MSI */
1274 efx->interrupt_mode = EFX_INT_MODE_MSI;
1275 netif_err(efx, drv, efx->net_dev,
1276 "could not enable MSI-X\n");
1277 }
1278 }
1279
1280 /* Try single interrupt MSI */
1281 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
1282 efx->n_channels = 1;
1283 efx->n_rx_channels = 1;
1284 efx->n_tx_channels = 1;
1285 rc = pci_enable_msi(efx->pci_dev);
1286 if (rc == 0) {
1287 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
1288 } else {
1289 netif_err(efx, drv, efx->net_dev,
1290 "could not enable MSI\n");
1291 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1292 }
1293 }
1294
1295 /* Assume legacy interrupts */
1296 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
1297 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
1298 efx->n_rx_channels = 1;
1299 efx->n_tx_channels = 1;
1300 efx->legacy_irq = efx->pci_dev->irq;
1301 }
1302
1303 return 0;
1304}
1305
1306static void efx_remove_interrupts(struct efx_nic *efx)
1307{
1308 struct efx_channel *channel;
1309
1310 /* Remove MSI/MSI-X interrupts */
1311 efx_for_each_channel(channel, efx)
1312 channel->irq = 0;
1313 pci_disable_msi(efx->pci_dev);
1314 pci_disable_msix(efx->pci_dev);
1315
1316 /* Remove legacy interrupt */
1317 efx->legacy_irq = 0;
1318}
1319
1320static void efx_set_channels(struct efx_nic *efx)
1321{
1322 efx->tx_channel_offset =
1323 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
1324}
1325
1326static int efx_probe_nic(struct efx_nic *efx)
1327{
1328 size_t i;
1329 int rc;
1330
1331 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
1332
1333 /* Carry out hardware-type specific initialisation */
1334 rc = efx->type->probe(efx);
1335 if (rc)
1336 return rc;
1337
1338 /* Determine the number of channels and queues by trying to hook
1339 * in MSI-X interrupts. */
1340 rc = efx_probe_interrupts(efx);
1341 if (rc)
1342 goto fail;
1343
1344 if (efx->n_channels > 1)
1345 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
1346 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
1347 efx->rx_indir_table[i] = i % efx->n_rx_channels;
1348
1349 efx_set_channels(efx);
1350 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1351 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
1352
1353 /* Initialise the interrupt moderation settings */
1354 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true);
1355
1356 return 0;
1357
1358fail:
1359 efx->type->remove(efx);
1360 return rc;
1361}
1362
1363static void efx_remove_nic(struct efx_nic *efx)
1364{
1365 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
1366
1367 efx_remove_interrupts(efx);
1368 efx->type->remove(efx);
1369}
1370
1371/**************************************************************************
1372 *
1373 * NIC startup/shutdown
1374 *
1375 *************************************************************************/
1376
1377static int efx_probe_all(struct efx_nic *efx)
1378{
1379 int rc;
1380
1381 rc = efx_probe_nic(efx);
1382 if (rc) {
1383 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
1384 goto fail1;
1385 }
1386
1387 rc = efx_probe_port(efx);
1388 if (rc) {
1389 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
1390 goto fail2;
1391 }
1392
1393 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
1394 rc = efx_probe_channels(efx);
1395 if (rc)
1396 goto fail3;
1397
1398 rc = efx_probe_filters(efx);
1399 if (rc) {
1400 netif_err(efx, probe, efx->net_dev,
1401 "failed to create filter tables\n");
1402 goto fail4;
1403 }
1404
1405 return 0;
1406
1407 fail4:
1408 efx_remove_channels(efx);
1409 fail3:
1410 efx_remove_port(efx);
1411 fail2:
1412 efx_remove_nic(efx);
1413 fail1:
1414 return rc;
1415}
1416
1417/* Called after previous invocation(s) of efx_stop_all, restarts the
1418 * port, kernel transmit queue, NAPI processing and hardware interrupts,
1419 * and ensures that the port is scheduled to be reconfigured.
1420 * This function is safe to call multiple times when the NIC is in any
1421 * state. */
1422static void efx_start_all(struct efx_nic *efx)
1423{
1424 struct efx_channel *channel;
1425
1426 EFX_ASSERT_RESET_SERIALISED(efx);
1427
1428 /* Check that it is appropriate to restart the interface. All
1429 * of these flags are safe to read under just the rtnl lock */
1430 if (efx->port_enabled)
1431 return;
1432 if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT))
1433 return;
1434 if (efx_dev_registered(efx) && !netif_running(efx->net_dev))
1435 return;
1436
1437 /* Mark the port as enabled so port reconfigurations can start, then
1438 * restart the transmit interface early so the watchdog timer stops */
1439 efx_start_port(efx);
1440
1441 if (efx_dev_registered(efx) && !efx->port_inhibited)
1442 netif_tx_wake_all_queues(efx->net_dev);
1443
1444 efx_for_each_channel(channel, efx)
1445 efx_start_channel(channel);
1446
1447 if (efx->legacy_irq)
1448 efx->legacy_irq_enabled = true;
1449 efx_nic_enable_interrupts(efx);
1450
1451 /* Switch to event based MCDI completions after enabling interrupts.
1452 * If a reset has been scheduled, then we need to stay in polled mode.
1453 * Rather than serialising efx_mcdi_mode_event() [which sleeps] and
1454 * reset_pending [modified from an atomic context], we instead guarantee
1455 * that efx_mcdi_mode_poll() isn't reverted erroneously */
1456 efx_mcdi_mode_event(efx);
1457 if (efx->reset_pending != RESET_TYPE_NONE)
1458 efx_mcdi_mode_poll(efx);
1459
1460 /* Start the hardware monitor if there is one. Otherwise (we're link
1461 * event driven), we have to poll the PHY because after an event queue
1462 * flush, we could have a missed a link state change */
1463 if (efx->type->monitor != NULL) {
1464 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1465 efx_monitor_interval);
1466 } else {
1467 mutex_lock(&efx->mac_lock);
1468 if (efx->phy_op->poll(efx))
1469 efx_link_status_changed(efx);
1470 mutex_unlock(&efx->mac_lock);
1471 }
1472
1473 efx->type->start_stats(efx);
1474}
1475
1476/* Flush all delayed work. Should only be called when no more delayed work
1477 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1478 * since we're holding the rtnl_lock at this point. */
1479static void efx_flush_all(struct efx_nic *efx)
1480{
1481 /* Make sure the hardware monitor is stopped */
1482 cancel_delayed_work_sync(&efx->monitor_work);
1483 /* Stop scheduled port reconfigurations */
1484 cancel_work_sync(&efx->mac_work);
1485}
1486
1487/* Quiesce hardware and software without bringing the link down.
1488 * Safe to call multiple times, when the nic and interface is in any
1489 * state. The caller is guaranteed to subsequently be in a position
1490 * to modify any hardware and software state they see fit without
1491 * taking locks. */
1492static void efx_stop_all(struct efx_nic *efx)
1493{
1494 struct efx_channel *channel;
1495
1496 EFX_ASSERT_RESET_SERIALISED(efx);
1497
1498 /* port_enabled can be read safely under the rtnl lock */
1499 if (!efx->port_enabled)
1500 return;
1501
1502 efx->type->stop_stats(efx);
1503
1504 /* Switch to MCDI polling on Siena before disabling interrupts */
1505 efx_mcdi_mode_poll(efx);
1506
1507 /* Disable interrupts and wait for ISR to complete */
1508 efx_nic_disable_interrupts(efx);
1509 if (efx->legacy_irq) {
1510 synchronize_irq(efx->legacy_irq);
1511 efx->legacy_irq_enabled = false;
1512 }
1513 efx_for_each_channel(channel, efx) {
1514 if (channel->irq)
1515 synchronize_irq(channel->irq);
1516 }
1517
1518 /* Stop all NAPI processing and synchronous rx refills */
1519 efx_for_each_channel(channel, efx)
1520 efx_stop_channel(channel);
1521
1522 /* Stop all asynchronous port reconfigurations. Since all
1523 * event processing has already been stopped, there is no
1524 * window to loose phy events */
1525 efx_stop_port(efx);
1526
1527 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
1528 efx_flush_all(efx);
1529
1530 /* Stop the kernel transmit interface late, so the watchdog
1531 * timer isn't ticking over the flush */
1532 if (efx_dev_registered(efx)) {
1533 netif_tx_stop_all_queues(efx->net_dev);
1534 netif_tx_lock_bh(efx->net_dev);
1535 netif_tx_unlock_bh(efx->net_dev);
1536 }
1537}
1538
1539static void efx_remove_all(struct efx_nic *efx)
1540{
1541 efx_remove_filters(efx);
1542 efx_remove_channels(efx);
1543 efx_remove_port(efx);
1544 efx_remove_nic(efx);
1545}
1546
1547/**************************************************************************
1548 *
1549 * Interrupt moderation
1550 *
1551 **************************************************************************/
1552
1553static unsigned irq_mod_ticks(int usecs, int resolution)
1554{
1555 if (usecs <= 0)
1556 return 0; /* cannot receive interrupts ahead of time :-) */
1557 if (usecs < resolution)
1558 return 1; /* never round down to 0 */
1559 return usecs / resolution;
1560}
1561
1562/* Set interrupt moderation parameters */
1563void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs,
1564 bool rx_adaptive)
1565{
1566 struct efx_channel *channel;
1567 unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION);
1568 unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION);
1569
1570 EFX_ASSERT_RESET_SERIALISED(efx);
1571
1572 efx->irq_rx_adaptive = rx_adaptive;
1573 efx->irq_rx_moderation = rx_ticks;
1574 efx_for_each_channel(channel, efx) {
1575 if (efx_channel_has_rx_queue(channel))
1576 channel->irq_moderation = rx_ticks;
1577 else if (efx_channel_has_tx_queues(channel))
1578 channel->irq_moderation = tx_ticks;
1579 }
1580}
1581
1582/**************************************************************************
1583 *
1584 * Hardware monitor
1585 *
1586 **************************************************************************/
1587
1588/* Run periodically off the general workqueue */
1589static void efx_monitor(struct work_struct *data)
1590{
1591 struct efx_nic *efx = container_of(data, struct efx_nic,
1592 monitor_work.work);
1593
1594 netif_vdbg(efx, timer, efx->net_dev,
1595 "hardware monitor executing on CPU %d\n",
1596 raw_smp_processor_id());
1597 BUG_ON(efx->type->monitor == NULL);
1598
1599 /* If the mac_lock is already held then it is likely a port
1600 * reconfiguration is already in place, which will likely do
1601 * most of the work of monitor() anyway. */
1602 if (mutex_trylock(&efx->mac_lock)) {
1603 if (efx->port_enabled)
1604 efx->type->monitor(efx);
1605 mutex_unlock(&efx->mac_lock);
1606 }
1607
1608 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1609 efx_monitor_interval);
1610}
1611
1612/**************************************************************************
1613 *
1614 * ioctls
1615 *
1616 *************************************************************************/
1617
1618/* Net device ioctl
1619 * Context: process, rtnl_lock() held.
1620 */
1621static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1622{
1623 struct efx_nic *efx = netdev_priv(net_dev);
1624 struct mii_ioctl_data *data = if_mii(ifr);
1625
1626 EFX_ASSERT_RESET_SERIALISED(efx);
1627
1628 /* Convert phy_id from older PRTAD/DEVAD format */
1629 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1630 (data->phy_id & 0xfc00) == 0x0400)
1631 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1632
1633 return mdio_mii_ioctl(&efx->mdio, data, cmd);
1634}
1635
1636/**************************************************************************
1637 *
1638 * NAPI interface
1639 *
1640 **************************************************************************/
1641
1642static void efx_init_napi(struct efx_nic *efx)
1643{
1644 struct efx_channel *channel;
1645
1646 efx_for_each_channel(channel, efx) {
1647 channel->napi_dev = efx->net_dev;
1648 netif_napi_add(channel->napi_dev, &channel->napi_str,
1649 efx_poll, napi_weight);
1650 }
1651}
1652
1653static void efx_fini_napi_channel(struct efx_channel *channel)
1654{
1655 if (channel->napi_dev)
1656 netif_napi_del(&channel->napi_str);
1657 channel->napi_dev = NULL;
1658}
1659
1660static void efx_fini_napi(struct efx_nic *efx)
1661{
1662 struct efx_channel *channel;
1663
1664 efx_for_each_channel(channel, efx)
1665 efx_fini_napi_channel(channel);
1666}
1667
1668/**************************************************************************
1669 *
1670 * Kernel netpoll interface
1671 *
1672 *************************************************************************/
1673
1674#ifdef CONFIG_NET_POLL_CONTROLLER
1675
1676/* Although in the common case interrupts will be disabled, this is not
1677 * guaranteed. However, all our work happens inside the NAPI callback,
1678 * so no locking is required.
1679 */
1680static void efx_netpoll(struct net_device *net_dev)
1681{
1682 struct efx_nic *efx = netdev_priv(net_dev);
1683 struct efx_channel *channel;
1684
1685 efx_for_each_channel(channel, efx)
1686 efx_schedule_channel(channel);
1687}
1688
1689#endif
1690
1691/**************************************************************************
1692 *
1693 * Kernel net device interface
1694 *
1695 *************************************************************************/
1696
1697/* Context: process, rtnl_lock() held. */
1698static int efx_net_open(struct net_device *net_dev)
1699{
1700 struct efx_nic *efx = netdev_priv(net_dev);
1701 EFX_ASSERT_RESET_SERIALISED(efx);
1702
1703 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1704 raw_smp_processor_id());
1705
1706 if (efx->state == STATE_DISABLED)
1707 return -EIO;
1708 if (efx->phy_mode & PHY_MODE_SPECIAL)
1709 return -EBUSY;
1710 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1711 return -EIO;
1712
1713 /* Notify the kernel of the link state polled during driver load,
1714 * before the monitor starts running */
1715 efx_link_status_changed(efx);
1716
1717 efx_start_all(efx);
1718 return 0;
1719}
1720
1721/* Context: process, rtnl_lock() held.
1722 * Note that the kernel will ignore our return code; this method
1723 * should really be a void.
1724 */
1725static int efx_net_stop(struct net_device *net_dev)
1726{
1727 struct efx_nic *efx = netdev_priv(net_dev);
1728
1729 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1730 raw_smp_processor_id());
1731
1732 if (efx->state != STATE_DISABLED) {
1733 /* Stop the device and flush all the channels */
1734 efx_stop_all(efx);
1735 efx_fini_channels(efx);
1736 efx_init_channels(efx);
1737 }
1738
1739 return 0;
1740}
1741
1742/* Context: process, dev_base_lock or RTNL held, non-blocking. */
1743static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, struct rtnl_link_stats64 *stats)
1744{
1745 struct efx_nic *efx = netdev_priv(net_dev);
1746 struct efx_mac_stats *mac_stats = &efx->mac_stats;
1747
1748 spin_lock_bh(&efx->stats_lock);
1749 efx->type->update_stats(efx);
1750 spin_unlock_bh(&efx->stats_lock);
1751
1752 stats->rx_packets = mac_stats->rx_packets;
1753 stats->tx_packets = mac_stats->tx_packets;
1754 stats->rx_bytes = mac_stats->rx_bytes;
1755 stats->tx_bytes = mac_stats->tx_bytes;
1756 stats->rx_dropped = efx->n_rx_nodesc_drop_cnt;
1757 stats->multicast = mac_stats->rx_multicast;
1758 stats->collisions = mac_stats->tx_collision;
1759 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1760 mac_stats->rx_length_error);
1761 stats->rx_crc_errors = mac_stats->rx_bad;
1762 stats->rx_frame_errors = mac_stats->rx_align_error;
1763 stats->rx_fifo_errors = mac_stats->rx_overflow;
1764 stats->rx_missed_errors = mac_stats->rx_missed;
1765 stats->tx_window_errors = mac_stats->tx_late_collision;
1766
1767 stats->rx_errors = (stats->rx_length_errors +
1768 stats->rx_crc_errors +
1769 stats->rx_frame_errors +
1770 mac_stats->rx_symbol_error);
1771 stats->tx_errors = (stats->tx_window_errors +
1772 mac_stats->tx_bad);
1773
1774 return stats;
1775}
1776
1777/* Context: netif_tx_lock held, BHs disabled. */
1778static void efx_watchdog(struct net_device *net_dev)
1779{
1780 struct efx_nic *efx = netdev_priv(net_dev);
1781
1782 netif_err(efx, tx_err, efx->net_dev,
1783 "TX stuck with port_enabled=%d: resetting channels\n",
1784 efx->port_enabled);
1785
1786 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
1787}
1788
1789
1790/* Context: process, rtnl_lock() held. */
1791static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1792{
1793 struct efx_nic *efx = netdev_priv(net_dev);
1794 int rc = 0;
1795
1796 EFX_ASSERT_RESET_SERIALISED(efx);
1797
1798 if (new_mtu > EFX_MAX_MTU)
1799 return -EINVAL;
1800
1801 efx_stop_all(efx);
1802
1803 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
1804
1805 efx_fini_channels(efx);
1806
1807 mutex_lock(&efx->mac_lock);
1808 /* Reconfigure the MAC before enabling the dma queues so that
1809 * the RX buffers don't overflow */
1810 net_dev->mtu = new_mtu;
1811 efx->mac_op->reconfigure(efx);
1812 mutex_unlock(&efx->mac_lock);
1813
1814 efx_init_channels(efx);
1815
1816 efx_start_all(efx);
1817 return rc;
1818}
1819
1820static int efx_set_mac_address(struct net_device *net_dev, void *data)
1821{
1822 struct efx_nic *efx = netdev_priv(net_dev);
1823 struct sockaddr *addr = data;
1824 char *new_addr = addr->sa_data;
1825
1826 EFX_ASSERT_RESET_SERIALISED(efx);
1827
1828 if (!is_valid_ether_addr(new_addr)) {
1829 netif_err(efx, drv, efx->net_dev,
1830 "invalid ethernet MAC address requested: %pM\n",
1831 new_addr);
1832 return -EINVAL;
1833 }
1834
1835 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
1836
1837 /* Reconfigure the MAC */
1838 mutex_lock(&efx->mac_lock);
1839 efx->mac_op->reconfigure(efx);
1840 mutex_unlock(&efx->mac_lock);
1841
1842 return 0;
1843}
1844
1845/* Context: netif_addr_lock held, BHs disabled. */
1846static void efx_set_multicast_list(struct net_device *net_dev)
1847{
1848 struct efx_nic *efx = netdev_priv(net_dev);
1849 struct netdev_hw_addr *ha;
1850 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1851 u32 crc;
1852 int bit;
1853
1854 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC);
1855
1856 /* Build multicast hash table */
1857 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
1858 memset(mc_hash, 0xff, sizeof(*mc_hash));
1859 } else {
1860 memset(mc_hash, 0x00, sizeof(*mc_hash));
1861 netdev_for_each_mc_addr(ha, net_dev) {
1862 crc = ether_crc_le(ETH_ALEN, ha->addr);
1863 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
1864 set_bit_le(bit, mc_hash->byte);
1865 }
1866
1867 /* Broadcast packets go through the multicast hash filter.
1868 * ether_crc_le() of the broadcast address is 0xbe2612ff
1869 * so we always add bit 0xff to the mask.
1870 */
1871 set_bit_le(0xff, mc_hash->byte);
1872 }
1873
1874 if (efx->port_enabled)
1875 queue_work(efx->workqueue, &efx->mac_work);
1876 /* Otherwise efx_start_port() will do this */
1877}
1878
1879static int efx_set_features(struct net_device *net_dev, u32 data)
1880{
1881 struct efx_nic *efx = netdev_priv(net_dev);
1882
1883 /* If disabling RX n-tuple filtering, clear existing filters */
1884 if (net_dev->features & ~data & NETIF_F_NTUPLE)
1885 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
1886
1887 return 0;
1888}
1889
1890static const struct net_device_ops efx_netdev_ops = {
1891 .ndo_open = efx_net_open,
1892 .ndo_stop = efx_net_stop,
1893 .ndo_get_stats64 = efx_net_stats,
1894 .ndo_tx_timeout = efx_watchdog,
1895 .ndo_start_xmit = efx_hard_start_xmit,
1896 .ndo_validate_addr = eth_validate_addr,
1897 .ndo_do_ioctl = efx_ioctl,
1898 .ndo_change_mtu = efx_change_mtu,
1899 .ndo_set_mac_address = efx_set_mac_address,
1900 .ndo_set_multicast_list = efx_set_multicast_list,
1901 .ndo_set_features = efx_set_features,
1902#ifdef CONFIG_NET_POLL_CONTROLLER
1903 .ndo_poll_controller = efx_netpoll,
1904#endif
1905 .ndo_setup_tc = efx_setup_tc,
1906#ifdef CONFIG_RFS_ACCEL
1907 .ndo_rx_flow_steer = efx_filter_rfs,
1908#endif
1909};
1910
1911static void efx_update_name(struct efx_nic *efx)
1912{
1913 strcpy(efx->name, efx->net_dev->name);
1914 efx_mtd_rename(efx);
1915 efx_set_channel_names(efx);
1916}
1917
1918static int efx_netdev_event(struct notifier_block *this,
1919 unsigned long event, void *ptr)
1920{
1921 struct net_device *net_dev = ptr;
1922
1923 if (net_dev->netdev_ops == &efx_netdev_ops &&
1924 event == NETDEV_CHANGENAME)
1925 efx_update_name(netdev_priv(net_dev));
1926
1927 return NOTIFY_DONE;
1928}
1929
1930static struct notifier_block efx_netdev_notifier = {
1931 .notifier_call = efx_netdev_event,
1932};
1933
1934static ssize_t
1935show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
1936{
1937 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
1938 return sprintf(buf, "%d\n", efx->phy_type);
1939}
1940static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
1941
1942static int efx_register_netdev(struct efx_nic *efx)
1943{
1944 struct net_device *net_dev = efx->net_dev;
1945 struct efx_channel *channel;
1946 int rc;
1947
1948 net_dev->watchdog_timeo = 5 * HZ;
1949 net_dev->irq = efx->pci_dev->irq;
1950 net_dev->netdev_ops = &efx_netdev_ops;
1951 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
1952
1953 /* Clear MAC statistics */
1954 efx->mac_op->update_stats(efx);
1955 memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
1956
1957 rtnl_lock();
1958
1959 rc = dev_alloc_name(net_dev, net_dev->name);
1960 if (rc < 0)
1961 goto fail_locked;
1962 efx_update_name(efx);
1963
1964 rc = register_netdevice(net_dev);
1965 if (rc)
1966 goto fail_locked;
1967
1968 efx_for_each_channel(channel, efx) {
1969 struct efx_tx_queue *tx_queue;
1970 efx_for_each_channel_tx_queue(tx_queue, channel)
1971 efx_init_tx_queue_core_txq(tx_queue);
1972 }
1973
1974 /* Always start with carrier off; PHY events will detect the link */
1975 netif_carrier_off(efx->net_dev);
1976
1977 rtnl_unlock();
1978
1979 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
1980 if (rc) {
1981 netif_err(efx, drv, efx->net_dev,
1982 "failed to init net dev attributes\n");
1983 goto fail_registered;
1984 }
1985
1986 return 0;
1987
1988fail_locked:
1989 rtnl_unlock();
1990 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
1991 return rc;
1992
1993fail_registered:
1994 unregister_netdev(net_dev);
1995 return rc;
1996}
1997
1998static void efx_unregister_netdev(struct efx_nic *efx)
1999{
2000 struct efx_channel *channel;
2001 struct efx_tx_queue *tx_queue;
2002
2003 if (!efx->net_dev)
2004 return;
2005
2006 BUG_ON(netdev_priv(efx->net_dev) != efx);
2007
2008 /* Free up any skbs still remaining. This has to happen before
2009 * we try to unregister the netdev as running their destructors
2010 * may be needed to get the device ref. count to 0. */
2011 efx_for_each_channel(channel, efx) {
2012 efx_for_each_channel_tx_queue(tx_queue, channel)
2013 efx_release_tx_buffers(tx_queue);
2014 }
2015
2016 if (efx_dev_registered(efx)) {
2017 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2018 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2019 unregister_netdev(efx->net_dev);
2020 }
2021}
2022
2023/**************************************************************************
2024 *
2025 * Device reset and suspend
2026 *
2027 **************************************************************************/
2028
2029/* Tears down the entire software state and most of the hardware state
2030 * before reset. */
2031void efx_reset_down(struct efx_nic *efx, enum reset_type method)
2032{
2033 EFX_ASSERT_RESET_SERIALISED(efx);
2034
2035 efx_stop_all(efx);
2036 mutex_lock(&efx->mac_lock);
2037
2038 efx_fini_channels(efx);
2039 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2040 efx->phy_op->fini(efx);
2041 efx->type->fini(efx);
2042}
2043
2044/* This function will always ensure that the locks acquired in
2045 * efx_reset_down() are released. A failure return code indicates
2046 * that we were unable to reinitialise the hardware, and the
2047 * driver should be disabled. If ok is false, then the rx and tx
2048 * engines are not restarted, pending a RESET_DISABLE. */
2049int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
2050{
2051 int rc;
2052
2053 EFX_ASSERT_RESET_SERIALISED(efx);
2054
2055 rc = efx->type->init(efx);
2056 if (rc) {
2057 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
2058 goto fail;
2059 }
2060
2061 if (!ok)
2062 goto fail;
2063
2064 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
2065 rc = efx->phy_op->init(efx);
2066 if (rc)
2067 goto fail;
2068 if (efx->phy_op->reconfigure(efx))
2069 netif_err(efx, drv, efx->net_dev,
2070 "could not restore PHY settings\n");
2071 }
2072
2073 efx->mac_op->reconfigure(efx);
2074
2075 efx_init_channels(efx);
2076 efx_restore_filters(efx);
2077
2078 mutex_unlock(&efx->mac_lock);
2079
2080 efx_start_all(efx);
2081
2082 return 0;
2083
2084fail:
2085 efx->port_initialized = false;
2086
2087 mutex_unlock(&efx->mac_lock);
2088
2089 return rc;
2090}
2091
2092/* Reset the NIC using the specified method. Note that the reset may
2093 * fail, in which case the card will be left in an unusable state.
2094 *
2095 * Caller must hold the rtnl_lock.
2096 */
2097int efx_reset(struct efx_nic *efx, enum reset_type method)
2098{
2099 int rc, rc2;
2100 bool disabled;
2101
2102 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2103 RESET_TYPE(method));
2104
2105 efx_reset_down(efx, method);
2106
2107 rc = efx->type->reset(efx, method);
2108 if (rc) {
2109 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
2110 goto out;
2111 }
2112
2113 /* Allow resets to be rescheduled. */
2114 efx->reset_pending = RESET_TYPE_NONE;
2115
2116 /* Reinitialise bus-mastering, which may have been turned off before
2117 * the reset was scheduled. This is still appropriate, even in the
2118 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2119 * can respond to requests. */
2120 pci_set_master(efx->pci_dev);
2121
2122out:
2123 /* Leave device stopped if necessary */
2124 disabled = rc || method == RESET_TYPE_DISABLE;
2125 rc2 = efx_reset_up(efx, method, !disabled);
2126 if (rc2) {
2127 disabled = true;
2128 if (!rc)
2129 rc = rc2;
2130 }
2131
2132 if (disabled) {
2133 dev_close(efx->net_dev);
2134 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
2135 efx->state = STATE_DISABLED;
2136 } else {
2137 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
2138 }
2139 return rc;
2140}
2141
2142/* The worker thread exists so that code that cannot sleep can
2143 * schedule a reset for later.
2144 */
2145static void efx_reset_work(struct work_struct *data)
2146{
2147 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
2148
2149 if (efx->reset_pending == RESET_TYPE_NONE)
2150 return;
2151
2152 /* If we're not RUNNING then don't reset. Leave the reset_pending
2153 * flag set so that efx_pci_probe_main will be retried */
2154 if (efx->state != STATE_RUNNING) {
2155 netif_info(efx, drv, efx->net_dev,
2156 "scheduled reset quenched. NIC not RUNNING\n");
2157 return;
2158 }
2159
2160 rtnl_lock();
2161 (void)efx_reset(efx, efx->reset_pending);
2162 rtnl_unlock();
2163}
2164
2165void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2166{
2167 enum reset_type method;
2168
2169 if (efx->reset_pending != RESET_TYPE_NONE) {
2170 netif_info(efx, drv, efx->net_dev,
2171 "quenching already scheduled reset\n");
2172 return;
2173 }
2174
2175 switch (type) {
2176 case RESET_TYPE_INVISIBLE:
2177 case RESET_TYPE_ALL:
2178 case RESET_TYPE_WORLD:
2179 case RESET_TYPE_DISABLE:
2180 method = type;
2181 break;
2182 case RESET_TYPE_RX_RECOVERY:
2183 case RESET_TYPE_RX_DESC_FETCH:
2184 case RESET_TYPE_TX_DESC_FETCH:
2185 case RESET_TYPE_TX_SKIP:
2186 method = RESET_TYPE_INVISIBLE;
2187 break;
2188 case RESET_TYPE_MC_FAILURE:
2189 default:
2190 method = RESET_TYPE_ALL;
2191 break;
2192 }
2193
2194 if (method != type)
2195 netif_dbg(efx, drv, efx->net_dev,
2196 "scheduling %s reset for %s\n",
2197 RESET_TYPE(method), RESET_TYPE(type));
2198 else
2199 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2200 RESET_TYPE(method));
2201
2202 efx->reset_pending = method;
2203
2204 /* efx_process_channel() will no longer read events once a
2205 * reset is scheduled. So switch back to poll'd MCDI completions. */
2206 efx_mcdi_mode_poll(efx);
2207
2208 queue_work(reset_workqueue, &efx->reset_work);
2209}
2210
2211/**************************************************************************
2212 *
2213 * List of NICs we support
2214 *
2215 **************************************************************************/
2216
2217/* PCI device ID table */
2218static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
2219 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID),
2220 .driver_data = (unsigned long) &falcon_a1_nic_type},
2221 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID),
2222 .driver_data = (unsigned long) &falcon_b0_nic_type},
2223 {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID),
2224 .driver_data = (unsigned long) &siena_a0_nic_type},
2225 {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID),
2226 .driver_data = (unsigned long) &siena_a0_nic_type},
2227 {0} /* end of list */
2228};
2229
2230/**************************************************************************
2231 *
2232 * Dummy PHY/MAC operations
2233 *
2234 * Can be used for some unimplemented operations
2235 * Needed so all function pointers are valid and do not have to be tested
2236 * before use
2237 *
2238 **************************************************************************/
2239int efx_port_dummy_op_int(struct efx_nic *efx)
2240{
2241 return 0;
2242}
2243void efx_port_dummy_op_void(struct efx_nic *efx) {}
2244
2245static bool efx_port_dummy_op_poll(struct efx_nic *efx)
2246{
2247 return false;
2248}
2249
2250static const struct efx_phy_operations efx_dummy_phy_operations = {
2251 .init = efx_port_dummy_op_int,
2252 .reconfigure = efx_port_dummy_op_int,
2253 .poll = efx_port_dummy_op_poll,
2254 .fini = efx_port_dummy_op_void,
2255};
2256
2257/**************************************************************************
2258 *
2259 * Data housekeeping
2260 *
2261 **************************************************************************/
2262
2263/* This zeroes out and then fills in the invariants in a struct
2264 * efx_nic (including all sub-structures).
2265 */
2266static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type,
2267 struct pci_dev *pci_dev, struct net_device *net_dev)
2268{
2269 int i;
2270
2271 /* Initialise common structures */
2272 memset(efx, 0, sizeof(*efx));
2273 spin_lock_init(&efx->biu_lock);
2274#ifdef CONFIG_SFC_MTD
2275 INIT_LIST_HEAD(&efx->mtd_list);
2276#endif
2277 INIT_WORK(&efx->reset_work, efx_reset_work);
2278 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
2279 efx->pci_dev = pci_dev;
2280 efx->msg_enable = debug;
2281 efx->state = STATE_INIT;
2282 efx->reset_pending = RESET_TYPE_NONE;
2283 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
2284
2285 efx->net_dev = net_dev;
2286 spin_lock_init(&efx->stats_lock);
2287 mutex_init(&efx->mac_lock);
2288 efx->mac_op = type->default_mac_ops;
2289 efx->phy_op = &efx_dummy_phy_operations;
2290 efx->mdio.dev = net_dev;
2291 INIT_WORK(&efx->mac_work, efx_mac_work);
2292
2293 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
2294 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2295 if (!efx->channel[i])
2296 goto fail;
2297 }
2298
2299 efx->type = type;
2300
2301 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
2302
2303 /* Higher numbered interrupt modes are less capable! */
2304 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2305 interrupt_mode);
2306
2307 /* Would be good to use the net_dev name, but we're too early */
2308 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2309 pci_name(pci_dev));
2310 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
2311 if (!efx->workqueue)
2312 goto fail;
2313
2314 return 0;
2315
2316fail:
2317 efx_fini_struct(efx);
2318 return -ENOMEM;
2319}
2320
2321static void efx_fini_struct(struct efx_nic *efx)
2322{
2323 int i;
2324
2325 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2326 kfree(efx->channel[i]);
2327
2328 if (efx->workqueue) {
2329 destroy_workqueue(efx->workqueue);
2330 efx->workqueue = NULL;
2331 }
2332}
2333
2334/**************************************************************************
2335 *
2336 * PCI interface
2337 *
2338 **************************************************************************/
2339
2340/* Main body of final NIC shutdown code
2341 * This is called only at module unload (or hotplug removal).
2342 */
2343static void efx_pci_remove_main(struct efx_nic *efx)
2344{
2345#ifdef CONFIG_RFS_ACCEL
2346 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
2347 efx->net_dev->rx_cpu_rmap = NULL;
2348#endif
2349 efx_nic_fini_interrupt(efx);
2350 efx_fini_channels(efx);
2351 efx_fini_port(efx);
2352 efx->type->fini(efx);
2353 efx_fini_napi(efx);
2354 efx_remove_all(efx);
2355}
2356
2357/* Final NIC shutdown
2358 * This is called only at module unload (or hotplug removal).
2359 */
2360static void efx_pci_remove(struct pci_dev *pci_dev)
2361{
2362 struct efx_nic *efx;
2363
2364 efx = pci_get_drvdata(pci_dev);
2365 if (!efx)
2366 return;
2367
2368 /* Mark the NIC as fini, then stop the interface */
2369 rtnl_lock();
2370 efx->state = STATE_FINI;
2371 dev_close(efx->net_dev);
2372
2373 /* Allow any queued efx_resets() to complete */
2374 rtnl_unlock();
2375
2376 efx_unregister_netdev(efx);
2377
2378 efx_mtd_remove(efx);
2379
2380 /* Wait for any scheduled resets to complete. No more will be
2381 * scheduled from this point because efx_stop_all() has been
2382 * called, we are no longer registered with driverlink, and
2383 * the net_device's have been removed. */
2384 cancel_work_sync(&efx->reset_work);
2385
2386 efx_pci_remove_main(efx);
2387
2388 efx_fini_io(efx);
2389 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
2390
2391 pci_set_drvdata(pci_dev, NULL);
2392 efx_fini_struct(efx);
2393 free_netdev(efx->net_dev);
2394};
2395
2396/* Main body of NIC initialisation
2397 * This is called at module load (or hotplug insertion, theoretically).
2398 */
2399static int efx_pci_probe_main(struct efx_nic *efx)
2400{
2401 int rc;
2402
2403 /* Do start-of-day initialisation */
2404 rc = efx_probe_all(efx);
2405 if (rc)
2406 goto fail1;
2407
2408 efx_init_napi(efx);
2409
2410 rc = efx->type->init(efx);
2411 if (rc) {
2412 netif_err(efx, probe, efx->net_dev,
2413 "failed to initialise NIC\n");
2414 goto fail3;
2415 }
2416
2417 rc = efx_init_port(efx);
2418 if (rc) {
2419 netif_err(efx, probe, efx->net_dev,
2420 "failed to initialise port\n");
2421 goto fail4;
2422 }
2423
2424 efx_init_channels(efx);
2425
2426 rc = efx_nic_init_interrupt(efx);
2427 if (rc)
2428 goto fail5;
2429
2430 return 0;
2431
2432 fail5:
2433 efx_fini_channels(efx);
2434 efx_fini_port(efx);
2435 fail4:
2436 efx->type->fini(efx);
2437 fail3:
2438 efx_fini_napi(efx);
2439 efx_remove_all(efx);
2440 fail1:
2441 return rc;
2442}
2443
2444/* NIC initialisation
2445 *
2446 * This is called at module load (or hotplug insertion,
2447 * theoretically). It sets up PCI mappings, tests and resets the NIC,
2448 * sets up and registers the network devices with the kernel and hooks
2449 * the interrupt service routine. It does not prepare the device for
2450 * transmission; this is left to the first time one of the network
2451 * interfaces is brought up (i.e. efx_net_open).
2452 */
2453static int __devinit efx_pci_probe(struct pci_dev *pci_dev,
2454 const struct pci_device_id *entry)
2455{
2456 const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data;
2457 struct net_device *net_dev;
2458 struct efx_nic *efx;
2459 int i, rc;
2460
2461 /* Allocate and initialise a struct net_device and struct efx_nic */
2462 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2463 EFX_MAX_RX_QUEUES);
2464 if (!net_dev)
2465 return -ENOMEM;
2466 net_dev->features |= (type->offload_features | NETIF_F_SG |
2467 NETIF_F_HIGHDMA | NETIF_F_TSO |
2468 NETIF_F_RXCSUM);
2469 if (type->offload_features & NETIF_F_V6_CSUM)
2470 net_dev->features |= NETIF_F_TSO6;
2471 /* Mask for features that also apply to VLAN devices */
2472 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
2473 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2474 NETIF_F_RXCSUM);
2475 /* All offloads can be toggled */
2476 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
2477 efx = netdev_priv(net_dev);
2478 pci_set_drvdata(pci_dev, efx);
2479 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
2480 rc = efx_init_struct(efx, type, pci_dev, net_dev);
2481 if (rc)
2482 goto fail1;
2483
2484 netif_info(efx, probe, efx->net_dev,
2485 "Solarflare Communications NIC detected\n");
2486
2487 /* Set up basic I/O (BAR mappings etc) */
2488 rc = efx_init_io(efx);
2489 if (rc)
2490 goto fail2;
2491
2492 /* No serialisation is required with the reset path because
2493 * we're in STATE_INIT. */
2494 for (i = 0; i < 5; i++) {
2495 rc = efx_pci_probe_main(efx);
2496
2497 /* Serialise against efx_reset(). No more resets will be
2498 * scheduled since efx_stop_all() has been called, and we
2499 * have not and never have been registered with either
2500 * the rtnetlink or driverlink layers. */
2501 cancel_work_sync(&efx->reset_work);
2502
2503 if (rc == 0) {
2504 if (efx->reset_pending != RESET_TYPE_NONE) {
2505 /* If there was a scheduled reset during
2506 * probe, the NIC is probably hosed anyway */
2507 efx_pci_remove_main(efx);
2508 rc = -EIO;
2509 } else {
2510 break;
2511 }
2512 }
2513
2514 /* Retry if a recoverably reset event has been scheduled */
2515 if ((efx->reset_pending != RESET_TYPE_INVISIBLE) &&
2516 (efx->reset_pending != RESET_TYPE_ALL))
2517 goto fail3;
2518
2519 efx->reset_pending = RESET_TYPE_NONE;
2520 }
2521
2522 if (rc) {
2523 netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n");
2524 goto fail4;
2525 }
2526
2527 /* Switch to the running state before we expose the device to the OS,
2528 * so that dev_open()|efx_start_all() will actually start the device */
2529 efx->state = STATE_RUNNING;
2530
2531 rc = efx_register_netdev(efx);
2532 if (rc)
2533 goto fail5;
2534
2535 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
2536
2537 rtnl_lock();
2538 efx_mtd_probe(efx); /* allowed to fail */
2539 rtnl_unlock();
2540 return 0;
2541
2542 fail5:
2543 efx_pci_remove_main(efx);
2544 fail4:
2545 fail3:
2546 efx_fini_io(efx);
2547 fail2:
2548 efx_fini_struct(efx);
2549 fail1:
2550 WARN_ON(rc > 0);
2551 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
2552 free_netdev(net_dev);
2553 return rc;
2554}
2555
2556static int efx_pm_freeze(struct device *dev)
2557{
2558 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2559
2560 efx->state = STATE_FINI;
2561
2562 netif_device_detach(efx->net_dev);
2563
2564 efx_stop_all(efx);
2565 efx_fini_channels(efx);
2566
2567 return 0;
2568}
2569
2570static int efx_pm_thaw(struct device *dev)
2571{
2572 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2573
2574 efx->state = STATE_INIT;
2575
2576 efx_init_channels(efx);
2577
2578 mutex_lock(&efx->mac_lock);
2579 efx->phy_op->reconfigure(efx);
2580 mutex_unlock(&efx->mac_lock);
2581
2582 efx_start_all(efx);
2583
2584 netif_device_attach(efx->net_dev);
2585
2586 efx->state = STATE_RUNNING;
2587
2588 efx->type->resume_wol(efx);
2589
2590 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2591 queue_work(reset_workqueue, &efx->reset_work);
2592
2593 return 0;
2594}
2595
2596static int efx_pm_poweroff(struct device *dev)
2597{
2598 struct pci_dev *pci_dev = to_pci_dev(dev);
2599 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2600
2601 efx->type->fini(efx);
2602
2603 efx->reset_pending = RESET_TYPE_NONE;
2604
2605 pci_save_state(pci_dev);
2606 return pci_set_power_state(pci_dev, PCI_D3hot);
2607}
2608
2609/* Used for both resume and restore */
2610static int efx_pm_resume(struct device *dev)
2611{
2612 struct pci_dev *pci_dev = to_pci_dev(dev);
2613 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2614 int rc;
2615
2616 rc = pci_set_power_state(pci_dev, PCI_D0);
2617 if (rc)
2618 return rc;
2619 pci_restore_state(pci_dev);
2620 rc = pci_enable_device(pci_dev);
2621 if (rc)
2622 return rc;
2623 pci_set_master(efx->pci_dev);
2624 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2625 if (rc)
2626 return rc;
2627 rc = efx->type->init(efx);
2628 if (rc)
2629 return rc;
2630 efx_pm_thaw(dev);
2631 return 0;
2632}
2633
2634static int efx_pm_suspend(struct device *dev)
2635{
2636 int rc;
2637
2638 efx_pm_freeze(dev);
2639 rc = efx_pm_poweroff(dev);
2640 if (rc)
2641 efx_pm_resume(dev);
2642 return rc;
2643}
2644
2645static struct dev_pm_ops efx_pm_ops = {
2646 .suspend = efx_pm_suspend,
2647 .resume = efx_pm_resume,
2648 .freeze = efx_pm_freeze,
2649 .thaw = efx_pm_thaw,
2650 .poweroff = efx_pm_poweroff,
2651 .restore = efx_pm_resume,
2652};
2653
2654static struct pci_driver efx_pci_driver = {
2655 .name = KBUILD_MODNAME,
2656 .id_table = efx_pci_table,
2657 .probe = efx_pci_probe,
2658 .remove = efx_pci_remove,
2659 .driver.pm = &efx_pm_ops,
2660};
2661
2662/**************************************************************************
2663 *
2664 * Kernel module interface
2665 *
2666 *************************************************************************/
2667
2668module_param(interrupt_mode, uint, 0444);
2669MODULE_PARM_DESC(interrupt_mode,
2670 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2671
2672static int __init efx_init_module(void)
2673{
2674 int rc;
2675
2676 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2677
2678 rc = register_netdevice_notifier(&efx_netdev_notifier);
2679 if (rc)
2680 goto err_notifier;
2681
2682 reset_workqueue = create_singlethread_workqueue("sfc_reset");
2683 if (!reset_workqueue) {
2684 rc = -ENOMEM;
2685 goto err_reset;
2686 }
2687
2688 rc = pci_register_driver(&efx_pci_driver);
2689 if (rc < 0)
2690 goto err_pci;
2691
2692 return 0;
2693
2694 err_pci:
2695 destroy_workqueue(reset_workqueue);
2696 err_reset:
2697 unregister_netdevice_notifier(&efx_netdev_notifier);
2698 err_notifier:
2699 return rc;
2700}
2701
2702static void __exit efx_exit_module(void)
2703{
2704 printk(KERN_INFO "Solarflare NET driver unloading\n");
2705
2706 pci_unregister_driver(&efx_pci_driver);
2707 destroy_workqueue(reset_workqueue);
2708 unregister_netdevice_notifier(&efx_netdev_notifier);
2709
2710}
2711
2712module_init(efx_init_module);
2713module_exit(efx_exit_module);
2714
2715MODULE_AUTHOR("Solarflare Communications and "
2716 "Michael Brown <mbrown@fensystems.co.uk>");
2717MODULE_DESCRIPTION("Solarflare Communications network driver");
2718MODULE_LICENSE("GPL");
2719MODULE_DEVICE_TABLE(pci, efx_pci_table);
kernel source for telekom puls (alcatel/mediatek)