| 1 | #define VERSION "0.23" |
| 2 | /* ns83820.c by Benjamin LaHaise with contributions. |
| 3 | * |
| 4 | * Questions/comments/discussion to linux-ns83820@kvack.org. |
| 5 | * |
| 6 | * $Revision: 1.34.2.23 $ |
| 7 | * |
| 8 | * Copyright 2001 Benjamin LaHaise. |
| 9 | * Copyright 2001, 2002 Red Hat. |
| 10 | * |
| 11 | * Mmmm, chocolate vanilla mocha... |
| 12 | * |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, write to the Free Software |
| 26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 27 | * |
| 28 | * |
| 29 | * ChangeLog |
| 30 | * ========= |
| 31 | * 20010414 0.1 - created |
| 32 | * 20010622 0.2 - basic rx and tx. |
| 33 | * 20010711 0.3 - added duplex and link state detection support. |
| 34 | * 20010713 0.4 - zero copy, no hangs. |
| 35 | * 0.5 - 64 bit dma support (davem will hate me for this) |
| 36 | * - disable jumbo frames to avoid tx hangs |
| 37 | * - work around tx deadlocks on my 1.02 card via |
| 38 | * fiddling with TXCFG |
| 39 | * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64 |
| 40 | * 20010816 0.7 - misc cleanups |
| 41 | * 20010826 0.8 - fix critical zero copy bugs |
| 42 | * 0.9 - internal experiment |
| 43 | * 20010827 0.10 - fix ia64 unaligned access. |
| 44 | * 20010906 0.11 - accept all packets with checksum errors as |
| 45 | * otherwise fragments get lost |
| 46 | * - fix >> 32 bugs |
| 47 | * 0.12 - add statistics counters |
| 48 | * - add allmulti/promisc support |
| 49 | * 20011009 0.13 - hotplug support, other smaller pci api cleanups |
| 50 | * 20011204 0.13a - optical transceiver support added |
| 51 | * by Michael Clark <michael@metaparadigm.com> |
| 52 | * 20011205 0.13b - call register_netdev earlier in initialization |
| 53 | * suppress duplicate link status messages |
| 54 | * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik |
| 55 | * 20011204 0.15 get ppc (big endian) working |
| 56 | * 20011218 0.16 various cleanups |
| 57 | * 20020310 0.17 speedups |
| 58 | * 20020610 0.18 - actually use the pci dma api for highmem |
| 59 | * - remove pci latency register fiddling |
| 60 | * 0.19 - better bist support |
| 61 | * - add ihr and reset_phy parameters |
| 62 | * - gmii bus probing |
| 63 | * - fix missed txok introduced during performance |
| 64 | * tuning |
| 65 | * 0.20 - fix stupid RFEN thinko. i am such a smurf. |
| 66 | * 20040828 0.21 - add hardware vlan accleration |
| 67 | * by Neil Horman <nhorman@redhat.com> |
| 68 | * 20050406 0.22 - improved DAC ifdefs from Andi Kleen |
| 69 | * - removal of dead code from Adrian Bunk |
| 70 | * - fix half duplex collision behaviour |
| 71 | * Driver Overview |
| 72 | * =============== |
| 73 | * |
| 74 | * This driver was originally written for the National Semiconductor |
| 75 | * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully |
| 76 | * this code will turn out to be a) clean, b) correct, and c) fast. |
| 77 | * With that in mind, I'm aiming to split the code up as much as |
| 78 | * reasonably possible. At present there are X major sections that |
| 79 | * break down into a) packet receive, b) packet transmit, c) link |
| 80 | * management, d) initialization and configuration. Where possible, |
| 81 | * these code paths are designed to run in parallel. |
| 82 | * |
| 83 | * This driver has been tested and found to work with the following |
| 84 | * cards (in no particular order): |
| 85 | * |
| 86 | * Cameo SOHO-GA2000T SOHO-GA2500T |
| 87 | * D-Link DGE-500T |
| 88 | * PureData PDP8023Z-TG |
| 89 | * SMC SMC9452TX SMC9462TX |
| 90 | * Netgear GA621 |
| 91 | * |
| 92 | * Special thanks to SMC for providing hardware to test this driver on. |
| 93 | * |
| 94 | * Reports of success or failure would be greatly appreciated. |
| 95 | */ |
| 96 | //#define dprintk printk |
| 97 | #define dprintk(x...) do { } while (0) |
| 98 | |
| 99 | #include <linux/module.h> |
| 100 | #include <linux/moduleparam.h> |
| 101 | #include <linux/types.h> |
| 102 | #include <linux/pci.h> |
| 103 | #include <linux/dma-mapping.h> |
| 104 | #include <linux/netdevice.h> |
| 105 | #include <linux/etherdevice.h> |
| 106 | #include <linux/delay.h> |
| 107 | #include <linux/workqueue.h> |
| 108 | #include <linux/init.h> |
| 109 | #include <linux/ip.h> /* for iph */ |
| 110 | #include <linux/in.h> /* for IPPROTO_... */ |
| 111 | #include <linux/compiler.h> |
| 112 | #include <linux/prefetch.h> |
| 113 | #include <linux/ethtool.h> |
| 114 | #include <linux/timer.h> |
| 115 | #include <linux/if_vlan.h> |
| 116 | #include <linux/rtnetlink.h> |
| 117 | #include <linux/jiffies.h> |
| 118 | |
| 119 | #include <asm/io.h> |
| 120 | #include <asm/uaccess.h> |
| 121 | #include <asm/system.h> |
| 122 | |
| 123 | #define DRV_NAME "ns83820" |
| 124 | |
| 125 | /* Global parameters. See module_param near the bottom. */ |
| 126 | static int ihr = 2; |
| 127 | static int reset_phy = 0; |
| 128 | static int lnksts = 0; /* CFG_LNKSTS bit polarity */ |
| 129 | |
| 130 | /* Dprintk is used for more interesting debug events */ |
| 131 | #undef Dprintk |
| 132 | #define Dprintk dprintk |
| 133 | |
| 134 | /* tunables */ |
| 135 | #define RX_BUF_SIZE 1500 /* 8192 */ |
| 136 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
| 137 | #define NS83820_VLAN_ACCEL_SUPPORT |
| 138 | #endif |
| 139 | |
| 140 | /* Must not exceed ~65000. */ |
| 141 | #define NR_RX_DESC 64 |
| 142 | #define NR_TX_DESC 128 |
| 143 | |
| 144 | /* not tunable */ |
| 145 | #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */ |
| 146 | |
| 147 | #define MIN_TX_DESC_FREE 8 |
| 148 | |
| 149 | /* register defines */ |
| 150 | #define CFGCS 0x04 |
| 151 | |
| 152 | #define CR_TXE 0x00000001 |
| 153 | #define CR_TXD 0x00000002 |
| 154 | /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE |
| 155 | * The Receive engine skips one descriptor and moves |
| 156 | * onto the next one!! */ |
| 157 | #define CR_RXE 0x00000004 |
| 158 | #define CR_RXD 0x00000008 |
| 159 | #define CR_TXR 0x00000010 |
| 160 | #define CR_RXR 0x00000020 |
| 161 | #define CR_SWI 0x00000080 |
| 162 | #define CR_RST 0x00000100 |
| 163 | |
| 164 | #define PTSCR_EEBIST_FAIL 0x00000001 |
| 165 | #define PTSCR_EEBIST_EN 0x00000002 |
| 166 | #define PTSCR_EELOAD_EN 0x00000004 |
| 167 | #define PTSCR_RBIST_FAIL 0x000001b8 |
| 168 | #define PTSCR_RBIST_DONE 0x00000200 |
| 169 | #define PTSCR_RBIST_EN 0x00000400 |
| 170 | #define PTSCR_RBIST_RST 0x00002000 |
| 171 | |
| 172 | #define MEAR_EEDI 0x00000001 |
| 173 | #define MEAR_EEDO 0x00000002 |
| 174 | #define MEAR_EECLK 0x00000004 |
| 175 | #define MEAR_EESEL 0x00000008 |
| 176 | #define MEAR_MDIO 0x00000010 |
| 177 | #define MEAR_MDDIR 0x00000020 |
| 178 | #define MEAR_MDC 0x00000040 |
| 179 | |
| 180 | #define ISR_TXDESC3 0x40000000 |
| 181 | #define ISR_TXDESC2 0x20000000 |
| 182 | #define ISR_TXDESC1 0x10000000 |
| 183 | #define ISR_TXDESC0 0x08000000 |
| 184 | #define ISR_RXDESC3 0x04000000 |
| 185 | #define ISR_RXDESC2 0x02000000 |
| 186 | #define ISR_RXDESC1 0x01000000 |
| 187 | #define ISR_RXDESC0 0x00800000 |
| 188 | #define ISR_TXRCMP 0x00400000 |
| 189 | #define ISR_RXRCMP 0x00200000 |
| 190 | #define ISR_DPERR 0x00100000 |
| 191 | #define ISR_SSERR 0x00080000 |
| 192 | #define ISR_RMABT 0x00040000 |
| 193 | #define ISR_RTABT 0x00020000 |
| 194 | #define ISR_RXSOVR 0x00010000 |
| 195 | #define ISR_HIBINT 0x00008000 |
| 196 | #define ISR_PHY 0x00004000 |
| 197 | #define ISR_PME 0x00002000 |
| 198 | #define ISR_SWI 0x00001000 |
| 199 | #define ISR_MIB 0x00000800 |
| 200 | #define ISR_TXURN 0x00000400 |
| 201 | #define ISR_TXIDLE 0x00000200 |
| 202 | #define ISR_TXERR 0x00000100 |
| 203 | #define ISR_TXDESC 0x00000080 |
| 204 | #define ISR_TXOK 0x00000040 |
| 205 | #define ISR_RXORN 0x00000020 |
| 206 | #define ISR_RXIDLE 0x00000010 |
| 207 | #define ISR_RXEARLY 0x00000008 |
| 208 | #define ISR_RXERR 0x00000004 |
| 209 | #define ISR_RXDESC 0x00000002 |
| 210 | #define ISR_RXOK 0x00000001 |
| 211 | |
| 212 | #define TXCFG_CSI 0x80000000 |
| 213 | #define TXCFG_HBI 0x40000000 |
| 214 | #define TXCFG_MLB 0x20000000 |
| 215 | #define TXCFG_ATP 0x10000000 |
| 216 | #define TXCFG_ECRETRY 0x00800000 |
| 217 | #define TXCFG_BRST_DIS 0x00080000 |
| 218 | #define TXCFG_MXDMA1024 0x00000000 |
| 219 | #define TXCFG_MXDMA512 0x00700000 |
| 220 | #define TXCFG_MXDMA256 0x00600000 |
| 221 | #define TXCFG_MXDMA128 0x00500000 |
| 222 | #define TXCFG_MXDMA64 0x00400000 |
| 223 | #define TXCFG_MXDMA32 0x00300000 |
| 224 | #define TXCFG_MXDMA16 0x00200000 |
| 225 | #define TXCFG_MXDMA8 0x00100000 |
| 226 | |
| 227 | #define CFG_LNKSTS 0x80000000 |
| 228 | #define CFG_SPDSTS 0x60000000 |
| 229 | #define CFG_SPDSTS1 0x40000000 |
| 230 | #define CFG_SPDSTS0 0x20000000 |
| 231 | #define CFG_DUPSTS 0x10000000 |
| 232 | #define CFG_TBI_EN 0x01000000 |
| 233 | #define CFG_MODE_1000 0x00400000 |
| 234 | /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy. |
| 235 | * Read the Phy response and then configure the MAC accordingly */ |
| 236 | #define CFG_AUTO_1000 0x00200000 |
| 237 | #define CFG_PINT_CTL 0x001c0000 |
| 238 | #define CFG_PINT_DUPSTS 0x00100000 |
| 239 | #define CFG_PINT_LNKSTS 0x00080000 |
| 240 | #define CFG_PINT_SPDSTS 0x00040000 |
| 241 | #define CFG_TMRTEST 0x00020000 |
| 242 | #define CFG_MRM_DIS 0x00010000 |
| 243 | #define CFG_MWI_DIS 0x00008000 |
| 244 | #define CFG_T64ADDR 0x00004000 |
| 245 | #define CFG_PCI64_DET 0x00002000 |
| 246 | #define CFG_DATA64_EN 0x00001000 |
| 247 | #define CFG_M64ADDR 0x00000800 |
| 248 | #define CFG_PHY_RST 0x00000400 |
| 249 | #define CFG_PHY_DIS 0x00000200 |
| 250 | #define CFG_EXTSTS_EN 0x00000100 |
| 251 | #define CFG_REQALG 0x00000080 |
| 252 | #define CFG_SB 0x00000040 |
| 253 | #define CFG_POW 0x00000020 |
| 254 | #define CFG_EXD 0x00000010 |
| 255 | #define CFG_PESEL 0x00000008 |
| 256 | #define CFG_BROM_DIS 0x00000004 |
| 257 | #define CFG_EXT_125 0x00000002 |
| 258 | #define CFG_BEM 0x00000001 |
| 259 | |
| 260 | #define EXTSTS_UDPPKT 0x00200000 |
| 261 | #define EXTSTS_TCPPKT 0x00080000 |
| 262 | #define EXTSTS_IPPKT 0x00020000 |
| 263 | #define EXTSTS_VPKT 0x00010000 |
| 264 | #define EXTSTS_VTG_MASK 0x0000ffff |
| 265 | |
| 266 | #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) |
| 267 | |
| 268 | #define MIBC_MIBS 0x00000008 |
| 269 | #define MIBC_ACLR 0x00000004 |
| 270 | #define MIBC_FRZ 0x00000002 |
| 271 | #define MIBC_WRN 0x00000001 |
| 272 | |
| 273 | #define PCR_PSEN (1 << 31) |
| 274 | #define PCR_PS_MCAST (1 << 30) |
| 275 | #define PCR_PS_DA (1 << 29) |
| 276 | #define PCR_STHI_8 (3 << 23) |
| 277 | #define PCR_STLO_4 (1 << 23) |
| 278 | #define PCR_FFHI_8K (3 << 21) |
| 279 | #define PCR_FFLO_4K (1 << 21) |
| 280 | #define PCR_PAUSE_CNT 0xFFFE |
| 281 | |
| 282 | #define RXCFG_AEP 0x80000000 |
| 283 | #define RXCFG_ARP 0x40000000 |
| 284 | #define RXCFG_STRIPCRC 0x20000000 |
| 285 | #define RXCFG_RX_FD 0x10000000 |
| 286 | #define RXCFG_ALP 0x08000000 |
| 287 | #define RXCFG_AIRL 0x04000000 |
| 288 | #define RXCFG_MXDMA512 0x00700000 |
| 289 | #define RXCFG_DRTH 0x0000003e |
| 290 | #define RXCFG_DRTH0 0x00000002 |
| 291 | |
| 292 | #define RFCR_RFEN 0x80000000 |
| 293 | #define RFCR_AAB 0x40000000 |
| 294 | #define RFCR_AAM 0x20000000 |
| 295 | #define RFCR_AAU 0x10000000 |
| 296 | #define RFCR_APM 0x08000000 |
| 297 | #define RFCR_APAT 0x07800000 |
| 298 | #define RFCR_APAT3 0x04000000 |
| 299 | #define RFCR_APAT2 0x02000000 |
| 300 | #define RFCR_APAT1 0x01000000 |
| 301 | #define RFCR_APAT0 0x00800000 |
| 302 | #define RFCR_AARP 0x00400000 |
| 303 | #define RFCR_MHEN 0x00200000 |
| 304 | #define RFCR_UHEN 0x00100000 |
| 305 | #define RFCR_ULM 0x00080000 |
| 306 | |
| 307 | #define VRCR_RUDPE 0x00000080 |
| 308 | #define VRCR_RTCPE 0x00000040 |
| 309 | #define VRCR_RIPE 0x00000020 |
| 310 | #define VRCR_IPEN 0x00000010 |
| 311 | #define VRCR_DUTF 0x00000008 |
| 312 | #define VRCR_DVTF 0x00000004 |
| 313 | #define VRCR_VTREN 0x00000002 |
| 314 | #define VRCR_VTDEN 0x00000001 |
| 315 | |
| 316 | #define VTCR_PPCHK 0x00000008 |
| 317 | #define VTCR_GCHK 0x00000004 |
| 318 | #define VTCR_VPPTI 0x00000002 |
| 319 | #define VTCR_VGTI 0x00000001 |
| 320 | |
| 321 | #define CR 0x00 |
| 322 | #define CFG 0x04 |
| 323 | #define MEAR 0x08 |
| 324 | #define PTSCR 0x0c |
| 325 | #define ISR 0x10 |
| 326 | #define IMR 0x14 |
| 327 | #define IER 0x18 |
| 328 | #define IHR 0x1c |
| 329 | #define TXDP 0x20 |
| 330 | #define TXDP_HI 0x24 |
| 331 | #define TXCFG 0x28 |
| 332 | #define GPIOR 0x2c |
| 333 | #define RXDP 0x30 |
| 334 | #define RXDP_HI 0x34 |
| 335 | #define RXCFG 0x38 |
| 336 | #define PQCR 0x3c |
| 337 | #define WCSR 0x40 |
| 338 | #define PCR 0x44 |
| 339 | #define RFCR 0x48 |
| 340 | #define RFDR 0x4c |
| 341 | |
| 342 | #define SRR 0x58 |
| 343 | |
| 344 | #define VRCR 0xbc |
| 345 | #define VTCR 0xc0 |
| 346 | #define VDR 0xc4 |
| 347 | #define CCSR 0xcc |
| 348 | |
| 349 | #define TBICR 0xe0 |
| 350 | #define TBISR 0xe4 |
| 351 | #define TANAR 0xe8 |
| 352 | #define TANLPAR 0xec |
| 353 | #define TANER 0xf0 |
| 354 | #define TESR 0xf4 |
| 355 | |
| 356 | #define TBICR_MR_AN_ENABLE 0x00001000 |
| 357 | #define TBICR_MR_RESTART_AN 0x00000200 |
| 358 | |
| 359 | #define TBISR_MR_LINK_STATUS 0x00000020 |
| 360 | #define TBISR_MR_AN_COMPLETE 0x00000004 |
| 361 | |
| 362 | #define TANAR_PS2 0x00000100 |
| 363 | #define TANAR_PS1 0x00000080 |
| 364 | #define TANAR_HALF_DUP 0x00000040 |
| 365 | #define TANAR_FULL_DUP 0x00000020 |
| 366 | |
| 367 | #define GPIOR_GP5_OE 0x00000200 |
| 368 | #define GPIOR_GP4_OE 0x00000100 |
| 369 | #define GPIOR_GP3_OE 0x00000080 |
| 370 | #define GPIOR_GP2_OE 0x00000040 |
| 371 | #define GPIOR_GP1_OE 0x00000020 |
| 372 | #define GPIOR_GP3_OUT 0x00000004 |
| 373 | #define GPIOR_GP1_OUT 0x00000001 |
| 374 | |
| 375 | #define LINK_AUTONEGOTIATE 0x01 |
| 376 | #define LINK_DOWN 0x02 |
| 377 | #define LINK_UP 0x04 |
| 378 | |
| 379 | #define HW_ADDR_LEN sizeof(dma_addr_t) |
| 380 | #define desc_addr_set(desc, addr) \ |
| 381 | do { \ |
| 382 | ((desc)[0] = cpu_to_le32(addr)); \ |
| 383 | if (HW_ADDR_LEN == 8) \ |
| 384 | (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \ |
| 385 | } while(0) |
| 386 | #define desc_addr_get(desc) \ |
| 387 | (le32_to_cpu((desc)[0]) | \ |
| 388 | (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0)) |
| 389 | |
| 390 | #define DESC_LINK 0 |
| 391 | #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4) |
| 392 | #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4) |
| 393 | #define DESC_EXTSTS (DESC_CMDSTS + 4/4) |
| 394 | |
| 395 | #define CMDSTS_OWN 0x80000000 |
| 396 | #define CMDSTS_MORE 0x40000000 |
| 397 | #define CMDSTS_INTR 0x20000000 |
| 398 | #define CMDSTS_ERR 0x10000000 |
| 399 | #define CMDSTS_OK 0x08000000 |
| 400 | #define CMDSTS_RUNT 0x00200000 |
| 401 | #define CMDSTS_LEN_MASK 0x0000ffff |
| 402 | |
| 403 | #define CMDSTS_DEST_MASK 0x01800000 |
| 404 | #define CMDSTS_DEST_SELF 0x00800000 |
| 405 | #define CMDSTS_DEST_MULTI 0x01000000 |
| 406 | |
| 407 | #define DESC_SIZE 8 /* Should be cache line sized */ |
| 408 | |
| 409 | struct rx_info { |
| 410 | spinlock_t lock; |
| 411 | int up; |
| 412 | unsigned long idle; |
| 413 | |
| 414 | struct sk_buff *skbs[NR_RX_DESC]; |
| 415 | |
| 416 | __le32 *next_rx_desc; |
| 417 | u16 next_rx, next_empty; |
| 418 | |
| 419 | __le32 *descs; |
| 420 | dma_addr_t phy_descs; |
| 421 | }; |
| 422 | |
| 423 | |
| 424 | struct ns83820 { |
| 425 | struct net_device_stats stats; |
| 426 | u8 __iomem *base; |
| 427 | |
| 428 | struct pci_dev *pci_dev; |
| 429 | struct net_device *ndev; |
| 430 | |
| 431 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 432 | struct vlan_group *vlgrp; |
| 433 | #endif |
| 434 | |
| 435 | struct rx_info rx_info; |
| 436 | struct tasklet_struct rx_tasklet; |
| 437 | |
| 438 | unsigned ihr; |
| 439 | struct work_struct tq_refill; |
| 440 | |
| 441 | /* protects everything below. irqsave when using. */ |
| 442 | spinlock_t misc_lock; |
| 443 | |
| 444 | u32 CFG_cache; |
| 445 | |
| 446 | u32 MEAR_cache; |
| 447 | u32 IMR_cache; |
| 448 | |
| 449 | unsigned linkstate; |
| 450 | |
| 451 | spinlock_t tx_lock; |
| 452 | |
| 453 | u16 tx_done_idx; |
| 454 | u16 tx_idx; |
| 455 | volatile u16 tx_free_idx; /* idx of free desc chain */ |
| 456 | u16 tx_intr_idx; |
| 457 | |
| 458 | atomic_t nr_tx_skbs; |
| 459 | struct sk_buff *tx_skbs[NR_TX_DESC]; |
| 460 | |
| 461 | char pad[16] __attribute__((aligned(16))); |
| 462 | __le32 *tx_descs; |
| 463 | dma_addr_t tx_phy_descs; |
| 464 | |
| 465 | struct timer_list tx_watchdog; |
| 466 | }; |
| 467 | |
| 468 | static inline struct ns83820 *PRIV(struct net_device *dev) |
| 469 | { |
| 470 | return netdev_priv(dev); |
| 471 | } |
| 472 | |
| 473 | #define __kick_rx(dev) writel(CR_RXE, dev->base + CR) |
| 474 | |
| 475 | static inline void kick_rx(struct net_device *ndev) |
| 476 | { |
| 477 | struct ns83820 *dev = PRIV(ndev); |
| 478 | dprintk("kick_rx: maybe kicking\n"); |
| 479 | if (test_and_clear_bit(0, &dev->rx_info.idle)) { |
| 480 | dprintk("actually kicking\n"); |
| 481 | writel(dev->rx_info.phy_descs + |
| 482 | (4 * DESC_SIZE * dev->rx_info.next_rx), |
| 483 | dev->base + RXDP); |
| 484 | if (dev->rx_info.next_rx == dev->rx_info.next_empty) |
| 485 | printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n", |
| 486 | ndev->name); |
| 487 | __kick_rx(dev); |
| 488 | } |
| 489 | } |
| 490 | |
| 491 | //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC |
| 492 | #define start_tx_okay(dev) \ |
| 493 | (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE) |
| 494 | |
| 495 | |
| 496 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 497 | static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp) |
| 498 | { |
| 499 | struct ns83820 *dev = PRIV(ndev); |
| 500 | |
| 501 | spin_lock_irq(&dev->misc_lock); |
| 502 | spin_lock(&dev->tx_lock); |
| 503 | |
| 504 | dev->vlgrp = grp; |
| 505 | |
| 506 | spin_unlock(&dev->tx_lock); |
| 507 | spin_unlock_irq(&dev->misc_lock); |
| 508 | } |
| 509 | #endif |
| 510 | |
| 511 | /* Packet Receiver |
| 512 | * |
| 513 | * The hardware supports linked lists of receive descriptors for |
| 514 | * which ownership is transfered back and forth by means of an |
| 515 | * ownership bit. While the hardware does support the use of a |
| 516 | * ring for receive descriptors, we only make use of a chain in |
| 517 | * an attempt to reduce bus traffic under heavy load scenarios. |
| 518 | * This will also make bugs a bit more obvious. The current code |
| 519 | * only makes use of a single rx chain; I hope to implement |
| 520 | * priority based rx for version 1.0. Goal: even under overload |
| 521 | * conditions, still route realtime traffic with as low jitter as |
| 522 | * possible. |
| 523 | */ |
| 524 | static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts) |
| 525 | { |
| 526 | desc_addr_set(desc + DESC_LINK, link); |
| 527 | desc_addr_set(desc + DESC_BUFPTR, buf); |
| 528 | desc[DESC_EXTSTS] = cpu_to_le32(extsts); |
| 529 | mb(); |
| 530 | desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); |
| 531 | } |
| 532 | |
| 533 | #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC) |
| 534 | static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb) |
| 535 | { |
| 536 | unsigned next_empty; |
| 537 | u32 cmdsts; |
| 538 | __le32 *sg; |
| 539 | dma_addr_t buf; |
| 540 | |
| 541 | next_empty = dev->rx_info.next_empty; |
| 542 | |
| 543 | /* don't overrun last rx marker */ |
| 544 | if (unlikely(nr_rx_empty(dev) <= 2)) { |
| 545 | kfree_skb(skb); |
| 546 | return 1; |
| 547 | } |
| 548 | |
| 549 | #if 0 |
| 550 | dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n", |
| 551 | dev->rx_info.next_empty, |
| 552 | dev->rx_info.nr_used, |
| 553 | dev->rx_info.next_rx |
| 554 | ); |
| 555 | #endif |
| 556 | |
| 557 | sg = dev->rx_info.descs + (next_empty * DESC_SIZE); |
| 558 | BUG_ON(NULL != dev->rx_info.skbs[next_empty]); |
| 559 | dev->rx_info.skbs[next_empty] = skb; |
| 560 | |
| 561 | dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC; |
| 562 | cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR; |
| 563 | buf = pci_map_single(dev->pci_dev, skb->data, |
| 564 | REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); |
| 565 | build_rx_desc(dev, sg, 0, buf, cmdsts, 0); |
| 566 | /* update link of previous rx */ |
| 567 | if (likely(next_empty != dev->rx_info.next_rx)) |
| 568 | dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4)); |
| 569 | |
| 570 | return 0; |
| 571 | } |
| 572 | |
| 573 | static inline int rx_refill(struct net_device *ndev, gfp_t gfp) |
| 574 | { |
| 575 | struct ns83820 *dev = PRIV(ndev); |
| 576 | unsigned i; |
| 577 | unsigned long flags = 0; |
| 578 | |
| 579 | if (unlikely(nr_rx_empty(dev) <= 2)) |
| 580 | return 0; |
| 581 | |
| 582 | dprintk("rx_refill(%p)\n", ndev); |
| 583 | if (gfp == GFP_ATOMIC) |
| 584 | spin_lock_irqsave(&dev->rx_info.lock, flags); |
| 585 | for (i=0; i<NR_RX_DESC; i++) { |
| 586 | struct sk_buff *skb; |
| 587 | long res; |
| 588 | |
| 589 | /* extra 16 bytes for alignment */ |
| 590 | skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp); |
| 591 | if (unlikely(!skb)) |
| 592 | break; |
| 593 | |
| 594 | skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16)); |
| 595 | if (gfp != GFP_ATOMIC) |
| 596 | spin_lock_irqsave(&dev->rx_info.lock, flags); |
| 597 | res = ns83820_add_rx_skb(dev, skb); |
| 598 | if (gfp != GFP_ATOMIC) |
| 599 | spin_unlock_irqrestore(&dev->rx_info.lock, flags); |
| 600 | if (res) { |
| 601 | i = 1; |
| 602 | break; |
| 603 | } |
| 604 | } |
| 605 | if (gfp == GFP_ATOMIC) |
| 606 | spin_unlock_irqrestore(&dev->rx_info.lock, flags); |
| 607 | |
| 608 | return i ? 0 : -ENOMEM; |
| 609 | } |
| 610 | |
| 611 | static void rx_refill_atomic(struct net_device *ndev) |
| 612 | { |
| 613 | rx_refill(ndev, GFP_ATOMIC); |
| 614 | } |
| 615 | |
| 616 | /* REFILL */ |
| 617 | static inline void queue_refill(struct work_struct *work) |
| 618 | { |
| 619 | struct ns83820 *dev = container_of(work, struct ns83820, tq_refill); |
| 620 | struct net_device *ndev = dev->ndev; |
| 621 | |
| 622 | rx_refill(ndev, GFP_KERNEL); |
| 623 | if (dev->rx_info.up) |
| 624 | kick_rx(ndev); |
| 625 | } |
| 626 | |
| 627 | static inline void clear_rx_desc(struct ns83820 *dev, unsigned i) |
| 628 | { |
| 629 | build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0); |
| 630 | } |
| 631 | |
| 632 | static void phy_intr(struct net_device *ndev) |
| 633 | { |
| 634 | struct ns83820 *dev = PRIV(ndev); |
| 635 | static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" }; |
| 636 | u32 cfg, new_cfg; |
| 637 | u32 tbisr, tanar, tanlpar; |
| 638 | int speed, fullduplex, newlinkstate; |
| 639 | |
| 640 | cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; |
| 641 | |
| 642 | if (dev->CFG_cache & CFG_TBI_EN) { |
| 643 | /* we have an optical transceiver */ |
| 644 | tbisr = readl(dev->base + TBISR); |
| 645 | tanar = readl(dev->base + TANAR); |
| 646 | tanlpar = readl(dev->base + TANLPAR); |
| 647 | dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n", |
| 648 | tbisr, tanar, tanlpar); |
| 649 | |
| 650 | if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) |
| 651 | && (tanar & TANAR_FULL_DUP)) ) { |
| 652 | |
| 653 | /* both of us are full duplex */ |
| 654 | writel(readl(dev->base + TXCFG) |
| 655 | | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP, |
| 656 | dev->base + TXCFG); |
| 657 | writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, |
| 658 | dev->base + RXCFG); |
| 659 | /* Light up full duplex LED */ |
| 660 | writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, |
| 661 | dev->base + GPIOR); |
| 662 | |
| 663 | } else if(((tanlpar & TANAR_HALF_DUP) |
| 664 | && (tanar & TANAR_HALF_DUP)) |
| 665 | || ((tanlpar & TANAR_FULL_DUP) |
| 666 | && (tanar & TANAR_HALF_DUP)) |
| 667 | || ((tanlpar & TANAR_HALF_DUP) |
| 668 | && (tanar & TANAR_FULL_DUP))) { |
| 669 | |
| 670 | /* one or both of us are half duplex */ |
| 671 | writel((readl(dev->base + TXCFG) |
| 672 | & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP, |
| 673 | dev->base + TXCFG); |
| 674 | writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, |
| 675 | dev->base + RXCFG); |
| 676 | /* Turn off full duplex LED */ |
| 677 | writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, |
| 678 | dev->base + GPIOR); |
| 679 | } |
| 680 | |
| 681 | speed = 4; /* 1000F */ |
| 682 | |
| 683 | } else { |
| 684 | /* we have a copper transceiver */ |
| 685 | new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS); |
| 686 | |
| 687 | if (cfg & CFG_SPDSTS1) |
| 688 | new_cfg |= CFG_MODE_1000; |
| 689 | else |
| 690 | new_cfg &= ~CFG_MODE_1000; |
| 691 | |
| 692 | speed = ((cfg / CFG_SPDSTS0) & 3); |
| 693 | fullduplex = (cfg & CFG_DUPSTS); |
| 694 | |
| 695 | if (fullduplex) { |
| 696 | new_cfg |= CFG_SB; |
| 697 | writel(readl(dev->base + TXCFG) |
| 698 | | TXCFG_CSI | TXCFG_HBI, |
| 699 | dev->base + TXCFG); |
| 700 | writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, |
| 701 | dev->base + RXCFG); |
| 702 | } else { |
| 703 | writel(readl(dev->base + TXCFG) |
| 704 | & ~(TXCFG_CSI | TXCFG_HBI), |
| 705 | dev->base + TXCFG); |
| 706 | writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD), |
| 707 | dev->base + RXCFG); |
| 708 | } |
| 709 | |
| 710 | if ((cfg & CFG_LNKSTS) && |
| 711 | ((new_cfg ^ dev->CFG_cache) != 0)) { |
| 712 | writel(new_cfg, dev->base + CFG); |
| 713 | dev->CFG_cache = new_cfg; |
| 714 | } |
| 715 | |
| 716 | dev->CFG_cache &= ~CFG_SPDSTS; |
| 717 | dev->CFG_cache |= cfg & CFG_SPDSTS; |
| 718 | } |
| 719 | |
| 720 | newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN; |
| 721 | |
| 722 | if (newlinkstate & LINK_UP |
| 723 | && dev->linkstate != newlinkstate) { |
| 724 | netif_start_queue(ndev); |
| 725 | netif_wake_queue(ndev); |
| 726 | printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n", |
| 727 | ndev->name, |
| 728 | speeds[speed], |
| 729 | fullduplex ? "full" : "half"); |
| 730 | } else if (newlinkstate & LINK_DOWN |
| 731 | && dev->linkstate != newlinkstate) { |
| 732 | netif_stop_queue(ndev); |
| 733 | printk(KERN_INFO "%s: link now down.\n", ndev->name); |
| 734 | } |
| 735 | |
| 736 | dev->linkstate = newlinkstate; |
| 737 | } |
| 738 | |
| 739 | static int ns83820_setup_rx(struct net_device *ndev) |
| 740 | { |
| 741 | struct ns83820 *dev = PRIV(ndev); |
| 742 | unsigned i; |
| 743 | int ret; |
| 744 | |
| 745 | dprintk("ns83820_setup_rx(%p)\n", ndev); |
| 746 | |
| 747 | dev->rx_info.idle = 1; |
| 748 | dev->rx_info.next_rx = 0; |
| 749 | dev->rx_info.next_rx_desc = dev->rx_info.descs; |
| 750 | dev->rx_info.next_empty = 0; |
| 751 | |
| 752 | for (i=0; i<NR_RX_DESC; i++) |
| 753 | clear_rx_desc(dev, i); |
| 754 | |
| 755 | writel(0, dev->base + RXDP_HI); |
| 756 | writel(dev->rx_info.phy_descs, dev->base + RXDP); |
| 757 | |
| 758 | ret = rx_refill(ndev, GFP_KERNEL); |
| 759 | if (!ret) { |
| 760 | dprintk("starting receiver\n"); |
| 761 | /* prevent the interrupt handler from stomping on us */ |
| 762 | spin_lock_irq(&dev->rx_info.lock); |
| 763 | |
| 764 | writel(0x0001, dev->base + CCSR); |
| 765 | writel(0, dev->base + RFCR); |
| 766 | writel(0x7fc00000, dev->base + RFCR); |
| 767 | writel(0xffc00000, dev->base + RFCR); |
| 768 | |
| 769 | dev->rx_info.up = 1; |
| 770 | |
| 771 | phy_intr(ndev); |
| 772 | |
| 773 | /* Okay, let it rip */ |
| 774 | spin_lock_irq(&dev->misc_lock); |
| 775 | dev->IMR_cache |= ISR_PHY; |
| 776 | dev->IMR_cache |= ISR_RXRCMP; |
| 777 | //dev->IMR_cache |= ISR_RXERR; |
| 778 | //dev->IMR_cache |= ISR_RXOK; |
| 779 | dev->IMR_cache |= ISR_RXORN; |
| 780 | dev->IMR_cache |= ISR_RXSOVR; |
| 781 | dev->IMR_cache |= ISR_RXDESC; |
| 782 | dev->IMR_cache |= ISR_RXIDLE; |
| 783 | dev->IMR_cache |= ISR_TXDESC; |
| 784 | dev->IMR_cache |= ISR_TXIDLE; |
| 785 | |
| 786 | writel(dev->IMR_cache, dev->base + IMR); |
| 787 | writel(1, dev->base + IER); |
| 788 | spin_unlock(&dev->misc_lock); |
| 789 | |
| 790 | kick_rx(ndev); |
| 791 | |
| 792 | spin_unlock_irq(&dev->rx_info.lock); |
| 793 | } |
| 794 | return ret; |
| 795 | } |
| 796 | |
| 797 | static void ns83820_cleanup_rx(struct ns83820 *dev) |
| 798 | { |
| 799 | unsigned i; |
| 800 | unsigned long flags; |
| 801 | |
| 802 | dprintk("ns83820_cleanup_rx(%p)\n", dev); |
| 803 | |
| 804 | /* disable receive interrupts */ |
| 805 | spin_lock_irqsave(&dev->misc_lock, flags); |
| 806 | dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE); |
| 807 | writel(dev->IMR_cache, dev->base + IMR); |
| 808 | spin_unlock_irqrestore(&dev->misc_lock, flags); |
| 809 | |
| 810 | /* synchronize with the interrupt handler and kill it */ |
| 811 | dev->rx_info.up = 0; |
| 812 | synchronize_irq(dev->pci_dev->irq); |
| 813 | |
| 814 | /* touch the pci bus... */ |
| 815 | readl(dev->base + IMR); |
| 816 | |
| 817 | /* assumes the transmitter is already disabled and reset */ |
| 818 | writel(0, dev->base + RXDP_HI); |
| 819 | writel(0, dev->base + RXDP); |
| 820 | |
| 821 | for (i=0; i<NR_RX_DESC; i++) { |
| 822 | struct sk_buff *skb = dev->rx_info.skbs[i]; |
| 823 | dev->rx_info.skbs[i] = NULL; |
| 824 | clear_rx_desc(dev, i); |
| 825 | kfree_skb(skb); |
| 826 | } |
| 827 | } |
| 828 | |
| 829 | static void ns83820_rx_kick(struct net_device *ndev) |
| 830 | { |
| 831 | struct ns83820 *dev = PRIV(ndev); |
| 832 | /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ { |
| 833 | if (dev->rx_info.up) { |
| 834 | rx_refill_atomic(ndev); |
| 835 | kick_rx(ndev); |
| 836 | } |
| 837 | } |
| 838 | |
| 839 | if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4) |
| 840 | schedule_work(&dev->tq_refill); |
| 841 | else |
| 842 | kick_rx(ndev); |
| 843 | if (dev->rx_info.idle) |
| 844 | printk(KERN_DEBUG "%s: BAD\n", ndev->name); |
| 845 | } |
| 846 | |
| 847 | /* rx_irq |
| 848 | * |
| 849 | */ |
| 850 | static void rx_irq(struct net_device *ndev) |
| 851 | { |
| 852 | struct ns83820 *dev = PRIV(ndev); |
| 853 | struct rx_info *info = &dev->rx_info; |
| 854 | unsigned next_rx; |
| 855 | int rx_rc, len; |
| 856 | u32 cmdsts; |
| 857 | __le32 *desc; |
| 858 | unsigned long flags; |
| 859 | int nr = 0; |
| 860 | |
| 861 | dprintk("rx_irq(%p)\n", ndev); |
| 862 | dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n", |
| 863 | readl(dev->base + RXDP), |
| 864 | (long)(dev->rx_info.phy_descs), |
| 865 | (int)dev->rx_info.next_rx, |
| 866 | (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)), |
| 867 | (int)dev->rx_info.next_empty, |
| 868 | (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty)) |
| 869 | ); |
| 870 | |
| 871 | spin_lock_irqsave(&info->lock, flags); |
| 872 | if (!info->up) |
| 873 | goto out; |
| 874 | |
| 875 | dprintk("walking descs\n"); |
| 876 | next_rx = info->next_rx; |
| 877 | desc = info->next_rx_desc; |
| 878 | while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) && |
| 879 | (cmdsts != CMDSTS_OWN)) { |
| 880 | struct sk_buff *skb; |
| 881 | u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]); |
| 882 | dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR); |
| 883 | |
| 884 | dprintk("cmdsts: %08x\n", cmdsts); |
| 885 | dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK])); |
| 886 | dprintk("extsts: %08x\n", extsts); |
| 887 | |
| 888 | skb = info->skbs[next_rx]; |
| 889 | info->skbs[next_rx] = NULL; |
| 890 | info->next_rx = (next_rx + 1) % NR_RX_DESC; |
| 891 | |
| 892 | mb(); |
| 893 | clear_rx_desc(dev, next_rx); |
| 894 | |
| 895 | pci_unmap_single(dev->pci_dev, bufptr, |
| 896 | RX_BUF_SIZE, PCI_DMA_FROMDEVICE); |
| 897 | len = cmdsts & CMDSTS_LEN_MASK; |
| 898 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 899 | /* NH: As was mentioned below, this chip is kinda |
| 900 | * brain dead about vlan tag stripping. Frames |
| 901 | * that are 64 bytes with a vlan header appended |
| 902 | * like arp frames, or pings, are flagged as Runts |
| 903 | * when the tag is stripped and hardware. This |
| 904 | * also means that the OK bit in the descriptor |
| 905 | * is cleared when the frame comes in so we have |
| 906 | * to do a specific length check here to make sure |
| 907 | * the frame would have been ok, had we not stripped |
| 908 | * the tag. |
| 909 | */ |
| 910 | if (likely((CMDSTS_OK & cmdsts) || |
| 911 | ((cmdsts & CMDSTS_RUNT) && len >= 56))) { |
| 912 | #else |
| 913 | if (likely(CMDSTS_OK & cmdsts)) { |
| 914 | #endif |
| 915 | skb_put(skb, len); |
| 916 | if (unlikely(!skb)) |
| 917 | goto netdev_mangle_me_harder_failed; |
| 918 | if (cmdsts & CMDSTS_DEST_MULTI) |
| 919 | dev->stats.multicast ++; |
| 920 | dev->stats.rx_packets ++; |
| 921 | dev->stats.rx_bytes += len; |
| 922 | if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) { |
| 923 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 924 | } else { |
| 925 | skb->ip_summed = CHECKSUM_NONE; |
| 926 | } |
| 927 | skb->protocol = eth_type_trans(skb, ndev); |
| 928 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 929 | if(extsts & EXTSTS_VPKT) { |
| 930 | unsigned short tag; |
| 931 | tag = ntohs(extsts & EXTSTS_VTG_MASK); |
| 932 | rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag); |
| 933 | } else { |
| 934 | rx_rc = netif_rx(skb); |
| 935 | } |
| 936 | #else |
| 937 | rx_rc = netif_rx(skb); |
| 938 | #endif |
| 939 | if (NET_RX_DROP == rx_rc) { |
| 940 | netdev_mangle_me_harder_failed: |
| 941 | dev->stats.rx_dropped ++; |
| 942 | } |
| 943 | } else { |
| 944 | kfree_skb(skb); |
| 945 | } |
| 946 | |
| 947 | nr++; |
| 948 | next_rx = info->next_rx; |
| 949 | desc = info->descs + (DESC_SIZE * next_rx); |
| 950 | } |
| 951 | info->next_rx = next_rx; |
| 952 | info->next_rx_desc = info->descs + (DESC_SIZE * next_rx); |
| 953 | |
| 954 | out: |
| 955 | if (0 && !nr) { |
| 956 | Dprintk("dazed: cmdsts_f: %08x\n", cmdsts); |
| 957 | } |
| 958 | |
| 959 | spin_unlock_irqrestore(&info->lock, flags); |
| 960 | } |
| 961 | |
| 962 | static void rx_action(unsigned long _dev) |
| 963 | { |
| 964 | struct net_device *ndev = (void *)_dev; |
| 965 | struct ns83820 *dev = PRIV(ndev); |
| 966 | rx_irq(ndev); |
| 967 | writel(ihr, dev->base + IHR); |
| 968 | |
| 969 | spin_lock_irq(&dev->misc_lock); |
| 970 | dev->IMR_cache |= ISR_RXDESC; |
| 971 | writel(dev->IMR_cache, dev->base + IMR); |
| 972 | spin_unlock_irq(&dev->misc_lock); |
| 973 | |
| 974 | rx_irq(ndev); |
| 975 | ns83820_rx_kick(ndev); |
| 976 | } |
| 977 | |
| 978 | /* Packet Transmit code |
| 979 | */ |
| 980 | static inline void kick_tx(struct ns83820 *dev) |
| 981 | { |
| 982 | dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n", |
| 983 | dev, dev->tx_idx, dev->tx_free_idx); |
| 984 | writel(CR_TXE, dev->base + CR); |
| 985 | } |
| 986 | |
| 987 | /* No spinlock needed on the transmit irq path as the interrupt handler is |
| 988 | * serialized. |
| 989 | */ |
| 990 | static void do_tx_done(struct net_device *ndev) |
| 991 | { |
| 992 | struct ns83820 *dev = PRIV(ndev); |
| 993 | u32 cmdsts, tx_done_idx; |
| 994 | __le32 *desc; |
| 995 | |
| 996 | dprintk("do_tx_done(%p)\n", ndev); |
| 997 | tx_done_idx = dev->tx_done_idx; |
| 998 | desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); |
| 999 | |
| 1000 | dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n", |
| 1001 | tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); |
| 1002 | while ((tx_done_idx != dev->tx_free_idx) && |
| 1003 | !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) { |
| 1004 | struct sk_buff *skb; |
| 1005 | unsigned len; |
| 1006 | dma_addr_t addr; |
| 1007 | |
| 1008 | if (cmdsts & CMDSTS_ERR) |
| 1009 | dev->stats.tx_errors ++; |
| 1010 | if (cmdsts & CMDSTS_OK) |
| 1011 | dev->stats.tx_packets ++; |
| 1012 | if (cmdsts & CMDSTS_OK) |
| 1013 | dev->stats.tx_bytes += cmdsts & 0xffff; |
| 1014 | |
| 1015 | dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n", |
| 1016 | tx_done_idx, dev->tx_free_idx, cmdsts); |
| 1017 | skb = dev->tx_skbs[tx_done_idx]; |
| 1018 | dev->tx_skbs[tx_done_idx] = NULL; |
| 1019 | dprintk("done(%p)\n", skb); |
| 1020 | |
| 1021 | len = cmdsts & CMDSTS_LEN_MASK; |
| 1022 | addr = desc_addr_get(desc + DESC_BUFPTR); |
| 1023 | if (skb) { |
| 1024 | pci_unmap_single(dev->pci_dev, |
| 1025 | addr, |
| 1026 | len, |
| 1027 | PCI_DMA_TODEVICE); |
| 1028 | dev_kfree_skb_irq(skb); |
| 1029 | atomic_dec(&dev->nr_tx_skbs); |
| 1030 | } else |
| 1031 | pci_unmap_page(dev->pci_dev, |
| 1032 | addr, |
| 1033 | len, |
| 1034 | PCI_DMA_TODEVICE); |
| 1035 | |
| 1036 | tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC; |
| 1037 | dev->tx_done_idx = tx_done_idx; |
| 1038 | desc[DESC_CMDSTS] = cpu_to_le32(0); |
| 1039 | mb(); |
| 1040 | desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); |
| 1041 | } |
| 1042 | |
| 1043 | /* Allow network stack to resume queueing packets after we've |
| 1044 | * finished transmitting at least 1/4 of the packets in the queue. |
| 1045 | */ |
| 1046 | if (netif_queue_stopped(ndev) && start_tx_okay(dev)) { |
| 1047 | dprintk("start_queue(%p)\n", ndev); |
| 1048 | netif_start_queue(ndev); |
| 1049 | netif_wake_queue(ndev); |
| 1050 | } |
| 1051 | } |
| 1052 | |
| 1053 | static void ns83820_cleanup_tx(struct ns83820 *dev) |
| 1054 | { |
| 1055 | unsigned i; |
| 1056 | |
| 1057 | for (i=0; i<NR_TX_DESC; i++) { |
| 1058 | struct sk_buff *skb = dev->tx_skbs[i]; |
| 1059 | dev->tx_skbs[i] = NULL; |
| 1060 | if (skb) { |
| 1061 | __le32 *desc = dev->tx_descs + (i * DESC_SIZE); |
| 1062 | pci_unmap_single(dev->pci_dev, |
| 1063 | desc_addr_get(desc + DESC_BUFPTR), |
| 1064 | le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK, |
| 1065 | PCI_DMA_TODEVICE); |
| 1066 | dev_kfree_skb_irq(skb); |
| 1067 | atomic_dec(&dev->nr_tx_skbs); |
| 1068 | } |
| 1069 | } |
| 1070 | |
| 1071 | memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4); |
| 1072 | } |
| 1073 | |
| 1074 | /* transmit routine. This code relies on the network layer serializing |
| 1075 | * its calls in, but will run happily in parallel with the interrupt |
| 1076 | * handler. This code currently has provisions for fragmenting tx buffers |
| 1077 | * while trying to track down a bug in either the zero copy code or |
| 1078 | * the tx fifo (hence the MAX_FRAG_LEN). |
| 1079 | */ |
| 1080 | static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb, |
| 1081 | struct net_device *ndev) |
| 1082 | { |
| 1083 | struct ns83820 *dev = PRIV(ndev); |
| 1084 | u32 free_idx, cmdsts, extsts; |
| 1085 | int nr_free, nr_frags; |
| 1086 | unsigned tx_done_idx, last_idx; |
| 1087 | dma_addr_t buf; |
| 1088 | unsigned len; |
| 1089 | skb_frag_t *frag; |
| 1090 | int stopped = 0; |
| 1091 | int do_intr = 0; |
| 1092 | volatile __le32 *first_desc; |
| 1093 | |
| 1094 | dprintk("ns83820_hard_start_xmit\n"); |
| 1095 | |
| 1096 | nr_frags = skb_shinfo(skb)->nr_frags; |
| 1097 | again: |
| 1098 | if (unlikely(dev->CFG_cache & CFG_LNKSTS)) { |
| 1099 | netif_stop_queue(ndev); |
| 1100 | if (unlikely(dev->CFG_cache & CFG_LNKSTS)) |
| 1101 | return NETDEV_TX_BUSY; |
| 1102 | netif_start_queue(ndev); |
| 1103 | } |
| 1104 | |
| 1105 | last_idx = free_idx = dev->tx_free_idx; |
| 1106 | tx_done_idx = dev->tx_done_idx; |
| 1107 | nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC; |
| 1108 | nr_free -= 1; |
| 1109 | if (nr_free <= nr_frags) { |
| 1110 | dprintk("stop_queue - not enough(%p)\n", ndev); |
| 1111 | netif_stop_queue(ndev); |
| 1112 | |
| 1113 | /* Check again: we may have raced with a tx done irq */ |
| 1114 | if (dev->tx_done_idx != tx_done_idx) { |
| 1115 | dprintk("restart queue(%p)\n", ndev); |
| 1116 | netif_start_queue(ndev); |
| 1117 | goto again; |
| 1118 | } |
| 1119 | return NETDEV_TX_BUSY; |
| 1120 | } |
| 1121 | |
| 1122 | if (free_idx == dev->tx_intr_idx) { |
| 1123 | do_intr = 1; |
| 1124 | dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC; |
| 1125 | } |
| 1126 | |
| 1127 | nr_free -= nr_frags; |
| 1128 | if (nr_free < MIN_TX_DESC_FREE) { |
| 1129 | dprintk("stop_queue - last entry(%p)\n", ndev); |
| 1130 | netif_stop_queue(ndev); |
| 1131 | stopped = 1; |
| 1132 | } |
| 1133 | |
| 1134 | frag = skb_shinfo(skb)->frags; |
| 1135 | if (!nr_frags) |
| 1136 | frag = NULL; |
| 1137 | extsts = 0; |
| 1138 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
| 1139 | extsts |= EXTSTS_IPPKT; |
| 1140 | if (IPPROTO_TCP == ip_hdr(skb)->protocol) |
| 1141 | extsts |= EXTSTS_TCPPKT; |
| 1142 | else if (IPPROTO_UDP == ip_hdr(skb)->protocol) |
| 1143 | extsts |= EXTSTS_UDPPKT; |
| 1144 | } |
| 1145 | |
| 1146 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 1147 | if(vlan_tx_tag_present(skb)) { |
| 1148 | /* fetch the vlan tag info out of the |
| 1149 | * ancilliary data if the vlan code |
| 1150 | * is using hw vlan acceleration |
| 1151 | */ |
| 1152 | short tag = vlan_tx_tag_get(skb); |
| 1153 | extsts |= (EXTSTS_VPKT | htons(tag)); |
| 1154 | } |
| 1155 | #endif |
| 1156 | |
| 1157 | len = skb->len; |
| 1158 | if (nr_frags) |
| 1159 | len -= skb->data_len; |
| 1160 | buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
| 1161 | |
| 1162 | first_desc = dev->tx_descs + (free_idx * DESC_SIZE); |
| 1163 | |
| 1164 | for (;;) { |
| 1165 | volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE); |
| 1166 | |
| 1167 | dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len, |
| 1168 | (unsigned long long)buf); |
| 1169 | last_idx = free_idx; |
| 1170 | free_idx = (free_idx + 1) % NR_TX_DESC; |
| 1171 | desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4)); |
| 1172 | desc_addr_set(desc + DESC_BUFPTR, buf); |
| 1173 | desc[DESC_EXTSTS] = cpu_to_le32(extsts); |
| 1174 | |
| 1175 | cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0); |
| 1176 | cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN; |
| 1177 | cmdsts |= len; |
| 1178 | desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); |
| 1179 | |
| 1180 | if (!nr_frags) |
| 1181 | break; |
| 1182 | |
| 1183 | buf = pci_map_page(dev->pci_dev, frag->page, |
| 1184 | frag->page_offset, |
| 1185 | frag->size, PCI_DMA_TODEVICE); |
| 1186 | dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n", |
| 1187 | (long long)buf, (long) page_to_pfn(frag->page), |
| 1188 | frag->page_offset); |
| 1189 | len = frag->size; |
| 1190 | frag++; |
| 1191 | nr_frags--; |
| 1192 | } |
| 1193 | dprintk("done pkt\n"); |
| 1194 | |
| 1195 | spin_lock_irq(&dev->tx_lock); |
| 1196 | dev->tx_skbs[last_idx] = skb; |
| 1197 | first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN); |
| 1198 | dev->tx_free_idx = free_idx; |
| 1199 | atomic_inc(&dev->nr_tx_skbs); |
| 1200 | spin_unlock_irq(&dev->tx_lock); |
| 1201 | |
| 1202 | kick_tx(dev); |
| 1203 | |
| 1204 | /* Check again: we may have raced with a tx done irq */ |
| 1205 | if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev)) |
| 1206 | netif_start_queue(ndev); |
| 1207 | |
| 1208 | return NETDEV_TX_OK; |
| 1209 | } |
| 1210 | |
| 1211 | static void ns83820_update_stats(struct ns83820 *dev) |
| 1212 | { |
| 1213 | u8 __iomem *base = dev->base; |
| 1214 | |
| 1215 | /* the DP83820 will freeze counters, so we need to read all of them */ |
| 1216 | dev->stats.rx_errors += readl(base + 0x60) & 0xffff; |
| 1217 | dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff; |
| 1218 | dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff; |
| 1219 | dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff; |
| 1220 | /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70); |
| 1221 | dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff; |
| 1222 | dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff; |
| 1223 | /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c); |
| 1224 | /*dev->stats.rx_pause_count += */ readl(base + 0x80); |
| 1225 | /*dev->stats.tx_pause_count += */ readl(base + 0x84); |
| 1226 | dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff; |
| 1227 | } |
| 1228 | |
| 1229 | static struct net_device_stats *ns83820_get_stats(struct net_device *ndev) |
| 1230 | { |
| 1231 | struct ns83820 *dev = PRIV(ndev); |
| 1232 | |
| 1233 | /* somewhat overkill */ |
| 1234 | spin_lock_irq(&dev->misc_lock); |
| 1235 | ns83820_update_stats(dev); |
| 1236 | spin_unlock_irq(&dev->misc_lock); |
| 1237 | |
| 1238 | return &dev->stats; |
| 1239 | } |
| 1240 | |
| 1241 | /* Let ethtool retrieve info */ |
| 1242 | static int ns83820_get_settings(struct net_device *ndev, |
| 1243 | struct ethtool_cmd *cmd) |
| 1244 | { |
| 1245 | struct ns83820 *dev = PRIV(ndev); |
| 1246 | u32 cfg, tanar, tbicr; |
| 1247 | int have_optical = 0; |
| 1248 | int fullduplex = 0; |
| 1249 | |
| 1250 | /* |
| 1251 | * Here's the list of available ethtool commands from other drivers: |
| 1252 | * cmd->advertising = |
| 1253 | * cmd->speed = |
| 1254 | * cmd->duplex = |
| 1255 | * cmd->port = 0; |
| 1256 | * cmd->phy_address = |
| 1257 | * cmd->transceiver = 0; |
| 1258 | * cmd->autoneg = |
| 1259 | * cmd->maxtxpkt = 0; |
| 1260 | * cmd->maxrxpkt = 0; |
| 1261 | */ |
| 1262 | |
| 1263 | /* read current configuration */ |
| 1264 | cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; |
| 1265 | tanar = readl(dev->base + TANAR); |
| 1266 | tbicr = readl(dev->base + TBICR); |
| 1267 | |
| 1268 | if (dev->CFG_cache & CFG_TBI_EN) { |
| 1269 | /* we have an optical interface */ |
| 1270 | have_optical = 1; |
| 1271 | fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0; |
| 1272 | |
| 1273 | } else { |
| 1274 | /* We have copper */ |
| 1275 | fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0; |
| 1276 | } |
| 1277 | |
| 1278 | cmd->supported = SUPPORTED_Autoneg; |
| 1279 | |
| 1280 | /* we have optical interface */ |
| 1281 | if (dev->CFG_cache & CFG_TBI_EN) { |
| 1282 | cmd->supported |= SUPPORTED_1000baseT_Half | |
| 1283 | SUPPORTED_1000baseT_Full | |
| 1284 | SUPPORTED_FIBRE; |
| 1285 | cmd->port = PORT_FIBRE; |
| 1286 | } /* TODO: else copper related support */ |
| 1287 | |
| 1288 | cmd->duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF; |
| 1289 | switch (cfg / CFG_SPDSTS0 & 3) { |
| 1290 | case 2: |
| 1291 | cmd->speed = SPEED_1000; |
| 1292 | break; |
| 1293 | case 1: |
| 1294 | cmd->speed = SPEED_100; |
| 1295 | break; |
| 1296 | default: |
| 1297 | cmd->speed = SPEED_10; |
| 1298 | break; |
| 1299 | } |
| 1300 | cmd->autoneg = (tbicr & TBICR_MR_AN_ENABLE) ? 1: 0; |
| 1301 | return 0; |
| 1302 | } |
| 1303 | |
| 1304 | /* Let ethool change settings*/ |
| 1305 | static int ns83820_set_settings(struct net_device *ndev, |
| 1306 | struct ethtool_cmd *cmd) |
| 1307 | { |
| 1308 | struct ns83820 *dev = PRIV(ndev); |
| 1309 | u32 cfg, tanar; |
| 1310 | int have_optical = 0; |
| 1311 | int fullduplex = 0; |
| 1312 | |
| 1313 | /* read current configuration */ |
| 1314 | cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; |
| 1315 | tanar = readl(dev->base + TANAR); |
| 1316 | |
| 1317 | if (dev->CFG_cache & CFG_TBI_EN) { |
| 1318 | /* we have optical */ |
| 1319 | have_optical = 1; |
| 1320 | fullduplex = (tanar & TANAR_FULL_DUP); |
| 1321 | |
| 1322 | } else { |
| 1323 | /* we have copper */ |
| 1324 | fullduplex = cfg & CFG_DUPSTS; |
| 1325 | } |
| 1326 | |
| 1327 | spin_lock_irq(&dev->misc_lock); |
| 1328 | spin_lock(&dev->tx_lock); |
| 1329 | |
| 1330 | /* Set duplex */ |
| 1331 | if (cmd->duplex != fullduplex) { |
| 1332 | if (have_optical) { |
| 1333 | /*set full duplex*/ |
| 1334 | if (cmd->duplex == DUPLEX_FULL) { |
| 1335 | /* force full duplex */ |
| 1336 | writel(readl(dev->base + TXCFG) |
| 1337 | | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP, |
| 1338 | dev->base + TXCFG); |
| 1339 | writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, |
| 1340 | dev->base + RXCFG); |
| 1341 | /* Light up full duplex LED */ |
| 1342 | writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, |
| 1343 | dev->base + GPIOR); |
| 1344 | } else { |
| 1345 | /*TODO: set half duplex */ |
| 1346 | } |
| 1347 | |
| 1348 | } else { |
| 1349 | /*we have copper*/ |
| 1350 | /* TODO: Set duplex for copper cards */ |
| 1351 | } |
| 1352 | printk(KERN_INFO "%s: Duplex set via ethtool\n", |
| 1353 | ndev->name); |
| 1354 | } |
| 1355 | |
| 1356 | /* Set autonegotiation */ |
| 1357 | if (1) { |
| 1358 | if (cmd->autoneg == AUTONEG_ENABLE) { |
| 1359 | /* restart auto negotiation */ |
| 1360 | writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, |
| 1361 | dev->base + TBICR); |
| 1362 | writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); |
| 1363 | dev->linkstate = LINK_AUTONEGOTIATE; |
| 1364 | |
| 1365 | printk(KERN_INFO "%s: autoneg enabled via ethtool\n", |
| 1366 | ndev->name); |
| 1367 | } else { |
| 1368 | /* disable auto negotiation */ |
| 1369 | writel(0x00000000, dev->base + TBICR); |
| 1370 | } |
| 1371 | |
| 1372 | printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name, |
| 1373 | cmd->autoneg ? "ENABLED" : "DISABLED"); |
| 1374 | } |
| 1375 | |
| 1376 | phy_intr(ndev); |
| 1377 | spin_unlock(&dev->tx_lock); |
| 1378 | spin_unlock_irq(&dev->misc_lock); |
| 1379 | |
| 1380 | return 0; |
| 1381 | } |
| 1382 | /* end ethtool get/set support -df */ |
| 1383 | |
| 1384 | static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info) |
| 1385 | { |
| 1386 | struct ns83820 *dev = PRIV(ndev); |
| 1387 | strcpy(info->driver, "ns83820"); |
| 1388 | strcpy(info->version, VERSION); |
| 1389 | strcpy(info->bus_info, pci_name(dev->pci_dev)); |
| 1390 | } |
| 1391 | |
| 1392 | static u32 ns83820_get_link(struct net_device *ndev) |
| 1393 | { |
| 1394 | struct ns83820 *dev = PRIV(ndev); |
| 1395 | u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; |
| 1396 | return cfg & CFG_LNKSTS ? 1 : 0; |
| 1397 | } |
| 1398 | |
| 1399 | static const struct ethtool_ops ops = { |
| 1400 | .get_settings = ns83820_get_settings, |
| 1401 | .set_settings = ns83820_set_settings, |
| 1402 | .get_drvinfo = ns83820_get_drvinfo, |
| 1403 | .get_link = ns83820_get_link |
| 1404 | }; |
| 1405 | |
| 1406 | /* this function is called in irq context from the ISR */ |
| 1407 | static void ns83820_mib_isr(struct ns83820 *dev) |
| 1408 | { |
| 1409 | unsigned long flags; |
| 1410 | spin_lock_irqsave(&dev->misc_lock, flags); |
| 1411 | ns83820_update_stats(dev); |
| 1412 | spin_unlock_irqrestore(&dev->misc_lock, flags); |
| 1413 | } |
| 1414 | |
| 1415 | static void ns83820_do_isr(struct net_device *ndev, u32 isr); |
| 1416 | static irqreturn_t ns83820_irq(int foo, void *data) |
| 1417 | { |
| 1418 | struct net_device *ndev = data; |
| 1419 | struct ns83820 *dev = PRIV(ndev); |
| 1420 | u32 isr; |
| 1421 | dprintk("ns83820_irq(%p)\n", ndev); |
| 1422 | |
| 1423 | dev->ihr = 0; |
| 1424 | |
| 1425 | isr = readl(dev->base + ISR); |
| 1426 | dprintk("irq: %08x\n", isr); |
| 1427 | ns83820_do_isr(ndev, isr); |
| 1428 | return IRQ_HANDLED; |
| 1429 | } |
| 1430 | |
| 1431 | static void ns83820_do_isr(struct net_device *ndev, u32 isr) |
| 1432 | { |
| 1433 | struct ns83820 *dev = PRIV(ndev); |
| 1434 | unsigned long flags; |
| 1435 | |
| 1436 | #ifdef DEBUG |
| 1437 | if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC)) |
| 1438 | Dprintk("odd isr? 0x%08x\n", isr); |
| 1439 | #endif |
| 1440 | |
| 1441 | if (ISR_RXIDLE & isr) { |
| 1442 | dev->rx_info.idle = 1; |
| 1443 | Dprintk("oh dear, we are idle\n"); |
| 1444 | ns83820_rx_kick(ndev); |
| 1445 | } |
| 1446 | |
| 1447 | if ((ISR_RXDESC | ISR_RXOK) & isr) { |
| 1448 | prefetch(dev->rx_info.next_rx_desc); |
| 1449 | |
| 1450 | spin_lock_irqsave(&dev->misc_lock, flags); |
| 1451 | dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK); |
| 1452 | writel(dev->IMR_cache, dev->base + IMR); |
| 1453 | spin_unlock_irqrestore(&dev->misc_lock, flags); |
| 1454 | |
| 1455 | tasklet_schedule(&dev->rx_tasklet); |
| 1456 | //rx_irq(ndev); |
| 1457 | //writel(4, dev->base + IHR); |
| 1458 | } |
| 1459 | |
| 1460 | if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr) |
| 1461 | ns83820_rx_kick(ndev); |
| 1462 | |
| 1463 | if (unlikely(ISR_RXSOVR & isr)) { |
| 1464 | //printk("overrun: rxsovr\n"); |
| 1465 | dev->stats.rx_fifo_errors ++; |
| 1466 | } |
| 1467 | |
| 1468 | if (unlikely(ISR_RXORN & isr)) { |
| 1469 | //printk("overrun: rxorn\n"); |
| 1470 | dev->stats.rx_fifo_errors ++; |
| 1471 | } |
| 1472 | |
| 1473 | if ((ISR_RXRCMP & isr) && dev->rx_info.up) |
| 1474 | writel(CR_RXE, dev->base + CR); |
| 1475 | |
| 1476 | if (ISR_TXIDLE & isr) { |
| 1477 | u32 txdp; |
| 1478 | txdp = readl(dev->base + TXDP); |
| 1479 | dprintk("txdp: %08x\n", txdp); |
| 1480 | txdp -= dev->tx_phy_descs; |
| 1481 | dev->tx_idx = txdp / (DESC_SIZE * 4); |
| 1482 | if (dev->tx_idx >= NR_TX_DESC) { |
| 1483 | printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name); |
| 1484 | dev->tx_idx = 0; |
| 1485 | } |
| 1486 | /* The may have been a race between a pci originated read |
| 1487 | * and the descriptor update from the cpu. Just in case, |
| 1488 | * kick the transmitter if the hardware thinks it is on a |
| 1489 | * different descriptor than we are. |
| 1490 | */ |
| 1491 | if (dev->tx_idx != dev->tx_free_idx) |
| 1492 | kick_tx(dev); |
| 1493 | } |
| 1494 | |
| 1495 | /* Defer tx ring processing until more than a minimum amount of |
| 1496 | * work has accumulated |
| 1497 | */ |
| 1498 | if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) { |
| 1499 | spin_lock_irqsave(&dev->tx_lock, flags); |
| 1500 | do_tx_done(ndev); |
| 1501 | spin_unlock_irqrestore(&dev->tx_lock, flags); |
| 1502 | |
| 1503 | /* Disable TxOk if there are no outstanding tx packets. |
| 1504 | */ |
| 1505 | if ((dev->tx_done_idx == dev->tx_free_idx) && |
| 1506 | (dev->IMR_cache & ISR_TXOK)) { |
| 1507 | spin_lock_irqsave(&dev->misc_lock, flags); |
| 1508 | dev->IMR_cache &= ~ISR_TXOK; |
| 1509 | writel(dev->IMR_cache, dev->base + IMR); |
| 1510 | spin_unlock_irqrestore(&dev->misc_lock, flags); |
| 1511 | } |
| 1512 | } |
| 1513 | |
| 1514 | /* The TxIdle interrupt can come in before the transmit has |
| 1515 | * completed. Normally we reap packets off of the combination |
| 1516 | * of TxDesc and TxIdle and leave TxOk disabled (since it |
| 1517 | * occurs on every packet), but when no further irqs of this |
| 1518 | * nature are expected, we must enable TxOk. |
| 1519 | */ |
| 1520 | if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) { |
| 1521 | spin_lock_irqsave(&dev->misc_lock, flags); |
| 1522 | dev->IMR_cache |= ISR_TXOK; |
| 1523 | writel(dev->IMR_cache, dev->base + IMR); |
| 1524 | spin_unlock_irqrestore(&dev->misc_lock, flags); |
| 1525 | } |
| 1526 | |
| 1527 | /* MIB interrupt: one of the statistics counters is about to overflow */ |
| 1528 | if (unlikely(ISR_MIB & isr)) |
| 1529 | ns83820_mib_isr(dev); |
| 1530 | |
| 1531 | /* PHY: Link up/down/negotiation state change */ |
| 1532 | if (unlikely(ISR_PHY & isr)) |
| 1533 | phy_intr(ndev); |
| 1534 | |
| 1535 | #if 0 /* Still working on the interrupt mitigation strategy */ |
| 1536 | if (dev->ihr) |
| 1537 | writel(dev->ihr, dev->base + IHR); |
| 1538 | #endif |
| 1539 | } |
| 1540 | |
| 1541 | static void ns83820_do_reset(struct ns83820 *dev, u32 which) |
| 1542 | { |
| 1543 | Dprintk("resetting chip...\n"); |
| 1544 | writel(which, dev->base + CR); |
| 1545 | do { |
| 1546 | schedule(); |
| 1547 | } while (readl(dev->base + CR) & which); |
| 1548 | Dprintk("okay!\n"); |
| 1549 | } |
| 1550 | |
| 1551 | static int ns83820_stop(struct net_device *ndev) |
| 1552 | { |
| 1553 | struct ns83820 *dev = PRIV(ndev); |
| 1554 | |
| 1555 | /* FIXME: protect against interrupt handler? */ |
| 1556 | del_timer_sync(&dev->tx_watchdog); |
| 1557 | |
| 1558 | /* disable interrupts */ |
| 1559 | writel(0, dev->base + IMR); |
| 1560 | writel(0, dev->base + IER); |
| 1561 | readl(dev->base + IER); |
| 1562 | |
| 1563 | dev->rx_info.up = 0; |
| 1564 | synchronize_irq(dev->pci_dev->irq); |
| 1565 | |
| 1566 | ns83820_do_reset(dev, CR_RST); |
| 1567 | |
| 1568 | synchronize_irq(dev->pci_dev->irq); |
| 1569 | |
| 1570 | spin_lock_irq(&dev->misc_lock); |
| 1571 | dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK); |
| 1572 | spin_unlock_irq(&dev->misc_lock); |
| 1573 | |
| 1574 | ns83820_cleanup_rx(dev); |
| 1575 | ns83820_cleanup_tx(dev); |
| 1576 | |
| 1577 | return 0; |
| 1578 | } |
| 1579 | |
| 1580 | static void ns83820_tx_timeout(struct net_device *ndev) |
| 1581 | { |
| 1582 | struct ns83820 *dev = PRIV(ndev); |
| 1583 | u32 tx_done_idx; |
| 1584 | __le32 *desc; |
| 1585 | unsigned long flags; |
| 1586 | |
| 1587 | spin_lock_irqsave(&dev->tx_lock, flags); |
| 1588 | |
| 1589 | tx_done_idx = dev->tx_done_idx; |
| 1590 | desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); |
| 1591 | |
| 1592 | printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n", |
| 1593 | ndev->name, |
| 1594 | tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); |
| 1595 | |
| 1596 | #if defined(DEBUG) |
| 1597 | { |
| 1598 | u32 isr; |
| 1599 | isr = readl(dev->base + ISR); |
| 1600 | printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache); |
| 1601 | ns83820_do_isr(ndev, isr); |
| 1602 | } |
| 1603 | #endif |
| 1604 | |
| 1605 | do_tx_done(ndev); |
| 1606 | |
| 1607 | tx_done_idx = dev->tx_done_idx; |
| 1608 | desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); |
| 1609 | |
| 1610 | printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n", |
| 1611 | ndev->name, |
| 1612 | tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); |
| 1613 | |
| 1614 | spin_unlock_irqrestore(&dev->tx_lock, flags); |
| 1615 | } |
| 1616 | |
| 1617 | static void ns83820_tx_watch(unsigned long data) |
| 1618 | { |
| 1619 | struct net_device *ndev = (void *)data; |
| 1620 | struct ns83820 *dev = PRIV(ndev); |
| 1621 | |
| 1622 | #if defined(DEBUG) |
| 1623 | printk("ns83820_tx_watch: %u %u %d\n", |
| 1624 | dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs) |
| 1625 | ); |
| 1626 | #endif |
| 1627 | |
| 1628 | if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) && |
| 1629 | dev->tx_done_idx != dev->tx_free_idx) { |
| 1630 | printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n", |
| 1631 | ndev->name, |
| 1632 | dev->tx_done_idx, dev->tx_free_idx, |
| 1633 | atomic_read(&dev->nr_tx_skbs)); |
| 1634 | ns83820_tx_timeout(ndev); |
| 1635 | } |
| 1636 | |
| 1637 | mod_timer(&dev->tx_watchdog, jiffies + 2*HZ); |
| 1638 | } |
| 1639 | |
| 1640 | static int ns83820_open(struct net_device *ndev) |
| 1641 | { |
| 1642 | struct ns83820 *dev = PRIV(ndev); |
| 1643 | unsigned i; |
| 1644 | u32 desc; |
| 1645 | int ret; |
| 1646 | |
| 1647 | dprintk("ns83820_open\n"); |
| 1648 | |
| 1649 | writel(0, dev->base + PQCR); |
| 1650 | |
| 1651 | ret = ns83820_setup_rx(ndev); |
| 1652 | if (ret) |
| 1653 | goto failed; |
| 1654 | |
| 1655 | memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE); |
| 1656 | for (i=0; i<NR_TX_DESC; i++) { |
| 1657 | dev->tx_descs[(i * DESC_SIZE) + DESC_LINK] |
| 1658 | = cpu_to_le32( |
| 1659 | dev->tx_phy_descs |
| 1660 | + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4); |
| 1661 | } |
| 1662 | |
| 1663 | dev->tx_idx = 0; |
| 1664 | dev->tx_done_idx = 0; |
| 1665 | desc = dev->tx_phy_descs; |
| 1666 | writel(0, dev->base + TXDP_HI); |
| 1667 | writel(desc, dev->base + TXDP); |
| 1668 | |
| 1669 | init_timer(&dev->tx_watchdog); |
| 1670 | dev->tx_watchdog.data = (unsigned long)ndev; |
| 1671 | dev->tx_watchdog.function = ns83820_tx_watch; |
| 1672 | mod_timer(&dev->tx_watchdog, jiffies + 2*HZ); |
| 1673 | |
| 1674 | netif_start_queue(ndev); /* FIXME: wait for phy to come up */ |
| 1675 | |
| 1676 | return 0; |
| 1677 | |
| 1678 | failed: |
| 1679 | ns83820_stop(ndev); |
| 1680 | return ret; |
| 1681 | } |
| 1682 | |
| 1683 | static void ns83820_getmac(struct ns83820 *dev, u8 *mac) |
| 1684 | { |
| 1685 | unsigned i; |
| 1686 | for (i=0; i<3; i++) { |
| 1687 | u32 data; |
| 1688 | |
| 1689 | /* Read from the perfect match memory: this is loaded by |
| 1690 | * the chip from the EEPROM via the EELOAD self test. |
| 1691 | */ |
| 1692 | writel(i*2, dev->base + RFCR); |
| 1693 | data = readl(dev->base + RFDR); |
| 1694 | |
| 1695 | *mac++ = data; |
| 1696 | *mac++ = data >> 8; |
| 1697 | } |
| 1698 | } |
| 1699 | |
| 1700 | static int ns83820_change_mtu(struct net_device *ndev, int new_mtu) |
| 1701 | { |
| 1702 | if (new_mtu > RX_BUF_SIZE) |
| 1703 | return -EINVAL; |
| 1704 | ndev->mtu = new_mtu; |
| 1705 | return 0; |
| 1706 | } |
| 1707 | |
| 1708 | static void ns83820_set_multicast(struct net_device *ndev) |
| 1709 | { |
| 1710 | struct ns83820 *dev = PRIV(ndev); |
| 1711 | u8 __iomem *rfcr = dev->base + RFCR; |
| 1712 | u32 and_mask = 0xffffffff; |
| 1713 | u32 or_mask = 0; |
| 1714 | u32 val; |
| 1715 | |
| 1716 | if (ndev->flags & IFF_PROMISC) |
| 1717 | or_mask |= RFCR_AAU | RFCR_AAM; |
| 1718 | else |
| 1719 | and_mask &= ~(RFCR_AAU | RFCR_AAM); |
| 1720 | |
| 1721 | if (ndev->flags & IFF_ALLMULTI || ndev->mc_count) |
| 1722 | or_mask |= RFCR_AAM; |
| 1723 | else |
| 1724 | and_mask &= ~RFCR_AAM; |
| 1725 | |
| 1726 | spin_lock_irq(&dev->misc_lock); |
| 1727 | val = (readl(rfcr) & and_mask) | or_mask; |
| 1728 | /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */ |
| 1729 | writel(val & ~RFCR_RFEN, rfcr); |
| 1730 | writel(val, rfcr); |
| 1731 | spin_unlock_irq(&dev->misc_lock); |
| 1732 | } |
| 1733 | |
| 1734 | static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail) |
| 1735 | { |
| 1736 | struct ns83820 *dev = PRIV(ndev); |
| 1737 | int timed_out = 0; |
| 1738 | unsigned long start; |
| 1739 | u32 status; |
| 1740 | int loops = 0; |
| 1741 | |
| 1742 | dprintk("%s: start %s\n", ndev->name, name); |
| 1743 | |
| 1744 | start = jiffies; |
| 1745 | |
| 1746 | writel(enable, dev->base + PTSCR); |
| 1747 | for (;;) { |
| 1748 | loops++; |
| 1749 | status = readl(dev->base + PTSCR); |
| 1750 | if (!(status & enable)) |
| 1751 | break; |
| 1752 | if (status & done) |
| 1753 | break; |
| 1754 | if (status & fail) |
| 1755 | break; |
| 1756 | if (time_after_eq(jiffies, start + HZ)) { |
| 1757 | timed_out = 1; |
| 1758 | break; |
| 1759 | } |
| 1760 | schedule_timeout_uninterruptible(1); |
| 1761 | } |
| 1762 | |
| 1763 | if (status & fail) |
| 1764 | printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n", |
| 1765 | ndev->name, name, status, fail); |
| 1766 | else if (timed_out) |
| 1767 | printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n", |
| 1768 | ndev->name, name, status); |
| 1769 | |
| 1770 | dprintk("%s: done %s in %d loops\n", ndev->name, name, loops); |
| 1771 | } |
| 1772 | |
| 1773 | #ifdef PHY_CODE_IS_FINISHED |
| 1774 | static void ns83820_mii_write_bit(struct ns83820 *dev, int bit) |
| 1775 | { |
| 1776 | /* drive MDC low */ |
| 1777 | dev->MEAR_cache &= ~MEAR_MDC; |
| 1778 | writel(dev->MEAR_cache, dev->base + MEAR); |
| 1779 | readl(dev->base + MEAR); |
| 1780 | |
| 1781 | /* enable output, set bit */ |
| 1782 | dev->MEAR_cache |= MEAR_MDDIR; |
| 1783 | if (bit) |
| 1784 | dev->MEAR_cache |= MEAR_MDIO; |
| 1785 | else |
| 1786 | dev->MEAR_cache &= ~MEAR_MDIO; |
| 1787 | |
| 1788 | /* set the output bit */ |
| 1789 | writel(dev->MEAR_cache, dev->base + MEAR); |
| 1790 | readl(dev->base + MEAR); |
| 1791 | |
| 1792 | /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */ |
| 1793 | udelay(1); |
| 1794 | |
| 1795 | /* drive MDC high causing the data bit to be latched */ |
| 1796 | dev->MEAR_cache |= MEAR_MDC; |
| 1797 | writel(dev->MEAR_cache, dev->base + MEAR); |
| 1798 | readl(dev->base + MEAR); |
| 1799 | |
| 1800 | /* Wait again... */ |
| 1801 | udelay(1); |
| 1802 | } |
| 1803 | |
| 1804 | static int ns83820_mii_read_bit(struct ns83820 *dev) |
| 1805 | { |
| 1806 | int bit; |
| 1807 | |
| 1808 | /* drive MDC low, disable output */ |
| 1809 | dev->MEAR_cache &= ~MEAR_MDC; |
| 1810 | dev->MEAR_cache &= ~MEAR_MDDIR; |
| 1811 | writel(dev->MEAR_cache, dev->base + MEAR); |
| 1812 | readl(dev->base + MEAR); |
| 1813 | |
| 1814 | /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */ |
| 1815 | udelay(1); |
| 1816 | |
| 1817 | /* drive MDC high causing the data bit to be latched */ |
| 1818 | bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0; |
| 1819 | dev->MEAR_cache |= MEAR_MDC; |
| 1820 | writel(dev->MEAR_cache, dev->base + MEAR); |
| 1821 | |
| 1822 | /* Wait again... */ |
| 1823 | udelay(1); |
| 1824 | |
| 1825 | return bit; |
| 1826 | } |
| 1827 | |
| 1828 | static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg) |
| 1829 | { |
| 1830 | unsigned data = 0; |
| 1831 | int i; |
| 1832 | |
| 1833 | /* read some garbage so that we eventually sync up */ |
| 1834 | for (i=0; i<64; i++) |
| 1835 | ns83820_mii_read_bit(dev); |
| 1836 | |
| 1837 | ns83820_mii_write_bit(dev, 0); /* start */ |
| 1838 | ns83820_mii_write_bit(dev, 1); |
| 1839 | ns83820_mii_write_bit(dev, 1); /* opcode read */ |
| 1840 | ns83820_mii_write_bit(dev, 0); |
| 1841 | |
| 1842 | /* write out the phy address: 5 bits, msb first */ |
| 1843 | for (i=0; i<5; i++) |
| 1844 | ns83820_mii_write_bit(dev, phy & (0x10 >> i)); |
| 1845 | |
| 1846 | /* write out the register address, 5 bits, msb first */ |
| 1847 | for (i=0; i<5; i++) |
| 1848 | ns83820_mii_write_bit(dev, reg & (0x10 >> i)); |
| 1849 | |
| 1850 | ns83820_mii_read_bit(dev); /* turn around cycles */ |
| 1851 | ns83820_mii_read_bit(dev); |
| 1852 | |
| 1853 | /* read in the register data, 16 bits msb first */ |
| 1854 | for (i=0; i<16; i++) { |
| 1855 | data <<= 1; |
| 1856 | data |= ns83820_mii_read_bit(dev); |
| 1857 | } |
| 1858 | |
| 1859 | return data; |
| 1860 | } |
| 1861 | |
| 1862 | static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data) |
| 1863 | { |
| 1864 | int i; |
| 1865 | |
| 1866 | /* read some garbage so that we eventually sync up */ |
| 1867 | for (i=0; i<64; i++) |
| 1868 | ns83820_mii_read_bit(dev); |
| 1869 | |
| 1870 | ns83820_mii_write_bit(dev, 0); /* start */ |
| 1871 | ns83820_mii_write_bit(dev, 1); |
| 1872 | ns83820_mii_write_bit(dev, 0); /* opcode read */ |
| 1873 | ns83820_mii_write_bit(dev, 1); |
| 1874 | |
| 1875 | /* write out the phy address: 5 bits, msb first */ |
| 1876 | for (i=0; i<5; i++) |
| 1877 | ns83820_mii_write_bit(dev, phy & (0x10 >> i)); |
| 1878 | |
| 1879 | /* write out the register address, 5 bits, msb first */ |
| 1880 | for (i=0; i<5; i++) |
| 1881 | ns83820_mii_write_bit(dev, reg & (0x10 >> i)); |
| 1882 | |
| 1883 | ns83820_mii_read_bit(dev); /* turn around cycles */ |
| 1884 | ns83820_mii_read_bit(dev); |
| 1885 | |
| 1886 | /* read in the register data, 16 bits msb first */ |
| 1887 | for (i=0; i<16; i++) |
| 1888 | ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1); |
| 1889 | |
| 1890 | return data; |
| 1891 | } |
| 1892 | |
| 1893 | static void ns83820_probe_phy(struct net_device *ndev) |
| 1894 | { |
| 1895 | struct ns83820 *dev = PRIV(ndev); |
| 1896 | static int first; |
| 1897 | int i; |
| 1898 | #define MII_PHYIDR1 0x02 |
| 1899 | #define MII_PHYIDR2 0x03 |
| 1900 | |
| 1901 | #if 0 |
| 1902 | if (!first) { |
| 1903 | unsigned tmp; |
| 1904 | ns83820_mii_read_reg(dev, 1, 0x09); |
| 1905 | ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e); |
| 1906 | |
| 1907 | tmp = ns83820_mii_read_reg(dev, 1, 0x00); |
| 1908 | ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000); |
| 1909 | udelay(1300); |
| 1910 | ns83820_mii_read_reg(dev, 1, 0x09); |
| 1911 | } |
| 1912 | #endif |
| 1913 | first = 1; |
| 1914 | |
| 1915 | for (i=1; i<2; i++) { |
| 1916 | int j; |
| 1917 | unsigned a, b; |
| 1918 | a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1); |
| 1919 | b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2); |
| 1920 | |
| 1921 | //printk("%s: phy %d: 0x%04x 0x%04x\n", |
| 1922 | // ndev->name, i, a, b); |
| 1923 | |
| 1924 | for (j=0; j<0x16; j+=4) { |
| 1925 | dprintk("%s: [0x%02x] %04x %04x %04x %04x\n", |
| 1926 | ndev->name, j, |
| 1927 | ns83820_mii_read_reg(dev, i, 0 + j), |
| 1928 | ns83820_mii_read_reg(dev, i, 1 + j), |
| 1929 | ns83820_mii_read_reg(dev, i, 2 + j), |
| 1930 | ns83820_mii_read_reg(dev, i, 3 + j) |
| 1931 | ); |
| 1932 | } |
| 1933 | } |
| 1934 | { |
| 1935 | unsigned a, b; |
| 1936 | /* read firmware version: memory addr is 0x8402 and 0x8403 */ |
| 1937 | ns83820_mii_write_reg(dev, 1, 0x16, 0x000d); |
| 1938 | ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e); |
| 1939 | a = ns83820_mii_read_reg(dev, 1, 0x1d); |
| 1940 | |
| 1941 | ns83820_mii_write_reg(dev, 1, 0x16, 0x000d); |
| 1942 | ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e); |
| 1943 | b = ns83820_mii_read_reg(dev, 1, 0x1d); |
| 1944 | dprintk("version: 0x%04x 0x%04x\n", a, b); |
| 1945 | } |
| 1946 | } |
| 1947 | #endif |
| 1948 | |
| 1949 | static const struct net_device_ops netdev_ops = { |
| 1950 | .ndo_open = ns83820_open, |
| 1951 | .ndo_stop = ns83820_stop, |
| 1952 | .ndo_start_xmit = ns83820_hard_start_xmit, |
| 1953 | .ndo_get_stats = ns83820_get_stats, |
| 1954 | .ndo_change_mtu = ns83820_change_mtu, |
| 1955 | .ndo_set_multicast_list = ns83820_set_multicast, |
| 1956 | .ndo_validate_addr = eth_validate_addr, |
| 1957 | .ndo_set_mac_address = eth_mac_addr, |
| 1958 | .ndo_tx_timeout = ns83820_tx_timeout, |
| 1959 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 1960 | .ndo_vlan_rx_register = ns83820_vlan_rx_register, |
| 1961 | #endif |
| 1962 | }; |
| 1963 | |
| 1964 | static int __devinit ns83820_init_one(struct pci_dev *pci_dev, |
| 1965 | const struct pci_device_id *id) |
| 1966 | { |
| 1967 | struct net_device *ndev; |
| 1968 | struct ns83820 *dev; |
| 1969 | long addr; |
| 1970 | int err; |
| 1971 | int using_dac = 0; |
| 1972 | |
| 1973 | /* See if we can set the dma mask early on; failure is fatal. */ |
| 1974 | if (sizeof(dma_addr_t) == 8 && |
| 1975 | !pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) { |
| 1976 | using_dac = 1; |
| 1977 | } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) { |
| 1978 | using_dac = 0; |
| 1979 | } else { |
| 1980 | dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n"); |
| 1981 | return -ENODEV; |
| 1982 | } |
| 1983 | |
| 1984 | ndev = alloc_etherdev(sizeof(struct ns83820)); |
| 1985 | dev = PRIV(ndev); |
| 1986 | |
| 1987 | err = -ENOMEM; |
| 1988 | if (!dev) |
| 1989 | goto out; |
| 1990 | |
| 1991 | dev->ndev = ndev; |
| 1992 | |
| 1993 | spin_lock_init(&dev->rx_info.lock); |
| 1994 | spin_lock_init(&dev->tx_lock); |
| 1995 | spin_lock_init(&dev->misc_lock); |
| 1996 | dev->pci_dev = pci_dev; |
| 1997 | |
| 1998 | SET_NETDEV_DEV(ndev, &pci_dev->dev); |
| 1999 | |
| 2000 | INIT_WORK(&dev->tq_refill, queue_refill); |
| 2001 | tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev); |
| 2002 | |
| 2003 | err = pci_enable_device(pci_dev); |
| 2004 | if (err) { |
| 2005 | dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err); |
| 2006 | goto out_free; |
| 2007 | } |
| 2008 | |
| 2009 | pci_set_master(pci_dev); |
| 2010 | addr = pci_resource_start(pci_dev, 1); |
| 2011 | dev->base = ioremap_nocache(addr, PAGE_SIZE); |
| 2012 | dev->tx_descs = pci_alloc_consistent(pci_dev, |
| 2013 | 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs); |
| 2014 | dev->rx_info.descs = pci_alloc_consistent(pci_dev, |
| 2015 | 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs); |
| 2016 | err = -ENOMEM; |
| 2017 | if (!dev->base || !dev->tx_descs || !dev->rx_info.descs) |
| 2018 | goto out_disable; |
| 2019 | |
| 2020 | dprintk("%p: %08lx %p: %08lx\n", |
| 2021 | dev->tx_descs, (long)dev->tx_phy_descs, |
| 2022 | dev->rx_info.descs, (long)dev->rx_info.phy_descs); |
| 2023 | |
| 2024 | /* disable interrupts */ |
| 2025 | writel(0, dev->base + IMR); |
| 2026 | writel(0, dev->base + IER); |
| 2027 | readl(dev->base + IER); |
| 2028 | |
| 2029 | dev->IMR_cache = 0; |
| 2030 | |
| 2031 | err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED, |
| 2032 | DRV_NAME, ndev); |
| 2033 | if (err) { |
| 2034 | dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n", |
| 2035 | pci_dev->irq, err); |
| 2036 | goto out_disable; |
| 2037 | } |
| 2038 | |
| 2039 | /* |
| 2040 | * FIXME: we are holding rtnl_lock() over obscenely long area only |
| 2041 | * because some of the setup code uses dev->name. It's Wrong(tm) - |
| 2042 | * we should be using driver-specific names for all that stuff. |
| 2043 | * For now that will do, but we really need to come back and kill |
| 2044 | * most of the dev_alloc_name() users later. |
| 2045 | */ |
| 2046 | rtnl_lock(); |
| 2047 | err = dev_alloc_name(ndev, ndev->name); |
| 2048 | if (err < 0) { |
| 2049 | dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err); |
| 2050 | goto out_free_irq; |
| 2051 | } |
| 2052 | |
| 2053 | printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n", |
| 2054 | ndev->name, le32_to_cpu(readl(dev->base + 0x22c)), |
| 2055 | pci_dev->subsystem_vendor, pci_dev->subsystem_device); |
| 2056 | |
| 2057 | ndev->netdev_ops = &netdev_ops; |
| 2058 | SET_ETHTOOL_OPS(ndev, &ops); |
| 2059 | ndev->watchdog_timeo = 5 * HZ; |
| 2060 | pci_set_drvdata(pci_dev, ndev); |
| 2061 | |
| 2062 | ns83820_do_reset(dev, CR_RST); |
| 2063 | |
| 2064 | /* Must reset the ram bist before running it */ |
| 2065 | writel(PTSCR_RBIST_RST, dev->base + PTSCR); |
| 2066 | ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN, |
| 2067 | PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL); |
| 2068 | ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0, |
| 2069 | PTSCR_EEBIST_FAIL); |
| 2070 | ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0); |
| 2071 | |
| 2072 | /* I love config registers */ |
| 2073 | dev->CFG_cache = readl(dev->base + CFG); |
| 2074 | |
| 2075 | if ((dev->CFG_cache & CFG_PCI64_DET)) { |
| 2076 | printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n", |
| 2077 | ndev->name); |
| 2078 | /*dev->CFG_cache |= CFG_DATA64_EN;*/ |
| 2079 | if (!(dev->CFG_cache & CFG_DATA64_EN)) |
| 2080 | printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n", |
| 2081 | ndev->name); |
| 2082 | } else |
| 2083 | dev->CFG_cache &= ~(CFG_DATA64_EN); |
| 2084 | |
| 2085 | dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS | |
| 2086 | CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 | |
| 2087 | CFG_M64ADDR); |
| 2088 | dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS | |
| 2089 | CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL; |
| 2090 | dev->CFG_cache |= CFG_REQALG; |
| 2091 | dev->CFG_cache |= CFG_POW; |
| 2092 | dev->CFG_cache |= CFG_TMRTEST; |
| 2093 | |
| 2094 | /* When compiled with 64 bit addressing, we must always enable |
| 2095 | * the 64 bit descriptor format. |
| 2096 | */ |
| 2097 | if (sizeof(dma_addr_t) == 8) |
| 2098 | dev->CFG_cache |= CFG_M64ADDR; |
| 2099 | if (using_dac) |
| 2100 | dev->CFG_cache |= CFG_T64ADDR; |
| 2101 | |
| 2102 | /* Big endian mode does not seem to do what the docs suggest */ |
| 2103 | dev->CFG_cache &= ~CFG_BEM; |
| 2104 | |
| 2105 | /* setup optical transceiver if we have one */ |
| 2106 | if (dev->CFG_cache & CFG_TBI_EN) { |
| 2107 | printk(KERN_INFO "%s: enabling optical transceiver\n", |
| 2108 | ndev->name); |
| 2109 | writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR); |
| 2110 | |
| 2111 | /* setup auto negotiation feature advertisement */ |
| 2112 | writel(readl(dev->base + TANAR) |
| 2113 | | TANAR_HALF_DUP | TANAR_FULL_DUP, |
| 2114 | dev->base + TANAR); |
| 2115 | |
| 2116 | /* start auto negotiation */ |
| 2117 | writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, |
| 2118 | dev->base + TBICR); |
| 2119 | writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); |
| 2120 | dev->linkstate = LINK_AUTONEGOTIATE; |
| 2121 | |
| 2122 | dev->CFG_cache |= CFG_MODE_1000; |
| 2123 | } |
| 2124 | |
| 2125 | writel(dev->CFG_cache, dev->base + CFG); |
| 2126 | dprintk("CFG: %08x\n", dev->CFG_cache); |
| 2127 | |
| 2128 | if (reset_phy) { |
| 2129 | printk(KERN_INFO "%s: resetting phy\n", ndev->name); |
| 2130 | writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG); |
| 2131 | msleep(10); |
| 2132 | writel(dev->CFG_cache, dev->base + CFG); |
| 2133 | } |
| 2134 | |
| 2135 | #if 0 /* Huh? This sets the PCI latency register. Should be done via |
| 2136 | * the PCI layer. FIXME. |
| 2137 | */ |
| 2138 | if (readl(dev->base + SRR)) |
| 2139 | writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c); |
| 2140 | #endif |
| 2141 | |
| 2142 | /* Note! The DMA burst size interacts with packet |
| 2143 | * transmission, such that the largest packet that |
| 2144 | * can be transmitted is 8192 - FLTH - burst size. |
| 2145 | * If only the transmit fifo was larger... |
| 2146 | */ |
| 2147 | /* Ramit : 1024 DMA is not a good idea, it ends up banging |
| 2148 | * some DELL and COMPAQ SMP systems */ |
| 2149 | writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512 |
| 2150 | | ((1600 / 32) * 0x100), |
| 2151 | dev->base + TXCFG); |
| 2152 | |
| 2153 | /* Flush the interrupt holdoff timer */ |
| 2154 | writel(0x000, dev->base + IHR); |
| 2155 | writel(0x100, dev->base + IHR); |
| 2156 | writel(0x000, dev->base + IHR); |
| 2157 | |
| 2158 | /* Set Rx to full duplex, don't accept runt, errored, long or length |
| 2159 | * range errored packets. Use 512 byte DMA. |
| 2160 | */ |
| 2161 | /* Ramit : 1024 DMA is not a good idea, it ends up banging |
| 2162 | * some DELL and COMPAQ SMP systems |
| 2163 | * Turn on ALP, only we are accpeting Jumbo Packets */ |
| 2164 | writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD |
| 2165 | | RXCFG_STRIPCRC |
| 2166 | //| RXCFG_ALP |
| 2167 | | (RXCFG_MXDMA512) | 0, dev->base + RXCFG); |
| 2168 | |
| 2169 | /* Disable priority queueing */ |
| 2170 | writel(0, dev->base + PQCR); |
| 2171 | |
| 2172 | /* Enable IP checksum validation and detetion of VLAN headers. |
| 2173 | * Note: do not set the reject options as at least the 0x102 |
| 2174 | * revision of the chip does not properly accept IP fragments |
| 2175 | * at least for UDP. |
| 2176 | */ |
| 2177 | /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since |
| 2178 | * the MAC it calculates the packetsize AFTER stripping the VLAN |
| 2179 | * header, and if a VLAN Tagged packet of 64 bytes is received (like |
| 2180 | * a ping with a VLAN header) then the card, strips the 4 byte VLAN |
| 2181 | * tag and then checks the packet size, so if RXCFG_ARP is not enabled, |
| 2182 | * it discrards it!. These guys...... |
| 2183 | * also turn on tag stripping if hardware acceleration is enabled |
| 2184 | */ |
| 2185 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 2186 | #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN) |
| 2187 | #else |
| 2188 | #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN) |
| 2189 | #endif |
| 2190 | writel(VRCR_INIT_VALUE, dev->base + VRCR); |
| 2191 | |
| 2192 | /* Enable per-packet TCP/UDP/IP checksumming |
| 2193 | * and per packet vlan tag insertion if |
| 2194 | * vlan hardware acceleration is enabled |
| 2195 | */ |
| 2196 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 2197 | #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI) |
| 2198 | #else |
| 2199 | #define VTCR_INIT_VALUE VTCR_PPCHK |
| 2200 | #endif |
| 2201 | writel(VTCR_INIT_VALUE, dev->base + VTCR); |
| 2202 | |
| 2203 | /* Ramit : Enable async and sync pause frames */ |
| 2204 | /* writel(0, dev->base + PCR); */ |
| 2205 | writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K | |
| 2206 | PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT), |
| 2207 | dev->base + PCR); |
| 2208 | |
| 2209 | /* Disable Wake On Lan */ |
| 2210 | writel(0, dev->base + WCSR); |
| 2211 | |
| 2212 | ns83820_getmac(dev, ndev->dev_addr); |
| 2213 | |
| 2214 | /* Yes, we support dumb IP checksum on transmit */ |
| 2215 | ndev->features |= NETIF_F_SG; |
| 2216 | ndev->features |= NETIF_F_IP_CSUM; |
| 2217 | |
| 2218 | #ifdef NS83820_VLAN_ACCEL_SUPPORT |
| 2219 | /* We also support hardware vlan acceleration */ |
| 2220 | ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
| 2221 | #endif |
| 2222 | |
| 2223 | if (using_dac) { |
| 2224 | printk(KERN_INFO "%s: using 64 bit addressing.\n", |
| 2225 | ndev->name); |
| 2226 | ndev->features |= NETIF_F_HIGHDMA; |
| 2227 | } |
| 2228 | |
| 2229 | printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n", |
| 2230 | ndev->name, |
| 2231 | (unsigned)readl(dev->base + SRR) >> 8, |
| 2232 | (unsigned)readl(dev->base + SRR) & 0xff, |
| 2233 | ndev->dev_addr, addr, pci_dev->irq, |
| 2234 | (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg" |
| 2235 | ); |
| 2236 | |
| 2237 | #ifdef PHY_CODE_IS_FINISHED |
| 2238 | ns83820_probe_phy(ndev); |
| 2239 | #endif |
| 2240 | |
| 2241 | err = register_netdevice(ndev); |
| 2242 | if (err) { |
| 2243 | printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err); |
| 2244 | goto out_cleanup; |
| 2245 | } |
| 2246 | rtnl_unlock(); |
| 2247 | |
| 2248 | return 0; |
| 2249 | |
| 2250 | out_cleanup: |
| 2251 | writel(0, dev->base + IMR); /* paranoia */ |
| 2252 | writel(0, dev->base + IER); |
| 2253 | readl(dev->base + IER); |
| 2254 | out_free_irq: |
| 2255 | rtnl_unlock(); |
| 2256 | free_irq(pci_dev->irq, ndev); |
| 2257 | out_disable: |
| 2258 | if (dev->base) |
| 2259 | iounmap(dev->base); |
| 2260 | pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs); |
| 2261 | pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs); |
| 2262 | pci_disable_device(pci_dev); |
| 2263 | out_free: |
| 2264 | free_netdev(ndev); |
| 2265 | pci_set_drvdata(pci_dev, NULL); |
| 2266 | out: |
| 2267 | return err; |
| 2268 | } |
| 2269 | |
| 2270 | static void __devexit ns83820_remove_one(struct pci_dev *pci_dev) |
| 2271 | { |
| 2272 | struct net_device *ndev = pci_get_drvdata(pci_dev); |
| 2273 | struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */ |
| 2274 | |
| 2275 | if (!ndev) /* paranoia */ |
| 2276 | return; |
| 2277 | |
| 2278 | writel(0, dev->base + IMR); /* paranoia */ |
| 2279 | writel(0, dev->base + IER); |
| 2280 | readl(dev->base + IER); |
| 2281 | |
| 2282 | unregister_netdev(ndev); |
| 2283 | free_irq(dev->pci_dev->irq, ndev); |
| 2284 | iounmap(dev->base); |
| 2285 | pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC, |
| 2286 | dev->tx_descs, dev->tx_phy_descs); |
| 2287 | pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC, |
| 2288 | dev->rx_info.descs, dev->rx_info.phy_descs); |
| 2289 | pci_disable_device(dev->pci_dev); |
| 2290 | free_netdev(ndev); |
| 2291 | pci_set_drvdata(pci_dev, NULL); |
| 2292 | } |
| 2293 | |
| 2294 | static struct pci_device_id ns83820_pci_tbl[] = { |
| 2295 | { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, }, |
| 2296 | { 0, }, |
| 2297 | }; |
| 2298 | |
| 2299 | static struct pci_driver driver = { |
| 2300 | .name = "ns83820", |
| 2301 | .id_table = ns83820_pci_tbl, |
| 2302 | .probe = ns83820_init_one, |
| 2303 | .remove = __devexit_p(ns83820_remove_one), |
| 2304 | #if 0 /* FIXME: implement */ |
| 2305 | .suspend = , |
| 2306 | .resume = , |
| 2307 | #endif |
| 2308 | }; |
| 2309 | |
| 2310 | |
| 2311 | static int __init ns83820_init(void) |
| 2312 | { |
| 2313 | printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n"); |
| 2314 | return pci_register_driver(&driver); |
| 2315 | } |
| 2316 | |
| 2317 | static void __exit ns83820_exit(void) |
| 2318 | { |
| 2319 | pci_unregister_driver(&driver); |
| 2320 | } |
| 2321 | |
| 2322 | MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>"); |
| 2323 | MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver"); |
| 2324 | MODULE_LICENSE("GPL"); |
| 2325 | |
| 2326 | MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl); |
| 2327 | |
| 2328 | module_param(lnksts, int, 0); |
| 2329 | MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit"); |
| 2330 | |
| 2331 | module_param(ihr, int, 0); |
| 2332 | MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)"); |
| 2333 | |
| 2334 | module_param(reset_phy, int, 0); |
| 2335 | MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup"); |
| 2336 | |
| 2337 | module_init(ns83820_init); |
| 2338 | module_exit(ns83820_exit); |