| 1 | /* niu.h: Definitions for Neptune ethernet driver. |
| 2 | * |
| 3 | * Copyright (C) 2007 David S. Miller (davem@davemloft.net) |
| 4 | */ |
| 5 | |
| 6 | #ifndef _NIU_H |
| 7 | #define _NIU_H |
| 8 | |
| 9 | #define PIO 0x000000UL |
| 10 | #define FZC_PIO 0x080000UL |
| 11 | #define FZC_MAC 0x180000UL |
| 12 | #define FZC_IPP 0x280000UL |
| 13 | #define FFLP 0x300000UL |
| 14 | #define FZC_FFLP 0x380000UL |
| 15 | #define PIO_VADDR 0x400000UL |
| 16 | #define ZCP 0x500000UL |
| 17 | #define FZC_ZCP 0x580000UL |
| 18 | #define DMC 0x600000UL |
| 19 | #define FZC_DMC 0x680000UL |
| 20 | #define TXC 0x700000UL |
| 21 | #define FZC_TXC 0x780000UL |
| 22 | #define PIO_LDSV 0x800000UL |
| 23 | #define PIO_PIO_LDGIM 0x900000UL |
| 24 | #define PIO_IMASK0 0xa00000UL |
| 25 | #define PIO_IMASK1 0xb00000UL |
| 26 | #define FZC_PROM 0xc80000UL |
| 27 | #define FZC_PIM 0xd80000UL |
| 28 | |
| 29 | #define LDSV0(LDG) (PIO_LDSV + 0x00000UL + (LDG) * 0x2000UL) |
| 30 | #define LDSV1(LDG) (PIO_LDSV + 0x00008UL + (LDG) * 0x2000UL) |
| 31 | #define LDSV2(LDG) (PIO_LDSV + 0x00010UL + (LDG) * 0x2000UL) |
| 32 | |
| 33 | #define LDG_IMGMT(LDG) (PIO_LDSV + 0x00018UL + (LDG) * 0x2000UL) |
| 34 | #define LDG_IMGMT_ARM 0x0000000080000000ULL |
| 35 | #define LDG_IMGMT_TIMER 0x000000000000003fULL |
| 36 | |
| 37 | #define LD_IM0(IDX) (PIO_IMASK0 + 0x00000UL + (IDX) * 0x2000UL) |
| 38 | #define LD_IM0_MASK 0x0000000000000003ULL |
| 39 | |
| 40 | #define LD_IM1(IDX) (PIO_IMASK1 + 0x00000UL + (IDX) * 0x2000UL) |
| 41 | #define LD_IM1_MASK 0x0000000000000003ULL |
| 42 | |
| 43 | #define LDG_TIMER_RES (FZC_PIO + 0x00008UL) |
| 44 | #define LDG_TIMER_RES_VAL 0x00000000000fffffULL |
| 45 | |
| 46 | #define DIRTY_TID_CTL (FZC_PIO + 0x00010UL) |
| 47 | #define DIRTY_TID_CTL_NPTHRED 0x00000000003f0000ULL |
| 48 | #define DIRTY_TID_CTL_RDTHRED 0x00000000000003f0ULL |
| 49 | #define DIRTY_TID_CTL_DTIDCLR 0x0000000000000002ULL |
| 50 | #define DIRTY_TID_CTL_DTIDENAB 0x0000000000000001ULL |
| 51 | |
| 52 | #define DIRTY_TID_STAT (FZC_PIO + 0x00018UL) |
| 53 | #define DIRTY_TID_STAT_NPWSTAT 0x0000000000003f00ULL |
| 54 | #define DIRTY_TID_STAT_RDSTAT 0x000000000000003fULL |
| 55 | |
| 56 | #define RST_CTL (FZC_PIO + 0x00038UL) |
| 57 | #define RST_CTL_MAC_RST3 0x0000000000400000ULL |
| 58 | #define RST_CTL_MAC_RST2 0x0000000000200000ULL |
| 59 | #define RST_CTL_MAC_RST1 0x0000000000100000ULL |
| 60 | #define RST_CTL_MAC_RST0 0x0000000000080000ULL |
| 61 | #define RST_CTL_ACK_TO_EN 0x0000000000000800ULL |
| 62 | #define RST_CTL_ACK_TO_VAL 0x00000000000007feULL |
| 63 | |
| 64 | #define SMX_CFIG_DAT (FZC_PIO + 0x00040UL) |
| 65 | #define SMX_CFIG_DAT_RAS_DET 0x0000000080000000ULL |
| 66 | #define SMX_CFIG_DAT_RAS_INJ 0x0000000040000000ULL |
| 67 | #define SMX_CFIG_DAT_XACT_TO 0x000000000fffffffULL |
| 68 | |
| 69 | #define SMX_INT_STAT (FZC_PIO + 0x00048UL) |
| 70 | #define SMX_INT_STAT_STAT 0x00000000ffffffffULL |
| 71 | |
| 72 | #define SMX_CTL (FZC_PIO + 0x00050UL) |
| 73 | #define SMX_CTL_CTL 0x00000000ffffffffULL |
| 74 | |
| 75 | #define SMX_DBG_VEC (FZC_PIO + 0x00058UL) |
| 76 | #define SMX_DBG_VEC_VEC 0x00000000ffffffffULL |
| 77 | |
| 78 | #define PIO_DBG_SEL (FZC_PIO + 0x00060UL) |
| 79 | #define PIO_DBG_SEL_SEL 0x000000000000003fULL |
| 80 | |
| 81 | #define PIO_TRAIN_VEC (FZC_PIO + 0x00068UL) |
| 82 | #define PIO_TRAIN_VEC_VEC 0x00000000ffffffffULL |
| 83 | |
| 84 | #define PIO_ARB_CTL (FZC_PIO + 0x00070UL) |
| 85 | #define PIO_ARB_CTL_CTL 0x00000000ffffffffULL |
| 86 | |
| 87 | #define PIO_ARB_DBG_VEC (FZC_PIO + 0x00078UL) |
| 88 | #define PIO_ARB_DBG_VEC_VEC 0x00000000ffffffffULL |
| 89 | |
| 90 | #define SYS_ERR_MASK (FZC_PIO + 0x00090UL) |
| 91 | #define SYS_ERR_MASK_META2 0x0000000000000400ULL |
| 92 | #define SYS_ERR_MASK_META1 0x0000000000000200ULL |
| 93 | #define SYS_ERR_MASK_PEU 0x0000000000000100ULL |
| 94 | #define SYS_ERR_MASK_TXC 0x0000000000000080ULL |
| 95 | #define SYS_ERR_MASK_RDMC 0x0000000000000040ULL |
| 96 | #define SYS_ERR_MASK_TDMC 0x0000000000000020ULL |
| 97 | #define SYS_ERR_MASK_ZCP 0x0000000000000010ULL |
| 98 | #define SYS_ERR_MASK_FFLP 0x0000000000000008ULL |
| 99 | #define SYS_ERR_MASK_IPP 0x0000000000000004ULL |
| 100 | #define SYS_ERR_MASK_MAC 0x0000000000000002ULL |
| 101 | #define SYS_ERR_MASK_SMX 0x0000000000000001ULL |
| 102 | |
| 103 | #define SYS_ERR_STAT (FZC_PIO + 0x00098UL) |
| 104 | #define SYS_ERR_STAT_META2 0x0000000000000400ULL |
| 105 | #define SYS_ERR_STAT_META1 0x0000000000000200ULL |
| 106 | #define SYS_ERR_STAT_PEU 0x0000000000000100ULL |
| 107 | #define SYS_ERR_STAT_TXC 0x0000000000000080ULL |
| 108 | #define SYS_ERR_STAT_RDMC 0x0000000000000040ULL |
| 109 | #define SYS_ERR_STAT_TDMC 0x0000000000000020ULL |
| 110 | #define SYS_ERR_STAT_ZCP 0x0000000000000010ULL |
| 111 | #define SYS_ERR_STAT_FFLP 0x0000000000000008ULL |
| 112 | #define SYS_ERR_STAT_IPP 0x0000000000000004ULL |
| 113 | #define SYS_ERR_STAT_MAC 0x0000000000000002ULL |
| 114 | #define SYS_ERR_STAT_SMX 0x0000000000000001ULL |
| 115 | |
| 116 | #define SID(LDG) (FZC_PIO + 0x10200UL + (LDG) * 8UL) |
| 117 | #define SID_FUNC 0x0000000000000060ULL |
| 118 | #define SID_FUNC_SHIFT 5 |
| 119 | #define SID_VECTOR 0x000000000000001fULL |
| 120 | #define SID_VECTOR_SHIFT 0 |
| 121 | |
| 122 | #define LDG_NUM(LDN) (FZC_PIO + 0x20000UL + (LDN) * 8UL) |
| 123 | |
| 124 | #define XMAC_PORT0_OFF (FZC_MAC + 0x000000) |
| 125 | #define XMAC_PORT1_OFF (FZC_MAC + 0x006000) |
| 126 | #define BMAC_PORT2_OFF (FZC_MAC + 0x00c000) |
| 127 | #define BMAC_PORT3_OFF (FZC_MAC + 0x010000) |
| 128 | |
| 129 | /* XMAC registers, offset from np->mac_regs */ |
| 130 | |
| 131 | #define XTXMAC_SW_RST 0x00000UL |
| 132 | #define XTXMAC_SW_RST_REG_RS 0x0000000000000002ULL |
| 133 | #define XTXMAC_SW_RST_SOFT_RST 0x0000000000000001ULL |
| 134 | |
| 135 | #define XRXMAC_SW_RST 0x00008UL |
| 136 | #define XRXMAC_SW_RST_REG_RS 0x0000000000000002ULL |
| 137 | #define XRXMAC_SW_RST_SOFT_RST 0x0000000000000001ULL |
| 138 | |
| 139 | #define XTXMAC_STATUS 0x00020UL |
| 140 | #define XTXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000800ULL |
| 141 | #define XTXMAC_STATUS_BYTE_CNT_EXP 0x0000000000000400ULL |
| 142 | #define XTXMAC_STATUS_TXFIFO_XFR_ERR 0x0000000000000010ULL |
| 143 | #define XTXMAC_STATUS_TXMAC_OFLOW 0x0000000000000008ULL |
| 144 | #define XTXMAC_STATUS_MAX_PSIZE_ERR 0x0000000000000004ULL |
| 145 | #define XTXMAC_STATUS_TXMAC_UFLOW 0x0000000000000002ULL |
| 146 | #define XTXMAC_STATUS_FRAME_XMITED 0x0000000000000001ULL |
| 147 | |
| 148 | #define XRXMAC_STATUS 0x00028UL |
| 149 | #define XRXMAC_STATUS_RXHIST7_CNT_EXP 0x0000000000100000ULL |
| 150 | #define XRXMAC_STATUS_LCL_FLT_STATUS 0x0000000000080000ULL |
| 151 | #define XRXMAC_STATUS_RFLT_DET 0x0000000000040000ULL |
| 152 | #define XRXMAC_STATUS_LFLT_CNT_EXP 0x0000000000020000ULL |
| 153 | #define XRXMAC_STATUS_PHY_MDINT 0x0000000000010000ULL |
| 154 | #define XRXMAC_STATUS_ALIGNERR_CNT_EXP 0x0000000000010000ULL |
| 155 | #define XRXMAC_STATUS_RXFRAG_CNT_EXP 0x0000000000008000ULL |
| 156 | #define XRXMAC_STATUS_RXMULTF_CNT_EXP 0x0000000000004000ULL |
| 157 | #define XRXMAC_STATUS_RXBCAST_CNT_EXP 0x0000000000002000ULL |
| 158 | #define XRXMAC_STATUS_RXHIST6_CNT_EXP 0x0000000000001000ULL |
| 159 | #define XRXMAC_STATUS_RXHIST5_CNT_EXP 0x0000000000000800ULL |
| 160 | #define XRXMAC_STATUS_RXHIST4_CNT_EXP 0x0000000000000400ULL |
| 161 | #define XRXMAC_STATUS_RXHIST3_CNT_EXP 0x0000000000000200ULL |
| 162 | #define XRXMAC_STATUS_RXHIST2_CNT_EXP 0x0000000000000100ULL |
| 163 | #define XRXMAC_STATUS_RXHIST1_CNT_EXP 0x0000000000000080ULL |
| 164 | #define XRXMAC_STATUS_RXOCTET_CNT_EXP 0x0000000000000040ULL |
| 165 | #define XRXMAC_STATUS_CVIOLERR_CNT_EXP 0x0000000000000020ULL |
| 166 | #define XRXMAC_STATUS_LENERR_CNT_EXP 0x0000000000000010ULL |
| 167 | #define XRXMAC_STATUS_CRCERR_CNT_EXP 0x0000000000000008ULL |
| 168 | #define XRXMAC_STATUS_RXUFLOW 0x0000000000000004ULL |
| 169 | #define XRXMAC_STATUS_RXOFLOW 0x0000000000000002ULL |
| 170 | #define XRXMAC_STATUS_FRAME_RCVD 0x0000000000000001ULL |
| 171 | |
| 172 | #define XMAC_FC_STAT 0x00030UL |
| 173 | #define XMAC_FC_STAT_RX_RCV_PAUSE_TIME 0x00000000ffff0000ULL |
| 174 | #define XMAC_FC_STAT_TX_MAC_NPAUSE 0x0000000000000004ULL |
| 175 | #define XMAC_FC_STAT_TX_MAC_PAUSE 0x0000000000000002ULL |
| 176 | #define XMAC_FC_STAT_RX_MAC_RPAUSE 0x0000000000000001ULL |
| 177 | |
| 178 | #define XTXMAC_STAT_MSK 0x00040UL |
| 179 | #define XTXMAC_STAT_MSK_FRAME_CNT_EXP 0x0000000000000800ULL |
| 180 | #define XTXMAC_STAT_MSK_BYTE_CNT_EXP 0x0000000000000400ULL |
| 181 | #define XTXMAC_STAT_MSK_TXFIFO_XFR_ERR 0x0000000000000010ULL |
| 182 | #define XTXMAC_STAT_MSK_TXMAC_OFLOW 0x0000000000000008ULL |
| 183 | #define XTXMAC_STAT_MSK_MAX_PSIZE_ERR 0x0000000000000004ULL |
| 184 | #define XTXMAC_STAT_MSK_TXMAC_UFLOW 0x0000000000000002ULL |
| 185 | #define XTXMAC_STAT_MSK_FRAME_XMITED 0x0000000000000001ULL |
| 186 | |
| 187 | #define XRXMAC_STAT_MSK 0x00048UL |
| 188 | #define XRXMAC_STAT_MSK_LCL_FLT_STAT_MSK 0x0000000000080000ULL |
| 189 | #define XRXMAC_STAT_MSK_RFLT_DET 0x0000000000040000ULL |
| 190 | #define XRXMAC_STAT_MSK_LFLT_CNT_EXP 0x0000000000020000ULL |
| 191 | #define XRXMAC_STAT_MSK_PHY_MDINT 0x0000000000010000ULL |
| 192 | #define XRXMAC_STAT_MSK_RXFRAG_CNT_EXP 0x0000000000008000ULL |
| 193 | #define XRXMAC_STAT_MSK_RXMULTF_CNT_EXP 0x0000000000004000ULL |
| 194 | #define XRXMAC_STAT_MSK_RXBCAST_CNT_EXP 0x0000000000002000ULL |
| 195 | #define XRXMAC_STAT_MSK_RXHIST6_CNT_EXP 0x0000000000001000ULL |
| 196 | #define XRXMAC_STAT_MSK_RXHIST5_CNT_EXP 0x0000000000000800ULL |
| 197 | #define XRXMAC_STAT_MSK_RXHIST4_CNT_EXP 0x0000000000000400ULL |
| 198 | #define XRXMAC_STAT_MSK_RXHIST3_CNT_EXP 0x0000000000000200ULL |
| 199 | #define XRXMAC_STAT_MSK_RXHIST2_CNT_EXP 0x0000000000000100ULL |
| 200 | #define XRXMAC_STAT_MSK_RXHIST1_CNT_EXP 0x0000000000000080ULL |
| 201 | #define XRXMAC_STAT_MSK_RXOCTET_CNT_EXP 0x0000000000000040ULL |
| 202 | #define XRXMAC_STAT_MSK_CVIOLERR_CNT_EXP 0x0000000000000020ULL |
| 203 | #define XRXMAC_STAT_MSK_LENERR_CNT_EXP 0x0000000000000010ULL |
| 204 | #define XRXMAC_STAT_MSK_CRCERR_CNT_EXP 0x0000000000000008ULL |
| 205 | #define XRXMAC_STAT_MSK_RXUFLOW_CNT_EXP 0x0000000000000004ULL |
| 206 | #define XRXMAC_STAT_MSK_RXOFLOW_CNT_EXP 0x0000000000000002ULL |
| 207 | #define XRXMAC_STAT_MSK_FRAME_RCVD 0x0000000000000001ULL |
| 208 | |
| 209 | #define XMAC_FC_MSK 0x00050UL |
| 210 | #define XMAC_FC_MSK_TX_MAC_NPAUSE 0x0000000000000004ULL |
| 211 | #define XMAC_FC_MSK_TX_MAC_PAUSE 0x0000000000000002ULL |
| 212 | #define XMAC_FC_MSK_RX_MAC_RPAUSE 0x0000000000000001ULL |
| 213 | |
| 214 | #define XMAC_CONFIG 0x00060UL |
| 215 | #define XMAC_CONFIG_SEL_CLK_25MHZ 0x0000000080000000ULL |
| 216 | #define XMAC_CONFIG_1G_PCS_BYPASS 0x0000000040000000ULL |
| 217 | #define XMAC_CONFIG_10G_XPCS_BYPASS 0x0000000020000000ULL |
| 218 | #define XMAC_CONFIG_MODE_MASK 0x0000000018000000ULL |
| 219 | #define XMAC_CONFIG_MODE_XGMII 0x0000000000000000ULL |
| 220 | #define XMAC_CONFIG_MODE_GMII 0x0000000008000000ULL |
| 221 | #define XMAC_CONFIG_MODE_MII 0x0000000010000000ULL |
| 222 | #define XMAC_CONFIG_LFS_DISABLE 0x0000000004000000ULL |
| 223 | #define XMAC_CONFIG_LOOPBACK 0x0000000002000000ULL |
| 224 | #define XMAC_CONFIG_TX_OUTPUT_EN 0x0000000001000000ULL |
| 225 | #define XMAC_CONFIG_SEL_POR_CLK_SRC 0x0000000000800000ULL |
| 226 | #define XMAC_CONFIG_LED_POLARITY 0x0000000000400000ULL |
| 227 | #define XMAC_CONFIG_FORCE_LED_ON 0x0000000000200000ULL |
| 228 | #define XMAC_CONFIG_PASS_FLOW_CTRL 0x0000000000100000ULL |
| 229 | #define XMAC_CONFIG_RCV_PAUSE_ENABLE 0x0000000000080000ULL |
| 230 | #define XMAC_CONFIG_MAC2IPP_PKT_CNT_EN 0x0000000000040000ULL |
| 231 | #define XMAC_CONFIG_STRIP_CRC 0x0000000000020000ULL |
| 232 | #define XMAC_CONFIG_ADDR_FILTER_EN 0x0000000000010000ULL |
| 233 | #define XMAC_CONFIG_HASH_FILTER_EN 0x0000000000008000ULL |
| 234 | #define XMAC_CONFIG_RX_CODEV_CHK_DIS 0x0000000000004000ULL |
| 235 | #define XMAC_CONFIG_RESERVED_MULTICAST 0x0000000000002000ULL |
| 236 | #define XMAC_CONFIG_RX_CRC_CHK_DIS 0x0000000000001000ULL |
| 237 | #define XMAC_CONFIG_ERR_CHK_DIS 0x0000000000000800ULL |
| 238 | #define XMAC_CONFIG_PROMISC_GROUP 0x0000000000000400ULL |
| 239 | #define XMAC_CONFIG_PROMISCUOUS 0x0000000000000200ULL |
| 240 | #define XMAC_CONFIG_RX_MAC_ENABLE 0x0000000000000100ULL |
| 241 | #define XMAC_CONFIG_WARNING_MSG_EN 0x0000000000000080ULL |
| 242 | #define XMAC_CONFIG_ALWAYS_NO_CRC 0x0000000000000008ULL |
| 243 | #define XMAC_CONFIG_VAR_MIN_IPG_EN 0x0000000000000004ULL |
| 244 | #define XMAC_CONFIG_STRETCH_MODE 0x0000000000000002ULL |
| 245 | #define XMAC_CONFIG_TX_ENABLE 0x0000000000000001ULL |
| 246 | |
| 247 | #define XMAC_IPG 0x00080UL |
| 248 | #define XMAC_IPG_STRETCH_CONST 0x0000000000e00000ULL |
| 249 | #define XMAC_IPG_STRETCH_CONST_SHIFT 21 |
| 250 | #define XMAC_IPG_STRETCH_RATIO 0x00000000001f0000ULL |
| 251 | #define XMAC_IPG_STRETCH_RATIO_SHIFT 16 |
| 252 | #define XMAC_IPG_IPG_MII_GMII 0x000000000000ff00ULL |
| 253 | #define XMAC_IPG_IPG_MII_GMII_SHIFT 8 |
| 254 | #define XMAC_IPG_IPG_XGMII 0x0000000000000007ULL |
| 255 | #define XMAC_IPG_IPG_XGMII_SHIFT 0 |
| 256 | |
| 257 | #define IPG_12_15_XGMII 3 |
| 258 | #define IPG_16_19_XGMII 4 |
| 259 | #define IPG_20_23_XGMII 5 |
| 260 | #define IPG_12_MII_GMII 10 |
| 261 | #define IPG_13_MII_GMII 11 |
| 262 | #define IPG_14_MII_GMII 12 |
| 263 | #define IPG_15_MII_GMII 13 |
| 264 | #define IPG_16_MII_GMII 14 |
| 265 | |
| 266 | #define XMAC_MIN 0x00088UL |
| 267 | #define XMAC_MIN_RX_MIN_PKT_SIZE 0x000000003ff00000ULL |
| 268 | #define XMAC_MIN_RX_MIN_PKT_SIZE_SHFT 20 |
| 269 | #define XMAC_MIN_SLOT_TIME 0x000000000003fc00ULL |
| 270 | #define XMAC_MIN_SLOT_TIME_SHFT 10 |
| 271 | #define XMAC_MIN_TX_MIN_PKT_SIZE 0x00000000000003ffULL |
| 272 | #define XMAC_MIN_TX_MIN_PKT_SIZE_SHFT 0 |
| 273 | |
| 274 | #define XMAC_MAX 0x00090UL |
| 275 | #define XMAC_MAX_FRAME_SIZE 0x0000000000003fffULL |
| 276 | #define XMAC_MAX_FRAME_SIZE_SHFT 0 |
| 277 | |
| 278 | #define XMAC_ADDR0 0x000a0UL |
| 279 | #define XMAC_ADDR0_ADDR0 0x000000000000ffffULL |
| 280 | |
| 281 | #define XMAC_ADDR1 0x000a8UL |
| 282 | #define XMAC_ADDR1_ADDR1 0x000000000000ffffULL |
| 283 | |
| 284 | #define XMAC_ADDR2 0x000b0UL |
| 285 | #define XMAC_ADDR2_ADDR2 0x000000000000ffffULL |
| 286 | |
| 287 | #define XMAC_ADDR_CMPEN 0x00208UL |
| 288 | #define XMAC_ADDR_CMPEN_EN15 0x0000000000008000ULL |
| 289 | #define XMAC_ADDR_CMPEN_EN14 0x0000000000004000ULL |
| 290 | #define XMAC_ADDR_CMPEN_EN13 0x0000000000002000ULL |
| 291 | #define XMAC_ADDR_CMPEN_EN12 0x0000000000001000ULL |
| 292 | #define XMAC_ADDR_CMPEN_EN11 0x0000000000000800ULL |
| 293 | #define XMAC_ADDR_CMPEN_EN10 0x0000000000000400ULL |
| 294 | #define XMAC_ADDR_CMPEN_EN9 0x0000000000000200ULL |
| 295 | #define XMAC_ADDR_CMPEN_EN8 0x0000000000000100ULL |
| 296 | #define XMAC_ADDR_CMPEN_EN7 0x0000000000000080ULL |
| 297 | #define XMAC_ADDR_CMPEN_EN6 0x0000000000000040ULL |
| 298 | #define XMAC_ADDR_CMPEN_EN5 0x0000000000000020ULL |
| 299 | #define XMAC_ADDR_CMPEN_EN4 0x0000000000000010ULL |
| 300 | #define XMAC_ADDR_CMPEN_EN3 0x0000000000000008ULL |
| 301 | #define XMAC_ADDR_CMPEN_EN2 0x0000000000000004ULL |
| 302 | #define XMAC_ADDR_CMPEN_EN1 0x0000000000000002ULL |
| 303 | #define XMAC_ADDR_CMPEN_EN0 0x0000000000000001ULL |
| 304 | |
| 305 | #define XMAC_NUM_ALT_ADDR 16 |
| 306 | |
| 307 | #define XMAC_ALT_ADDR0(NUM) (0x00218UL + (NUM)*0x18UL) |
| 308 | #define XMAC_ALT_ADDR0_ADDR0 0x000000000000ffffULL |
| 309 | |
| 310 | #define XMAC_ALT_ADDR1(NUM) (0x00220UL + (NUM)*0x18UL) |
| 311 | #define XMAC_ALT_ADDR1_ADDR1 0x000000000000ffffULL |
| 312 | |
| 313 | #define XMAC_ALT_ADDR2(NUM) (0x00228UL + (NUM)*0x18UL) |
| 314 | #define XMAC_ALT_ADDR2_ADDR2 0x000000000000ffffULL |
| 315 | |
| 316 | #define XMAC_ADD_FILT0 0x00818UL |
| 317 | #define XMAC_ADD_FILT0_FILT0 0x000000000000ffffULL |
| 318 | |
| 319 | #define XMAC_ADD_FILT1 0x00820UL |
| 320 | #define XMAC_ADD_FILT1_FILT1 0x000000000000ffffULL |
| 321 | |
| 322 | #define XMAC_ADD_FILT2 0x00828UL |
| 323 | #define XMAC_ADD_FILT2_FILT2 0x000000000000ffffULL |
| 324 | |
| 325 | #define XMAC_ADD_FILT12_MASK 0x00830UL |
| 326 | #define XMAC_ADD_FILT12_MASK_VAL 0x00000000000000ffULL |
| 327 | |
| 328 | #define XMAC_ADD_FILT00_MASK 0x00838UL |
| 329 | #define XMAC_ADD_FILT00_MASK_VAL 0x000000000000ffffULL |
| 330 | |
| 331 | #define XMAC_HASH_TBL(NUM) (0x00840UL + (NUM) * 0x8UL) |
| 332 | #define XMAC_HASH_TBL_VAL 0x000000000000ffffULL |
| 333 | |
| 334 | #define XMAC_NUM_HOST_INFO 20 |
| 335 | |
| 336 | #define XMAC_HOST_INFO(NUM) (0x00900UL + (NUM) * 0x8UL) |
| 337 | |
| 338 | #define XMAC_PA_DATA0 0x00b80UL |
| 339 | #define XMAC_PA_DATA0_VAL 0x00000000ffffffffULL |
| 340 | |
| 341 | #define XMAC_PA_DATA1 0x00b88UL |
| 342 | #define XMAC_PA_DATA1_VAL 0x00000000ffffffffULL |
| 343 | |
| 344 | #define XMAC_DEBUG_SEL 0x00b90UL |
| 345 | #define XMAC_DEBUG_SEL_XMAC 0x0000000000000078ULL |
| 346 | #define XMAC_DEBUG_SEL_MAC 0x0000000000000007ULL |
| 347 | |
| 348 | #define XMAC_TRAIN_VEC 0x00b98UL |
| 349 | #define XMAC_TRAIN_VEC_VAL 0x00000000ffffffffULL |
| 350 | |
| 351 | #define RXMAC_BT_CNT 0x00100UL |
| 352 | #define RXMAC_BT_CNT_COUNT 0x00000000ffffffffULL |
| 353 | |
| 354 | #define RXMAC_BC_FRM_CNT 0x00108UL |
| 355 | #define RXMAC_BC_FRM_CNT_COUNT 0x00000000001fffffULL |
| 356 | |
| 357 | #define RXMAC_MC_FRM_CNT 0x00110UL |
| 358 | #define RXMAC_MC_FRM_CNT_COUNT 0x00000000001fffffULL |
| 359 | |
| 360 | #define RXMAC_FRAG_CNT 0x00118UL |
| 361 | #define RXMAC_FRAG_CNT_COUNT 0x00000000001fffffULL |
| 362 | |
| 363 | #define RXMAC_HIST_CNT1 0x00120UL |
| 364 | #define RXMAC_HIST_CNT1_COUNT 0x00000000001fffffULL |
| 365 | |
| 366 | #define RXMAC_HIST_CNT2 0x00128UL |
| 367 | #define RXMAC_HIST_CNT2_COUNT 0x00000000001fffffULL |
| 368 | |
| 369 | #define RXMAC_HIST_CNT3 0x00130UL |
| 370 | #define RXMAC_HIST_CNT3_COUNT 0x00000000000fffffULL |
| 371 | |
| 372 | #define RXMAC_HIST_CNT4 0x00138UL |
| 373 | #define RXMAC_HIST_CNT4_COUNT 0x000000000007ffffULL |
| 374 | |
| 375 | #define RXMAC_HIST_CNT5 0x00140UL |
| 376 | #define RXMAC_HIST_CNT5_COUNT 0x000000000003ffffULL |
| 377 | |
| 378 | #define RXMAC_HIST_CNT6 0x00148UL |
| 379 | #define RXMAC_HIST_CNT6_COUNT 0x000000000000ffffULL |
| 380 | |
| 381 | #define RXMAC_MPSZER_CNT 0x00150UL |
| 382 | #define RXMAC_MPSZER_CNT_COUNT 0x00000000000000ffULL |
| 383 | |
| 384 | #define RXMAC_CRC_ER_CNT 0x00158UL |
| 385 | #define RXMAC_CRC_ER_CNT_COUNT 0x00000000000000ffULL |
| 386 | |
| 387 | #define RXMAC_CD_VIO_CNT 0x00160UL |
| 388 | #define RXMAC_CD_VIO_CNT_COUNT 0x00000000000000ffULL |
| 389 | |
| 390 | #define RXMAC_ALIGN_ERR_CNT 0x00168UL |
| 391 | #define RXMAC_ALIGN_ERR_CNT_COUNT 0x00000000000000ffULL |
| 392 | |
| 393 | #define TXMAC_FRM_CNT 0x00170UL |
| 394 | #define TXMAC_FRM_CNT_COUNT 0x00000000ffffffffULL |
| 395 | |
| 396 | #define TXMAC_BYTE_CNT 0x00178UL |
| 397 | #define TXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL |
| 398 | |
| 399 | #define LINK_FAULT_CNT 0x00180UL |
| 400 | #define LINK_FAULT_CNT_COUNT 0x00000000000000ffULL |
| 401 | |
| 402 | #define RXMAC_HIST_CNT7 0x00188UL |
| 403 | #define RXMAC_HIST_CNT7_COUNT 0x0000000007ffffffULL |
| 404 | |
| 405 | #define XMAC_SM_REG 0x001a8UL |
| 406 | #define XMAC_SM_REG_STATE 0x00000000ffffffffULL |
| 407 | |
| 408 | #define XMAC_INTER1 0x001b0UL |
| 409 | #define XMAC_INTERN1_SIGNALS1 0x00000000ffffffffULL |
| 410 | |
| 411 | #define XMAC_INTER2 0x001b8UL |
| 412 | #define XMAC_INTERN2_SIGNALS2 0x00000000ffffffffULL |
| 413 | |
| 414 | /* BMAC registers, offset from np->mac_regs */ |
| 415 | |
| 416 | #define BTXMAC_SW_RST 0x00000UL |
| 417 | #define BTXMAC_SW_RST_RESET 0x0000000000000001ULL |
| 418 | |
| 419 | #define BRXMAC_SW_RST 0x00008UL |
| 420 | #define BRXMAC_SW_RST_RESET 0x0000000000000001ULL |
| 421 | |
| 422 | #define BMAC_SEND_PAUSE 0x00010UL |
| 423 | #define BMAC_SEND_PAUSE_SEND 0x0000000000010000ULL |
| 424 | #define BMAC_SEND_PAUSE_TIME 0x000000000000ffffULL |
| 425 | |
| 426 | #define BTXMAC_STATUS 0x00020UL |
| 427 | #define BTXMAC_STATUS_XMIT 0x0000000000000001ULL |
| 428 | #define BTXMAC_STATUS_UNDERRUN 0x0000000000000002ULL |
| 429 | #define BTXMAC_STATUS_MAX_PKT_ERR 0x0000000000000004ULL |
| 430 | #define BTXMAC_STATUS_BYTE_CNT_EXP 0x0000000000000400ULL |
| 431 | #define BTXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000800ULL |
| 432 | |
| 433 | #define BRXMAC_STATUS 0x00028UL |
| 434 | #define BRXMAC_STATUS_RX_PKT 0x0000000000000001ULL |
| 435 | #define BRXMAC_STATUS_OVERFLOW 0x0000000000000002ULL |
| 436 | #define BRXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000004ULL |
| 437 | #define BRXMAC_STATUS_ALIGN_ERR_EXP 0x0000000000000008ULL |
| 438 | #define BRXMAC_STATUS_CRC_ERR_EXP 0x0000000000000010ULL |
| 439 | #define BRXMAC_STATUS_LEN_ERR_EXP 0x0000000000000020ULL |
| 440 | |
| 441 | #define BMAC_CTRL_STATUS 0x00030UL |
| 442 | #define BMAC_CTRL_STATUS_PAUSE_RECV 0x0000000000000001ULL |
| 443 | #define BMAC_CTRL_STATUS_PAUSE 0x0000000000000002ULL |
| 444 | #define BMAC_CTRL_STATUS_NOPAUSE 0x0000000000000004ULL |
| 445 | #define BMAC_CTRL_STATUS_TIME 0x00000000ffff0000ULL |
| 446 | #define BMAC_CTRL_STATUS_TIME_SHIFT 16 |
| 447 | |
| 448 | #define BTXMAC_STATUS_MASK 0x00040UL |
| 449 | #define BRXMAC_STATUS_MASK 0x00048UL |
| 450 | #define BMAC_CTRL_STATUS_MASK 0x00050UL |
| 451 | |
| 452 | #define BTXMAC_CONFIG 0x00060UL |
| 453 | #define BTXMAC_CONFIG_ENABLE 0x0000000000000001ULL |
| 454 | #define BTXMAC_CONFIG_FCS_DISABLE 0x0000000000000002ULL |
| 455 | |
| 456 | #define BRXMAC_CONFIG 0x00068UL |
| 457 | #define BRXMAC_CONFIG_DISCARD_DIS 0x0000000000000080ULL |
| 458 | #define BRXMAC_CONFIG_ADDR_FILT_EN 0x0000000000000040ULL |
| 459 | #define BRXMAC_CONFIG_HASH_FILT_EN 0x0000000000000020ULL |
| 460 | #define BRXMAC_CONFIG_PROMISC_GRP 0x0000000000000010ULL |
| 461 | #define BRXMAC_CONFIG_PROMISC 0x0000000000000008ULL |
| 462 | #define BRXMAC_CONFIG_STRIP_FCS 0x0000000000000004ULL |
| 463 | #define BRXMAC_CONFIG_STRIP_PAD 0x0000000000000002ULL |
| 464 | #define BRXMAC_CONFIG_ENABLE 0x0000000000000001ULL |
| 465 | |
| 466 | #define BMAC_CTRL_CONFIG 0x00070UL |
| 467 | #define BMAC_CTRL_CONFIG_TX_PAUSE_EN 0x0000000000000001ULL |
| 468 | #define BMAC_CTRL_CONFIG_RX_PAUSE_EN 0x0000000000000002ULL |
| 469 | #define BMAC_CTRL_CONFIG_PASS_CTRL 0x0000000000000004ULL |
| 470 | |
| 471 | #define BMAC_XIF_CONFIG 0x00078UL |
| 472 | #define BMAC_XIF_CONFIG_TX_OUTPUT_EN 0x0000000000000001ULL |
| 473 | #define BMAC_XIF_CONFIG_MII_LOOPBACK 0x0000000000000002ULL |
| 474 | #define BMAC_XIF_CONFIG_GMII_MODE 0x0000000000000008ULL |
| 475 | #define BMAC_XIF_CONFIG_LINK_LED 0x0000000000000020ULL |
| 476 | #define BMAC_XIF_CONFIG_LED_POLARITY 0x0000000000000040ULL |
| 477 | #define BMAC_XIF_CONFIG_25MHZ_CLOCK 0x0000000000000080ULL |
| 478 | |
| 479 | #define BMAC_MIN_FRAME 0x000a0UL |
| 480 | #define BMAC_MIN_FRAME_VAL 0x00000000000003ffULL |
| 481 | |
| 482 | #define BMAC_MAX_FRAME 0x000a8UL |
| 483 | #define BMAC_MAX_FRAME_MAX_BURST 0x000000003fff0000ULL |
| 484 | #define BMAC_MAX_FRAME_MAX_BURST_SHIFT 16 |
| 485 | #define BMAC_MAX_FRAME_MAX_FRAME 0x0000000000003fffULL |
| 486 | #define BMAC_MAX_FRAME_MAX_FRAME_SHIFT 0 |
| 487 | |
| 488 | #define BMAC_PREAMBLE_SIZE 0x000b0UL |
| 489 | #define BMAC_PREAMBLE_SIZE_VAL 0x00000000000003ffULL |
| 490 | |
| 491 | #define BMAC_CTRL_TYPE 0x000c8UL |
| 492 | |
| 493 | #define BMAC_ADDR0 0x00100UL |
| 494 | #define BMAC_ADDR0_ADDR0 0x000000000000ffffULL |
| 495 | |
| 496 | #define BMAC_ADDR1 0x00108UL |
| 497 | #define BMAC_ADDR1_ADDR1 0x000000000000ffffULL |
| 498 | |
| 499 | #define BMAC_ADDR2 0x00110UL |
| 500 | #define BMAC_ADDR2_ADDR2 0x000000000000ffffULL |
| 501 | |
| 502 | #define BMAC_NUM_ALT_ADDR 6 |
| 503 | |
| 504 | #define BMAC_ALT_ADDR0(NUM) (0x00118UL + (NUM)*0x18UL) |
| 505 | #define BMAC_ALT_ADDR0_ADDR0 0x000000000000ffffULL |
| 506 | |
| 507 | #define BMAC_ALT_ADDR1(NUM) (0x00120UL + (NUM)*0x18UL) |
| 508 | #define BMAC_ALT_ADDR1_ADDR1 0x000000000000ffffULL |
| 509 | |
| 510 | #define BMAC_ALT_ADDR2(NUM) (0x00128UL + (NUM)*0x18UL) |
| 511 | #define BMAC_ALT_ADDR2_ADDR2 0x000000000000ffffULL |
| 512 | |
| 513 | #define BMAC_FC_ADDR0 0x00268UL |
| 514 | #define BMAC_FC_ADDR0_ADDR0 0x000000000000ffffULL |
| 515 | |
| 516 | #define BMAC_FC_ADDR1 0x00270UL |
| 517 | #define BMAC_FC_ADDR1_ADDR1 0x000000000000ffffULL |
| 518 | |
| 519 | #define BMAC_FC_ADDR2 0x00278UL |
| 520 | #define BMAC_FC_ADDR2_ADDR2 0x000000000000ffffULL |
| 521 | |
| 522 | #define BMAC_ADD_FILT0 0x00298UL |
| 523 | #define BMAC_ADD_FILT0_FILT0 0x000000000000ffffULL |
| 524 | |
| 525 | #define BMAC_ADD_FILT1 0x002a0UL |
| 526 | #define BMAC_ADD_FILT1_FILT1 0x000000000000ffffULL |
| 527 | |
| 528 | #define BMAC_ADD_FILT2 0x002a8UL |
| 529 | #define BMAC_ADD_FILT2_FILT2 0x000000000000ffffULL |
| 530 | |
| 531 | #define BMAC_ADD_FILT12_MASK 0x002b0UL |
| 532 | #define BMAC_ADD_FILT12_MASK_VAL 0x00000000000000ffULL |
| 533 | |
| 534 | #define BMAC_ADD_FILT00_MASK 0x002b8UL |
| 535 | #define BMAC_ADD_FILT00_MASK_VAL 0x000000000000ffffULL |
| 536 | |
| 537 | #define BMAC_HASH_TBL(NUM) (0x002c0UL + (NUM) * 0x8UL) |
| 538 | #define BMAC_HASH_TBL_VAL 0x000000000000ffffULL |
| 539 | |
| 540 | #define BRXMAC_FRAME_CNT 0x00370 |
| 541 | #define BRXMAC_FRAME_CNT_COUNT 0x000000000000ffffULL |
| 542 | |
| 543 | #define BRXMAC_MAX_LEN_ERR_CNT 0x00378 |
| 544 | |
| 545 | #define BRXMAC_ALIGN_ERR_CNT 0x00380 |
| 546 | #define BRXMAC_ALIGN_ERR_CNT_COUNT 0x000000000000ffffULL |
| 547 | |
| 548 | #define BRXMAC_CRC_ERR_CNT 0x00388 |
| 549 | #define BRXMAC_ALIGN_ERR_CNT_COUNT 0x000000000000ffffULL |
| 550 | |
| 551 | #define BRXMAC_CODE_VIOL_ERR_CNT 0x00390 |
| 552 | #define BRXMAC_CODE_VIOL_ERR_CNT_COUNT 0x000000000000ffffULL |
| 553 | |
| 554 | #define BMAC_STATE_MACHINE 0x003a0 |
| 555 | |
| 556 | #define BMAC_ADDR_CMPEN 0x003f8UL |
| 557 | #define BMAC_ADDR_CMPEN_EN15 0x0000000000008000ULL |
| 558 | #define BMAC_ADDR_CMPEN_EN14 0x0000000000004000ULL |
| 559 | #define BMAC_ADDR_CMPEN_EN13 0x0000000000002000ULL |
| 560 | #define BMAC_ADDR_CMPEN_EN12 0x0000000000001000ULL |
| 561 | #define BMAC_ADDR_CMPEN_EN11 0x0000000000000800ULL |
| 562 | #define BMAC_ADDR_CMPEN_EN10 0x0000000000000400ULL |
| 563 | #define BMAC_ADDR_CMPEN_EN9 0x0000000000000200ULL |
| 564 | #define BMAC_ADDR_CMPEN_EN8 0x0000000000000100ULL |
| 565 | #define BMAC_ADDR_CMPEN_EN7 0x0000000000000080ULL |
| 566 | #define BMAC_ADDR_CMPEN_EN6 0x0000000000000040ULL |
| 567 | #define BMAC_ADDR_CMPEN_EN5 0x0000000000000020ULL |
| 568 | #define BMAC_ADDR_CMPEN_EN4 0x0000000000000010ULL |
| 569 | #define BMAC_ADDR_CMPEN_EN3 0x0000000000000008ULL |
| 570 | #define BMAC_ADDR_CMPEN_EN2 0x0000000000000004ULL |
| 571 | #define BMAC_ADDR_CMPEN_EN1 0x0000000000000002ULL |
| 572 | #define BMAC_ADDR_CMPEN_EN0 0x0000000000000001ULL |
| 573 | |
| 574 | #define BMAC_NUM_HOST_INFO 9 |
| 575 | |
| 576 | #define BMAC_HOST_INFO(NUM) (0x00400UL + (NUM) * 0x8UL) |
| 577 | |
| 578 | #define BTXMAC_BYTE_CNT 0x00448UL |
| 579 | #define BTXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL |
| 580 | |
| 581 | #define BTXMAC_FRM_CNT 0x00450UL |
| 582 | #define BTXMAC_FRM_CNT_COUNT 0x00000000ffffffffULL |
| 583 | |
| 584 | #define BRXMAC_BYTE_CNT 0x00458UL |
| 585 | #define BRXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL |
| 586 | |
| 587 | #define HOST_INFO_MPR 0x0000000000000100ULL |
| 588 | #define HOST_INFO_MACRDCTBLN 0x0000000000000007ULL |
| 589 | |
| 590 | /* XPCS registers, offset from np->regs + np->xpcs_off */ |
| 591 | |
| 592 | #define XPCS_CONTROL1 (FZC_MAC + 0x00000UL) |
| 593 | #define XPCS_CONTROL1_RESET 0x0000000000008000ULL |
| 594 | #define XPCS_CONTROL1_LOOPBACK 0x0000000000004000ULL |
| 595 | #define XPCS_CONTROL1_SPEED_SELECT3 0x0000000000002000ULL |
| 596 | #define XPCS_CONTROL1_CSR_LOW_PWR 0x0000000000000800ULL |
| 597 | #define XPCS_CONTROL1_CSR_SPEED1 0x0000000000000040ULL |
| 598 | #define XPCS_CONTROL1_CSR_SPEED0 0x000000000000003cULL |
| 599 | |
| 600 | #define XPCS_STATUS1 (FZC_MAC + 0x00008UL) |
| 601 | #define XPCS_STATUS1_CSR_FAULT 0x0000000000000080ULL |
| 602 | #define XPCS_STATUS1_CSR_RXLNK_STAT 0x0000000000000004ULL |
| 603 | #define XPCS_STATUS1_CSR_LPWR_ABLE 0x0000000000000002ULL |
| 604 | |
| 605 | #define XPCS_DEVICE_IDENTIFIER (FZC_MAC + 0x00010UL) |
| 606 | #define XPCS_DEVICE_IDENTIFIER_VAL 0x00000000ffffffffULL |
| 607 | |
| 608 | #define XPCS_SPEED_ABILITY (FZC_MAC + 0x00018UL) |
| 609 | #define XPCS_SPEED_ABILITY_10GIG 0x0000000000000001ULL |
| 610 | |
| 611 | #define XPCS_DEV_IN_PKG (FZC_MAC + 0x00020UL) |
| 612 | #define XPCS_DEV_IN_PKG_CSR_VEND2 0x0000000080000000ULL |
| 613 | #define XPCS_DEV_IN_PKG_CSR_VEND1 0x0000000040000000ULL |
| 614 | #define XPCS_DEV_IN_PKG_DTE_XS 0x0000000000000020ULL |
| 615 | #define XPCS_DEV_IN_PKG_PHY_XS 0x0000000000000010ULL |
| 616 | #define XPCS_DEV_IN_PKG_PCS 0x0000000000000008ULL |
| 617 | #define XPCS_DEV_IN_PKG_WIS 0x0000000000000004ULL |
| 618 | #define XPCS_DEV_IN_PKG_PMD_PMA 0x0000000000000002ULL |
| 619 | #define XPCS_DEV_IN_PKG_CLS22 0x0000000000000001ULL |
| 620 | |
| 621 | #define XPCS_CONTROL2 (FZC_MAC + 0x00028UL) |
| 622 | #define XPCS_CONTROL2_CSR_PSC_SEL 0x0000000000000003ULL |
| 623 | |
| 624 | #define XPCS_STATUS2 (FZC_MAC + 0x00030UL) |
| 625 | #define XPCS_STATUS2_CSR_DEV_PRES 0x000000000000c000ULL |
| 626 | #define XPCS_STATUS2_CSR_TX_FAULT 0x0000000000000800ULL |
| 627 | #define XPCS_STATUS2_CSR_RCV_FAULT 0x0000000000000400ULL |
| 628 | #define XPCS_STATUS2_TEN_GBASE_W 0x0000000000000004ULL |
| 629 | #define XPCS_STATUS2_TEN_GBASE_X 0x0000000000000002ULL |
| 630 | #define XPCS_STATUS2_TEN_GBASE_R 0x0000000000000001ULL |
| 631 | |
| 632 | #define XPCS_PKG_ID (FZC_MAC + 0x00038UL) |
| 633 | #define XPCS_PKG_ID_VAL 0x00000000ffffffffULL |
| 634 | |
| 635 | #define XPCS_STATUS(IDX) (FZC_MAC + 0x00040UL) |
| 636 | #define XPCS_STATUS_CSR_LANE_ALIGN 0x0000000000001000ULL |
| 637 | #define XPCS_STATUS_CSR_PATTEST_CAP 0x0000000000000800ULL |
| 638 | #define XPCS_STATUS_CSR_LANE3_SYNC 0x0000000000000008ULL |
| 639 | #define XPCS_STATUS_CSR_LANE2_SYNC 0x0000000000000004ULL |
| 640 | #define XPCS_STATUS_CSR_LANE1_SYNC 0x0000000000000002ULL |
| 641 | #define XPCS_STATUS_CSR_LANE0_SYNC 0x0000000000000001ULL |
| 642 | |
| 643 | #define XPCS_TEST_CONTROL (FZC_MAC + 0x00048UL) |
| 644 | #define XPCS_TEST_CONTROL_TXTST_EN 0x0000000000000004ULL |
| 645 | #define XPCS_TEST_CONTROL_TPAT_SEL 0x0000000000000003ULL |
| 646 | |
| 647 | #define XPCS_CFG_VENDOR1 (FZC_MAC + 0x00050UL) |
| 648 | #define XPCS_CFG_VENDOR1_DBG_IOTST 0x0000000000000080ULL |
| 649 | #define XPCS_CFG_VENDOR1_DBG_SEL 0x0000000000000078ULL |
| 650 | #define XPCS_CFG_VENDOR1_BYPASS_DET 0x0000000000000004ULL |
| 651 | #define XPCS_CFG_VENDOR1_TXBUF_EN 0x0000000000000002ULL |
| 652 | #define XPCS_CFG_VENDOR1_XPCS_EN 0x0000000000000001ULL |
| 653 | |
| 654 | #define XPCS_DIAG_VENDOR2 (FZC_MAC + 0x00058UL) |
| 655 | #define XPCS_DIAG_VENDOR2_SSM_LANE3 0x0000000001e00000ULL |
| 656 | #define XPCS_DIAG_VENDOR2_SSM_LANE2 0x00000000001e0000ULL |
| 657 | #define XPCS_DIAG_VENDOR2_SSM_LANE1 0x000000000001e000ULL |
| 658 | #define XPCS_DIAG_VENDOR2_SSM_LANE0 0x0000000000001e00ULL |
| 659 | #define XPCS_DIAG_VENDOR2_EBUF_SM 0x00000000000001feULL |
| 660 | #define XPCS_DIAG_VENDOR2_RCV_SM 0x0000000000000001ULL |
| 661 | |
| 662 | #define XPCS_MASK1 (FZC_MAC + 0x00060UL) |
| 663 | #define XPCS_MASK1_FAULT_MASK 0x0000000000000080ULL |
| 664 | #define XPCS_MASK1_RXALIGN_STAT_MSK 0x0000000000000004ULL |
| 665 | |
| 666 | #define XPCS_PKT_COUNT (FZC_MAC + 0x00068UL) |
| 667 | #define XPCS_PKT_COUNT_TX 0x00000000ffff0000ULL |
| 668 | #define XPCS_PKT_COUNT_RX 0x000000000000ffffULL |
| 669 | |
| 670 | #define XPCS_TX_SM (FZC_MAC + 0x00070UL) |
| 671 | #define XPCS_TX_SM_VAL 0x000000000000000fULL |
| 672 | |
| 673 | #define XPCS_DESKEW_ERR_CNT (FZC_MAC + 0x00078UL) |
| 674 | #define XPCS_DESKEW_ERR_CNT_VAL 0x00000000000000ffULL |
| 675 | |
| 676 | #define XPCS_SYMERR_CNT01 (FZC_MAC + 0x00080UL) |
| 677 | #define XPCS_SYMERR_CNT01_LANE1 0x00000000ffff0000ULL |
| 678 | #define XPCS_SYMERR_CNT01_LANE0 0x000000000000ffffULL |
| 679 | |
| 680 | #define XPCS_SYMERR_CNT23 (FZC_MAC + 0x00088UL) |
| 681 | #define XPCS_SYMERR_CNT23_LANE3 0x00000000ffff0000ULL |
| 682 | #define XPCS_SYMERR_CNT23_LANE2 0x000000000000ffffULL |
| 683 | |
| 684 | #define XPCS_TRAINING_VECTOR (FZC_MAC + 0x00090UL) |
| 685 | #define XPCS_TRAINING_VECTOR_VAL 0x00000000ffffffffULL |
| 686 | |
| 687 | /* PCS registers, offset from np->regs + np->pcs_off */ |
| 688 | |
| 689 | #define PCS_MII_CTL (FZC_MAC + 0x00000UL) |
| 690 | #define PCS_MII_CTL_RST 0x0000000000008000ULL |
| 691 | #define PCS_MII_CTL_10_100_SPEED 0x0000000000002000ULL |
| 692 | #define PCS_MII_AUTONEG_EN 0x0000000000001000ULL |
| 693 | #define PCS_MII_PWR_DOWN 0x0000000000000800ULL |
| 694 | #define PCS_MII_ISOLATE 0x0000000000000400ULL |
| 695 | #define PCS_MII_AUTONEG_RESTART 0x0000000000000200ULL |
| 696 | #define PCS_MII_DUPLEX 0x0000000000000100ULL |
| 697 | #define PCS_MII_COLL_TEST 0x0000000000000080ULL |
| 698 | #define PCS_MII_1000MB_SPEED 0x0000000000000040ULL |
| 699 | |
| 700 | #define PCS_MII_STAT (FZC_MAC + 0x00008UL) |
| 701 | #define PCS_MII_STAT_EXT_STATUS 0x0000000000000100ULL |
| 702 | #define PCS_MII_STAT_AUTONEG_DONE 0x0000000000000020ULL |
| 703 | #define PCS_MII_STAT_REMOTE_FAULT 0x0000000000000010ULL |
| 704 | #define PCS_MII_STAT_AUTONEG_ABLE 0x0000000000000008ULL |
| 705 | #define PCS_MII_STAT_LINK_STATUS 0x0000000000000004ULL |
| 706 | #define PCS_MII_STAT_JABBER_DET 0x0000000000000002ULL |
| 707 | #define PCS_MII_STAT_EXT_CAP 0x0000000000000001ULL |
| 708 | |
| 709 | #define PCS_MII_ADV (FZC_MAC + 0x00010UL) |
| 710 | #define PCS_MII_ADV_NEXT_PAGE 0x0000000000008000ULL |
| 711 | #define PCS_MII_ADV_ACK 0x0000000000004000ULL |
| 712 | #define PCS_MII_ADV_REMOTE_FAULT 0x0000000000003000ULL |
| 713 | #define PCS_MII_ADV_ASM_DIR 0x0000000000000100ULL |
| 714 | #define PCS_MII_ADV_PAUSE 0x0000000000000080ULL |
| 715 | #define PCS_MII_ADV_HALF_DUPLEX 0x0000000000000040ULL |
| 716 | #define PCS_MII_ADV_FULL_DUPLEX 0x0000000000000020ULL |
| 717 | |
| 718 | #define PCS_MII_PARTNER (FZC_MAC + 0x00018UL) |
| 719 | #define PCS_MII_PARTNER_NEXT_PAGE 0x0000000000008000ULL |
| 720 | #define PCS_MII_PARTNER_ACK 0x0000000000004000ULL |
| 721 | #define PCS_MII_PARTNER_REMOTE_FAULT 0x0000000000002000ULL |
| 722 | #define PCS_MII_PARTNER_PAUSE 0x0000000000000180ULL |
| 723 | #define PCS_MII_PARTNER_HALF_DUPLEX 0x0000000000000040ULL |
| 724 | #define PCS_MII_PARTNER_FULL_DUPLEX 0x0000000000000020ULL |
| 725 | |
| 726 | #define PCS_CONF (FZC_MAC + 0x00020UL) |
| 727 | #define PCS_CONF_MASK 0x0000000000000040ULL |
| 728 | #define PCS_CONF_10MS_TMR_OVERRIDE 0x0000000000000020ULL |
| 729 | #define PCS_CONF_JITTER_STUDY 0x0000000000000018ULL |
| 730 | #define PCS_CONF_SIGDET_ACTIVE_LOW 0x0000000000000004ULL |
| 731 | #define PCS_CONF_SIGDET_OVERRIDE 0x0000000000000002ULL |
| 732 | #define PCS_CONF_ENABLE 0x0000000000000001ULL |
| 733 | |
| 734 | #define PCS_STATE (FZC_MAC + 0x00028UL) |
| 735 | #define PCS_STATE_D_PARTNER_FAIL 0x0000000020000000ULL |
| 736 | #define PCS_STATE_D_WAIT_C_CODES_ACK 0x0000000010000000ULL |
| 737 | #define PCS_STATE_D_SYNC_LOSS 0x0000000008000000ULL |
| 738 | #define PCS_STATE_D_NO_GOOD_C_CODES 0x0000000004000000ULL |
| 739 | #define PCS_STATE_D_SERDES 0x0000000002000000ULL |
| 740 | #define PCS_STATE_D_BREAKLINK_C_CODES 0x0000000001000000ULL |
| 741 | #define PCS_STATE_L_SIGDET 0x0000000000400000ULL |
| 742 | #define PCS_STATE_L_SYNC_LOSS 0x0000000000200000ULL |
| 743 | #define PCS_STATE_L_C_CODES 0x0000000000100000ULL |
| 744 | #define PCS_STATE_LINK_CFG_STATE 0x000000000001e000ULL |
| 745 | #define PCS_STATE_SEQ_DET_STATE 0x0000000000001800ULL |
| 746 | #define PCS_STATE_WORD_SYNC_STATE 0x0000000000000700ULL |
| 747 | #define PCS_STATE_NO_IDLE 0x000000000000000fULL |
| 748 | |
| 749 | #define PCS_INTERRUPT (FZC_MAC + 0x00030UL) |
| 750 | #define PCS_INTERRUPT_LSTATUS 0x0000000000000004ULL |
| 751 | |
| 752 | #define PCS_DPATH_MODE (FZC_MAC + 0x000a0UL) |
| 753 | #define PCS_DPATH_MODE_PCS 0x0000000000000000ULL |
| 754 | #define PCS_DPATH_MODE_MII 0x0000000000000002ULL |
| 755 | #define PCS_DPATH_MODE_LINKUP_F_ENAB 0x0000000000000001ULL |
| 756 | |
| 757 | #define PCS_PKT_CNT (FZC_MAC + 0x000c0UL) |
| 758 | #define PCS_PKT_CNT_RX 0x0000000007ff0000ULL |
| 759 | #define PCS_PKT_CNT_TX 0x00000000000007ffULL |
| 760 | |
| 761 | #define MIF_BB_MDC (FZC_MAC + 0x16000UL) |
| 762 | #define MIF_BB_MDC_CLK 0x0000000000000001ULL |
| 763 | |
| 764 | #define MIF_BB_MDO (FZC_MAC + 0x16008UL) |
| 765 | #define MIF_BB_MDO_DAT 0x0000000000000001ULL |
| 766 | |
| 767 | #define MIF_BB_MDO_EN (FZC_MAC + 0x16010UL) |
| 768 | #define MIF_BB_MDO_EN_VAL 0x0000000000000001ULL |
| 769 | |
| 770 | #define MIF_FRAME_OUTPUT (FZC_MAC + 0x16018UL) |
| 771 | #define MIF_FRAME_OUTPUT_ST 0x00000000c0000000ULL |
| 772 | #define MIF_FRAME_OUTPUT_ST_SHIFT 30 |
| 773 | #define MIF_FRAME_OUTPUT_OP_ADDR 0x0000000000000000ULL |
| 774 | #define MIF_FRAME_OUTPUT_OP_WRITE 0x0000000010000000ULL |
| 775 | #define MIF_FRAME_OUTPUT_OP_READ_INC 0x0000000020000000ULL |
| 776 | #define MIF_FRAME_OUTPUT_OP_READ 0x0000000030000000ULL |
| 777 | #define MIF_FRAME_OUTPUT_OP_SHIFT 28 |
| 778 | #define MIF_FRAME_OUTPUT_PORT 0x000000000f800000ULL |
| 779 | #define MIF_FRAME_OUTPUT_PORT_SHIFT 23 |
| 780 | #define MIF_FRAME_OUTPUT_REG 0x00000000007c0000ULL |
| 781 | #define MIF_FRAME_OUTPUT_REG_SHIFT 18 |
| 782 | #define MIF_FRAME_OUTPUT_TA 0x0000000000030000ULL |
| 783 | #define MIF_FRAME_OUTPUT_TA_SHIFT 16 |
| 784 | #define MIF_FRAME_OUTPUT_DATA 0x000000000000ffffULL |
| 785 | #define MIF_FRAME_OUTPUT_DATA_SHIFT 0 |
| 786 | |
| 787 | #define MDIO_ADDR_OP(port, dev, reg) \ |
| 788 | ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \ |
| 789 | MIF_FRAME_OUTPUT_OP_ADDR | \ |
| 790 | (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \ |
| 791 | (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \ |
| 792 | (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \ |
| 793 | (reg << MIF_FRAME_OUTPUT_DATA_SHIFT)) |
| 794 | |
| 795 | #define MDIO_READ_OP(port, dev) \ |
| 796 | ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \ |
| 797 | MIF_FRAME_OUTPUT_OP_READ | \ |
| 798 | (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \ |
| 799 | (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \ |
| 800 | (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT)) |
| 801 | |
| 802 | #define MDIO_WRITE_OP(port, dev, data) \ |
| 803 | ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \ |
| 804 | MIF_FRAME_OUTPUT_OP_WRITE | \ |
| 805 | (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \ |
| 806 | (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \ |
| 807 | (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \ |
| 808 | (data << MIF_FRAME_OUTPUT_DATA_SHIFT)) |
| 809 | |
| 810 | #define MII_READ_OP(port, reg) \ |
| 811 | ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \ |
| 812 | (2 << MIF_FRAME_OUTPUT_OP_SHIFT) | \ |
| 813 | (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \ |
| 814 | (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \ |
| 815 | (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT)) |
| 816 | |
| 817 | #define MII_WRITE_OP(port, reg, data) \ |
| 818 | ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \ |
| 819 | (1 << MIF_FRAME_OUTPUT_OP_SHIFT) | \ |
| 820 | (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \ |
| 821 | (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \ |
| 822 | (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \ |
| 823 | (data << MIF_FRAME_OUTPUT_DATA_SHIFT)) |
| 824 | |
| 825 | #define MIF_CONFIG (FZC_MAC + 0x16020UL) |
| 826 | #define MIF_CONFIG_ATCA_GE 0x0000000000010000ULL |
| 827 | #define MIF_CONFIG_INDIRECT_MODE 0x0000000000008000ULL |
| 828 | #define MIF_CONFIG_POLL_PRT_PHYADDR 0x0000000000003c00ULL |
| 829 | #define MIF_CONFIG_POLL_DEV_REG_ADDR 0x00000000000003e0ULL |
| 830 | #define MIF_CONFIG_BB_MODE 0x0000000000000010ULL |
| 831 | #define MIF_CONFIG_POLL_EN 0x0000000000000008ULL |
| 832 | #define MIF_CONFIG_BB_SER_SEL 0x0000000000000006ULL |
| 833 | #define MIF_CONFIG_MANUAL_MODE 0x0000000000000001ULL |
| 834 | |
| 835 | #define MIF_POLL_STATUS (FZC_MAC + 0x16028UL) |
| 836 | #define MIF_POLL_STATUS_DATA 0x00000000ffff0000ULL |
| 837 | #define MIF_POLL_STATUS_STAT 0x000000000000ffffULL |
| 838 | |
| 839 | #define MIF_POLL_MASK (FZC_MAC + 0x16030UL) |
| 840 | #define MIF_POLL_MASK_VAL 0x000000000000ffffULL |
| 841 | |
| 842 | #define MIF_SM (FZC_MAC + 0x16038UL) |
| 843 | #define MIF_SM_PORT_ADDR 0x00000000001f0000ULL |
| 844 | #define MIF_SM_MDI_1 0x0000000000004000ULL |
| 845 | #define MIF_SM_MDI_0 0x0000000000002400ULL |
| 846 | #define MIF_SM_MDCLK 0x0000000000001000ULL |
| 847 | #define MIF_SM_MDO_EN 0x0000000000000800ULL |
| 848 | #define MIF_SM_MDO 0x0000000000000400ULL |
| 849 | #define MIF_SM_MDI 0x0000000000000200ULL |
| 850 | #define MIF_SM_CTL 0x00000000000001c0ULL |
| 851 | #define MIF_SM_EX 0x000000000000003fULL |
| 852 | |
| 853 | #define MIF_STATUS (FZC_MAC + 0x16040UL) |
| 854 | #define MIF_STATUS_MDINT1 0x0000000000000020ULL |
| 855 | #define MIF_STATUS_MDINT0 0x0000000000000010ULL |
| 856 | |
| 857 | #define MIF_MASK (FZC_MAC + 0x16048UL) |
| 858 | #define MIF_MASK_MDINT1 0x0000000000000020ULL |
| 859 | #define MIF_MASK_MDINT0 0x0000000000000010ULL |
| 860 | #define MIF_MASK_PEU_ERR 0x0000000000000008ULL |
| 861 | #define MIF_MASK_YC 0x0000000000000004ULL |
| 862 | #define MIF_MASK_XGE_ERR0 0x0000000000000002ULL |
| 863 | #define MIF_MASK_MIF_INIT_DONE 0x0000000000000001ULL |
| 864 | |
| 865 | #define ENET_SERDES_RESET (FZC_MAC + 0x14000UL) |
| 866 | #define ENET_SERDES_RESET_1 0x0000000000000002ULL |
| 867 | #define ENET_SERDES_RESET_0 0x0000000000000001ULL |
| 868 | |
| 869 | #define ENET_SERDES_CFG (FZC_MAC + 0x14008UL) |
| 870 | #define ENET_SERDES_BE_LOOPBACK 0x0000000000000002ULL |
| 871 | #define ENET_SERDES_CFG_FORCE_RDY 0x0000000000000001ULL |
| 872 | |
| 873 | #define ENET_SERDES_0_PLL_CFG (FZC_MAC + 0x14010UL) |
| 874 | #define ENET_SERDES_PLL_FBDIV0 0x0000000000000001ULL |
| 875 | #define ENET_SERDES_PLL_FBDIV1 0x0000000000000002ULL |
| 876 | #define ENET_SERDES_PLL_FBDIV2 0x0000000000000004ULL |
| 877 | #define ENET_SERDES_PLL_HRATE0 0x0000000000000008ULL |
| 878 | #define ENET_SERDES_PLL_HRATE1 0x0000000000000010ULL |
| 879 | #define ENET_SERDES_PLL_HRATE2 0x0000000000000020ULL |
| 880 | #define ENET_SERDES_PLL_HRATE3 0x0000000000000040ULL |
| 881 | |
| 882 | #define ENET_SERDES_0_CTRL_CFG (FZC_MAC + 0x14018UL) |
| 883 | #define ENET_SERDES_CTRL_SDET_0 0x0000000000000001ULL |
| 884 | #define ENET_SERDES_CTRL_SDET_1 0x0000000000000002ULL |
| 885 | #define ENET_SERDES_CTRL_SDET_2 0x0000000000000004ULL |
| 886 | #define ENET_SERDES_CTRL_SDET_3 0x0000000000000008ULL |
| 887 | #define ENET_SERDES_CTRL_EMPH_0 0x0000000000000070ULL |
| 888 | #define ENET_SERDES_CTRL_EMPH_0_SHIFT 4 |
| 889 | #define ENET_SERDES_CTRL_EMPH_1 0x0000000000000380ULL |
| 890 | #define ENET_SERDES_CTRL_EMPH_1_SHIFT 7 |
| 891 | #define ENET_SERDES_CTRL_EMPH_2 0x0000000000001c00ULL |
| 892 | #define ENET_SERDES_CTRL_EMPH_2_SHIFT 10 |
| 893 | #define ENET_SERDES_CTRL_EMPH_3 0x000000000000e000ULL |
| 894 | #define ENET_SERDES_CTRL_EMPH_3_SHIFT 13 |
| 895 | #define ENET_SERDES_CTRL_LADJ_0 0x0000000000070000ULL |
| 896 | #define ENET_SERDES_CTRL_LADJ_0_SHIFT 16 |
| 897 | #define ENET_SERDES_CTRL_LADJ_1 0x0000000000380000ULL |
| 898 | #define ENET_SERDES_CTRL_LADJ_1_SHIFT 19 |
| 899 | #define ENET_SERDES_CTRL_LADJ_2 0x0000000001c00000ULL |
| 900 | #define ENET_SERDES_CTRL_LADJ_2_SHIFT 22 |
| 901 | #define ENET_SERDES_CTRL_LADJ_3 0x000000000e000000ULL |
| 902 | #define ENET_SERDES_CTRL_LADJ_3_SHIFT 25 |
| 903 | #define ENET_SERDES_CTRL_RXITERM_0 0x0000000010000000ULL |
| 904 | #define ENET_SERDES_CTRL_RXITERM_1 0x0000000020000000ULL |
| 905 | #define ENET_SERDES_CTRL_RXITERM_2 0x0000000040000000ULL |
| 906 | #define ENET_SERDES_CTRL_RXITERM_3 0x0000000080000000ULL |
| 907 | |
| 908 | #define ENET_SERDES_0_TEST_CFG (FZC_MAC + 0x14020UL) |
| 909 | #define ENET_SERDES_TEST_MD_0 0x0000000000000003ULL |
| 910 | #define ENET_SERDES_TEST_MD_0_SHIFT 0 |
| 911 | #define ENET_SERDES_TEST_MD_1 0x000000000000000cULL |
| 912 | #define ENET_SERDES_TEST_MD_1_SHIFT 2 |
| 913 | #define ENET_SERDES_TEST_MD_2 0x0000000000000030ULL |
| 914 | #define ENET_SERDES_TEST_MD_2_SHIFT 4 |
| 915 | #define ENET_SERDES_TEST_MD_3 0x00000000000000c0ULL |
| 916 | #define ENET_SERDES_TEST_MD_3_SHIFT 6 |
| 917 | |
| 918 | #define ENET_TEST_MD_NO_LOOPBACK 0x0 |
| 919 | #define ENET_TEST_MD_EWRAP 0x1 |
| 920 | #define ENET_TEST_MD_PAD_LOOPBACK 0x2 |
| 921 | #define ENET_TEST_MD_REV_LOOPBACK 0x3 |
| 922 | |
| 923 | #define ENET_SERDES_1_PLL_CFG (FZC_MAC + 0x14028UL) |
| 924 | #define ENET_SERDES_1_CTRL_CFG (FZC_MAC + 0x14030UL) |
| 925 | #define ENET_SERDES_1_TEST_CFG (FZC_MAC + 0x14038UL) |
| 926 | |
| 927 | #define ENET_RGMII_CFG_REG (FZC_MAC + 0x14040UL) |
| 928 | |
| 929 | #define ESR_INT_SIGNALS (FZC_MAC + 0x14800UL) |
| 930 | #define ESR_INT_SIGNALS_ALL 0x00000000ffffffffULL |
| 931 | #define ESR_INT_SIGNALS_P0_BITS 0x0000000033e0000fULL |
| 932 | #define ESR_INT_SIGNALS_P1_BITS 0x000000000c1f00f0ULL |
| 933 | #define ESR_INT_SRDY0_P0 0x0000000020000000ULL |
| 934 | #define ESR_INT_DET0_P0 0x0000000010000000ULL |
| 935 | #define ESR_INT_SRDY0_P1 0x0000000008000000ULL |
| 936 | #define ESR_INT_DET0_P1 0x0000000004000000ULL |
| 937 | #define ESR_INT_XSRDY_P0 0x0000000002000000ULL |
| 938 | #define ESR_INT_XDP_P0_CH3 0x0000000001000000ULL |
| 939 | #define ESR_INT_XDP_P0_CH2 0x0000000000800000ULL |
| 940 | #define ESR_INT_XDP_P0_CH1 0x0000000000400000ULL |
| 941 | #define ESR_INT_XDP_P0_CH0 0x0000000000200000ULL |
| 942 | #define ESR_INT_XSRDY_P1 0x0000000000100000ULL |
| 943 | #define ESR_INT_XDP_P1_CH3 0x0000000000080000ULL |
| 944 | #define ESR_INT_XDP_P1_CH2 0x0000000000040000ULL |
| 945 | #define ESR_INT_XDP_P1_CH1 0x0000000000020000ULL |
| 946 | #define ESR_INT_XDP_P1_CH0 0x0000000000010000ULL |
| 947 | #define ESR_INT_SLOSS_P1_CH3 0x0000000000000080ULL |
| 948 | #define ESR_INT_SLOSS_P1_CH2 0x0000000000000040ULL |
| 949 | #define ESR_INT_SLOSS_P1_CH1 0x0000000000000020ULL |
| 950 | #define ESR_INT_SLOSS_P1_CH0 0x0000000000000010ULL |
| 951 | #define ESR_INT_SLOSS_P0_CH3 0x0000000000000008ULL |
| 952 | #define ESR_INT_SLOSS_P0_CH2 0x0000000000000004ULL |
| 953 | #define ESR_INT_SLOSS_P0_CH1 0x0000000000000002ULL |
| 954 | #define ESR_INT_SLOSS_P0_CH0 0x0000000000000001ULL |
| 955 | |
| 956 | #define ESR_DEBUG_SEL (FZC_MAC + 0x14808UL) |
| 957 | #define ESR_DEBUG_SEL_VAL 0x000000000000003fULL |
| 958 | |
| 959 | /* SerDes registers behind MIF */ |
| 960 | #define NIU_ESR_DEV_ADDR 0x1e |
| 961 | #define ESR_BASE 0x0000 |
| 962 | |
| 963 | #define ESR_RXTX_COMM_CTRL_L (ESR_BASE + 0x0000) |
| 964 | #define ESR_RXTX_COMM_CTRL_H (ESR_BASE + 0x0001) |
| 965 | |
| 966 | #define ESR_RXTX_RESET_CTRL_L (ESR_BASE + 0x0002) |
| 967 | #define ESR_RXTX_RESET_CTRL_H (ESR_BASE + 0x0003) |
| 968 | |
| 969 | #define ESR_RX_POWER_CTRL_L (ESR_BASE + 0x0004) |
| 970 | #define ESR_RX_POWER_CTRL_H (ESR_BASE + 0x0005) |
| 971 | |
| 972 | #define ESR_TX_POWER_CTRL_L (ESR_BASE + 0x0006) |
| 973 | #define ESR_TX_POWER_CTRL_H (ESR_BASE + 0x0007) |
| 974 | |
| 975 | #define ESR_MISC_POWER_CTRL_L (ESR_BASE + 0x0008) |
| 976 | #define ESR_MISC_POWER_CTRL_H (ESR_BASE + 0x0009) |
| 977 | |
| 978 | #define ESR_RXTX_CTRL_L(CHAN) (ESR_BASE + 0x0080 + (CHAN) * 0x10) |
| 979 | #define ESR_RXTX_CTRL_H(CHAN) (ESR_BASE + 0x0081 + (CHAN) * 0x10) |
| 980 | #define ESR_RXTX_CTRL_BIASCNTL 0x80000000 |
| 981 | #define ESR_RXTX_CTRL_RESV1 0x7c000000 |
| 982 | #define ESR_RXTX_CTRL_TDENFIFO 0x02000000 |
| 983 | #define ESR_RXTX_CTRL_TDWS20 0x01000000 |
| 984 | #define ESR_RXTX_CTRL_VMUXLO 0x00c00000 |
| 985 | #define ESR_RXTX_CTRL_VMUXLO_SHIFT 22 |
| 986 | #define ESR_RXTX_CTRL_VPULSELO 0x00300000 |
| 987 | #define ESR_RXTX_CTRL_VPULSELO_SHIFT 20 |
| 988 | #define ESR_RXTX_CTRL_RESV2 0x000f0000 |
| 989 | #define ESR_RXTX_CTRL_RESV3 0x0000c000 |
| 990 | #define ESR_RXTX_CTRL_RXPRESWIN 0x00003000 |
| 991 | #define ESR_RXTX_CTRL_RXPRESWIN_SHIFT 12 |
| 992 | #define ESR_RXTX_CTRL_RESV4 0x00000800 |
| 993 | #define ESR_RXTX_CTRL_RISEFALL 0x00000700 |
| 994 | #define ESR_RXTX_CTRL_RISEFALL_SHIFT 8 |
| 995 | #define ESR_RXTX_CTRL_RESV5 0x000000fe |
| 996 | #define ESR_RXTX_CTRL_ENSTRETCH 0x00000001 |
| 997 | |
| 998 | #define ESR_RXTX_TUNING_L(CHAN) (ESR_BASE + 0x0082 + (CHAN) * 0x10) |
| 999 | #define ESR_RXTX_TUNING_H(CHAN) (ESR_BASE + 0x0083 + (CHAN) * 0x10) |
| 1000 | |
| 1001 | #define ESR_RX_SYNCCHAR_L(CHAN) (ESR_BASE + 0x0084 + (CHAN) * 0x10) |
| 1002 | #define ESR_RX_SYNCCHAR_H(CHAN) (ESR_BASE + 0x0085 + (CHAN) * 0x10) |
| 1003 | |
| 1004 | #define ESR_RXTX_TEST_L(CHAN) (ESR_BASE + 0x0086 + (CHAN) * 0x10) |
| 1005 | #define ESR_RXTX_TEST_H(CHAN) (ESR_BASE + 0x0087 + (CHAN) * 0x10) |
| 1006 | |
| 1007 | #define ESR_GLUE_CTRL0_L(CHAN) (ESR_BASE + 0x0088 + (CHAN) * 0x10) |
| 1008 | #define ESR_GLUE_CTRL0_H(CHAN) (ESR_BASE + 0x0089 + (CHAN) * 0x10) |
| 1009 | #define ESR_GLUE_CTRL0_RESV1 0xf8000000 |
| 1010 | #define ESR_GLUE_CTRL0_BLTIME 0x07000000 |
| 1011 | #define ESR_GLUE_CTRL0_BLTIME_SHIFT 24 |
| 1012 | #define ESR_GLUE_CTRL0_RESV2 0x00ff0000 |
| 1013 | #define ESR_GLUE_CTRL0_RXLOS_TEST 0x00008000 |
| 1014 | #define ESR_GLUE_CTRL0_RESV3 0x00004000 |
| 1015 | #define ESR_GLUE_CTRL0_RXLOSENAB 0x00002000 |
| 1016 | #define ESR_GLUE_CTRL0_FASTRESYNC 0x00001000 |
| 1017 | #define ESR_GLUE_CTRL0_SRATE 0x00000f00 |
| 1018 | #define ESR_GLUE_CTRL0_SRATE_SHIFT 8 |
| 1019 | #define ESR_GLUE_CTRL0_THCNT 0x000000ff |
| 1020 | #define ESR_GLUE_CTRL0_THCNT_SHIFT 0 |
| 1021 | |
| 1022 | #define BLTIME_64_CYCLES 0 |
| 1023 | #define BLTIME_128_CYCLES 1 |
| 1024 | #define BLTIME_256_CYCLES 2 |
| 1025 | #define BLTIME_300_CYCLES 3 |
| 1026 | #define BLTIME_384_CYCLES 4 |
| 1027 | #define BLTIME_512_CYCLES 5 |
| 1028 | #define BLTIME_1024_CYCLES 6 |
| 1029 | #define BLTIME_2048_CYCLES 7 |
| 1030 | |
| 1031 | #define ESR_GLUE_CTRL1_L(CHAN) (ESR_BASE + 0x008a + (CHAN) * 0x10) |
| 1032 | #define ESR_GLUE_CTRL1_H(CHAN) (ESR_BASE + 0x008b + (CHAN) * 0x10) |
| 1033 | #define ESR_RXTX_TUNING1_L(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10) |
| 1034 | #define ESR_RXTX_TUNING1_H(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10) |
| 1035 | #define ESR_RXTX_TUNING2_L(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10) |
| 1036 | #define ESR_RXTX_TUNING2_H(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10) |
| 1037 | #define ESR_RXTX_TUNING3_L(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10) |
| 1038 | #define ESR_RXTX_TUNING3_H(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10) |
| 1039 | |
| 1040 | #define NIU_ESR2_DEV_ADDR 0x1e |
| 1041 | #define ESR2_BASE 0x8000 |
| 1042 | |
| 1043 | #define ESR2_TI_PLL_CFG_L (ESR2_BASE + 0x000) |
| 1044 | #define ESR2_TI_PLL_CFG_H (ESR2_BASE + 0x001) |
| 1045 | #define PLL_CFG_STD 0x00000c00 |
| 1046 | #define PLL_CFG_STD_SHIFT 10 |
| 1047 | #define PLL_CFG_LD 0x00000300 |
| 1048 | #define PLL_CFG_LD_SHIFT 8 |
| 1049 | #define PLL_CFG_MPY 0x0000001e |
| 1050 | #define PLL_CFG_MPY_SHIFT 1 |
| 1051 | #define PLL_CFG_MPY_4X 0x0 |
| 1052 | #define PLL_CFG_MPY_5X 0x00000002 |
| 1053 | #define PLL_CFG_MPY_6X 0x00000004 |
| 1054 | #define PLL_CFG_MPY_8X 0x00000008 |
| 1055 | #define PLL_CFG_MPY_10X 0x0000000a |
| 1056 | #define PLL_CFG_MPY_12X 0x0000000c |
| 1057 | #define PLL_CFG_MPY_12P5X 0x0000000e |
| 1058 | #define PLL_CFG_ENPLL 0x00000001 |
| 1059 | |
| 1060 | #define ESR2_TI_PLL_STS_L (ESR2_BASE + 0x002) |
| 1061 | #define ESR2_TI_PLL_STS_H (ESR2_BASE + 0x003) |
| 1062 | #define PLL_STS_LOCK 0x00000001 |
| 1063 | |
| 1064 | #define ESR2_TI_PLL_TEST_CFG_L (ESR2_BASE + 0x004) |
| 1065 | #define ESR2_TI_PLL_TEST_CFG_H (ESR2_BASE + 0x005) |
| 1066 | #define PLL_TEST_INVPATT 0x00004000 |
| 1067 | #define PLL_TEST_RATE 0x00003000 |
| 1068 | #define PLL_TEST_RATE_SHIFT 12 |
| 1069 | #define PLL_TEST_CFG_ENBSAC 0x00000400 |
| 1070 | #define PLL_TEST_CFG_ENBSRX 0x00000200 |
| 1071 | #define PLL_TEST_CFG_ENBSTX 0x00000100 |
| 1072 | #define PLL_TEST_CFG_LOOPBACK_PAD 0x00000040 |
| 1073 | #define PLL_TEST_CFG_LOOPBACK_CML_DIS 0x00000080 |
| 1074 | #define PLL_TEST_CFG_LOOPBACK_CML_EN 0x000000c0 |
| 1075 | #define PLL_TEST_CFG_CLKBYP 0x00000030 |
| 1076 | #define PLL_TEST_CFG_CLKBYP_SHIFT 4 |
| 1077 | #define PLL_TEST_CFG_EN_RXPATT 0x00000008 |
| 1078 | #define PLL_TEST_CFG_EN_TXPATT 0x00000004 |
| 1079 | #define PLL_TEST_CFG_TPATT 0x00000003 |
| 1080 | #define PLL_TEST_CFG_TPATT_SHIFT 0 |
| 1081 | |
| 1082 | #define ESR2_TI_PLL_TX_CFG_L(CHAN) (ESR2_BASE + 0x100 + (CHAN) * 4) |
| 1083 | #define ESR2_TI_PLL_TX_CFG_H(CHAN) (ESR2_BASE + 0x101 + (CHAN) * 4) |
| 1084 | #define PLL_TX_CFG_RDTCT 0x00600000 |
| 1085 | #define PLL_TX_CFG_RDTCT_SHIFT 21 |
| 1086 | #define PLL_TX_CFG_ENIDL 0x00100000 |
| 1087 | #define PLL_TX_CFG_BSTX 0x00020000 |
| 1088 | #define PLL_TX_CFG_ENFTP 0x00010000 |
| 1089 | #define PLL_TX_CFG_DE 0x0000f000 |
| 1090 | #define PLL_TX_CFG_DE_SHIFT 12 |
| 1091 | #define PLL_TX_CFG_SWING_125MV 0x00000000 |
| 1092 | #define PLL_TX_CFG_SWING_250MV 0x00000200 |
| 1093 | #define PLL_TX_CFG_SWING_500MV 0x00000400 |
| 1094 | #define PLL_TX_CFG_SWING_625MV 0x00000600 |
| 1095 | #define PLL_TX_CFG_SWING_750MV 0x00000800 |
| 1096 | #define PLL_TX_CFG_SWING_1000MV 0x00000a00 |
| 1097 | #define PLL_TX_CFG_SWING_1250MV 0x00000c00 |
| 1098 | #define PLL_TX_CFG_SWING_1375MV 0x00000e00 |
| 1099 | #define PLL_TX_CFG_CM 0x00000100 |
| 1100 | #define PLL_TX_CFG_INVPAIR 0x00000080 |
| 1101 | #define PLL_TX_CFG_RATE 0x00000060 |
| 1102 | #define PLL_TX_CFG_RATE_SHIFT 5 |
| 1103 | #define PLL_TX_CFG_RATE_FULL 0x0 |
| 1104 | #define PLL_TX_CFG_RATE_HALF 0x20 |
| 1105 | #define PLL_TX_CFG_RATE_QUAD 0x40 |
| 1106 | #define PLL_TX_CFG_BUSWIDTH 0x0000001c |
| 1107 | #define PLL_TX_CFG_BUSWIDTH_SHIFT 2 |
| 1108 | #define PLL_TX_CFG_ENTEST 0x00000002 |
| 1109 | #define PLL_TX_CFG_ENTX 0x00000001 |
| 1110 | |
| 1111 | #define ESR2_TI_PLL_TX_STS_L(CHAN) (ESR2_BASE + 0x102 + (CHAN) * 4) |
| 1112 | #define ESR2_TI_PLL_TX_STS_H(CHAN) (ESR2_BASE + 0x103 + (CHAN) * 4) |
| 1113 | #define PLL_TX_STS_RDTCTIP 0x00000002 |
| 1114 | #define PLL_TX_STS_TESTFAIL 0x00000001 |
| 1115 | |
| 1116 | #define ESR2_TI_PLL_RX_CFG_L(CHAN) (ESR2_BASE + 0x120 + (CHAN) * 4) |
| 1117 | #define ESR2_TI_PLL_RX_CFG_H(CHAN) (ESR2_BASE + 0x121 + (CHAN) * 4) |
| 1118 | #define PLL_RX_CFG_BSINRXN 0x02000000 |
| 1119 | #define PLL_RX_CFG_BSINRXP 0x01000000 |
| 1120 | #define PLL_RX_CFG_EQ_MAX_LF 0x00000000 |
| 1121 | #define PLL_RX_CFG_EQ_LP_ADAPTIVE 0x00080000 |
| 1122 | #define PLL_RX_CFG_EQ_LP_1084MHZ 0x00400000 |
| 1123 | #define PLL_RX_CFG_EQ_LP_805MHZ 0x00480000 |
| 1124 | #define PLL_RX_CFG_EQ_LP_573MHZ 0x00500000 |
| 1125 | #define PLL_RX_CFG_EQ_LP_402MHZ 0x00580000 |
| 1126 | #define PLL_RX_CFG_EQ_LP_304MHZ 0x00600000 |
| 1127 | #define PLL_RX_CFG_EQ_LP_216MHZ 0x00680000 |
| 1128 | #define PLL_RX_CFG_EQ_LP_156MHZ 0x00700000 |
| 1129 | #define PLL_RX_CFG_EQ_LP_135MHZ 0x00780000 |
| 1130 | #define PLL_RX_CFG_EQ_SHIFT 19 |
| 1131 | #define PLL_RX_CFG_CDR 0x00070000 |
| 1132 | #define PLL_RX_CFG_CDR_SHIFT 16 |
| 1133 | #define PLL_RX_CFG_LOS_DIS 0x00000000 |
| 1134 | #define PLL_RX_CFG_LOS_HTHRESH 0x00004000 |
| 1135 | #define PLL_RX_CFG_LOS_LTHRESH 0x00008000 |
| 1136 | #define PLL_RX_CFG_ALIGN_DIS 0x00000000 |
| 1137 | #define PLL_RX_CFG_ALIGN_ENA 0x00001000 |
| 1138 | #define PLL_RX_CFG_ALIGN_JOG 0x00002000 |
| 1139 | #define PLL_RX_CFG_TERM_VDDT 0x00000000 |
| 1140 | #define PLL_RX_CFG_TERM_0P8VDDT 0x00000100 |
| 1141 | #define PLL_RX_CFG_TERM_FLOAT 0x00000300 |
| 1142 | #define PLL_RX_CFG_INVPAIR 0x00000080 |
| 1143 | #define PLL_RX_CFG_RATE 0x00000060 |
| 1144 | #define PLL_RX_CFG_RATE_SHIFT 5 |
| 1145 | #define PLL_RX_CFG_RATE_FULL 0x0 |
| 1146 | #define PLL_RX_CFG_RATE_HALF 0x20 |
| 1147 | #define PLL_RX_CFG_RATE_QUAD 0x40 |
| 1148 | #define PLL_RX_CFG_BUSWIDTH 0x0000001c |
| 1149 | #define PLL_RX_CFG_BUSWIDTH_SHIFT 2 |
| 1150 | #define PLL_RX_CFG_ENTEST 0x00000002 |
| 1151 | #define PLL_RX_CFG_ENRX 0x00000001 |
| 1152 | |
| 1153 | #define ESR2_TI_PLL_RX_STS_L(CHAN) (ESR2_BASE + 0x122 + (CHAN) * 4) |
| 1154 | #define ESR2_TI_PLL_RX_STS_H(CHAN) (ESR2_BASE + 0x123 + (CHAN) * 4) |
| 1155 | #define PLL_RX_STS_CRCIDTCT 0x00000200 |
| 1156 | #define PLL_RX_STS_CWDTCT 0x00000100 |
| 1157 | #define PLL_RX_STS_BSRXN 0x00000020 |
| 1158 | #define PLL_RX_STS_BSRXP 0x00000010 |
| 1159 | #define PLL_RX_STS_LOSDTCT 0x00000008 |
| 1160 | #define PLL_RX_STS_ODDCG 0x00000004 |
| 1161 | #define PLL_RX_STS_SYNC 0x00000002 |
| 1162 | #define PLL_RX_STS_TESTFAIL 0x00000001 |
| 1163 | |
| 1164 | #define ENET_VLAN_TBL(IDX) (FZC_FFLP + 0x00000UL + (IDX) * 8UL) |
| 1165 | #define ENET_VLAN_TBL_PARITY1 0x0000000000020000ULL |
| 1166 | #define ENET_VLAN_TBL_PARITY0 0x0000000000010000ULL |
| 1167 | #define ENET_VLAN_TBL_VPR 0x0000000000000008ULL |
| 1168 | #define ENET_VLAN_TBL_VLANRDCTBLN 0x0000000000000007ULL |
| 1169 | #define ENET_VLAN_TBL_SHIFT(PORT) ((PORT) * 4) |
| 1170 | |
| 1171 | #define ENET_VLAN_TBL_NUM_ENTRIES 4096 |
| 1172 | |
| 1173 | #define FFLP_VLAN_PAR_ERR (FZC_FFLP + 0x0800UL) |
| 1174 | #define FFLP_VLAN_PAR_ERR_ERR 0x0000000080000000ULL |
| 1175 | #define FFLP_VLAN_PAR_ERR_M_ERR 0x0000000040000000ULL |
| 1176 | #define FFLP_VLAN_PAR_ERR_ADDR 0x000000003ffc0000ULL |
| 1177 | #define FFLP_VLAN_PAR_ERR_DATA 0x000000000003ffffULL |
| 1178 | |
| 1179 | #define L2_CLS(IDX) (FZC_FFLP + 0x20000UL + (IDX) * 8UL) |
| 1180 | #define L2_CLS_VLD 0x0000000000010000ULL |
| 1181 | #define L2_CLS_ETYPE 0x000000000000ffffULL |
| 1182 | #define L2_CLS_ETYPE_SHIFT 0 |
| 1183 | |
| 1184 | #define L3_CLS(IDX) (FZC_FFLP + 0x20010UL + (IDX) * 8UL) |
| 1185 | #define L3_CLS_VALID 0x0000000002000000ULL |
| 1186 | #define L3_CLS_IPVER 0x0000000001000000ULL |
| 1187 | #define L3_CLS_PID 0x0000000000ff0000ULL |
| 1188 | #define L3_CLS_PID_SHIFT 16 |
| 1189 | #define L3_CLS_TOSMASK 0x000000000000ff00ULL |
| 1190 | #define L3_CLS_TOSMASK_SHIFT 8 |
| 1191 | #define L3_CLS_TOS 0x00000000000000ffULL |
| 1192 | #define L3_CLS_TOS_SHIFT 0 |
| 1193 | |
| 1194 | #define TCAM_KEY(IDX) (FZC_FFLP + 0x20030UL + (IDX) * 8UL) |
| 1195 | #define TCAM_KEY_DISC 0x0000000000000008ULL |
| 1196 | #define TCAM_KEY_TSEL 0x0000000000000004ULL |
| 1197 | #define TCAM_KEY_IPADDR 0x0000000000000001ULL |
| 1198 | |
| 1199 | #define TCAM_KEY_0 (FZC_FFLP + 0x20090UL) |
| 1200 | #define TCAM_KEY_0_KEY 0x00000000000000ffULL /* bits 192-199 */ |
| 1201 | |
| 1202 | #define TCAM_KEY_1 (FZC_FFLP + 0x20098UL) |
| 1203 | #define TCAM_KEY_1_KEY 0xffffffffffffffffULL /* bits 128-191 */ |
| 1204 | |
| 1205 | #define TCAM_KEY_2 (FZC_FFLP + 0x200a0UL) |
| 1206 | #define TCAM_KEY_2_KEY 0xffffffffffffffffULL /* bits 64-127 */ |
| 1207 | |
| 1208 | #define TCAM_KEY_3 (FZC_FFLP + 0x200a8UL) |
| 1209 | #define TCAM_KEY_3_KEY 0xffffffffffffffffULL /* bits 0-63 */ |
| 1210 | |
| 1211 | #define TCAM_KEY_MASK_0 (FZC_FFLP + 0x200b0UL) |
| 1212 | #define TCAM_KEY_MASK_0_KEY_SEL 0x00000000000000ffULL /* bits 192-199 */ |
| 1213 | |
| 1214 | #define TCAM_KEY_MASK_1 (FZC_FFLP + 0x200b8UL) |
| 1215 | #define TCAM_KEY_MASK_1_KEY_SEL 0xffffffffffffffffULL /* bits 128-191 */ |
| 1216 | |
| 1217 | #define TCAM_KEY_MASK_2 (FZC_FFLP + 0x200c0UL) |
| 1218 | #define TCAM_KEY_MASK_2_KEY_SEL 0xffffffffffffffffULL /* bits 64-127 */ |
| 1219 | |
| 1220 | #define TCAM_KEY_MASK_3 (FZC_FFLP + 0x200c8UL) |
| 1221 | #define TCAM_KEY_MASK_3_KEY_SEL 0xffffffffffffffffULL /* bits 0-63 */ |
| 1222 | |
| 1223 | #define TCAM_CTL (FZC_FFLP + 0x200d0UL) |
| 1224 | #define TCAM_CTL_RWC 0x00000000001c0000ULL |
| 1225 | #define TCAM_CTL_RWC_TCAM_WRITE 0x0000000000000000ULL |
| 1226 | #define TCAM_CTL_RWC_TCAM_READ 0x0000000000040000ULL |
| 1227 | #define TCAM_CTL_RWC_TCAM_COMPARE 0x0000000000080000ULL |
| 1228 | #define TCAM_CTL_RWC_RAM_WRITE 0x0000000000100000ULL |
| 1229 | #define TCAM_CTL_RWC_RAM_READ 0x0000000000140000ULL |
| 1230 | #define TCAM_CTL_STAT 0x0000000000020000ULL |
| 1231 | #define TCAM_CTL_MATCH 0x0000000000010000ULL |
| 1232 | #define TCAM_CTL_LOC 0x00000000000003ffULL |
| 1233 | |
| 1234 | #define TCAM_ERR (FZC_FFLP + 0x200d8UL) |
| 1235 | #define TCAM_ERR_ERR 0x0000000080000000ULL |
| 1236 | #define TCAM_ERR_P_ECC 0x0000000040000000ULL |
| 1237 | #define TCAM_ERR_MULT 0x0000000020000000ULL |
| 1238 | #define TCAM_ERR_ADDR 0x0000000000ff0000ULL |
| 1239 | #define TCAM_ERR_SYNDROME 0x000000000000ffffULL |
| 1240 | |
| 1241 | #define HASH_LOOKUP_ERR_LOG1 (FZC_FFLP + 0x200e0UL) |
| 1242 | #define HASH_LOOKUP_ERR_LOG1_ERR 0x0000000000000008ULL |
| 1243 | #define HASH_LOOKUP_ERR_LOG1_MULT_LK 0x0000000000000004ULL |
| 1244 | #define HASH_LOOKUP_ERR_LOG1_CU 0x0000000000000002ULL |
| 1245 | #define HASH_LOOKUP_ERR_LOG1_MULT_BIT 0x0000000000000001ULL |
| 1246 | |
| 1247 | #define HASH_LOOKUP_ERR_LOG2 (FZC_FFLP + 0x200e8UL) |
| 1248 | #define HASH_LOOKUP_ERR_LOG2_H1 0x000000007ffff800ULL |
| 1249 | #define HASH_LOOKUP_ERR_LOG2_SUBAREA 0x0000000000000700ULL |
| 1250 | #define HASH_LOOKUP_ERR_LOG2_SYNDROME 0x00000000000000ffULL |
| 1251 | |
| 1252 | #define FFLP_CFG_1 (FZC_FFLP + 0x20100UL) |
| 1253 | #define FFLP_CFG_1_TCAM_DIS 0x0000000004000000ULL |
| 1254 | #define FFLP_CFG_1_PIO_DBG_SEL 0x0000000003800000ULL |
| 1255 | #define FFLP_CFG_1_PIO_FIO_RST 0x0000000000400000ULL |
| 1256 | #define FFLP_CFG_1_PIO_FIO_LAT 0x0000000000300000ULL |
| 1257 | #define FFLP_CFG_1_CAMLAT 0x00000000000f0000ULL |
| 1258 | #define FFLP_CFG_1_CAMLAT_SHIFT 16 |
| 1259 | #define FFLP_CFG_1_CAMRATIO 0x000000000000f000ULL |
| 1260 | #define FFLP_CFG_1_CAMRATIO_SHIFT 12 |
| 1261 | #define FFLP_CFG_1_FCRAMRATIO 0x0000000000000f00ULL |
| 1262 | #define FFLP_CFG_1_FCRAMRATIO_SHIFT 8 |
| 1263 | #define FFLP_CFG_1_FCRAMOUTDR_MASK 0x00000000000000f0ULL |
| 1264 | #define FFLP_CFG_1_FCRAMOUTDR_NORMAL 0x0000000000000000ULL |
| 1265 | #define FFLP_CFG_1_FCRAMOUTDR_STRONG 0x0000000000000050ULL |
| 1266 | #define FFLP_CFG_1_FCRAMOUTDR_WEAK 0x00000000000000a0ULL |
| 1267 | #define FFLP_CFG_1_FCRAMQS 0x0000000000000008ULL |
| 1268 | #define FFLP_CFG_1_ERRORDIS 0x0000000000000004ULL |
| 1269 | #define FFLP_CFG_1_FFLPINITDONE 0x0000000000000002ULL |
| 1270 | #define FFLP_CFG_1_LLCSNAP 0x0000000000000001ULL |
| 1271 | |
| 1272 | #define DEFAULT_FCRAMRATIO 10 |
| 1273 | |
| 1274 | #define DEFAULT_TCAM_LATENCY 4 |
| 1275 | #define DEFAULT_TCAM_ACCESS_RATIO 10 |
| 1276 | |
| 1277 | #define TCP_CFLAG_MSK (FZC_FFLP + 0x20108UL) |
| 1278 | #define TCP_CFLAG_MSK_MASK 0x0000000000000fffULL |
| 1279 | |
| 1280 | #define FCRAM_REF_TMR (FZC_FFLP + 0x20110UL) |
| 1281 | #define FCRAM_REF_TMR_MAX 0x00000000ffff0000ULL |
| 1282 | #define FCRAM_REF_TMR_MAX_SHIFT 16 |
| 1283 | #define FCRAM_REF_TMR_MIN 0x000000000000ffffULL |
| 1284 | #define FCRAM_REF_TMR_MIN_SHIFT 0 |
| 1285 | |
| 1286 | #define DEFAULT_FCRAM_REFRESH_MAX 512 |
| 1287 | #define DEFAULT_FCRAM_REFRESH_MIN 512 |
| 1288 | |
| 1289 | #define FCRAM_FIO_ADDR (FZC_FFLP + 0x20118UL) |
| 1290 | #define FCRAM_FIO_ADDR_ADDR 0x00000000000000ffULL |
| 1291 | |
| 1292 | #define FCRAM_FIO_DAT (FZC_FFLP + 0x20120UL) |
| 1293 | #define FCRAM_FIO_DAT_DATA 0x000000000000ffffULL |
| 1294 | |
| 1295 | #define FCRAM_ERR_TST0 (FZC_FFLP + 0x20128UL) |
| 1296 | #define FCRAM_ERR_TST0_SYND 0x00000000000000ffULL |
| 1297 | |
| 1298 | #define FCRAM_ERR_TST1 (FZC_FFLP + 0x20130UL) |
| 1299 | #define FCRAM_ERR_TST1_DAT 0x00000000ffffffffULL |
| 1300 | |
| 1301 | #define FCRAM_ERR_TST2 (FZC_FFLP + 0x20138UL) |
| 1302 | #define FCRAM_ERR_TST2_DAT 0x00000000ffffffffULL |
| 1303 | |
| 1304 | #define FFLP_ERR_MASK (FZC_FFLP + 0x20140UL) |
| 1305 | #define FFLP_ERR_MASK_HSH_TBL_DAT 0x00000000000007f8ULL |
| 1306 | #define FFLP_ERR_MASK_HSH_TBL_LKUP 0x0000000000000004ULL |
| 1307 | #define FFLP_ERR_MASK_TCAM 0x0000000000000002ULL |
| 1308 | #define FFLP_ERR_MASK_VLAN 0x0000000000000001ULL |
| 1309 | |
| 1310 | #define FFLP_DBG_TRAIN_VCT (FZC_FFLP + 0x20148UL) |
| 1311 | #define FFLP_DBG_TRAIN_VCT_VECTOR 0x00000000ffffffffULL |
| 1312 | |
| 1313 | #define FCRAM_PHY_RD_LAT (FZC_FFLP + 0x20150UL) |
| 1314 | #define FCRAM_PHY_RD_LAT_LAT 0x00000000000000ffULL |
| 1315 | |
| 1316 | /* Ethernet TCAM format */ |
| 1317 | #define TCAM_ETHKEY0_RESV1 0xffffffffffffff00ULL |
| 1318 | #define TCAM_ETHKEY0_CLASS_CODE 0x00000000000000f8ULL |
| 1319 | #define TCAM_ETHKEY0_CLASS_CODE_SHIFT 3 |
| 1320 | #define TCAM_ETHKEY0_RESV2 0x0000000000000007ULL |
| 1321 | #define TCAM_ETHKEY1_FRAME_BYTE0_7(NUM) (0xff << ((7 - NUM) * 8)) |
| 1322 | #define TCAM_ETHKEY2_FRAME_BYTE8 0xff00000000000000ULL |
| 1323 | #define TCAM_ETHKEY2_FRAME_BYTE8_SHIFT 56 |
| 1324 | #define TCAM_ETHKEY2_FRAME_BYTE9 0x00ff000000000000ULL |
| 1325 | #define TCAM_ETHKEY2_FRAME_BYTE9_SHIFT 48 |
| 1326 | #define TCAM_ETHKEY2_FRAME_BYTE10 0x0000ff0000000000ULL |
| 1327 | #define TCAM_ETHKEY2_FRAME_BYTE10_SHIFT 40 |
| 1328 | #define TCAM_ETHKEY2_FRAME_RESV 0x000000ffffffffffULL |
| 1329 | #define TCAM_ETHKEY3_FRAME_RESV 0xffffffffffffffffULL |
| 1330 | |
| 1331 | /* IPV4 TCAM format */ |
| 1332 | #define TCAM_V4KEY0_RESV1 0xffffffffffffff00ULL |
| 1333 | #define TCAM_V4KEY0_CLASS_CODE 0x00000000000000f8ULL |
| 1334 | #define TCAM_V4KEY0_CLASS_CODE_SHIFT 3 |
| 1335 | #define TCAM_V4KEY0_RESV2 0x0000000000000007ULL |
| 1336 | #define TCAM_V4KEY1_L2RDCNUM 0xf800000000000000ULL |
| 1337 | #define TCAM_V4KEY1_L2RDCNUM_SHIFT 59 |
| 1338 | #define TCAM_V4KEY1_NOPORT 0x0400000000000000ULL |
| 1339 | #define TCAM_V4KEY1_RESV 0x03ffffffffffffffULL |
| 1340 | #define TCAM_V4KEY2_RESV 0xffff000000000000ULL |
| 1341 | #define TCAM_V4KEY2_TOS 0x0000ff0000000000ULL |
| 1342 | #define TCAM_V4KEY2_TOS_SHIFT 40 |
| 1343 | #define TCAM_V4KEY2_PROTO 0x000000ff00000000ULL |
| 1344 | #define TCAM_V4KEY2_PROTO_SHIFT 32 |
| 1345 | #define TCAM_V4KEY2_PORT_SPI 0x00000000ffffffffULL |
| 1346 | #define TCAM_V4KEY2_PORT_SPI_SHIFT 0 |
| 1347 | #define TCAM_V4KEY3_SADDR 0xffffffff00000000ULL |
| 1348 | #define TCAM_V4KEY3_SADDR_SHIFT 32 |
| 1349 | #define TCAM_V4KEY3_DADDR 0x00000000ffffffffULL |
| 1350 | #define TCAM_V4KEY3_DADDR_SHIFT 0 |
| 1351 | |
| 1352 | /* IPV6 TCAM format */ |
| 1353 | #define TCAM_V6KEY0_RESV1 0xffffffffffffff00ULL |
| 1354 | #define TCAM_V6KEY0_CLASS_CODE 0x00000000000000f8ULL |
| 1355 | #define TCAM_V6KEY0_CLASS_CODE_SHIFT 3 |
| 1356 | #define TCAM_V6KEY0_RESV2 0x0000000000000007ULL |
| 1357 | #define TCAM_V6KEY1_L2RDCNUM 0xf800000000000000ULL |
| 1358 | #define TCAM_V6KEY1_L2RDCNUM_SHIFT 59 |
| 1359 | #define TCAM_V6KEY1_NOPORT 0x0400000000000000ULL |
| 1360 | #define TCAM_V6KEY1_RESV 0x03ff000000000000ULL |
| 1361 | #define TCAM_V6KEY1_TOS 0x0000ff0000000000ULL |
| 1362 | #define TCAM_V6KEY1_TOS_SHIFT 40 |
| 1363 | #define TCAM_V6KEY1_NEXT_HDR 0x000000ff00000000ULL |
| 1364 | #define TCAM_V6KEY1_NEXT_HDR_SHIFT 32 |
| 1365 | #define TCAM_V6KEY1_PORT_SPI 0x00000000ffffffffULL |
| 1366 | #define TCAM_V6KEY1_PORT_SPI_SHIFT 0 |
| 1367 | #define TCAM_V6KEY2_ADDR_HIGH 0xffffffffffffffffULL |
| 1368 | #define TCAM_V6KEY3_ADDR_LOW 0xffffffffffffffffULL |
| 1369 | |
| 1370 | #define TCAM_ASSOCDATA_SYNDROME 0x000003fffc000000ULL |
| 1371 | #define TCAM_ASSOCDATA_SYNDROME_SHIFT 26 |
| 1372 | #define TCAM_ASSOCDATA_ZFID 0x0000000003ffc000ULL |
| 1373 | #define TCAM_ASSOCDATA_ZFID_SHIFT 14 |
| 1374 | #define TCAM_ASSOCDATA_V4_ECC_OK 0x0000000000002000ULL |
| 1375 | #define TCAM_ASSOCDATA_DISC 0x0000000000001000ULL |
| 1376 | #define TCAM_ASSOCDATA_TRES_MASK 0x0000000000000c00ULL |
| 1377 | #define TCAM_ASSOCDATA_TRES_USE_L2RDC 0x0000000000000000ULL |
| 1378 | #define TCAM_ASSOCDATA_TRES_USE_OFFSET 0x0000000000000400ULL |
| 1379 | #define TCAM_ASSOCDATA_TRES_OVR_RDC 0x0000000000000800ULL |
| 1380 | #define TCAM_ASSOCDATA_TRES_OVR_RDC_OFF 0x0000000000000c00ULL |
| 1381 | #define TCAM_ASSOCDATA_RDCTBL 0x0000000000000380ULL |
| 1382 | #define TCAM_ASSOCDATA_RDCTBL_SHIFT 7 |
| 1383 | #define TCAM_ASSOCDATA_OFFSET 0x000000000000007cULL |
| 1384 | #define TCAM_ASSOCDATA_OFFSET_SHIFT 2 |
| 1385 | #define TCAM_ASSOCDATA_ZFVLD 0x0000000000000002ULL |
| 1386 | #define TCAM_ASSOCDATA_AGE 0x0000000000000001ULL |
| 1387 | |
| 1388 | #define FLOW_KEY(IDX) (FZC_FFLP + 0x40000UL + (IDX) * 8UL) |
| 1389 | #define FLOW_KEY_PORT 0x0000000000000200ULL |
| 1390 | #define FLOW_KEY_L2DA 0x0000000000000100ULL |
| 1391 | #define FLOW_KEY_VLAN 0x0000000000000080ULL |
| 1392 | #define FLOW_KEY_IPSA 0x0000000000000040ULL |
| 1393 | #define FLOW_KEY_IPDA 0x0000000000000020ULL |
| 1394 | #define FLOW_KEY_PROTO 0x0000000000000010ULL |
| 1395 | #define FLOW_KEY_L4_0 0x000000000000000cULL |
| 1396 | #define FLOW_KEY_L4_0_SHIFT 2 |
| 1397 | #define FLOW_KEY_L4_1 0x0000000000000003ULL |
| 1398 | #define FLOW_KEY_L4_1_SHIFT 0 |
| 1399 | |
| 1400 | #define FLOW_KEY_L4_NONE 0x0 |
| 1401 | #define FLOW_KEY_L4_RESV 0x1 |
| 1402 | #define FLOW_KEY_L4_BYTE12 0x2 |
| 1403 | #define FLOW_KEY_L4_BYTE56 0x3 |
| 1404 | |
| 1405 | #define H1POLY (FZC_FFLP + 0x40060UL) |
| 1406 | #define H1POLY_INITVAL 0x00000000ffffffffULL |
| 1407 | |
| 1408 | #define H2POLY (FZC_FFLP + 0x40068UL) |
| 1409 | #define H2POLY_INITVAL 0x000000000000ffffULL |
| 1410 | |
| 1411 | #define FLW_PRT_SEL(IDX) (FZC_FFLP + 0x40070UL + (IDX) * 8UL) |
| 1412 | #define FLW_PRT_SEL_EXT 0x0000000000010000ULL |
| 1413 | #define FLW_PRT_SEL_MASK 0x0000000000001f00ULL |
| 1414 | #define FLW_PRT_SEL_MASK_SHIFT 8 |
| 1415 | #define FLW_PRT_SEL_BASE 0x000000000000001fULL |
| 1416 | #define FLW_PRT_SEL_BASE_SHIFT 0 |
| 1417 | |
| 1418 | #define HASH_TBL_ADDR(IDX) (FFLP + 0x00000UL + (IDX) * 8192UL) |
| 1419 | #define HASH_TBL_ADDR_AUTOINC 0x0000000000800000ULL |
| 1420 | #define HASH_TBL_ADDR_ADDR 0x00000000007fffffULL |
| 1421 | |
| 1422 | #define HASH_TBL_DATA(IDX) (FFLP + 0x00008UL + (IDX) * 8192UL) |
| 1423 | #define HASH_TBL_DATA_DATA 0xffffffffffffffffULL |
| 1424 | |
| 1425 | /* FCRAM hash table entries are up to 8 64-bit words in size. |
| 1426 | * The layout of each entry is determined by the settings in the |
| 1427 | * first word, which is the header. |
| 1428 | * |
| 1429 | * The indexing is controllable per partition (there is one partition |
| 1430 | * per RDC group, thus a total of eight) using the BASE and MASK fields |
| 1431 | * of FLW_PRT_SEL above. |
| 1432 | */ |
| 1433 | #define FCRAM_SIZE 0x800000 |
| 1434 | #define FCRAM_NUM_PARTITIONS 8 |
| 1435 | |
| 1436 | /* Generic HASH entry header, used for all non-optimized formats. */ |
| 1437 | #define HASH_HEADER_FMT 0x8000000000000000ULL |
| 1438 | #define HASH_HEADER_EXT 0x4000000000000000ULL |
| 1439 | #define HASH_HEADER_VALID 0x2000000000000000ULL |
| 1440 | #define HASH_HEADER_RESVD 0x1000000000000000ULL |
| 1441 | #define HASH_HEADER_L2_DADDR 0x0ffffffffffff000ULL |
| 1442 | #define HASH_HEADER_L2_DADDR_SHIFT 12 |
| 1443 | #define HASH_HEADER_VLAN 0x0000000000000fffULL |
| 1444 | #define HASH_HEADER_VLAN_SHIFT 0 |
| 1445 | |
| 1446 | /* Optimized format, just a header with a special layout defined below. |
| 1447 | * Set FMT and EXT both to zero to indicate this layout is being used. |
| 1448 | */ |
| 1449 | #define HASH_OPT_HEADER_FMT 0x8000000000000000ULL |
| 1450 | #define HASH_OPT_HEADER_EXT 0x4000000000000000ULL |
| 1451 | #define HASH_OPT_HEADER_VALID 0x2000000000000000ULL |
| 1452 | #define HASH_OPT_HEADER_RDCOFF 0x1f00000000000000ULL |
| 1453 | #define HASH_OPT_HEADER_RDCOFF_SHIFT 56 |
| 1454 | #define HASH_OPT_HEADER_HASH2 0x00ffff0000000000ULL |
| 1455 | #define HASH_OPT_HEADER_HASH2_SHIFT 40 |
| 1456 | #define HASH_OPT_HEADER_RESVD 0x000000ff00000000ULL |
| 1457 | #define HASH_OPT_HEADER_USERINFO 0x00000000ffffffffULL |
| 1458 | #define HASH_OPT_HEADER_USERINFO_SHIFT 0 |
| 1459 | |
| 1460 | /* Port and protocol word used for ipv4 and ipv6 layouts. */ |
| 1461 | #define HASH_PORT_DPORT 0xffff000000000000ULL |
| 1462 | #define HASH_PORT_DPORT_SHIFT 48 |
| 1463 | #define HASH_PORT_SPORT 0x0000ffff00000000ULL |
| 1464 | #define HASH_PORT_SPORT_SHIFT 32 |
| 1465 | #define HASH_PORT_PROTO 0x00000000ff000000ULL |
| 1466 | #define HASH_PORT_PROTO_SHIFT 24 |
| 1467 | #define HASH_PORT_PORT_OFF 0x0000000000c00000ULL |
| 1468 | #define HASH_PORT_PORT_OFF_SHIFT 22 |
| 1469 | #define HASH_PORT_PORT_RESV 0x00000000003fffffULL |
| 1470 | |
| 1471 | /* Action word used for ipv4 and ipv6 layouts. */ |
| 1472 | #define HASH_ACTION_RESV1 0xe000000000000000ULL |
| 1473 | #define HASH_ACTION_RDCOFF 0x1f00000000000000ULL |
| 1474 | #define HASH_ACTION_RDCOFF_SHIFT 56 |
| 1475 | #define HASH_ACTION_ZFVALID 0x0080000000000000ULL |
| 1476 | #define HASH_ACTION_RESV2 0x0070000000000000ULL |
| 1477 | #define HASH_ACTION_ZFID 0x000fff0000000000ULL |
| 1478 | #define HASH_ACTION_ZFID_SHIFT 40 |
| 1479 | #define HASH_ACTION_RESV3 0x000000ff00000000ULL |
| 1480 | #define HASH_ACTION_USERINFO 0x00000000ffffffffULL |
| 1481 | #define HASH_ACTION_USERINFO_SHIFT 0 |
| 1482 | |
| 1483 | /* IPV4 address word. Addresses are in network endian. */ |
| 1484 | #define HASH_IP4ADDR_SADDR 0xffffffff00000000ULL |
| 1485 | #define HASH_IP4ADDR_SADDR_SHIFT 32 |
| 1486 | #define HASH_IP4ADDR_DADDR 0x00000000ffffffffULL |
| 1487 | #define HASH_IP4ADDR_DADDR_SHIFT 0 |
| 1488 | |
| 1489 | /* IPV6 address layout is 4 words, first two are saddr, next two |
| 1490 | * are daddr. Addresses are in network endian. |
| 1491 | */ |
| 1492 | |
| 1493 | struct fcram_hash_opt { |
| 1494 | u64 header; |
| 1495 | }; |
| 1496 | |
| 1497 | /* EXT=1, FMT=0 */ |
| 1498 | struct fcram_hash_ipv4 { |
| 1499 | u64 header; |
| 1500 | u64 addrs; |
| 1501 | u64 ports; |
| 1502 | u64 action; |
| 1503 | }; |
| 1504 | |
| 1505 | /* EXT=1, FMT=1 */ |
| 1506 | struct fcram_hash_ipv6 { |
| 1507 | u64 header; |
| 1508 | u64 addrs[4]; |
| 1509 | u64 ports; |
| 1510 | u64 action; |
| 1511 | }; |
| 1512 | |
| 1513 | #define HASH_TBL_DATA_LOG(IDX) (FFLP + 0x00010UL + (IDX) * 8192UL) |
| 1514 | #define HASH_TBL_DATA_LOG_ERR 0x0000000080000000ULL |
| 1515 | #define HASH_TBL_DATA_LOG_ADDR 0x000000007fffff00ULL |
| 1516 | #define HASH_TBL_DATA_LOG_SYNDROME 0x00000000000000ffULL |
| 1517 | |
| 1518 | #define RX_DMA_CK_DIV (FZC_DMC + 0x00000UL) |
| 1519 | #define RX_DMA_CK_DIV_CNT 0x000000000000ffffULL |
| 1520 | |
| 1521 | #define DEF_RDC(IDX) (FZC_DMC + 0x00008UL + (IDX) * 0x8UL) |
| 1522 | #define DEF_RDC_VAL 0x000000000000001fULL |
| 1523 | |
| 1524 | #define PT_DRR_WT(IDX) (FZC_DMC + 0x00028UL + (IDX) * 0x8UL) |
| 1525 | #define PT_DRR_WT_VAL 0x000000000000ffffULL |
| 1526 | |
| 1527 | #define PT_DRR_WEIGHT_DEFAULT_10G 0x0400 |
| 1528 | #define PT_DRR_WEIGHT_DEFAULT_1G 0x0066 |
| 1529 | |
| 1530 | #define PT_USE(IDX) (FZC_DMC + 0x00048UL + (IDX) * 0x8UL) |
| 1531 | #define PT_USE_CNT 0x00000000000fffffULL |
| 1532 | |
| 1533 | #define RED_RAN_INIT (FZC_DMC + 0x00068UL) |
| 1534 | #define RED_RAN_INIT_OPMODE 0x0000000000010000ULL |
| 1535 | #define RED_RAN_INIT_VAL 0x000000000000ffffULL |
| 1536 | |
| 1537 | #define RX_ADDR_MD (FZC_DMC + 0x00070UL) |
| 1538 | #define RX_ADDR_MD_DBG_PT_MUX_SEL 0x000000000000000cULL |
| 1539 | #define RX_ADDR_MD_RAM_ACC 0x0000000000000002ULL |
| 1540 | #define RX_ADDR_MD_MODE32 0x0000000000000001ULL |
| 1541 | |
| 1542 | #define RDMC_PRE_PAR_ERR (FZC_DMC + 0x00078UL) |
| 1543 | #define RDMC_PRE_PAR_ERR_ERR 0x0000000000008000ULL |
| 1544 | #define RDMC_PRE_PAR_ERR_MERR 0x0000000000004000ULL |
| 1545 | #define RDMC_PRE_PAR_ERR_ADDR 0x00000000000000ffULL |
| 1546 | |
| 1547 | #define RDMC_SHA_PAR_ERR (FZC_DMC + 0x00080UL) |
| 1548 | #define RDMC_SHA_PAR_ERR_ERR 0x0000000000008000ULL |
| 1549 | #define RDMC_SHA_PAR_ERR_MERR 0x0000000000004000ULL |
| 1550 | #define RDMC_SHA_PAR_ERR_ADDR 0x00000000000000ffULL |
| 1551 | |
| 1552 | #define RDMC_MEM_ADDR (FZC_DMC + 0x00088UL) |
| 1553 | #define RDMC_MEM_ADDR_PRE_SHAD 0x0000000000000100ULL |
| 1554 | #define RDMC_MEM_ADDR_ADDR 0x00000000000000ffULL |
| 1555 | |
| 1556 | #define RDMC_MEM_DAT0 (FZC_DMC + 0x00090UL) |
| 1557 | #define RDMC_MEM_DAT0_DATA 0x00000000ffffffffULL /* bits 31:0 */ |
| 1558 | |
| 1559 | #define RDMC_MEM_DAT1 (FZC_DMC + 0x00098UL) |
| 1560 | #define RDMC_MEM_DAT1_DATA 0x00000000ffffffffULL /* bits 63:32 */ |
| 1561 | |
| 1562 | #define RDMC_MEM_DAT2 (FZC_DMC + 0x000a0UL) |
| 1563 | #define RDMC_MEM_DAT2_DATA 0x00000000ffffffffULL /* bits 95:64 */ |
| 1564 | |
| 1565 | #define RDMC_MEM_DAT3 (FZC_DMC + 0x000a8UL) |
| 1566 | #define RDMC_MEM_DAT3_DATA 0x00000000ffffffffULL /* bits 127:96 */ |
| 1567 | |
| 1568 | #define RDMC_MEM_DAT4 (FZC_DMC + 0x000b0UL) |
| 1569 | #define RDMC_MEM_DAT4_DATA 0x00000000000fffffULL /* bits 147:128 */ |
| 1570 | |
| 1571 | #define RX_CTL_DAT_FIFO_STAT (FZC_DMC + 0x000b8UL) |
| 1572 | #define RX_CTL_DAT_FIFO_STAT_ID_MISMATCH 0x0000000000000100ULL |
| 1573 | #define RX_CTL_DAT_FIFO_STAT_ZCP_EOP_ERR 0x00000000000000f0ULL |
| 1574 | #define RX_CTL_DAT_FIFO_STAT_IPP_EOP_ERR 0x000000000000000fULL |
| 1575 | |
| 1576 | #define RX_CTL_DAT_FIFO_MASK (FZC_DMC + 0x000c0UL) |
| 1577 | #define RX_CTL_DAT_FIFO_MASK_ID_MISMATCH 0x0000000000000100ULL |
| 1578 | #define RX_CTL_DAT_FIFO_MASK_ZCP_EOP_ERR 0x00000000000000f0ULL |
| 1579 | #define RX_CTL_DAT_FIFO_MASK_IPP_EOP_ERR 0x000000000000000fULL |
| 1580 | |
| 1581 | #define RDMC_TRAINING_VECTOR (FZC_DMC + 0x000c8UL) |
| 1582 | #define RDMC_TRAINING_VECTOR_TRAINING_VECTOR 0x00000000ffffffffULL |
| 1583 | |
| 1584 | #define RX_CTL_DAT_FIFO_STAT_DBG (FZC_DMC + 0x000d0UL) |
| 1585 | #define RX_CTL_DAT_FIFO_STAT_DBG_ID_MISMATCH 0x0000000000000100ULL |
| 1586 | #define RX_CTL_DAT_FIFO_STAT_DBG_ZCP_EOP_ERR 0x00000000000000f0ULL |
| 1587 | #define RX_CTL_DAT_FIFO_STAT_DBG_IPP_EOP_ERR 0x000000000000000fULL |
| 1588 | |
| 1589 | #define RDC_TBL(TBL,SLOT) (FZC_ZCP + 0x10000UL + \ |
| 1590 | (TBL) * (8UL * 16UL) + \ |
| 1591 | (SLOT) * 8UL) |
| 1592 | #define RDC_TBL_RDC 0x000000000000000fULL |
| 1593 | |
| 1594 | #define RX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x20000UL + (IDX) * 0x40UL) |
| 1595 | #define RX_LOG_PAGE_VLD_FUNC 0x000000000000000cULL |
| 1596 | #define RX_LOG_PAGE_VLD_FUNC_SHIFT 2 |
| 1597 | #define RX_LOG_PAGE_VLD_PAGE1 0x0000000000000002ULL |
| 1598 | #define RX_LOG_PAGE_VLD_PAGE0 0x0000000000000001ULL |
| 1599 | |
| 1600 | #define RX_LOG_MASK1(IDX) (FZC_DMC + 0x20008UL + (IDX) * 0x40UL) |
| 1601 | #define RX_LOG_MASK1_MASK 0x00000000ffffffffULL |
| 1602 | |
| 1603 | #define RX_LOG_VAL1(IDX) (FZC_DMC + 0x20010UL + (IDX) * 0x40UL) |
| 1604 | #define RX_LOG_VAL1_VALUE 0x00000000ffffffffULL |
| 1605 | |
| 1606 | #define RX_LOG_MASK2(IDX) (FZC_DMC + 0x20018UL + (IDX) * 0x40UL) |
| 1607 | #define RX_LOG_MASK2_MASK 0x00000000ffffffffULL |
| 1608 | |
| 1609 | #define RX_LOG_VAL2(IDX) (FZC_DMC + 0x20020UL + (IDX) * 0x40UL) |
| 1610 | #define RX_LOG_VAL2_VALUE 0x00000000ffffffffULL |
| 1611 | |
| 1612 | #define RX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x20028UL + (IDX) * 0x40UL) |
| 1613 | #define RX_LOG_PAGE_RELO1_RELO 0x00000000ffffffffULL |
| 1614 | |
| 1615 | #define RX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x20030UL + (IDX) * 0x40UL) |
| 1616 | #define RX_LOG_PAGE_RELO2_RELO 0x00000000ffffffffULL |
| 1617 | |
| 1618 | #define RX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x20038UL + (IDX) * 0x40UL) |
| 1619 | #define RX_LOG_PAGE_HDL_HANDLE 0x00000000000fffffULL |
| 1620 | |
| 1621 | #define TX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x40000UL + (IDX) * 0x200UL) |
| 1622 | #define TX_LOG_PAGE_VLD_FUNC 0x000000000000000cULL |
| 1623 | #define TX_LOG_PAGE_VLD_FUNC_SHIFT 2 |
| 1624 | #define TX_LOG_PAGE_VLD_PAGE1 0x0000000000000002ULL |
| 1625 | #define TX_LOG_PAGE_VLD_PAGE0 0x0000000000000001ULL |
| 1626 | |
| 1627 | #define TX_LOG_MASK1(IDX) (FZC_DMC + 0x40008UL + (IDX) * 0x200UL) |
| 1628 | #define TX_LOG_MASK1_MASK 0x00000000ffffffffULL |
| 1629 | |
| 1630 | #define TX_LOG_VAL1(IDX) (FZC_DMC + 0x40010UL + (IDX) * 0x200UL) |
| 1631 | #define TX_LOG_VAL1_VALUE 0x00000000ffffffffULL |
| 1632 | |
| 1633 | #define TX_LOG_MASK2(IDX) (FZC_DMC + 0x40018UL + (IDX) * 0x200UL) |
| 1634 | #define TX_LOG_MASK2_MASK 0x00000000ffffffffULL |
| 1635 | |
| 1636 | #define TX_LOG_VAL2(IDX) (FZC_DMC + 0x40020UL + (IDX) * 0x200UL) |
| 1637 | #define TX_LOG_VAL2_VALUE 0x00000000ffffffffULL |
| 1638 | |
| 1639 | #define TX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x40028UL + (IDX) * 0x200UL) |
| 1640 | #define TX_LOG_PAGE_RELO1_RELO 0x00000000ffffffffULL |
| 1641 | |
| 1642 | #define TX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x40030UL + (IDX) * 0x200UL) |
| 1643 | #define TX_LOG_PAGE_RELO2_RELO 0x00000000ffffffffULL |
| 1644 | |
| 1645 | #define TX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x40038UL + (IDX) * 0x200UL) |
| 1646 | #define TX_LOG_PAGE_HDL_HANDLE 0x00000000000fffffULL |
| 1647 | |
| 1648 | #define TX_ADDR_MD (FZC_DMC + 0x45000UL) |
| 1649 | #define TX_ADDR_MD_MODE32 0x0000000000000001ULL |
| 1650 | |
| 1651 | #define RDC_RED_PARA(IDX) (FZC_DMC + 0x30000UL + (IDX) * 0x40UL) |
| 1652 | #define RDC_RED_PARA_THRE_SYN 0x00000000fff00000ULL |
| 1653 | #define RDC_RED_PARA_THRE_SYN_SHIFT 20 |
| 1654 | #define RDC_RED_PARA_WIN_SYN 0x00000000000f0000ULL |
| 1655 | #define RDC_RED_PARA_WIN_SYN_SHIFT 16 |
| 1656 | #define RDC_RED_PARA_THRE 0x000000000000fff0ULL |
| 1657 | #define RDC_RED_PARA_THRE_SHIFT 4 |
| 1658 | #define RDC_RED_PARA_WIN 0x000000000000000fULL |
| 1659 | #define RDC_RED_PARA_WIN_SHIFT 0 |
| 1660 | |
| 1661 | #define RED_DIS_CNT(IDX) (FZC_DMC + 0x30008UL + (IDX) * 0x40UL) |
| 1662 | #define RED_DIS_CNT_OFLOW 0x0000000000010000ULL |
| 1663 | #define RED_DIS_CNT_COUNT 0x000000000000ffffULL |
| 1664 | |
| 1665 | #define IPP_CFIG (FZC_IPP + 0x00000UL) |
| 1666 | #define IPP_CFIG_SOFT_RST 0x0000000080000000ULL |
| 1667 | #define IPP_CFIG_IP_MAX_PKT 0x0000000001ffff00ULL |
| 1668 | #define IPP_CFIG_IP_MAX_PKT_SHIFT 8 |
| 1669 | #define IPP_CFIG_FFLP_CS_PIO_W 0x0000000000000080ULL |
| 1670 | #define IPP_CFIG_PFIFO_PIO_W 0x0000000000000040ULL |
| 1671 | #define IPP_CFIG_DFIFO_PIO_W 0x0000000000000020ULL |
| 1672 | #define IPP_CFIG_CKSUM_EN 0x0000000000000010ULL |
| 1673 | #define IPP_CFIG_DROP_BAD_CRC 0x0000000000000008ULL |
| 1674 | #define IPP_CFIG_DFIFO_ECC_EN 0x0000000000000004ULL |
| 1675 | #define IPP_CFIG_DEBUG_BUS_OUT_EN 0x0000000000000002ULL |
| 1676 | #define IPP_CFIG_IPP_ENABLE 0x0000000000000001ULL |
| 1677 | |
| 1678 | #define IPP_PKT_DIS (FZC_IPP + 0x00020UL) |
| 1679 | #define IPP_PKT_DIS_COUNT 0x0000000000003fffULL |
| 1680 | |
| 1681 | #define IPP_BAD_CS_CNT (FZC_IPP + 0x00028UL) |
| 1682 | #define IPP_BAD_CS_CNT_COUNT 0x0000000000003fffULL |
| 1683 | |
| 1684 | #define IPP_ECC (FZC_IPP + 0x00030UL) |
| 1685 | #define IPP_ECC_COUNT 0x00000000000000ffULL |
| 1686 | |
| 1687 | #define IPP_INT_STAT (FZC_IPP + 0x00040UL) |
| 1688 | #define IPP_INT_STAT_SOP_MISS 0x0000000080000000ULL |
| 1689 | #define IPP_INT_STAT_EOP_MISS 0x0000000040000000ULL |
| 1690 | #define IPP_INT_STAT_DFIFO_UE 0x0000000030000000ULL |
| 1691 | #define IPP_INT_STAT_DFIFO_CE 0x000000000c000000ULL |
| 1692 | #define IPP_INT_STAT_DFIFO_ECC 0x0000000003000000ULL |
| 1693 | #define IPP_INT_STAT_DFIFO_ECC_IDX 0x00000000007ff000ULL |
| 1694 | #define IPP_INT_STAT_PFIFO_PERR 0x0000000000000800ULL |
| 1695 | #define IPP_INT_STAT_ECC_ERR_MAX 0x0000000000000400ULL |
| 1696 | #define IPP_INT_STAT_PFIFO_ERR_IDX 0x00000000000003f0ULL |
| 1697 | #define IPP_INT_STAT_PFIFO_OVER 0x0000000000000008ULL |
| 1698 | #define IPP_INT_STAT_PFIFO_UND 0x0000000000000004ULL |
| 1699 | #define IPP_INT_STAT_BAD_CS_MX 0x0000000000000002ULL |
| 1700 | #define IPP_INT_STAT_PKT_DIS_MX 0x0000000000000001ULL |
| 1701 | #define IPP_INT_STAT_ALL 0x00000000ff7fffffULL |
| 1702 | |
| 1703 | #define IPP_MSK (FZC_IPP + 0x00048UL) |
| 1704 | #define IPP_MSK_ECC_ERR_MX 0x0000000000000080ULL |
| 1705 | #define IPP_MSK_DFIFO_EOP_SOP 0x0000000000000040ULL |
| 1706 | #define IPP_MSK_DFIFO_UC 0x0000000000000020ULL |
| 1707 | #define IPP_MSK_PFIFO_PAR 0x0000000000000010ULL |
| 1708 | #define IPP_MSK_PFIFO_OVER 0x0000000000000008ULL |
| 1709 | #define IPP_MSK_PFIFO_UND 0x0000000000000004ULL |
| 1710 | #define IPP_MSK_BAD_CS 0x0000000000000002ULL |
| 1711 | #define IPP_MSK_PKT_DIS_CNT 0x0000000000000001ULL |
| 1712 | #define IPP_MSK_ALL 0x00000000000000ffULL |
| 1713 | |
| 1714 | #define IPP_PFIFO_RD0 (FZC_IPP + 0x00060UL) |
| 1715 | #define IPP_PFIFO_RD0_DATA 0x00000000ffffffffULL /* bits 31:0 */ |
| 1716 | |
| 1717 | #define IPP_PFIFO_RD1 (FZC_IPP + 0x00068UL) |
| 1718 | #define IPP_PFIFO_RD1_DATA 0x00000000ffffffffULL /* bits 63:32 */ |
| 1719 | |
| 1720 | #define IPP_PFIFO_RD2 (FZC_IPP + 0x00070UL) |
| 1721 | #define IPP_PFIFO_RD2_DATA 0x00000000ffffffffULL /* bits 95:64 */ |
| 1722 | |
| 1723 | #define IPP_PFIFO_RD3 (FZC_IPP + 0x00078UL) |
| 1724 | #define IPP_PFIFO_RD3_DATA 0x00000000ffffffffULL /* bits 127:96 */ |
| 1725 | |
| 1726 | #define IPP_PFIFO_RD4 (FZC_IPP + 0x00080UL) |
| 1727 | #define IPP_PFIFO_RD4_DATA 0x00000000ffffffffULL /* bits 145:128 */ |
| 1728 | |
| 1729 | #define IPP_PFIFO_WR0 (FZC_IPP + 0x00088UL) |
| 1730 | #define IPP_PFIFO_WR0_DATA 0x00000000ffffffffULL /* bits 31:0 */ |
| 1731 | |
| 1732 | #define IPP_PFIFO_WR1 (FZC_IPP + 0x00090UL) |
| 1733 | #define IPP_PFIFO_WR1_DATA 0x00000000ffffffffULL /* bits 63:32 */ |
| 1734 | |
| 1735 | #define IPP_PFIFO_WR2 (FZC_IPP + 0x00098UL) |
| 1736 | #define IPP_PFIFO_WR2_DATA 0x00000000ffffffffULL /* bits 95:64 */ |
| 1737 | |
| 1738 | #define IPP_PFIFO_WR3 (FZC_IPP + 0x000a0UL) |
| 1739 | #define IPP_PFIFO_WR3_DATA 0x00000000ffffffffULL /* bits 127:96 */ |
| 1740 | |
| 1741 | #define IPP_PFIFO_WR4 (FZC_IPP + 0x000a8UL) |
| 1742 | #define IPP_PFIFO_WR4_DATA 0x00000000ffffffffULL /* bits 145:128 */ |
| 1743 | |
| 1744 | #define IPP_PFIFO_RD_PTR (FZC_IPP + 0x000b0UL) |
| 1745 | #define IPP_PFIFO_RD_PTR_PTR 0x000000000000003fULL |
| 1746 | |
| 1747 | #define IPP_PFIFO_WR_PTR (FZC_IPP + 0x000b8UL) |
| 1748 | #define IPP_PFIFO_WR_PTR_PTR 0x000000000000007fULL |
| 1749 | |
| 1750 | #define IPP_DFIFO_RD0 (FZC_IPP + 0x000c0UL) |
| 1751 | #define IPP_DFIFO_RD0_DATA 0x00000000ffffffffULL /* bits 31:0 */ |
| 1752 | |
| 1753 | #define IPP_DFIFO_RD1 (FZC_IPP + 0x000c8UL) |
| 1754 | #define IPP_DFIFO_RD1_DATA 0x00000000ffffffffULL /* bits 63:32 */ |
| 1755 | |
| 1756 | #define IPP_DFIFO_RD2 (FZC_IPP + 0x000d0UL) |
| 1757 | #define IPP_DFIFO_RD2_DATA 0x00000000ffffffffULL /* bits 95:64 */ |
| 1758 | |
| 1759 | #define IPP_DFIFO_RD3 (FZC_IPP + 0x000d8UL) |
| 1760 | #define IPP_DFIFO_RD3_DATA 0x00000000ffffffffULL /* bits 127:96 */ |
| 1761 | |
| 1762 | #define IPP_DFIFO_RD4 (FZC_IPP + 0x000e0UL) |
| 1763 | #define IPP_DFIFO_RD4_DATA 0x00000000ffffffffULL /* bits 145:128 */ |
| 1764 | |
| 1765 | #define IPP_DFIFO_WR0 (FZC_IPP + 0x000e8UL) |
| 1766 | #define IPP_DFIFO_WR0_DATA 0x00000000ffffffffULL /* bits 31:0 */ |
| 1767 | |
| 1768 | #define IPP_DFIFO_WR1 (FZC_IPP + 0x000f0UL) |
| 1769 | #define IPP_DFIFO_WR1_DATA 0x00000000ffffffffULL /* bits 63:32 */ |
| 1770 | |
| 1771 | #define IPP_DFIFO_WR2 (FZC_IPP + 0x000f8UL) |
| 1772 | #define IPP_DFIFO_WR2_DATA 0x00000000ffffffffULL /* bits 95:64 */ |
| 1773 | |
| 1774 | #define IPP_DFIFO_WR3 (FZC_IPP + 0x00100UL) |
| 1775 | #define IPP_DFIFO_WR3_DATA 0x00000000ffffffffULL /* bits 127:96 */ |
| 1776 | |
| 1777 | #define IPP_DFIFO_WR4 (FZC_IPP + 0x00108UL) |
| 1778 | #define IPP_DFIFO_WR4_DATA 0x00000000ffffffffULL /* bits 145:128 */ |
| 1779 | |
| 1780 | #define IPP_DFIFO_RD_PTR (FZC_IPP + 0x00110UL) |
| 1781 | #define IPP_DFIFO_RD_PTR_PTR 0x0000000000000fffULL |
| 1782 | |
| 1783 | #define IPP_DFIFO_WR_PTR (FZC_IPP + 0x00118UL) |
| 1784 | #define IPP_DFIFO_WR_PTR_PTR 0x0000000000000fffULL |
| 1785 | |
| 1786 | #define IPP_SM (FZC_IPP + 0x00120UL) |
| 1787 | #define IPP_SM_SM 0x00000000ffffffffULL |
| 1788 | |
| 1789 | #define IPP_CS_STAT (FZC_IPP + 0x00128UL) |
| 1790 | #define IPP_CS_STAT_BCYC_CNT 0x00000000ff000000ULL |
| 1791 | #define IPP_CS_STAT_IP_LEN 0x0000000000fff000ULL |
| 1792 | #define IPP_CS_STAT_CS_FAIL 0x0000000000000800ULL |
| 1793 | #define IPP_CS_STAT_TERM 0x0000000000000400ULL |
| 1794 | #define IPP_CS_STAT_BAD_NUM 0x0000000000000200ULL |
| 1795 | #define IPP_CS_STAT_CS_STATE 0x00000000000001ffULL |
| 1796 | |
| 1797 | #define IPP_FFLP_CS_INFO (FZC_IPP + 0x00130UL) |
| 1798 | #define IPP_FFLP_CS_INFO_PKT_ID 0x0000000000003c00ULL |
| 1799 | #define IPP_FFLP_CS_INFO_L4_PROTO 0x0000000000000300ULL |
| 1800 | #define IPP_FFLP_CS_INFO_V4_HD_LEN 0x00000000000000f0ULL |
| 1801 | #define IPP_FFLP_CS_INFO_L3_VER 0x000000000000000cULL |
| 1802 | #define IPP_FFLP_CS_INFO_L2_OP 0x0000000000000003ULL |
| 1803 | |
| 1804 | #define IPP_DBG_SEL (FZC_IPP + 0x00138UL) |
| 1805 | #define IPP_DBG_SEL_SEL 0x000000000000000fULL |
| 1806 | |
| 1807 | #define IPP_DFIFO_ECC_SYND (FZC_IPP + 0x00140UL) |
| 1808 | #define IPP_DFIFO_ECC_SYND_SYND 0x000000000000ffffULL |
| 1809 | |
| 1810 | #define IPP_DFIFO_EOP_RD_PTR (FZC_IPP + 0x00148UL) |
| 1811 | #define IPP_DFIFO_EOP_RD_PTR_PTR 0x0000000000000fffULL |
| 1812 | |
| 1813 | #define IPP_ECC_CTL (FZC_IPP + 0x00150UL) |
| 1814 | #define IPP_ECC_CTL_DIS_DBL 0x0000000080000000ULL |
| 1815 | #define IPP_ECC_CTL_COR_DBL 0x0000000000020000ULL |
| 1816 | #define IPP_ECC_CTL_COR_SNG 0x0000000000010000ULL |
| 1817 | #define IPP_ECC_CTL_COR_ALL 0x0000000000000400ULL |
| 1818 | #define IPP_ECC_CTL_COR_1 0x0000000000000100ULL |
| 1819 | #define IPP_ECC_CTL_COR_LST 0x0000000000000004ULL |
| 1820 | #define IPP_ECC_CTL_COR_SND 0x0000000000000002ULL |
| 1821 | #define IPP_ECC_CTL_COR_FSR 0x0000000000000001ULL |
| 1822 | |
| 1823 | #define NIU_DFIFO_ENTRIES 1024 |
| 1824 | #define ATLAS_P0_P1_DFIFO_ENTRIES 2048 |
| 1825 | #define ATLAS_P2_P3_DFIFO_ENTRIES 1024 |
| 1826 | |
| 1827 | #define ZCP_CFIG (FZC_ZCP + 0x00000UL) |
| 1828 | #define ZCP_CFIG_ZCP_32BIT_MODE 0x0000000001000000ULL |
| 1829 | #define ZCP_CFIG_ZCP_DEBUG_SEL 0x0000000000ff0000ULL |
| 1830 | #define ZCP_CFIG_DMA_TH 0x000000000000ffe0ULL |
| 1831 | #define ZCP_CFIG_ECC_CHK_DIS 0x0000000000000010ULL |
| 1832 | #define ZCP_CFIG_PAR_CHK_DIS 0x0000000000000008ULL |
| 1833 | #define ZCP_CFIG_DIS_BUFF_RSP_IF 0x0000000000000004ULL |
| 1834 | #define ZCP_CFIG_DIS_BUFF_REQ_IF 0x0000000000000002ULL |
| 1835 | #define ZCP_CFIG_ZC_ENABLE 0x0000000000000001ULL |
| 1836 | |
| 1837 | #define ZCP_INT_STAT (FZC_ZCP + 0x00008UL) |
| 1838 | #define ZCP_INT_STAT_RRFIFO_UNDERRUN 0x0000000000008000ULL |
| 1839 | #define ZCP_INT_STAT_RRFIFO_OVERRUN 0x0000000000004000ULL |
| 1840 | #define ZCP_INT_STAT_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL |
| 1841 | #define ZCP_INT_STAT_BUFFER_OVERFLOW 0x0000000000000800ULL |
| 1842 | #define ZCP_INT_STAT_STAT_TBL_PERR 0x0000000000000400ULL |
| 1843 | #define ZCP_INT_STAT_DYN_TBL_PERR 0x0000000000000200ULL |
| 1844 | #define ZCP_INT_STAT_BUF_TBL_PERR 0x0000000000000100ULL |
| 1845 | #define ZCP_INT_STAT_TT_PROGRAM_ERR 0x0000000000000080ULL |
| 1846 | #define ZCP_INT_STAT_RSP_TT_INDEX_ERR 0x0000000000000040ULL |
| 1847 | #define ZCP_INT_STAT_SLV_TT_INDEX_ERR 0x0000000000000020ULL |
| 1848 | #define ZCP_INT_STAT_ZCP_TT_INDEX_ERR 0x0000000000000010ULL |
| 1849 | #define ZCP_INT_STAT_CFIFO_ECC3 0x0000000000000008ULL |
| 1850 | #define ZCP_INT_STAT_CFIFO_ECC2 0x0000000000000004ULL |
| 1851 | #define ZCP_INT_STAT_CFIFO_ECC1 0x0000000000000002ULL |
| 1852 | #define ZCP_INT_STAT_CFIFO_ECC0 0x0000000000000001ULL |
| 1853 | #define ZCP_INT_STAT_ALL 0x000000000000ffffULL |
| 1854 | |
| 1855 | #define ZCP_INT_MASK (FZC_ZCP + 0x00010UL) |
| 1856 | #define ZCP_INT_MASK_RRFIFO_UNDERRUN 0x0000000000008000ULL |
| 1857 | #define ZCP_INT_MASK_RRFIFO_OVERRUN 0x0000000000004000ULL |
| 1858 | #define ZCP_INT_MASK_LOJ 0x0000000000002000ULL |
| 1859 | #define ZCP_INT_MASK_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL |
| 1860 | #define ZCP_INT_MASK_BUFFER_OVERFLOW 0x0000000000000800ULL |
| 1861 | #define ZCP_INT_MASK_STAT_TBL_PERR 0x0000000000000400ULL |
| 1862 | #define ZCP_INT_MASK_DYN_TBL_PERR 0x0000000000000200ULL |
| 1863 | #define ZCP_INT_MASK_BUF_TBL_PERR 0x0000000000000100ULL |
| 1864 | #define ZCP_INT_MASK_TT_PROGRAM_ERR 0x0000000000000080ULL |
| 1865 | #define ZCP_INT_MASK_RSP_TT_INDEX_ERR 0x0000000000000040ULL |
| 1866 | #define ZCP_INT_MASK_SLV_TT_INDEX_ERR 0x0000000000000020ULL |
| 1867 | #define ZCP_INT_MASK_ZCP_TT_INDEX_ERR 0x0000000000000010ULL |
| 1868 | #define ZCP_INT_MASK_CFIFO_ECC3 0x0000000000000008ULL |
| 1869 | #define ZCP_INT_MASK_CFIFO_ECC2 0x0000000000000004ULL |
| 1870 | #define ZCP_INT_MASK_CFIFO_ECC1 0x0000000000000002ULL |
| 1871 | #define ZCP_INT_MASK_CFIFO_ECC0 0x0000000000000001ULL |
| 1872 | #define ZCP_INT_MASK_ALL 0x000000000000ffffULL |
| 1873 | |
| 1874 | #define BAM4BUF (FZC_ZCP + 0x00018UL) |
| 1875 | #define BAM4BUF_LOJ 0x0000000080000000ULL |
| 1876 | #define BAM4BUF_EN_CK 0x0000000040000000ULL |
| 1877 | #define BAM4BUF_IDX_END0 0x000000003ff00000ULL |
| 1878 | #define BAM4BUF_IDX_ST0 0x00000000000ffc00ULL |
| 1879 | #define BAM4BUF_OFFSET0 0x00000000000003ffULL |
| 1880 | |
| 1881 | #define BAM8BUF (FZC_ZCP + 0x00020UL) |
| 1882 | #define BAM8BUF_LOJ 0x0000000080000000ULL |
| 1883 | #define BAM8BUF_EN_CK 0x0000000040000000ULL |
| 1884 | #define BAM8BUF_IDX_END1 0x000000003ff00000ULL |
| 1885 | #define BAM8BUF_IDX_ST1 0x00000000000ffc00ULL |
| 1886 | #define BAM8BUF_OFFSET1 0x00000000000003ffULL |
| 1887 | |
| 1888 | #define BAM16BUF (FZC_ZCP + 0x00028UL) |
| 1889 | #define BAM16BUF_LOJ 0x0000000080000000ULL |
| 1890 | #define BAM16BUF_EN_CK 0x0000000040000000ULL |
| 1891 | #define BAM16BUF_IDX_END2 0x000000003ff00000ULL |
| 1892 | #define BAM16BUF_IDX_ST2 0x00000000000ffc00ULL |
| 1893 | #define BAM16BUF_OFFSET2 0x00000000000003ffULL |
| 1894 | |
| 1895 | #define BAM32BUF (FZC_ZCP + 0x00030UL) |
| 1896 | #define BAM32BUF_LOJ 0x0000000080000000ULL |
| 1897 | #define BAM32BUF_EN_CK 0x0000000040000000ULL |
| 1898 | #define BAM32BUF_IDX_END3 0x000000003ff00000ULL |
| 1899 | #define BAM32BUF_IDX_ST3 0x00000000000ffc00ULL |
| 1900 | #define BAM32BUF_OFFSET3 0x00000000000003ffULL |
| 1901 | |
| 1902 | #define DST4BUF (FZC_ZCP + 0x00038UL) |
| 1903 | #define DST4BUF_DS_OFFSET0 0x00000000000003ffULL |
| 1904 | |
| 1905 | #define DST8BUF (FZC_ZCP + 0x00040UL) |
| 1906 | #define DST8BUF_DS_OFFSET1 0x00000000000003ffULL |
| 1907 | |
| 1908 | #define DST16BUF (FZC_ZCP + 0x00048UL) |
| 1909 | #define DST16BUF_DS_OFFSET2 0x00000000000003ffULL |
| 1910 | |
| 1911 | #define DST32BUF (FZC_ZCP + 0x00050UL) |
| 1912 | #define DST32BUF_DS_OFFSET3 0x00000000000003ffULL |
| 1913 | |
| 1914 | #define ZCP_RAM_DATA0 (FZC_ZCP + 0x00058UL) |
| 1915 | #define ZCP_RAM_DATA0_DAT0 0x00000000ffffffffULL |
| 1916 | |
| 1917 | #define ZCP_RAM_DATA1 (FZC_ZCP + 0x00060UL) |
| 1918 | #define ZCP_RAM_DAT10_DAT1 0x00000000ffffffffULL |
| 1919 | |
| 1920 | #define ZCP_RAM_DATA2 (FZC_ZCP + 0x00068UL) |
| 1921 | #define ZCP_RAM_DATA2_DAT2 0x00000000ffffffffULL |
| 1922 | |
| 1923 | #define ZCP_RAM_DATA3 (FZC_ZCP + 0x00070UL) |
| 1924 | #define ZCP_RAM_DATA3_DAT3 0x00000000ffffffffULL |
| 1925 | |
| 1926 | #define ZCP_RAM_DATA4 (FZC_ZCP + 0x00078UL) |
| 1927 | #define ZCP_RAM_DATA4_DAT4 0x00000000000000ffULL |
| 1928 | |
| 1929 | #define ZCP_RAM_BE (FZC_ZCP + 0x00080UL) |
| 1930 | #define ZCP_RAM_BE_VAL 0x000000000001ffffULL |
| 1931 | |
| 1932 | #define ZCP_RAM_ACC (FZC_ZCP + 0x00088UL) |
| 1933 | #define ZCP_RAM_ACC_BUSY 0x0000000080000000ULL |
| 1934 | #define ZCP_RAM_ACC_READ 0x0000000040000000ULL |
| 1935 | #define ZCP_RAM_ACC_WRITE 0x0000000000000000ULL |
| 1936 | #define ZCP_RAM_ACC_LOJ 0x0000000020000000ULL |
| 1937 | #define ZCP_RAM_ACC_ZFCID 0x000000001ffe0000ULL |
| 1938 | #define ZCP_RAM_ACC_ZFCID_SHIFT 17 |
| 1939 | #define ZCP_RAM_ACC_RAM_SEL 0x000000000001f000ULL |
| 1940 | #define ZCP_RAM_ACC_RAM_SEL_SHIFT 12 |
| 1941 | #define ZCP_RAM_ACC_CFIFOADDR 0x0000000000000fffULL |
| 1942 | #define ZCP_RAM_ACC_CFIFOADDR_SHIFT 0 |
| 1943 | |
| 1944 | #define ZCP_RAM_SEL_BAM(INDEX) (0x00 + (INDEX)) |
| 1945 | #define ZCP_RAM_SEL_TT_STATIC 0x08 |
| 1946 | #define ZCP_RAM_SEL_TT_DYNAMIC 0x09 |
| 1947 | #define ZCP_RAM_SEL_CFIFO(PORT) (0x10 + (PORT)) |
| 1948 | |
| 1949 | #define NIU_CFIFO_ENTRIES 1024 |
| 1950 | #define ATLAS_P0_P1_CFIFO_ENTRIES 2048 |
| 1951 | #define ATLAS_P2_P3_CFIFO_ENTRIES 1024 |
| 1952 | |
| 1953 | #define CHK_BIT_DATA (FZC_ZCP + 0x00090UL) |
| 1954 | #define CHK_BIT_DATA_DATA 0x000000000000ffffULL |
| 1955 | |
| 1956 | #define RESET_CFIFO (FZC_ZCP + 0x00098UL) |
| 1957 | #define RESET_CFIFO_RST(PORT) (0x1 << (PORT)) |
| 1958 | |
| 1959 | #define CFIFO_ECC(PORT) (FZC_ZCP + 0x000a0UL + (PORT) * 8UL) |
| 1960 | #define CFIFO_ECC_DIS_DBLBIT_ERR 0x0000000080000000ULL |
| 1961 | #define CFIFO_ECC_DBLBIT_ERR 0x0000000000020000ULL |
| 1962 | #define CFIFO_ECC_SINGLEBIT_ERR 0x0000000000010000ULL |
| 1963 | #define CFIFO_ECC_ALL_PKT 0x0000000000000400ULL |
| 1964 | #define CFIFO_ECC_LAST_LINE 0x0000000000000004ULL |
| 1965 | #define CFIFO_ECC_2ND_LINE 0x0000000000000002ULL |
| 1966 | #define CFIFO_ECC_1ST_LINE 0x0000000000000001ULL |
| 1967 | |
| 1968 | #define ZCP_TRAINING_VECTOR (FZC_ZCP + 0x000c0UL) |
| 1969 | #define ZCP_TRAINING_VECTOR_VECTOR 0x00000000ffffffffULL |
| 1970 | |
| 1971 | #define ZCP_STATE_MACHINE (FZC_ZCP + 0x000c8UL) |
| 1972 | #define ZCP_STATE_MACHINE_SM 0x00000000ffffffffULL |
| 1973 | |
| 1974 | /* Same bits as ZCP_INT_STAT */ |
| 1975 | #define ZCP_INT_STAT_TEST (FZC_ZCP + 0x00108UL) |
| 1976 | |
| 1977 | #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL) |
| 1978 | #define RXDMA_CFIG1_EN 0x0000000080000000ULL |
| 1979 | #define RXDMA_CFIG1_RST 0x0000000040000000ULL |
| 1980 | #define RXDMA_CFIG1_QST 0x0000000020000000ULL |
| 1981 | #define RXDMA_CFIG1_MBADDR_H 0x0000000000000fffULL /* mboxaddr 43:32 */ |
| 1982 | |
| 1983 | #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL) |
| 1984 | #define RXDMA_CFIG2_MBADDR_L 0x00000000ffffffc0ULL /* mboxaddr 31:6 */ |
| 1985 | #define RXDMA_CFIG2_OFFSET 0x0000000000000006ULL |
| 1986 | #define RXDMA_CFIG2_OFFSET_SHIFT 1 |
| 1987 | #define RXDMA_CFIG2_FULL_HDR 0x0000000000000001ULL |
| 1988 | |
| 1989 | #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL) |
| 1990 | #define RBR_CFIG_A_LEN 0xffff000000000000ULL |
| 1991 | #define RBR_CFIG_A_LEN_SHIFT 48 |
| 1992 | #define RBR_CFIG_A_STADDR_BASE 0x00000ffffffc0000ULL |
| 1993 | #define RBR_CFIG_A_STADDR 0x000000000003ffc0ULL |
| 1994 | |
| 1995 | #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL) |
| 1996 | #define RBR_CFIG_B_BLKSIZE 0x0000000003000000ULL |
| 1997 | #define RBR_CFIG_B_BLKSIZE_SHIFT 24 |
| 1998 | #define RBR_CFIG_B_VLD2 0x0000000000800000ULL |
| 1999 | #define RBR_CFIG_B_BUFSZ2 0x0000000000030000ULL |
| 2000 | #define RBR_CFIG_B_BUFSZ2_SHIFT 16 |
| 2001 | #define RBR_CFIG_B_VLD1 0x0000000000008000ULL |
| 2002 | #define RBR_CFIG_B_BUFSZ1 0x0000000000000300ULL |
| 2003 | #define RBR_CFIG_B_BUFSZ1_SHIFT 8 |
| 2004 | #define RBR_CFIG_B_VLD0 0x0000000000000080ULL |
| 2005 | #define RBR_CFIG_B_BUFSZ0 0x0000000000000003ULL |
| 2006 | #define RBR_CFIG_B_BUFSZ0_SHIFT 0 |
| 2007 | |
| 2008 | #define RBR_BLKSIZE_4K 0x0 |
| 2009 | #define RBR_BLKSIZE_8K 0x1 |
| 2010 | #define RBR_BLKSIZE_16K 0x2 |
| 2011 | #define RBR_BLKSIZE_32K 0x3 |
| 2012 | #define RBR_BUFSZ2_2K 0x0 |
| 2013 | #define RBR_BUFSZ2_4K 0x1 |
| 2014 | #define RBR_BUFSZ2_8K 0x2 |
| 2015 | #define RBR_BUFSZ2_16K 0x3 |
| 2016 | #define RBR_BUFSZ1_1K 0x0 |
| 2017 | #define RBR_BUFSZ1_2K 0x1 |
| 2018 | #define RBR_BUFSZ1_4K 0x2 |
| 2019 | #define RBR_BUFSZ1_8K 0x3 |
| 2020 | #define RBR_BUFSZ0_256 0x0 |
| 2021 | #define RBR_BUFSZ0_512 0x1 |
| 2022 | #define RBR_BUFSZ0_1K 0x2 |
| 2023 | #define RBR_BUFSZ0_2K 0x3 |
| 2024 | |
| 2025 | #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL) |
| 2026 | #define RBR_KICK_BKADD 0x000000000000ffffULL |
| 2027 | |
| 2028 | #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL) |
| 2029 | #define RBR_STAT_QLEN 0x000000000000ffffULL |
| 2030 | |
| 2031 | #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL) |
| 2032 | #define RBR_HDH_HEAD_H 0x0000000000000fffULL |
| 2033 | |
| 2034 | #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL) |
| 2035 | #define RBR_HDL_HEAD_L 0x00000000fffffffcULL |
| 2036 | |
| 2037 | #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL) |
| 2038 | #define RCRCFIG_A_LEN 0xffff000000000000ULL |
| 2039 | #define RCRCFIG_A_LEN_SHIFT 48 |
| 2040 | #define RCRCFIG_A_STADDR_BASE 0x00000ffffff80000ULL |
| 2041 | #define RCRCFIG_A_STADDR 0x000000000007ffc0ULL |
| 2042 | |
| 2043 | #define RCRCFIG_B(IDX) (DMC + 0x00048UL + (IDX) * 0x200UL) |
| 2044 | #define RCRCFIG_B_PTHRES 0x00000000ffff0000ULL |
| 2045 | #define RCRCFIG_B_PTHRES_SHIFT 16 |
| 2046 | #define RCRCFIG_B_ENTOUT 0x0000000000008000ULL |
| 2047 | #define RCRCFIG_B_TIMEOUT 0x000000000000003fULL |
| 2048 | #define RCRCFIG_B_TIMEOUT_SHIFT 0 |
| 2049 | |
| 2050 | #define RCRSTAT_A(IDX) (DMC + 0x00050UL + (IDX) * 0x200UL) |
| 2051 | #define RCRSTAT_A_QLEN 0x000000000000ffffULL |
| 2052 | |
| 2053 | #define RCRSTAT_B(IDX) (DMC + 0x00058UL + (IDX) * 0x200UL) |
| 2054 | #define RCRSTAT_B_TIPTR_H 0x0000000000000fffULL |
| 2055 | |
| 2056 | #define RCRSTAT_C(IDX) (DMC + 0x00060UL + (IDX) * 0x200UL) |
| 2057 | #define RCRSTAT_C_TIPTR_L 0x00000000fffffff8ULL |
| 2058 | |
| 2059 | #define RX_DMA_CTL_STAT(IDX) (DMC + 0x00070UL + (IDX) * 0x200UL) |
| 2060 | #define RX_DMA_CTL_STAT_RBR_TMOUT 0x0020000000000000ULL |
| 2061 | #define RX_DMA_CTL_STAT_RSP_CNT_ERR 0x0010000000000000ULL |
| 2062 | #define RX_DMA_CTL_STAT_BYTE_EN_BUS 0x0008000000000000ULL |
| 2063 | #define RX_DMA_CTL_STAT_RSP_DAT_ERR 0x0004000000000000ULL |
| 2064 | #define RX_DMA_CTL_STAT_RCR_ACK_ERR 0x0002000000000000ULL |
| 2065 | #define RX_DMA_CTL_STAT_DC_FIFO_ERR 0x0001000000000000ULL |
| 2066 | #define RX_DMA_CTL_STAT_MEX 0x0000800000000000ULL |
| 2067 | #define RX_DMA_CTL_STAT_RCRTHRES 0x0000400000000000ULL |
| 2068 | #define RX_DMA_CTL_STAT_RCRTO 0x0000200000000000ULL |
| 2069 | #define RX_DMA_CTL_STAT_RCR_SHA_PAR 0x0000100000000000ULL |
| 2070 | #define RX_DMA_CTL_STAT_RBR_PRE_PAR 0x0000080000000000ULL |
| 2071 | #define RX_DMA_CTL_STAT_PORT_DROP_PKT 0x0000040000000000ULL |
| 2072 | #define RX_DMA_CTL_STAT_WRED_DROP 0x0000020000000000ULL |
| 2073 | #define RX_DMA_CTL_STAT_RBR_PRE_EMTY 0x0000010000000000ULL |
| 2074 | #define RX_DMA_CTL_STAT_RCRSHADOW_FULL 0x0000008000000000ULL |
| 2075 | #define RX_DMA_CTL_STAT_CONFIG_ERR 0x0000004000000000ULL |
| 2076 | #define RX_DMA_CTL_STAT_RCRINCON 0x0000002000000000ULL |
| 2077 | #define RX_DMA_CTL_STAT_RCRFULL 0x0000001000000000ULL |
| 2078 | #define RX_DMA_CTL_STAT_RBR_EMPTY 0x0000000800000000ULL |
| 2079 | #define RX_DMA_CTL_STAT_RBRFULL 0x0000000400000000ULL |
| 2080 | #define RX_DMA_CTL_STAT_RBRLOGPAGE 0x0000000200000000ULL |
| 2081 | #define RX_DMA_CTL_STAT_CFIGLOGPAGE 0x0000000100000000ULL |
| 2082 | #define RX_DMA_CTL_STAT_PTRREAD 0x00000000ffff0000ULL |
| 2083 | #define RX_DMA_CTL_STAT_PTRREAD_SHIFT 16 |
| 2084 | #define RX_DMA_CTL_STAT_PKTREAD 0x000000000000ffffULL |
| 2085 | #define RX_DMA_CTL_STAT_PKTREAD_SHIFT 0 |
| 2086 | |
| 2087 | #define RX_DMA_CTL_STAT_CHAN_FATAL (RX_DMA_CTL_STAT_RBR_TMOUT | \ |
| 2088 | RX_DMA_CTL_STAT_RSP_CNT_ERR | \ |
| 2089 | RX_DMA_CTL_STAT_BYTE_EN_BUS | \ |
| 2090 | RX_DMA_CTL_STAT_RSP_DAT_ERR | \ |
| 2091 | RX_DMA_CTL_STAT_RCR_ACK_ERR | \ |
| 2092 | RX_DMA_CTL_STAT_RCR_SHA_PAR | \ |
| 2093 | RX_DMA_CTL_STAT_RBR_PRE_PAR | \ |
| 2094 | RX_DMA_CTL_STAT_CONFIG_ERR | \ |
| 2095 | RX_DMA_CTL_STAT_RCRINCON | \ |
| 2096 | RX_DMA_CTL_STAT_RCRFULL | \ |
| 2097 | RX_DMA_CTL_STAT_RBRFULL | \ |
| 2098 | RX_DMA_CTL_STAT_RBRLOGPAGE | \ |
| 2099 | RX_DMA_CTL_STAT_CFIGLOGPAGE) |
| 2100 | |
| 2101 | #define RX_DMA_CTL_STAT_PORT_FATAL (RX_DMA_CTL_STAT_DC_FIFO_ERR) |
| 2102 | |
| 2103 | #define RX_DMA_CTL_WRITE_CLEAR_ERRS (RX_DMA_CTL_STAT_RBR_EMPTY | \ |
| 2104 | RX_DMA_CTL_STAT_RCRSHADOW_FULL | \ |
| 2105 | RX_DMA_CTL_STAT_RBR_PRE_EMTY | \ |
| 2106 | RX_DMA_CTL_STAT_WRED_DROP | \ |
| 2107 | RX_DMA_CTL_STAT_PORT_DROP_PKT | \ |
| 2108 | RX_DMA_CTL_STAT_RCRTO | \ |
| 2109 | RX_DMA_CTL_STAT_RCRTHRES | \ |
| 2110 | RX_DMA_CTL_STAT_DC_FIFO_ERR) |
| 2111 | |
| 2112 | #define RCR_FLSH(IDX) (DMC + 0x00078UL + (IDX) * 0x200UL) |
| 2113 | #define RCR_FLSH_FLSH 0x0000000000000001ULL |
| 2114 | |
| 2115 | #define RXMISC(IDX) (DMC + 0x00090UL + (IDX) * 0x200UL) |
| 2116 | #define RXMISC_OFLOW 0x0000000000010000ULL |
| 2117 | #define RXMISC_COUNT 0x000000000000ffffULL |
| 2118 | |
| 2119 | #define RX_DMA_CTL_STAT_DBG(IDX) (DMC + 0x00098UL + (IDX) * 0x200UL) |
| 2120 | #define RX_DMA_CTL_STAT_DBG_RBR_TMOUT 0x0020000000000000ULL |
| 2121 | #define RX_DMA_CTL_STAT_DBG_RSP_CNT_ERR 0x0010000000000000ULL |
| 2122 | #define RX_DMA_CTL_STAT_DBG_BYTE_EN_BUS 0x0008000000000000ULL |
| 2123 | #define RX_DMA_CTL_STAT_DBG_RSP_DAT_ERR 0x0004000000000000ULL |
| 2124 | #define RX_DMA_CTL_STAT_DBG_RCR_ACK_ERR 0x0002000000000000ULL |
| 2125 | #define RX_DMA_CTL_STAT_DBG_DC_FIFO_ERR 0x0001000000000000ULL |
| 2126 | #define RX_DMA_CTL_STAT_DBG_MEX 0x0000800000000000ULL |
| 2127 | #define RX_DMA_CTL_STAT_DBG_RCRTHRES 0x0000400000000000ULL |
| 2128 | #define RX_DMA_CTL_STAT_DBG_RCRTO 0x0000200000000000ULL |
| 2129 | #define RX_DMA_CTL_STAT_DBG_RCR_SHA_PAR 0x0000100000000000ULL |
| 2130 | #define RX_DMA_CTL_STAT_DBG_RBR_PRE_PAR 0x0000080000000000ULL |
| 2131 | #define RX_DMA_CTL_STAT_DBG_PORT_DROP_PKT 0x0000040000000000ULL |
| 2132 | #define RX_DMA_CTL_STAT_DBG_WRED_DROP 0x0000020000000000ULL |
| 2133 | #define RX_DMA_CTL_STAT_DBG_RBR_PRE_EMTY 0x0000010000000000ULL |
| 2134 | #define RX_DMA_CTL_STAT_DBG_RCRSHADOW_FULL 0x0000008000000000ULL |
| 2135 | #define RX_DMA_CTL_STAT_DBG_CONFIG_ERR 0x0000004000000000ULL |
| 2136 | #define RX_DMA_CTL_STAT_DBG_RCRINCON 0x0000002000000000ULL |
| 2137 | #define RX_DMA_CTL_STAT_DBG_RCRFULL 0x0000001000000000ULL |
| 2138 | #define RX_DMA_CTL_STAT_DBG_RBR_EMPTY 0x0000000800000000ULL |
| 2139 | #define RX_DMA_CTL_STAT_DBG_RBRFULL 0x0000000400000000ULL |
| 2140 | #define RX_DMA_CTL_STAT_DBG_RBRLOGPAGE 0x0000000200000000ULL |
| 2141 | #define RX_DMA_CTL_STAT_DBG_CFIGLOGPAGE 0x0000000100000000ULL |
| 2142 | #define RX_DMA_CTL_STAT_DBG_PTRREAD 0x00000000ffff0000ULL |
| 2143 | #define RX_DMA_CTL_STAT_DBG_PKTREAD 0x000000000000ffffULL |
| 2144 | |
| 2145 | #define RX_DMA_ENT_MSK(IDX) (DMC + 0x00068UL + (IDX) * 0x200UL) |
| 2146 | #define RX_DMA_ENT_MSK_RBR_TMOUT 0x0000000000200000ULL |
| 2147 | #define RX_DMA_ENT_MSK_RSP_CNT_ERR 0x0000000000100000ULL |
| 2148 | #define RX_DMA_ENT_MSK_BYTE_EN_BUS 0x0000000000080000ULL |
| 2149 | #define RX_DMA_ENT_MSK_RSP_DAT_ERR 0x0000000000040000ULL |
| 2150 | #define RX_DMA_ENT_MSK_RCR_ACK_ERR 0x0000000000020000ULL |
| 2151 | #define RX_DMA_ENT_MSK_DC_FIFO_ERR 0x0000000000010000ULL |
| 2152 | #define RX_DMA_ENT_MSK_RCRTHRES 0x0000000000004000ULL |
| 2153 | #define RX_DMA_ENT_MSK_RCRTO 0x0000000000002000ULL |
| 2154 | #define RX_DMA_ENT_MSK_RCR_SHA_PAR 0x0000000000001000ULL |
| 2155 | #define RX_DMA_ENT_MSK_RBR_PRE_PAR 0x0000000000000800ULL |
| 2156 | #define RX_DMA_ENT_MSK_PORT_DROP_PKT 0x0000000000000400ULL |
| 2157 | #define RX_DMA_ENT_MSK_WRED_DROP 0x0000000000000200ULL |
| 2158 | #define RX_DMA_ENT_MSK_RBR_PRE_EMTY 0x0000000000000100ULL |
| 2159 | #define RX_DMA_ENT_MSK_RCR_SHADOW_FULL 0x0000000000000080ULL |
| 2160 | #define RX_DMA_ENT_MSK_CONFIG_ERR 0x0000000000000040ULL |
| 2161 | #define RX_DMA_ENT_MSK_RCRINCON 0x0000000000000020ULL |
| 2162 | #define RX_DMA_ENT_MSK_RCRFULL 0x0000000000000010ULL |
| 2163 | #define RX_DMA_ENT_MSK_RBR_EMPTY 0x0000000000000008ULL |
| 2164 | #define RX_DMA_ENT_MSK_RBRFULL 0x0000000000000004ULL |
| 2165 | #define RX_DMA_ENT_MSK_RBRLOGPAGE 0x0000000000000002ULL |
| 2166 | #define RX_DMA_ENT_MSK_CFIGLOGPAGE 0x0000000000000001ULL |
| 2167 | #define RX_DMA_ENT_MSK_ALL 0x00000000003f7fffULL |
| 2168 | |
| 2169 | #define TX_RNG_CFIG(IDX) (DMC + 0x40000UL + (IDX) * 0x200UL) |
| 2170 | #define TX_RNG_CFIG_LEN 0x1fff000000000000ULL |
| 2171 | #define TX_RNG_CFIG_LEN_SHIFT 48 |
| 2172 | #define TX_RNG_CFIG_STADDR_BASE 0x00000ffffff80000ULL |
| 2173 | #define TX_RNG_CFIG_STADDR 0x000000000007ffc0ULL |
| 2174 | |
| 2175 | #define TX_RING_HDL(IDX) (DMC + 0x40010UL + (IDX) * 0x200UL) |
| 2176 | #define TX_RING_HDL_WRAP 0x0000000000080000ULL |
| 2177 | #define TX_RING_HDL_HEAD 0x000000000007fff8ULL |
| 2178 | #define TX_RING_HDL_HEAD_SHIFT 3 |
| 2179 | |
| 2180 | #define TX_RING_KICK(IDX) (DMC + 0x40018UL + (IDX) * 0x200UL) |
| 2181 | #define TX_RING_KICK_WRAP 0x0000000000080000ULL |
| 2182 | #define TX_RING_KICK_TAIL 0x000000000007fff8ULL |
| 2183 | |
| 2184 | #define TX_ENT_MSK(IDX) (DMC + 0x40020UL + (IDX) * 0x200UL) |
| 2185 | #define TX_ENT_MSK_MK 0x0000000000008000ULL |
| 2186 | #define TX_ENT_MSK_MBOX_ERR 0x0000000000000080ULL |
| 2187 | #define TX_ENT_MSK_PKT_SIZE_ERR 0x0000000000000040ULL |
| 2188 | #define TX_ENT_MSK_TX_RING_OFLOW 0x0000000000000020ULL |
| 2189 | #define TX_ENT_MSK_PREF_BUF_ECC_ERR 0x0000000000000010ULL |
| 2190 | #define TX_ENT_MSK_NACK_PREF 0x0000000000000008ULL |
| 2191 | #define TX_ENT_MSK_NACK_PKT_RD 0x0000000000000004ULL |
| 2192 | #define TX_ENT_MSK_CONF_PART_ERR 0x0000000000000002ULL |
| 2193 | #define TX_ENT_MSK_PKT_PRT_ERR 0x0000000000000001ULL |
| 2194 | |
| 2195 | #define TX_CS(IDX) (DMC + 0x40028UL + (IDX)*0x200UL) |
| 2196 | #define TX_CS_PKT_CNT 0x0fff000000000000ULL |
| 2197 | #define TX_CS_PKT_CNT_SHIFT 48 |
| 2198 | #define TX_CS_LASTMARK 0x00000fff00000000ULL |
| 2199 | #define TX_CS_LASTMARK_SHIFT 32 |
| 2200 | #define TX_CS_RST 0x0000000080000000ULL |
| 2201 | #define TX_CS_RST_STATE 0x0000000040000000ULL |
| 2202 | #define TX_CS_MB 0x0000000020000000ULL |
| 2203 | #define TX_CS_STOP_N_GO 0x0000000010000000ULL |
| 2204 | #define TX_CS_SNG_STATE 0x0000000008000000ULL |
| 2205 | #define TX_CS_MK 0x0000000000008000ULL |
| 2206 | #define TX_CS_MMK 0x0000000000004000ULL |
| 2207 | #define TX_CS_MBOX_ERR 0x0000000000000080ULL |
| 2208 | #define TX_CS_PKT_SIZE_ERR 0x0000000000000040ULL |
| 2209 | #define TX_CS_TX_RING_OFLOW 0x0000000000000020ULL |
| 2210 | #define TX_CS_PREF_BUF_PAR_ERR 0x0000000000000010ULL |
| 2211 | #define TX_CS_NACK_PREF 0x0000000000000008ULL |
| 2212 | #define TX_CS_NACK_PKT_RD 0x0000000000000004ULL |
| 2213 | #define TX_CS_CONF_PART_ERR 0x0000000000000002ULL |
| 2214 | #define TX_CS_PKT_PRT_ERR 0x0000000000000001ULL |
| 2215 | |
| 2216 | #define TXDMA_MBH(IDX) (DMC + 0x40030UL + (IDX) * 0x200UL) |
| 2217 | #define TXDMA_MBH_MBADDR 0x0000000000000fffULL |
| 2218 | |
| 2219 | #define TXDMA_MBL(IDX) (DMC + 0x40038UL + (IDX) * 0x200UL) |
| 2220 | #define TXDMA_MBL_MBADDR 0x00000000ffffffc0ULL |
| 2221 | |
| 2222 | #define TX_DMA_PRE_ST(IDX) (DMC + 0x40040UL + (IDX) * 0x200UL) |
| 2223 | #define TX_DMA_PRE_ST_SHADOW_HD 0x000000000007ffffULL |
| 2224 | |
| 2225 | #define TX_RNG_ERR_LOGH(IDX) (DMC + 0x40048UL + (IDX) * 0x200UL) |
| 2226 | #define TX_RNG_ERR_LOGH_ERR 0x0000000080000000ULL |
| 2227 | #define TX_RNG_ERR_LOGH_MERR 0x0000000040000000ULL |
| 2228 | #define TX_RNG_ERR_LOGH_ERRCODE 0x0000000038000000ULL |
| 2229 | #define TX_RNG_ERR_LOGH_ERRADDR 0x0000000000000fffULL |
| 2230 | |
| 2231 | #define TX_RNG_ERR_LOGL(IDX) (DMC + 0x40050UL + (IDX) * 0x200UL) |
| 2232 | #define TX_RNG_ERR_LOGL_ERRADDR 0x00000000ffffffffULL |
| 2233 | |
| 2234 | #define TDMC_INTR_DBG(IDX) (DMC + 0x40060UL + (IDX) * 0x200UL) |
| 2235 | #define TDMC_INTR_DBG_MK 0x0000000000008000ULL |
| 2236 | #define TDMC_INTR_DBG_MBOX_ERR 0x0000000000000080ULL |
| 2237 | #define TDMC_INTR_DBG_PKT_SIZE_ERR 0x0000000000000040ULL |
| 2238 | #define TDMC_INTR_DBG_TX_RING_OFLOW 0x0000000000000020ULL |
| 2239 | #define TDMC_INTR_DBG_PREF_BUF_PAR_ERR 0x0000000000000010ULL |
| 2240 | #define TDMC_INTR_DBG_NACK_PREF 0x0000000000000008ULL |
| 2241 | #define TDMC_INTR_DBG_NACK_PKT_RD 0x0000000000000004ULL |
| 2242 | #define TDMC_INTR_DBG_CONF_PART_ERR 0x0000000000000002ULL |
| 2243 | #define TDMC_INTR_DBG_PKT_PART_ERR 0x0000000000000001ULL |
| 2244 | |
| 2245 | #define TX_CS_DBG(IDX) (DMC + 0x40068UL + (IDX) * 0x200UL) |
| 2246 | #define TX_CS_DBG_PKT_CNT 0x0fff000000000000ULL |
| 2247 | |
| 2248 | #define TDMC_INJ_PAR_ERR(IDX) (DMC + 0x45040UL + (IDX) * 0x200UL) |
| 2249 | #define TDMC_INJ_PAR_ERR_VAL 0x000000000000ffffULL |
| 2250 | |
| 2251 | #define TDMC_DBG_SEL(IDX) (DMC + 0x45080UL + (IDX) * 0x200UL) |
| 2252 | #define TDMC_DBG_SEL_DBG_SEL 0x000000000000003fULL |
| 2253 | |
| 2254 | #define TDMC_TRAINING_VECTOR(IDX) (DMC + 0x45088UL + (IDX) * 0x200UL) |
| 2255 | #define TDMC_TRAINING_VECTOR_VEC 0x00000000ffffffffULL |
| 2256 | |
| 2257 | #define TXC_DMA_MAX(CHAN) (FZC_TXC + 0x00000UL + (CHAN)*0x1000UL) |
| 2258 | #define TXC_DMA_MAX_LEN(CHAN) (FZC_TXC + 0x00008UL + (CHAN)*0x1000UL) |
| 2259 | |
| 2260 | #define TXC_CONTROL (FZC_TXC + 0x20000UL) |
| 2261 | #define TXC_CONTROL_ENABLE 0x0000000000000010ULL |
| 2262 | #define TXC_CONTROL_PORT_ENABLE(X) (1 << (X)) |
| 2263 | |
| 2264 | #define TXC_TRAINING_VEC (FZC_TXC + 0x20008UL) |
| 2265 | #define TXC_TRAINING_VEC_MASK 0x00000000ffffffffULL |
| 2266 | |
| 2267 | #define TXC_DEBUG (FZC_TXC + 0x20010UL) |
| 2268 | #define TXC_DEBUG_SELECT 0x000000000000003fULL |
| 2269 | |
| 2270 | #define TXC_MAX_REORDER (FZC_TXC + 0x20018UL) |
| 2271 | #define TXC_MAX_REORDER_PORT3 0x000000000f000000ULL |
| 2272 | #define TXC_MAX_REORDER_PORT2 0x00000000000f0000ULL |
| 2273 | #define TXC_MAX_REORDER_PORT1 0x0000000000000f00ULL |
| 2274 | #define TXC_MAX_REORDER_PORT0 0x000000000000000fULL |
| 2275 | |
| 2276 | #define TXC_PORT_CTL(PORT) (FZC_TXC + 0x20020UL + (PORT)*0x100UL) |
| 2277 | #define TXC_PORT_CTL_CLR_ALL_STAT 0x0000000000000001ULL |
| 2278 | |
| 2279 | #define TXC_PKT_STUFFED(PORT) (FZC_TXC + 0x20030UL + (PORT)*0x100UL) |
| 2280 | #define TXC_PKT_STUFFED_PP_REORDER 0x00000000ffff0000ULL |
| 2281 | #define TXC_PKT_STUFFED_PP_PACKETASSY 0x000000000000ffffULL |
| 2282 | |
| 2283 | #define TXC_PKT_XMIT(PORT) (FZC_TXC + 0x20038UL + (PORT)*0x100UL) |
| 2284 | #define TXC_PKT_XMIT_BYTES 0x00000000ffff0000ULL |
| 2285 | #define TXC_PKT_XMIT_PKTS 0x000000000000ffffULL |
| 2286 | |
| 2287 | #define TXC_ROECC_CTL(PORT) (FZC_TXC + 0x20040UL + (PORT)*0x100UL) |
| 2288 | #define TXC_ROECC_CTL_DISABLE_UE 0x0000000080000000ULL |
| 2289 | #define TXC_ROECC_CTL_DBL_BIT_ERR 0x0000000000020000ULL |
| 2290 | #define TXC_ROECC_CTL_SNGL_BIT_ERR 0x0000000000010000ULL |
| 2291 | #define TXC_ROECC_CTL_ALL_PKTS 0x0000000000000400ULL |
| 2292 | #define TXC_ROECC_CTL_ALT_PKTS 0x0000000000000200ULL |
| 2293 | #define TXC_ROECC_CTL_ONE_PKT_ONLY 0x0000000000000100ULL |
| 2294 | #define TXC_ROECC_CTL_LST_PKT_LINE 0x0000000000000004ULL |
| 2295 | #define TXC_ROECC_CTL_2ND_PKT_LINE 0x0000000000000002ULL |
| 2296 | #define TXC_ROECC_CTL_1ST_PKT_LINE 0x0000000000000001ULL |
| 2297 | |
| 2298 | #define TXC_ROECC_ST(PORT) (FZC_TXC + 0x20048UL + (PORT)*0x100UL) |
| 2299 | #define TXC_ROECC_CLR_ST 0x0000000080000000ULL |
| 2300 | #define TXC_ROECC_CE 0x0000000000020000ULL |
| 2301 | #define TXC_ROECC_UE 0x0000000000010000ULL |
| 2302 | #define TXC_ROECC_ST_ECC_ADDR 0x00000000000003ffULL |
| 2303 | |
| 2304 | #define TXC_RO_DATA0(PORT) (FZC_TXC + 0x20050UL + (PORT)*0x100UL) |
| 2305 | #define TXC_RO_DATA0_DATA0 0x00000000ffffffffULL /* bits 31:0 */ |
| 2306 | |
| 2307 | #define TXC_RO_DATA1(PORT) (FZC_TXC + 0x20058UL + (PORT)*0x100UL) |
| 2308 | #define TXC_RO_DATA1_DATA1 0x00000000ffffffffULL /* bits 63:32 */ |
| 2309 | |
| 2310 | #define TXC_RO_DATA2(PORT) (FZC_TXC + 0x20060UL + (PORT)*0x100UL) |
| 2311 | #define TXC_RO_DATA2_DATA2 0x00000000ffffffffULL /* bits 95:64 */ |
| 2312 | |
| 2313 | #define TXC_RO_DATA3(PORT) (FZC_TXC + 0x20068UL + (PORT)*0x100UL) |
| 2314 | #define TXC_RO_DATA3_DATA3 0x00000000ffffffffULL /* bits 127:96 */ |
| 2315 | |
| 2316 | #define TXC_RO_DATA4(PORT) (FZC_TXC + 0x20070UL + (PORT)*0x100UL) |
| 2317 | #define TXC_RO_DATA4_DATA4 0x0000000000ffffffULL /* bits 151:128 */ |
| 2318 | |
| 2319 | #define TXC_SFECC_CTL(PORT) (FZC_TXC + 0x20078UL + (PORT)*0x100UL) |
| 2320 | #define TXC_SFECC_CTL_DISABLE_UE 0x0000000080000000ULL |
| 2321 | #define TXC_SFECC_CTL_DBL_BIT_ERR 0x0000000000020000ULL |
| 2322 | #define TXC_SFECC_CTL_SNGL_BIT_ERR 0x0000000000010000ULL |
| 2323 | #define TXC_SFECC_CTL_ALL_PKTS 0x0000000000000400ULL |
| 2324 | #define TXC_SFECC_CTL_ALT_PKTS 0x0000000000000200ULL |
| 2325 | #define TXC_SFECC_CTL_ONE_PKT_ONLY 0x0000000000000100ULL |
| 2326 | #define TXC_SFECC_CTL_LST_PKT_LINE 0x0000000000000004ULL |
| 2327 | #define TXC_SFECC_CTL_2ND_PKT_LINE 0x0000000000000002ULL |
| 2328 | #define TXC_SFECC_CTL_1ST_PKT_LINE 0x0000000000000001ULL |
| 2329 | |
| 2330 | #define TXC_SFECC_ST(PORT) (FZC_TXC + 0x20080UL + (PORT)*0x100UL) |
| 2331 | #define TXC_SFECC_ST_CLR_ST 0x0000000080000000ULL |
| 2332 | #define TXC_SFECC_ST_CE 0x0000000000020000ULL |
| 2333 | #define TXC_SFECC_ST_UE 0x0000000000010000ULL |
| 2334 | #define TXC_SFECC_ST_ECC_ADDR 0x00000000000003ffULL |
| 2335 | |
| 2336 | #define TXC_SF_DATA0(PORT) (FZC_TXC + 0x20088UL + (PORT)*0x100UL) |
| 2337 | #define TXC_SF_DATA0_DATA0 0x00000000ffffffffULL /* bits 31:0 */ |
| 2338 | |
| 2339 | #define TXC_SF_DATA1(PORT) (FZC_TXC + 0x20090UL + (PORT)*0x100UL) |
| 2340 | #define TXC_SF_DATA1_DATA1 0x00000000ffffffffULL /* bits 63:32 */ |
| 2341 | |
| 2342 | #define TXC_SF_DATA2(PORT) (FZC_TXC + 0x20098UL + (PORT)*0x100UL) |
| 2343 | #define TXC_SF_DATA2_DATA2 0x00000000ffffffffULL /* bits 95:64 */ |
| 2344 | |
| 2345 | #define TXC_SF_DATA3(PORT) (FZC_TXC + 0x200a0UL + (PORT)*0x100UL) |
| 2346 | #define TXC_SF_DATA3_DATA3 0x00000000ffffffffULL /* bits 127:96 */ |
| 2347 | |
| 2348 | #define TXC_SF_DATA4(PORT) (FZC_TXC + 0x200a8UL + (PORT)*0x100UL) |
| 2349 | #define TXC_SF_DATA4_DATA4 0x0000000000ffffffULL /* bits 151:128 */ |
| 2350 | |
| 2351 | #define TXC_RO_TIDS(PORT) (FZC_TXC + 0x200b0UL + (PORT)*0x100UL) |
| 2352 | #define TXC_RO_TIDS_IN_USE 0x00000000ffffffffULL |
| 2353 | |
| 2354 | #define TXC_RO_STATE0(PORT) (FZC_TXC + 0x200b8UL + (PORT)*0x100UL) |
| 2355 | #define TXC_RO_STATE0_DUPLICATE_TID 0x00000000ffffffffULL |
| 2356 | |
| 2357 | #define TXC_RO_STATE1(PORT) (FZC_TXC + 0x200c0UL + (PORT)*0x100UL) |
| 2358 | #define TXC_RO_STATE1_UNUSED_TID 0x00000000ffffffffULL |
| 2359 | |
| 2360 | #define TXC_RO_STATE2(PORT) (FZC_TXC + 0x200c8UL + (PORT)*0x100UL) |
| 2361 | #define TXC_RO_STATE2_TRANS_TIMEOUT 0x00000000ffffffffULL |
| 2362 | |
| 2363 | #define TXC_RO_STATE3(PORT) (FZC_TXC + 0x200d0UL + (PORT)*0x100UL) |
| 2364 | #define TXC_RO_STATE3_ENAB_SPC_WMARK 0x0000000080000000ULL |
| 2365 | #define TXC_RO_STATE3_RO_SPC_WMARK 0x000000007fe00000ULL |
| 2366 | #define TXC_RO_STATE3_ROFIFO_SPC_AVAIL 0x00000000001ff800ULL |
| 2367 | #define TXC_RO_STATE3_ENAB_RO_WMARK 0x0000000000000100ULL |
| 2368 | #define TXC_RO_STATE3_HIGH_RO_USED 0x00000000000000f0ULL |
| 2369 | #define TXC_RO_STATE3_NUM_RO_USED 0x000000000000000fULL |
| 2370 | |
| 2371 | #define TXC_RO_CTL(PORT) (FZC_TXC + 0x200d8UL + (PORT)*0x100UL) |
| 2372 | #define TXC_RO_CTL_CLR_FAIL_STATE 0x0000000080000000ULL |
| 2373 | #define TXC_RO_CTL_RO_ADDR 0x000000000f000000ULL |
| 2374 | #define TXC_RO_CTL_ADDR_FAILED 0x0000000000400000ULL |
| 2375 | #define TXC_RO_CTL_DMA_FAILED 0x0000000000200000ULL |
| 2376 | #define TXC_RO_CTL_LEN_FAILED 0x0000000000100000ULL |
| 2377 | #define TXC_RO_CTL_CAPT_ADDR_FAILED 0x0000000000040000ULL |
| 2378 | #define TXC_RO_CTL_CAPT_DMA_FAILED 0x0000000000020000ULL |
| 2379 | #define TXC_RO_CTL_CAPT_LEN_FAILED 0x0000000000010000ULL |
| 2380 | #define TXC_RO_CTL_RO_STATE_RD_DONE 0x0000000000000080ULL |
| 2381 | #define TXC_RO_CTL_RO_STATE_WR_DONE 0x0000000000000040ULL |
| 2382 | #define TXC_RO_CTL_RO_STATE_RD 0x0000000000000020ULL |
| 2383 | #define TXC_RO_CTL_RO_STATE_WR 0x0000000000000010ULL |
| 2384 | #define TXC_RO_CTL_RO_STATE_ADDR 0x000000000000000fULL |
| 2385 | |
| 2386 | #define TXC_RO_ST_DATA0(PORT) (FZC_TXC + 0x200e0UL + (PORT)*0x100UL) |
| 2387 | #define TXC_RO_ST_DATA0_DATA0 0x00000000ffffffffULL |
| 2388 | |
| 2389 | #define TXC_RO_ST_DATA1(PORT) (FZC_TXC + 0x200e8UL + (PORT)*0x100UL) |
| 2390 | #define TXC_RO_ST_DATA1_DATA1 0x00000000ffffffffULL |
| 2391 | |
| 2392 | #define TXC_RO_ST_DATA2(PORT) (FZC_TXC + 0x200f0UL + (PORT)*0x100UL) |
| 2393 | #define TXC_RO_ST_DATA2_DATA2 0x00000000ffffffffULL |
| 2394 | |
| 2395 | #define TXC_RO_ST_DATA3(PORT) (FZC_TXC + 0x200f8UL + (PORT)*0x100UL) |
| 2396 | #define TXC_RO_ST_DATA3_DATA3 0x00000000ffffffffULL |
| 2397 | |
| 2398 | #define TXC_PORT_PACKET_REQ(PORT) (FZC_TXC + 0x20100UL + (PORT)*0x100UL) |
| 2399 | #define TXC_PORT_PACKET_REQ_GATHER_REQ 0x00000000f0000000ULL |
| 2400 | #define TXC_PORT_PACKET_REQ_PKT_REQ 0x000000000fff0000ULL |
| 2401 | #define TXC_PORT_PACKET_REQ_PERR_ABRT 0x000000000000ffffULL |
| 2402 | |
| 2403 | /* bits are same as TXC_INT_STAT */ |
| 2404 | #define TXC_INT_STAT_DBG (FZC_TXC + 0x20420UL) |
| 2405 | |
| 2406 | #define TXC_INT_STAT (FZC_TXC + 0x20428UL) |
| 2407 | #define TXC_INT_STAT_VAL_SHIFT(PORT) ((PORT) * 8) |
| 2408 | #define TXC_INT_STAT_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT)) |
| 2409 | #define TXC_INT_STAT_SF_CE(PORT) (0x01 << TXC_INT_STAT_VAL_SHIFT(PORT)) |
| 2410 | #define TXC_INT_STAT_SF_UE(PORT) (0x02 << TXC_INT_STAT_VAL_SHIFT(PORT)) |
| 2411 | #define TXC_INT_STAT_RO_CE(PORT) (0x04 << TXC_INT_STAT_VAL_SHIFT(PORT)) |
| 2412 | #define TXC_INT_STAT_RO_UE(PORT) (0x08 << TXC_INT_STAT_VAL_SHIFT(PORT)) |
| 2413 | #define TXC_INT_STAT_REORDER_ERR(PORT) (0x10 << TXC_INT_STAT_VAL_SHIFT(PORT)) |
| 2414 | #define TXC_INT_STAT_PKTASM_DEAD(PORT) (0x20 << TXC_INT_STAT_VAL_SHIFT(PORT)) |
| 2415 | |
| 2416 | #define TXC_INT_MASK (FZC_TXC + 0x20430UL) |
| 2417 | #define TXC_INT_MASK_VAL_SHIFT(PORT) ((PORT) * 8) |
| 2418 | #define TXC_INT_MASK_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT)) |
| 2419 | |
| 2420 | #define TXC_INT_MASK_SF_CE 0x01 |
| 2421 | #define TXC_INT_MASK_SF_UE 0x02 |
| 2422 | #define TXC_INT_MASK_RO_CE 0x04 |
| 2423 | #define TXC_INT_MASK_RO_UE 0x08 |
| 2424 | #define TXC_INT_MASK_REORDER_ERR 0x10 |
| 2425 | #define TXC_INT_MASK_PKTASM_DEAD 0x20 |
| 2426 | #define TXC_INT_MASK_ALL 0x3f |
| 2427 | |
| 2428 | #define TXC_PORT_DMA(IDX) (FZC_TXC + 0x20028UL + (IDX)*0x100UL) |
| 2429 | |
| 2430 | #define ESPC_PIO_EN (FZC_PROM + 0x40000UL) |
| 2431 | #define ESPC_PIO_EN_ENABLE 0x0000000000000001ULL |
| 2432 | |
| 2433 | #define ESPC_PIO_STAT (FZC_PROM + 0x40008UL) |
| 2434 | #define ESPC_PIO_STAT_READ_START 0x0000000080000000ULL |
| 2435 | #define ESPC_PIO_STAT_READ_END 0x0000000040000000ULL |
| 2436 | #define ESPC_PIO_STAT_WRITE_INIT 0x0000000020000000ULL |
| 2437 | #define ESPC_PIO_STAT_WRITE_END 0x0000000010000000ULL |
| 2438 | #define ESPC_PIO_STAT_ADDR 0x0000000003ffff00ULL |
| 2439 | #define ESPC_PIO_STAT_ADDR_SHIFT 8 |
| 2440 | #define ESPC_PIO_STAT_DATA 0x00000000000000ffULL |
| 2441 | #define ESPC_PIO_STAT_DATA_SHIFT 0 |
| 2442 | |
| 2443 | #define ESPC_NCR(IDX) (FZC_PROM + 0x40020UL + (IDX)*0x8UL) |
| 2444 | #define ESPC_NCR_VAL 0x00000000ffffffffULL |
| 2445 | |
| 2446 | #define ESPC_MAC_ADDR0 ESPC_NCR(0) |
| 2447 | #define ESPC_MAC_ADDR1 ESPC_NCR(1) |
| 2448 | #define ESPC_NUM_PORTS_MACS ESPC_NCR(2) |
| 2449 | #define ESPC_NUM_PORTS_MACS_VAL 0x00000000000000ffULL |
| 2450 | #define ESPC_MOD_STR_LEN ESPC_NCR(4) |
| 2451 | #define ESPC_MOD_STR_1 ESPC_NCR(5) |
| 2452 | #define ESPC_MOD_STR_2 ESPC_NCR(6) |
| 2453 | #define ESPC_MOD_STR_3 ESPC_NCR(7) |
| 2454 | #define ESPC_MOD_STR_4 ESPC_NCR(8) |
| 2455 | #define ESPC_MOD_STR_5 ESPC_NCR(9) |
| 2456 | #define ESPC_MOD_STR_6 ESPC_NCR(10) |
| 2457 | #define ESPC_MOD_STR_7 ESPC_NCR(11) |
| 2458 | #define ESPC_MOD_STR_8 ESPC_NCR(12) |
| 2459 | #define ESPC_BD_MOD_STR_LEN ESPC_NCR(13) |
| 2460 | #define ESPC_BD_MOD_STR_1 ESPC_NCR(14) |
| 2461 | #define ESPC_BD_MOD_STR_2 ESPC_NCR(15) |
| 2462 | #define ESPC_BD_MOD_STR_3 ESPC_NCR(16) |
| 2463 | #define ESPC_BD_MOD_STR_4 ESPC_NCR(17) |
| 2464 | |
| 2465 | #define ESPC_PHY_TYPE ESPC_NCR(18) |
| 2466 | #define ESPC_PHY_TYPE_PORT0 0x00000000ff000000ULL |
| 2467 | #define ESPC_PHY_TYPE_PORT0_SHIFT 24 |
| 2468 | #define ESPC_PHY_TYPE_PORT1 0x0000000000ff0000ULL |
| 2469 | #define ESPC_PHY_TYPE_PORT1_SHIFT 16 |
| 2470 | #define ESPC_PHY_TYPE_PORT2 0x000000000000ff00ULL |
| 2471 | #define ESPC_PHY_TYPE_PORT2_SHIFT 8 |
| 2472 | #define ESPC_PHY_TYPE_PORT3 0x00000000000000ffULL |
| 2473 | #define ESPC_PHY_TYPE_PORT3_SHIFT 0 |
| 2474 | |
| 2475 | #define ESPC_PHY_TYPE_1G_COPPER 3 |
| 2476 | #define ESPC_PHY_TYPE_1G_FIBER 2 |
| 2477 | #define ESPC_PHY_TYPE_10G_COPPER 1 |
| 2478 | #define ESPC_PHY_TYPE_10G_FIBER 0 |
| 2479 | |
| 2480 | #define ESPC_MAX_FM_SZ ESPC_NCR(19) |
| 2481 | |
| 2482 | #define ESPC_INTR_NUM ESPC_NCR(20) |
| 2483 | #define ESPC_INTR_NUM_PORT0 0x00000000ff000000ULL |
| 2484 | #define ESPC_INTR_NUM_PORT1 0x0000000000ff0000ULL |
| 2485 | #define ESPC_INTR_NUM_PORT2 0x000000000000ff00ULL |
| 2486 | #define ESPC_INTR_NUM_PORT3 0x00000000000000ffULL |
| 2487 | |
| 2488 | #define ESPC_VER_IMGSZ ESPC_NCR(21) |
| 2489 | #define ESPC_VER_IMGSZ_IMGSZ 0x00000000ffff0000ULL |
| 2490 | #define ESPC_VER_IMGSZ_IMGSZ_SHIFT 16 |
| 2491 | #define ESPC_VER_IMGSZ_VER 0x000000000000ffffULL |
| 2492 | #define ESPC_VER_IMGSZ_VER_SHIFT 0 |
| 2493 | |
| 2494 | #define ESPC_CHKSUM ESPC_NCR(22) |
| 2495 | #define ESPC_CHKSUM_SUM 0x00000000000000ffULL |
| 2496 | |
| 2497 | #define ESPC_EEPROM_SIZE 0x100000 |
| 2498 | |
| 2499 | #define CLASS_CODE_UNRECOG 0x00 |
| 2500 | #define CLASS_CODE_DUMMY1 0x01 |
| 2501 | #define CLASS_CODE_ETHERTYPE1 0x02 |
| 2502 | #define CLASS_CODE_ETHERTYPE2 0x03 |
| 2503 | #define CLASS_CODE_USER_PROG1 0x04 |
| 2504 | #define CLASS_CODE_USER_PROG2 0x05 |
| 2505 | #define CLASS_CODE_USER_PROG3 0x06 |
| 2506 | #define CLASS_CODE_USER_PROG4 0x07 |
| 2507 | #define CLASS_CODE_TCP_IPV4 0x08 |
| 2508 | #define CLASS_CODE_UDP_IPV4 0x09 |
| 2509 | #define CLASS_CODE_AH_ESP_IPV4 0x0a |
| 2510 | #define CLASS_CODE_SCTP_IPV4 0x0b |
| 2511 | #define CLASS_CODE_TCP_IPV6 0x0c |
| 2512 | #define CLASS_CODE_UDP_IPV6 0x0d |
| 2513 | #define CLASS_CODE_AH_ESP_IPV6 0x0e |
| 2514 | #define CLASS_CODE_SCTP_IPV6 0x0f |
| 2515 | #define CLASS_CODE_ARP 0x10 |
| 2516 | #define CLASS_CODE_RARP 0x11 |
| 2517 | #define CLASS_CODE_DUMMY2 0x12 |
| 2518 | #define CLASS_CODE_DUMMY3 0x13 |
| 2519 | #define CLASS_CODE_DUMMY4 0x14 |
| 2520 | #define CLASS_CODE_DUMMY5 0x15 |
| 2521 | #define CLASS_CODE_DUMMY6 0x16 |
| 2522 | #define CLASS_CODE_DUMMY7 0x17 |
| 2523 | #define CLASS_CODE_DUMMY8 0x18 |
| 2524 | #define CLASS_CODE_DUMMY9 0x19 |
| 2525 | #define CLASS_CODE_DUMMY10 0x1a |
| 2526 | #define CLASS_CODE_DUMMY11 0x1b |
| 2527 | #define CLASS_CODE_DUMMY12 0x1c |
| 2528 | #define CLASS_CODE_DUMMY13 0x1d |
| 2529 | #define CLASS_CODE_DUMMY14 0x1e |
| 2530 | #define CLASS_CODE_DUMMY15 0x1f |
| 2531 | |
| 2532 | /* Logical devices and device groups */ |
| 2533 | #define LDN_RXDMA(CHAN) (0 + (CHAN)) |
| 2534 | #define LDN_RESV1(OFF) (16 + (OFF)) |
| 2535 | #define LDN_TXDMA(CHAN) (32 + (CHAN)) |
| 2536 | #define LDN_RESV2(OFF) (56 + (OFF)) |
| 2537 | #define LDN_MIF 63 |
| 2538 | #define LDN_MAC(PORT) (64 + (PORT)) |
| 2539 | #define LDN_DEVICE_ERROR 68 |
| 2540 | #define LDN_MAX LDN_DEVICE_ERROR |
| 2541 | |
| 2542 | #define NIU_LDG_MIN 0 |
| 2543 | #define NIU_LDG_MAX 63 |
| 2544 | #define NIU_NUM_LDG 64 |
| 2545 | #define LDG_INVALID 0xff |
| 2546 | |
| 2547 | /* PHY stuff */ |
| 2548 | #define NIU_PMA_PMD_DEV_ADDR 1 |
| 2549 | #define NIU_PCS_DEV_ADDR 3 |
| 2550 | |
| 2551 | #define NIU_PHY_ID_MASK 0xfffff0f0 |
| 2552 | #define NIU_PHY_ID_BCM8704 0x00206030 |
| 2553 | #define NIU_PHY_ID_BCM8706 0x00206035 |
| 2554 | #define NIU_PHY_ID_BCM5464R 0x002060b0 |
| 2555 | #define NIU_PHY_ID_MRVL88X2011 0x01410020 |
| 2556 | |
| 2557 | /* MRVL88X2011 register addresses */ |
| 2558 | #define MRVL88X2011_USER_DEV1_ADDR 1 |
| 2559 | #define MRVL88X2011_USER_DEV2_ADDR 2 |
| 2560 | #define MRVL88X2011_USER_DEV3_ADDR 3 |
| 2561 | #define MRVL88X2011_USER_DEV4_ADDR 4 |
| 2562 | #define MRVL88X2011_PMA_PMD_CTL_1 0x0000 |
| 2563 | #define MRVL88X2011_PMA_PMD_STATUS_1 0x0001 |
| 2564 | #define MRVL88X2011_10G_PMD_STATUS_2 0x0008 |
| 2565 | #define MRVL88X2011_10G_PMD_TX_DIS 0x0009 |
| 2566 | #define MRVL88X2011_10G_XGXS_LANE_STAT 0x0018 |
| 2567 | #define MRVL88X2011_GENERAL_CTL 0x8300 |
| 2568 | #define MRVL88X2011_LED_BLINK_CTL 0x8303 |
| 2569 | #define MRVL88X2011_LED_8_TO_11_CTL 0x8306 |
| 2570 | |
| 2571 | /* MRVL88X2011 register control */ |
| 2572 | #define MRVL88X2011_ENA_XFPREFCLK 0x0001 |
| 2573 | #define MRVL88X2011_ENA_PMDTX 0x0000 |
| 2574 | #define MRVL88X2011_LOOPBACK 0x1 |
| 2575 | #define MRVL88X2011_LED_ACT 0x1 |
| 2576 | #define MRVL88X2011_LNK_STATUS_OK 0x4 |
| 2577 | #define MRVL88X2011_LED_BLKRATE_MASK 0x70 |
| 2578 | #define MRVL88X2011_LED_BLKRATE_034MS 0x0 |
| 2579 | #define MRVL88X2011_LED_BLKRATE_067MS 0x1 |
| 2580 | #define MRVL88X2011_LED_BLKRATE_134MS 0x2 |
| 2581 | #define MRVL88X2011_LED_BLKRATE_269MS 0x3 |
| 2582 | #define MRVL88X2011_LED_BLKRATE_538MS 0x4 |
| 2583 | #define MRVL88X2011_LED_CTL_OFF 0x0 |
| 2584 | #define MRVL88X2011_LED_CTL_PCS_ACT 0x5 |
| 2585 | #define MRVL88X2011_LED_CTL_MASK 0x7 |
| 2586 | #define MRVL88X2011_LED(n,v) ((v)<<((n)*4)) |
| 2587 | #define MRVL88X2011_LED_STAT(n,v) ((v)>>((n)*4)) |
| 2588 | |
| 2589 | #define BCM8704_PMA_PMD_DEV_ADDR 1 |
| 2590 | #define BCM8704_PCS_DEV_ADDR 2 |
| 2591 | #define BCM8704_USER_DEV3_ADDR 3 |
| 2592 | #define BCM8704_PHYXS_DEV_ADDR 4 |
| 2593 | #define BCM8704_USER_DEV4_ADDR 4 |
| 2594 | |
| 2595 | #define BCM8704_PMD_RCV_SIGDET 0x000a |
| 2596 | #define PMD_RCV_SIGDET_LANE3 0x0010 |
| 2597 | #define PMD_RCV_SIGDET_LANE2 0x0008 |
| 2598 | #define PMD_RCV_SIGDET_LANE1 0x0004 |
| 2599 | #define PMD_RCV_SIGDET_LANE0 0x0002 |
| 2600 | #define PMD_RCV_SIGDET_GLOBAL 0x0001 |
| 2601 | |
| 2602 | #define BCM8704_PCS_10G_R_STATUS 0x0020 |
| 2603 | #define PCS_10G_R_STATUS_LINKSTAT 0x1000 |
| 2604 | #define PCS_10G_R_STATUS_PRBS31_ABLE 0x0004 |
| 2605 | #define PCS_10G_R_STATUS_HI_BER 0x0002 |
| 2606 | #define PCS_10G_R_STATUS_BLK_LOCK 0x0001 |
| 2607 | |
| 2608 | #define BCM8704_USER_CONTROL 0xc800 |
| 2609 | #define USER_CONTROL_OPTXENB_LVL 0x8000 |
| 2610 | #define USER_CONTROL_OPTXRST_LVL 0x4000 |
| 2611 | #define USER_CONTROL_OPBIASFLT_LVL 0x2000 |
| 2612 | #define USER_CONTROL_OBTMPFLT_LVL 0x1000 |
| 2613 | #define USER_CONTROL_OPPRFLT_LVL 0x0800 |
| 2614 | #define USER_CONTROL_OPTXFLT_LVL 0x0400 |
| 2615 | #define USER_CONTROL_OPRXLOS_LVL 0x0200 |
| 2616 | #define USER_CONTROL_OPRXFLT_LVL 0x0100 |
| 2617 | #define USER_CONTROL_OPTXON_LVL 0x0080 |
| 2618 | #define USER_CONTROL_RES1 0x007f |
| 2619 | #define USER_CONTROL_RES1_SHIFT 0 |
| 2620 | |
| 2621 | #define BCM8704_USER_ANALOG_CLK 0xc801 |
| 2622 | #define BCM8704_USER_PMD_RX_CONTROL 0xc802 |
| 2623 | |
| 2624 | #define BCM8704_USER_PMD_TX_CONTROL 0xc803 |
| 2625 | #define USER_PMD_TX_CTL_RES1 0xfe00 |
| 2626 | #define USER_PMD_TX_CTL_XFP_CLKEN 0x0100 |
| 2627 | #define USER_PMD_TX_CTL_TX_DAC_TXD 0x00c0 |
| 2628 | #define USER_PMD_TX_CTL_TX_DAC_TXD_SH 6 |
| 2629 | #define USER_PMD_TX_CTL_TX_DAC_TXCK 0x0030 |
| 2630 | #define USER_PMD_TX_CTL_TX_DAC_TXCK_SH 4 |
| 2631 | #define USER_PMD_TX_CTL_TSD_LPWREN 0x0008 |
| 2632 | #define USER_PMD_TX_CTL_TSCK_LPWREN 0x0004 |
| 2633 | #define USER_PMD_TX_CTL_CMU_LPWREN 0x0002 |
| 2634 | #define USER_PMD_TX_CTL_SFIFORST 0x0001 |
| 2635 | |
| 2636 | #define BCM8704_USER_ANALOG_STATUS0 0xc804 |
| 2637 | #define BCM8704_USER_OPT_DIGITAL_CTRL 0xc808 |
| 2638 | #define BCM8704_USER_TX_ALARM_STATUS 0x9004 |
| 2639 | |
| 2640 | #define USER_ODIG_CTRL_FMODE 0x8000 |
| 2641 | #define USER_ODIG_CTRL_TX_PDOWN 0x4000 |
| 2642 | #define USER_ODIG_CTRL_RX_PDOWN 0x2000 |
| 2643 | #define USER_ODIG_CTRL_EFILT_EN 0x1000 |
| 2644 | #define USER_ODIG_CTRL_OPT_RST 0x0800 |
| 2645 | #define USER_ODIG_CTRL_PCS_TIB 0x0400 |
| 2646 | #define USER_ODIG_CTRL_PCS_RI 0x0200 |
| 2647 | #define USER_ODIG_CTRL_RESV1 0x0180 |
| 2648 | #define USER_ODIG_CTRL_GPIOS 0x0060 |
| 2649 | #define USER_ODIG_CTRL_GPIOS_SHIFT 5 |
| 2650 | #define USER_ODIG_CTRL_RESV2 0x0010 |
| 2651 | #define USER_ODIG_CTRL_LB_ERR_DIS 0x0008 |
| 2652 | #define USER_ODIG_CTRL_RESV3 0x0006 |
| 2653 | #define USER_ODIG_CTRL_TXONOFF_PD_DIS 0x0001 |
| 2654 | |
| 2655 | #define BCM8704_PHYXS_XGXS_LANE_STAT 0x0018 |
| 2656 | #define PHYXS_XGXS_LANE_STAT_ALINGED 0x1000 |
| 2657 | #define PHYXS_XGXS_LANE_STAT_PATTEST 0x0800 |
| 2658 | #define PHYXS_XGXS_LANE_STAT_MAGIC 0x0400 |
| 2659 | #define PHYXS_XGXS_LANE_STAT_LANE3 0x0008 |
| 2660 | #define PHYXS_XGXS_LANE_STAT_LANE2 0x0004 |
| 2661 | #define PHYXS_XGXS_LANE_STAT_LANE1 0x0002 |
| 2662 | #define PHYXS_XGXS_LANE_STAT_LANE0 0x0001 |
| 2663 | |
| 2664 | #define BCM5464R_AUX_CTL 24 |
| 2665 | #define BCM5464R_AUX_CTL_EXT_LB 0x8000 |
| 2666 | #define BCM5464R_AUX_CTL_EXT_PLEN 0x4000 |
| 2667 | #define BCM5464R_AUX_CTL_ER1000 0x3000 |
| 2668 | #define BCM5464R_AUX_CTL_ER1000_SHIFT 12 |
| 2669 | #define BCM5464R_AUX_CTL_RESV1 0x0800 |
| 2670 | #define BCM5464R_AUX_CTL_WRITE_1 0x0400 |
| 2671 | #define BCM5464R_AUX_CTL_RESV2 0x0300 |
| 2672 | #define BCM5464R_AUX_CTL_PRESP_DIS 0x0080 |
| 2673 | #define BCM5464R_AUX_CTL_RESV3 0x0040 |
| 2674 | #define BCM5464R_AUX_CTL_ER100 0x0030 |
| 2675 | #define BCM5464R_AUX_CTL_ER100_SHIFT 4 |
| 2676 | #define BCM5464R_AUX_CTL_DIAG_MODE 0x0008 |
| 2677 | #define BCM5464R_AUX_CTL_SR_SEL 0x0007 |
| 2678 | #define BCM5464R_AUX_CTL_SR_SEL_SHIFT 0 |
| 2679 | |
| 2680 | #define BCM5464R_CTRL1000_AS_MASTER 0x0800 |
| 2681 | #define BCM5464R_CTRL1000_ENABLE_AS_MASTER 0x1000 |
| 2682 | |
| 2683 | #define RCR_ENTRY_MULTI 0x8000000000000000ULL |
| 2684 | #define RCR_ENTRY_PKT_TYPE 0x6000000000000000ULL |
| 2685 | #define RCR_ENTRY_PKT_TYPE_SHIFT 61 |
| 2686 | #define RCR_ENTRY_ZERO_COPY 0x1000000000000000ULL |
| 2687 | #define RCR_ENTRY_NOPORT 0x0800000000000000ULL |
| 2688 | #define RCR_ENTRY_PROMISC 0x0400000000000000ULL |
| 2689 | #define RCR_ENTRY_ERROR 0x0380000000000000ULL |
| 2690 | #define RCR_ENTRY_DCF_ERR 0x0040000000000000ULL |
| 2691 | #define RCR_ENTRY_L2_LEN 0x003fff0000000000ULL |
| 2692 | #define RCR_ENTRY_L2_LEN_SHIFT 40 |
| 2693 | #define RCR_ENTRY_PKTBUFSZ 0x000000c000000000ULL |
| 2694 | #define RCR_ENTRY_PKTBUFSZ_SHIFT 38 |
| 2695 | #define RCR_ENTRY_PKT_BUF_ADDR 0x0000003fffffffffULL /* bits 43:6 */ |
| 2696 | #define RCR_ENTRY_PKT_BUF_ADDR_SHIFT 6 |
| 2697 | |
| 2698 | #define RCR_PKT_TYPE_OTHER 0x0 |
| 2699 | #define RCR_PKT_TYPE_TCP 0x1 |
| 2700 | #define RCR_PKT_TYPE_UDP 0x2 |
| 2701 | #define RCR_PKT_TYPE_SCTP 0x3 |
| 2702 | |
| 2703 | #define NIU_RXPULL_MAX ETH_HLEN |
| 2704 | |
| 2705 | struct rx_pkt_hdr0 { |
| 2706 | #if defined(__LITTLE_ENDIAN_BITFIELD) |
| 2707 | u8 inputport:2, |
| 2708 | maccheck:1, |
| 2709 | class:4; |
| 2710 | u8 vlan:1, |
| 2711 | llcsnap:1, |
| 2712 | noport:1, |
| 2713 | badip:1, |
| 2714 | tcamhit:1, |
| 2715 | tres:2, |
| 2716 | tzfvld:1; |
| 2717 | #elif defined(__BIG_ENDIAN_BITFIELD) |
| 2718 | u8 class:4, |
| 2719 | maccheck:1, |
| 2720 | inputport:2; |
| 2721 | u8 tzfvld:1, |
| 2722 | tres:2, |
| 2723 | tcamhit:1, |
| 2724 | badip:1, |
| 2725 | noport:1, |
| 2726 | llcsnap:1, |
| 2727 | vlan:1; |
| 2728 | #endif |
| 2729 | }; |
| 2730 | |
| 2731 | struct rx_pkt_hdr1 { |
| 2732 | u8 hwrsvd1; |
| 2733 | u8 tcammatch; |
| 2734 | #if defined(__LITTLE_ENDIAN_BITFIELD) |
| 2735 | u8 hwrsvd2:2, |
| 2736 | hashit:1, |
| 2737 | exact:1, |
| 2738 | hzfvld:1, |
| 2739 | hashsidx:3; |
| 2740 | #elif defined(__BIG_ENDIAN_BITFIELD) |
| 2741 | u8 hashsidx:3, |
| 2742 | hzfvld:1, |
| 2743 | exact:1, |
| 2744 | hashit:1, |
| 2745 | hwrsvd2:2; |
| 2746 | #endif |
| 2747 | u8 zcrsvd; |
| 2748 | |
| 2749 | /* Bits 11:8 of zero copy flow ID. */ |
| 2750 | #if defined(__LITTLE_ENDIAN_BITFIELD) |
| 2751 | u8 hwrsvd3:4, zflowid0:4; |
| 2752 | #elif defined(__BIG_ENDIAN_BITFIELD) |
| 2753 | u8 zflowid0:4, hwrsvd3:4; |
| 2754 | #endif |
| 2755 | |
| 2756 | /* Bits 7:0 of zero copy flow ID. */ |
| 2757 | u8 zflowid1; |
| 2758 | |
| 2759 | /* Bits 15:8 of hash value, H2. */ |
| 2760 | u8 hashval2_0; |
| 2761 | |
| 2762 | /* Bits 7:0 of hash value, H2. */ |
| 2763 | u8 hashval2_1; |
| 2764 | |
| 2765 | /* Bits 19:16 of hash value, H1. */ |
| 2766 | #if defined(__LITTLE_ENDIAN_BITFIELD) |
| 2767 | u8 hwrsvd4:4, hashval1_0:4; |
| 2768 | #elif defined(__BIG_ENDIAN_BITFIELD) |
| 2769 | u8 hashval1_0:4, hwrsvd4:4; |
| 2770 | #endif |
| 2771 | |
| 2772 | /* Bits 15:8 of hash value, H1. */ |
| 2773 | u8 hashval1_1; |
| 2774 | |
| 2775 | /* Bits 7:0 of hash value, H1. */ |
| 2776 | u8 hashval1_2; |
| 2777 | |
| 2778 | u8 usrdata_0; /* Bits 39:32 of user data. */ |
| 2779 | u8 usrdata_1; /* Bits 31:24 of user data. */ |
| 2780 | u8 usrdata_2; /* Bits 23:16 of user data. */ |
| 2781 | u8 usrdata_3; /* Bits 15:8 of user data. */ |
| 2782 | u8 usrdata_4; /* Bits 7:0 of user data. */ |
| 2783 | }; |
| 2784 | |
| 2785 | struct tx_dma_mbox { |
| 2786 | u64 tx_dma_pre_st; |
| 2787 | u64 tx_cs; |
| 2788 | u64 tx_ring_kick; |
| 2789 | u64 tx_ring_hdl; |
| 2790 | u64 resv1; |
| 2791 | u32 tx_rng_err_logl; |
| 2792 | u32 tx_rng_err_logh; |
| 2793 | u64 resv2; |
| 2794 | u64 resv3; |
| 2795 | }; |
| 2796 | |
| 2797 | struct tx_pkt_hdr { |
| 2798 | __le64 flags; |
| 2799 | #define TXHDR_PAD 0x0000000000000007ULL |
| 2800 | #define TXHDR_PAD_SHIFT 0 |
| 2801 | #define TXHDR_LEN 0x000000003fff0000ULL |
| 2802 | #define TXHDR_LEN_SHIFT 16 |
| 2803 | #define TXHDR_L4STUFF 0x0000003f00000000ULL |
| 2804 | #define TXHDR_L4STUFF_SHIFT 32 |
| 2805 | #define TXHDR_L4START 0x00003f0000000000ULL |
| 2806 | #define TXHDR_L4START_SHIFT 40 |
| 2807 | #define TXHDR_L3START 0x000f000000000000ULL |
| 2808 | #define TXHDR_L3START_SHIFT 48 |
| 2809 | #define TXHDR_IHL 0x00f0000000000000ULL |
| 2810 | #define TXHDR_IHL_SHIFT 52 |
| 2811 | #define TXHDR_VLAN 0x0100000000000000ULL |
| 2812 | #define TXHDR_LLC 0x0200000000000000ULL |
| 2813 | #define TXHDR_IP_VER 0x2000000000000000ULL |
| 2814 | #define TXHDR_CSUM_NONE 0x0000000000000000ULL |
| 2815 | #define TXHDR_CSUM_TCP 0x4000000000000000ULL |
| 2816 | #define TXHDR_CSUM_UDP 0x8000000000000000ULL |
| 2817 | #define TXHDR_CSUM_SCTP 0xc000000000000000ULL |
| 2818 | __le64 resv; |
| 2819 | }; |
| 2820 | |
| 2821 | #define TX_DESC_SOP 0x8000000000000000ULL |
| 2822 | #define TX_DESC_MARK 0x4000000000000000ULL |
| 2823 | #define TX_DESC_NUM_PTR 0x3c00000000000000ULL |
| 2824 | #define TX_DESC_NUM_PTR_SHIFT 58 |
| 2825 | #define TX_DESC_TR_LEN 0x01fff00000000000ULL |
| 2826 | #define TX_DESC_TR_LEN_SHIFT 44 |
| 2827 | #define TX_DESC_SAD 0x00000fffffffffffULL |
| 2828 | #define TX_DESC_SAD_SHIFT 0 |
| 2829 | |
| 2830 | struct tx_buff_info { |
| 2831 | struct sk_buff *skb; |
| 2832 | u64 mapping; |
| 2833 | }; |
| 2834 | |
| 2835 | struct txdma_mailbox { |
| 2836 | __le64 tx_dma_pre_st; |
| 2837 | __le64 tx_cs; |
| 2838 | __le64 tx_ring_kick; |
| 2839 | __le64 tx_ring_hdl; |
| 2840 | __le64 resv1; |
| 2841 | __le32 tx_rng_err_logl; |
| 2842 | __le32 tx_rng_err_logh; |
| 2843 | __le64 resv2[2]; |
| 2844 | } __attribute__((aligned(64))); |
| 2845 | |
| 2846 | #define MAX_TX_RING_SIZE 256 |
| 2847 | #define MAX_TX_DESC_LEN 4076 |
| 2848 | |
| 2849 | struct tx_ring_info { |
| 2850 | struct tx_buff_info tx_buffs[MAX_TX_RING_SIZE]; |
| 2851 | struct niu *np; |
| 2852 | u64 tx_cs; |
| 2853 | int pending; |
| 2854 | int prod; |
| 2855 | int cons; |
| 2856 | int wrap_bit; |
| 2857 | u16 last_pkt_cnt; |
| 2858 | u16 tx_channel; |
| 2859 | u16 mark_counter; |
| 2860 | u16 mark_freq; |
| 2861 | u16 mark_pending; |
| 2862 | u16 __pad; |
| 2863 | struct txdma_mailbox *mbox; |
| 2864 | __le64 *descr; |
| 2865 | |
| 2866 | u64 tx_packets; |
| 2867 | u64 tx_bytes; |
| 2868 | u64 tx_errors; |
| 2869 | |
| 2870 | u64 mbox_dma; |
| 2871 | u64 descr_dma; |
| 2872 | int max_burst; |
| 2873 | }; |
| 2874 | |
| 2875 | #define NEXT_TX(tp, index) \ |
| 2876 | (((index) + 1) < (tp)->pending ? ((index) + 1) : 0) |
| 2877 | |
| 2878 | static inline u32 niu_tx_avail(struct tx_ring_info *tp) |
| 2879 | { |
| 2880 | return (tp->pending - |
| 2881 | ((tp->prod - tp->cons) & (MAX_TX_RING_SIZE - 1))); |
| 2882 | } |
| 2883 | |
| 2884 | struct rxdma_mailbox { |
| 2885 | __le64 rx_dma_ctl_stat; |
| 2886 | __le64 rbr_stat; |
| 2887 | __le32 rbr_hdl; |
| 2888 | __le32 rbr_hdh; |
| 2889 | __le64 resv1; |
| 2890 | __le32 rcrstat_c; |
| 2891 | __le32 rcrstat_b; |
| 2892 | __le64 rcrstat_a; |
| 2893 | __le64 resv2[2]; |
| 2894 | } __attribute__((aligned(64))); |
| 2895 | |
| 2896 | #define MAX_RBR_RING_SIZE 128 |
| 2897 | #define MAX_RCR_RING_SIZE (MAX_RBR_RING_SIZE * 2) |
| 2898 | |
| 2899 | #define RBR_REFILL_MIN 16 |
| 2900 | |
| 2901 | #define RX_SKB_ALLOC_SIZE 128 + NET_IP_ALIGN |
| 2902 | |
| 2903 | struct rx_ring_info { |
| 2904 | struct niu *np; |
| 2905 | int rx_channel; |
| 2906 | u16 rbr_block_size; |
| 2907 | u16 rbr_blocks_per_page; |
| 2908 | u16 rbr_sizes[4]; |
| 2909 | unsigned int rcr_index; |
| 2910 | unsigned int rcr_table_size; |
| 2911 | unsigned int rbr_index; |
| 2912 | unsigned int rbr_pending; |
| 2913 | unsigned int rbr_refill_pending; |
| 2914 | unsigned int rbr_kick_thresh; |
| 2915 | unsigned int rbr_table_size; |
| 2916 | struct page **rxhash; |
| 2917 | struct rxdma_mailbox *mbox; |
| 2918 | __le64 *rcr; |
| 2919 | __le32 *rbr; |
| 2920 | #define RBR_DESCR_ADDR_SHIFT 12 |
| 2921 | |
| 2922 | u64 rx_packets; |
| 2923 | u64 rx_bytes; |
| 2924 | u64 rx_dropped; |
| 2925 | u64 rx_errors; |
| 2926 | |
| 2927 | u64 mbox_dma; |
| 2928 | u64 rcr_dma; |
| 2929 | u64 rbr_dma; |
| 2930 | |
| 2931 | /* WRED */ |
| 2932 | int nonsyn_window; |
| 2933 | int nonsyn_threshold; |
| 2934 | int syn_window; |
| 2935 | int syn_threshold; |
| 2936 | |
| 2937 | /* interrupt mitigation */ |
| 2938 | int rcr_pkt_threshold; |
| 2939 | int rcr_timeout; |
| 2940 | }; |
| 2941 | |
| 2942 | #define NEXT_RCR(rp, index) \ |
| 2943 | (((index) + 1) < (rp)->rcr_table_size ? ((index) + 1) : 0) |
| 2944 | #define NEXT_RBR(rp, index) \ |
| 2945 | (((index) + 1) < (rp)->rbr_table_size ? ((index) + 1) : 0) |
| 2946 | |
| 2947 | #define NIU_MAX_PORTS 4 |
| 2948 | #define NIU_NUM_RXCHAN 16 |
| 2949 | #define NIU_NUM_TXCHAN 24 |
| 2950 | #define MAC_NUM_HASH 16 |
| 2951 | |
| 2952 | #define NIU_MAX_MTU 9216 |
| 2953 | |
| 2954 | /* VPD strings */ |
| 2955 | #define NIU_QGC_LP_BM_STR "501-7606" |
| 2956 | #define NIU_2XGF_LP_BM_STR "501-7283" |
| 2957 | #define NIU_QGC_PEM_BM_STR "501-7765" |
| 2958 | #define NIU_2XGF_PEM_BM_STR "501-7626" |
| 2959 | #define NIU_ALONSO_BM_STR "373-0202" |
| 2960 | #define NIU_FOXXY_BM_STR "501-7961" |
| 2961 | #define NIU_2XGF_MRVL_BM_STR "SK-6E82" |
| 2962 | #define NIU_QGC_LP_MDL_STR "SUNW,pcie-qgc" |
| 2963 | #define NIU_2XGF_LP_MDL_STR "SUNW,pcie-2xgf" |
| 2964 | #define NIU_QGC_PEM_MDL_STR "SUNW,pcie-qgc-pem" |
| 2965 | #define NIU_2XGF_PEM_MDL_STR "SUNW,pcie-2xgf-pem" |
| 2966 | #define NIU_ALONSO_MDL_STR "SUNW,CP3220" |
| 2967 | #define NIU_KIMI_MDL_STR "SUNW,CP3260" |
| 2968 | #define NIU_MARAMBA_MDL_STR "SUNW,pcie-neptune" |
| 2969 | #define NIU_FOXXY_MDL_STR "SUNW,pcie-rfem" |
| 2970 | #define NIU_2XGF_MRVL_MDL_STR "SysKonnect,pcie-2xgf" |
| 2971 | |
| 2972 | #define NIU_VPD_MIN_MAJOR 3 |
| 2973 | #define NIU_VPD_MIN_MINOR 4 |
| 2974 | |
| 2975 | #define NIU_VPD_MODEL_MAX 32 |
| 2976 | #define NIU_VPD_BD_MODEL_MAX 16 |
| 2977 | #define NIU_VPD_VERSION_MAX 64 |
| 2978 | #define NIU_VPD_PHY_TYPE_MAX 8 |
| 2979 | |
| 2980 | struct niu_vpd { |
| 2981 | char model[NIU_VPD_MODEL_MAX]; |
| 2982 | char board_model[NIU_VPD_BD_MODEL_MAX]; |
| 2983 | char version[NIU_VPD_VERSION_MAX]; |
| 2984 | char phy_type[NIU_VPD_PHY_TYPE_MAX]; |
| 2985 | u8 mac_num; |
| 2986 | u8 __pad; |
| 2987 | u8 local_mac[6]; |
| 2988 | int fcode_major; |
| 2989 | int fcode_minor; |
| 2990 | }; |
| 2991 | |
| 2992 | struct niu_altmac_rdc { |
| 2993 | u8 alt_mac_num; |
| 2994 | u8 rdc_num; |
| 2995 | u8 mac_pref; |
| 2996 | }; |
| 2997 | |
| 2998 | struct niu_vlan_rdc { |
| 2999 | u8 rdc_num; |
| 3000 | u8 vlan_pref; |
| 3001 | }; |
| 3002 | |
| 3003 | struct niu_classifier { |
| 3004 | struct niu_altmac_rdc alt_mac_mappings[16]; |
| 3005 | struct niu_vlan_rdc vlan_mappings[ENET_VLAN_TBL_NUM_ENTRIES]; |
| 3006 | |
| 3007 | u16 tcam_top; |
| 3008 | u16 tcam_sz; |
| 3009 | u16 tcam_valid_entries; |
| 3010 | u16 num_alt_mac_mappings; |
| 3011 | |
| 3012 | u32 h1_init; |
| 3013 | u16 h2_init; |
| 3014 | }; |
| 3015 | |
| 3016 | #define NIU_NUM_RDC_TABLES 8 |
| 3017 | #define NIU_RDC_TABLE_SLOTS 16 |
| 3018 | |
| 3019 | struct rdc_table { |
| 3020 | u8 rxdma_channel[NIU_RDC_TABLE_SLOTS]; |
| 3021 | }; |
| 3022 | |
| 3023 | struct niu_rdc_tables { |
| 3024 | struct rdc_table tables[NIU_NUM_RDC_TABLES]; |
| 3025 | int first_table_num; |
| 3026 | int num_tables; |
| 3027 | }; |
| 3028 | |
| 3029 | #define PHY_TYPE_PMA_PMD 0 |
| 3030 | #define PHY_TYPE_PCS 1 |
| 3031 | #define PHY_TYPE_MII 2 |
| 3032 | #define PHY_TYPE_MAX 3 |
| 3033 | |
| 3034 | struct phy_probe_info { |
| 3035 | u32 phy_id[PHY_TYPE_MAX][NIU_MAX_PORTS]; |
| 3036 | u8 phy_port[PHY_TYPE_MAX][NIU_MAX_PORTS]; |
| 3037 | u8 cur[PHY_TYPE_MAX]; |
| 3038 | |
| 3039 | struct device_attribute phy_port_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS]; |
| 3040 | struct device_attribute phy_type_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS]; |
| 3041 | struct device_attribute phy_id_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS]; |
| 3042 | }; |
| 3043 | |
| 3044 | struct niu_tcam_entry { |
| 3045 | u8 valid; |
| 3046 | u64 key[4]; |
| 3047 | u64 key_mask[4]; |
| 3048 | u64 assoc_data; |
| 3049 | }; |
| 3050 | |
| 3051 | struct device_node; |
| 3052 | union niu_parent_id { |
| 3053 | struct { |
| 3054 | int domain; |
| 3055 | int bus; |
| 3056 | int device; |
| 3057 | } pci; |
| 3058 | struct device_node *of; |
| 3059 | }; |
| 3060 | |
| 3061 | struct niu; |
| 3062 | struct niu_parent { |
| 3063 | struct platform_device *plat_dev; |
| 3064 | int index; |
| 3065 | |
| 3066 | union niu_parent_id id; |
| 3067 | |
| 3068 | struct niu *ports[NIU_MAX_PORTS]; |
| 3069 | |
| 3070 | atomic_t refcnt; |
| 3071 | struct list_head list; |
| 3072 | |
| 3073 | spinlock_t lock; |
| 3074 | |
| 3075 | u32 flags; |
| 3076 | #define PARENT_FLGS_CLS_HWINIT 0x00000001 |
| 3077 | |
| 3078 | u32 port_phy; |
| 3079 | #define PORT_PHY_UNKNOWN 0x00000000 |
| 3080 | #define PORT_PHY_INVALID 0xffffffff |
| 3081 | #define PORT_TYPE_10G 0x01 |
| 3082 | #define PORT_TYPE_1G 0x02 |
| 3083 | #define PORT_TYPE_MASK 0x03 |
| 3084 | |
| 3085 | u8 rxchan_per_port[NIU_MAX_PORTS]; |
| 3086 | u8 txchan_per_port[NIU_MAX_PORTS]; |
| 3087 | |
| 3088 | struct niu_rdc_tables rdc_group_cfg[NIU_MAX_PORTS]; |
| 3089 | u8 rdc_default[NIU_MAX_PORTS]; |
| 3090 | |
| 3091 | u8 ldg_map[LDN_MAX + 1]; |
| 3092 | |
| 3093 | u8 plat_type; |
| 3094 | #define PLAT_TYPE_INVALID 0x00 |
| 3095 | #define PLAT_TYPE_ATLAS 0x01 |
| 3096 | #define PLAT_TYPE_NIU 0x02 |
| 3097 | #define PLAT_TYPE_VF_P0 0x03 |
| 3098 | #define PLAT_TYPE_VF_P1 0x04 |
| 3099 | #define PLAT_TYPE_ATCA_CP3220 0x08 |
| 3100 | |
| 3101 | u8 num_ports; |
| 3102 | |
| 3103 | u16 tcam_num_entries; |
| 3104 | #define NIU_PCI_TCAM_ENTRIES 256 |
| 3105 | #define NIU_NONPCI_TCAM_ENTRIES 128 |
| 3106 | #define NIU_TCAM_ENTRIES_MAX 256 |
| 3107 | |
| 3108 | int rxdma_clock_divider; |
| 3109 | |
| 3110 | struct phy_probe_info phy_probe_info; |
| 3111 | |
| 3112 | struct niu_tcam_entry tcam[NIU_TCAM_ENTRIES_MAX]; |
| 3113 | |
| 3114 | #define NIU_L2_PROG_CLS 2 |
| 3115 | #define NIU_L3_PROG_CLS 4 |
| 3116 | u64 l2_cls[NIU_L2_PROG_CLS]; |
| 3117 | u64 l3_cls[NIU_L3_PROG_CLS]; |
| 3118 | u64 tcam_key[12]; |
| 3119 | u64 flow_key[12]; |
| 3120 | u16 l3_cls_refcnt[NIU_L3_PROG_CLS]; |
| 3121 | u8 l3_cls_pid[NIU_L3_PROG_CLS]; |
| 3122 | }; |
| 3123 | |
| 3124 | struct niu_ops { |
| 3125 | void *(*alloc_coherent)(struct device *dev, size_t size, |
| 3126 | u64 *handle, gfp_t flag); |
| 3127 | void (*free_coherent)(struct device *dev, size_t size, |
| 3128 | void *cpu_addr, u64 handle); |
| 3129 | u64 (*map_page)(struct device *dev, struct page *page, |
| 3130 | unsigned long offset, size_t size, |
| 3131 | enum dma_data_direction direction); |
| 3132 | void (*unmap_page)(struct device *dev, u64 dma_address, |
| 3133 | size_t size, enum dma_data_direction direction); |
| 3134 | u64 (*map_single)(struct device *dev, void *cpu_addr, |
| 3135 | size_t size, |
| 3136 | enum dma_data_direction direction); |
| 3137 | void (*unmap_single)(struct device *dev, u64 dma_address, |
| 3138 | size_t size, enum dma_data_direction direction); |
| 3139 | }; |
| 3140 | |
| 3141 | struct niu_link_config { |
| 3142 | u32 supported; |
| 3143 | |
| 3144 | /* Describes what we're trying to get. */ |
| 3145 | u32 advertising; |
| 3146 | u16 speed; |
| 3147 | u8 duplex; |
| 3148 | u8 autoneg; |
| 3149 | |
| 3150 | /* Describes what we actually have. */ |
| 3151 | u32 active_advertising; |
| 3152 | u16 active_speed; |
| 3153 | u8 active_duplex; |
| 3154 | u8 active_autoneg; |
| 3155 | #define SPEED_INVALID 0xffff |
| 3156 | #define DUPLEX_INVALID 0xff |
| 3157 | #define AUTONEG_INVALID 0xff |
| 3158 | |
| 3159 | u8 loopback_mode; |
| 3160 | #define LOOPBACK_DISABLED 0x00 |
| 3161 | #define LOOPBACK_PHY 0x01 |
| 3162 | #define LOOPBACK_MAC 0x02 |
| 3163 | }; |
| 3164 | |
| 3165 | struct niu_ldg { |
| 3166 | struct napi_struct napi; |
| 3167 | struct niu *np; |
| 3168 | u8 ldg_num; |
| 3169 | u8 timer; |
| 3170 | u64 v0, v1, v2; |
| 3171 | unsigned int irq; |
| 3172 | }; |
| 3173 | |
| 3174 | struct niu_xmac_stats { |
| 3175 | u64 tx_frames; |
| 3176 | u64 tx_bytes; |
| 3177 | u64 tx_fifo_errors; |
| 3178 | u64 tx_overflow_errors; |
| 3179 | u64 tx_max_pkt_size_errors; |
| 3180 | u64 tx_underflow_errors; |
| 3181 | |
| 3182 | u64 rx_local_faults; |
| 3183 | u64 rx_remote_faults; |
| 3184 | u64 rx_link_faults; |
| 3185 | u64 rx_align_errors; |
| 3186 | u64 rx_frags; |
| 3187 | u64 rx_mcasts; |
| 3188 | u64 rx_bcasts; |
| 3189 | u64 rx_hist_cnt1; |
| 3190 | u64 rx_hist_cnt2; |
| 3191 | u64 rx_hist_cnt3; |
| 3192 | u64 rx_hist_cnt4; |
| 3193 | u64 rx_hist_cnt5; |
| 3194 | u64 rx_hist_cnt6; |
| 3195 | u64 rx_hist_cnt7; |
| 3196 | u64 rx_octets; |
| 3197 | u64 rx_code_violations; |
| 3198 | u64 rx_len_errors; |
| 3199 | u64 rx_crc_errors; |
| 3200 | u64 rx_underflows; |
| 3201 | u64 rx_overflows; |
| 3202 | |
| 3203 | u64 pause_off_state; |
| 3204 | u64 pause_on_state; |
| 3205 | u64 pause_received; |
| 3206 | }; |
| 3207 | |
| 3208 | struct niu_bmac_stats { |
| 3209 | u64 tx_underflow_errors; |
| 3210 | u64 tx_max_pkt_size_errors; |
| 3211 | u64 tx_bytes; |
| 3212 | u64 tx_frames; |
| 3213 | |
| 3214 | u64 rx_overflows; |
| 3215 | u64 rx_frames; |
| 3216 | u64 rx_align_errors; |
| 3217 | u64 rx_crc_errors; |
| 3218 | u64 rx_len_errors; |
| 3219 | |
| 3220 | u64 pause_off_state; |
| 3221 | u64 pause_on_state; |
| 3222 | u64 pause_received; |
| 3223 | }; |
| 3224 | |
| 3225 | union niu_mac_stats { |
| 3226 | struct niu_xmac_stats xmac; |
| 3227 | struct niu_bmac_stats bmac; |
| 3228 | }; |
| 3229 | |
| 3230 | struct niu_phy_ops { |
| 3231 | int (*serdes_init)(struct niu *np); |
| 3232 | int (*xcvr_init)(struct niu *np); |
| 3233 | int (*link_status)(struct niu *np, int *); |
| 3234 | }; |
| 3235 | |
| 3236 | struct of_device; |
| 3237 | struct niu { |
| 3238 | void __iomem *regs; |
| 3239 | struct net_device *dev; |
| 3240 | struct pci_dev *pdev; |
| 3241 | struct device *device; |
| 3242 | struct niu_parent *parent; |
| 3243 | |
| 3244 | u32 flags; |
| 3245 | #define NIU_FLAGS_HOTPLUG_PHY_PRESENT 0x02000000 /* Removeable PHY detected*/ |
| 3246 | #define NIU_FLAGS_HOTPLUG_PHY 0x01000000 /* Removeable PHY */ |
| 3247 | #define NIU_FLAGS_VPD_VALID 0x00800000 /* VPD has valid version */ |
| 3248 | #define NIU_FLAGS_MSIX 0x00400000 /* MSI-X in use */ |
| 3249 | #define NIU_FLAGS_MCAST 0x00200000 /* multicast filter enabled */ |
| 3250 | #define NIU_FLAGS_PROMISC 0x00100000 /* PROMISC enabled */ |
| 3251 | #define NIU_FLAGS_XCVR_SERDES 0x00080000 /* 0=PHY 1=SERDES */ |
| 3252 | #define NIU_FLAGS_10G 0x00040000 /* 0=1G 1=10G */ |
| 3253 | #define NIU_FLAGS_FIBER 0x00020000 /* 0=COPPER 1=FIBER */ |
| 3254 | #define NIU_FLAGS_XMAC 0x00010000 /* 0=BMAC 1=XMAC */ |
| 3255 | |
| 3256 | u32 msg_enable; |
| 3257 | char irq_name[NIU_NUM_RXCHAN+NIU_NUM_TXCHAN+3][IFNAMSIZ + 6]; |
| 3258 | |
| 3259 | /* Protects hw programming, and ring state. */ |
| 3260 | spinlock_t lock; |
| 3261 | |
| 3262 | const struct niu_ops *ops; |
| 3263 | union niu_mac_stats mac_stats; |
| 3264 | |
| 3265 | struct rx_ring_info *rx_rings; |
| 3266 | struct tx_ring_info *tx_rings; |
| 3267 | int num_rx_rings; |
| 3268 | int num_tx_rings; |
| 3269 | |
| 3270 | struct niu_ldg ldg[NIU_NUM_LDG]; |
| 3271 | int num_ldg; |
| 3272 | |
| 3273 | void __iomem *mac_regs; |
| 3274 | unsigned long ipp_off; |
| 3275 | unsigned long pcs_off; |
| 3276 | unsigned long xpcs_off; |
| 3277 | |
| 3278 | struct timer_list timer; |
| 3279 | const struct niu_phy_ops *phy_ops; |
| 3280 | int phy_addr; |
| 3281 | |
| 3282 | struct niu_link_config link_config; |
| 3283 | |
| 3284 | struct work_struct reset_task; |
| 3285 | |
| 3286 | u8 port; |
| 3287 | u8 mac_xcvr; |
| 3288 | #define MAC_XCVR_MII 1 |
| 3289 | #define MAC_XCVR_PCS 2 |
| 3290 | #define MAC_XCVR_XPCS 3 |
| 3291 | |
| 3292 | struct niu_classifier clas; |
| 3293 | |
| 3294 | struct niu_vpd vpd; |
| 3295 | u32 eeprom_len; |
| 3296 | |
| 3297 | struct of_device *op; |
| 3298 | void __iomem *vir_regs_1; |
| 3299 | void __iomem *vir_regs_2; |
| 3300 | }; |
| 3301 | |
| 3302 | #endif /* _NIU_H */ |