| 1 | /* niu.c: Neptune ethernet driver. |
| 2 | * |
| 3 | * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net) |
| 4 | */ |
| 5 | |
| 6 | #include <linux/module.h> |
| 7 | #include <linux/init.h> |
| 8 | #include <linux/pci.h> |
| 9 | #include <linux/dma-mapping.h> |
| 10 | #include <linux/netdevice.h> |
| 11 | #include <linux/ethtool.h> |
| 12 | #include <linux/etherdevice.h> |
| 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/bitops.h> |
| 16 | #include <linux/mii.h> |
| 17 | #include <linux/if_ether.h> |
| 18 | #include <linux/if_vlan.h> |
| 19 | #include <linux/ip.h> |
| 20 | #include <linux/in.h> |
| 21 | #include <linux/ipv6.h> |
| 22 | #include <linux/log2.h> |
| 23 | #include <linux/jiffies.h> |
| 24 | #include <linux/crc32.h> |
| 25 | #include <linux/list.h> |
| 26 | |
| 27 | #include <linux/io.h> |
| 28 | |
| 29 | #ifdef CONFIG_SPARC64 |
| 30 | #include <linux/of_device.h> |
| 31 | #endif |
| 32 | |
| 33 | #include "niu.h" |
| 34 | |
| 35 | #define DRV_MODULE_NAME "niu" |
| 36 | #define PFX DRV_MODULE_NAME ": " |
| 37 | #define DRV_MODULE_VERSION "1.0" |
| 38 | #define DRV_MODULE_RELDATE "Nov 14, 2008" |
| 39 | |
| 40 | static char version[] __devinitdata = |
| 41 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
| 42 | |
| 43 | MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); |
| 44 | MODULE_DESCRIPTION("NIU ethernet driver"); |
| 45 | MODULE_LICENSE("GPL"); |
| 46 | MODULE_VERSION(DRV_MODULE_VERSION); |
| 47 | |
| 48 | #ifndef DMA_44BIT_MASK |
| 49 | #define DMA_44BIT_MASK 0x00000fffffffffffULL |
| 50 | #endif |
| 51 | |
| 52 | #ifndef readq |
| 53 | static u64 readq(void __iomem *reg) |
| 54 | { |
| 55 | return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32); |
| 56 | } |
| 57 | |
| 58 | static void writeq(u64 val, void __iomem *reg) |
| 59 | { |
| 60 | writel(val & 0xffffffff, reg); |
| 61 | writel(val >> 32, reg + 0x4UL); |
| 62 | } |
| 63 | #endif |
| 64 | |
| 65 | static struct pci_device_id niu_pci_tbl[] = { |
| 66 | {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)}, |
| 67 | {} |
| 68 | }; |
| 69 | |
| 70 | MODULE_DEVICE_TABLE(pci, niu_pci_tbl); |
| 71 | |
| 72 | #define NIU_TX_TIMEOUT (5 * HZ) |
| 73 | |
| 74 | #define nr64(reg) readq(np->regs + (reg)) |
| 75 | #define nw64(reg, val) writeq((val), np->regs + (reg)) |
| 76 | |
| 77 | #define nr64_mac(reg) readq(np->mac_regs + (reg)) |
| 78 | #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) |
| 79 | |
| 80 | #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg)) |
| 81 | #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) |
| 82 | |
| 83 | #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg)) |
| 84 | #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) |
| 85 | |
| 86 | #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg)) |
| 87 | #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) |
| 88 | |
| 89 | #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) |
| 90 | |
| 91 | static int niu_debug; |
| 92 | static int debug = -1; |
| 93 | module_param(debug, int, 0); |
| 94 | MODULE_PARM_DESC(debug, "NIU debug level"); |
| 95 | |
| 96 | #define niudbg(TYPE, f, a...) \ |
| 97 | do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \ |
| 98 | printk(KERN_DEBUG PFX f, ## a); \ |
| 99 | } while (0) |
| 100 | |
| 101 | #define niuinfo(TYPE, f, a...) \ |
| 102 | do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \ |
| 103 | printk(KERN_INFO PFX f, ## a); \ |
| 104 | } while (0) |
| 105 | |
| 106 | #define niuwarn(TYPE, f, a...) \ |
| 107 | do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \ |
| 108 | printk(KERN_WARNING PFX f, ## a); \ |
| 109 | } while (0) |
| 110 | |
| 111 | #define niu_lock_parent(np, flags) \ |
| 112 | spin_lock_irqsave(&np->parent->lock, flags) |
| 113 | #define niu_unlock_parent(np, flags) \ |
| 114 | spin_unlock_irqrestore(&np->parent->lock, flags) |
| 115 | |
| 116 | static int serdes_init_10g_serdes(struct niu *np); |
| 117 | |
| 118 | static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg, |
| 119 | u64 bits, int limit, int delay) |
| 120 | { |
| 121 | while (--limit >= 0) { |
| 122 | u64 val = nr64_mac(reg); |
| 123 | |
| 124 | if (!(val & bits)) |
| 125 | break; |
| 126 | udelay(delay); |
| 127 | } |
| 128 | if (limit < 0) |
| 129 | return -ENODEV; |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg, |
| 134 | u64 bits, int limit, int delay, |
| 135 | const char *reg_name) |
| 136 | { |
| 137 | int err; |
| 138 | |
| 139 | nw64_mac(reg, bits); |
| 140 | err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay); |
| 141 | if (err) |
| 142 | dev_err(np->device, PFX "%s: bits (%llx) of register %s " |
| 143 | "would not clear, val[%llx]\n", |
| 144 | np->dev->name, (unsigned long long) bits, reg_name, |
| 145 | (unsigned long long) nr64_mac(reg)); |
| 146 | return err; |
| 147 | } |
| 148 | |
| 149 | #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ |
| 150 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ |
| 151 | __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ |
| 152 | }) |
| 153 | |
| 154 | static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg, |
| 155 | u64 bits, int limit, int delay) |
| 156 | { |
| 157 | while (--limit >= 0) { |
| 158 | u64 val = nr64_ipp(reg); |
| 159 | |
| 160 | if (!(val & bits)) |
| 161 | break; |
| 162 | udelay(delay); |
| 163 | } |
| 164 | if (limit < 0) |
| 165 | return -ENODEV; |
| 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg, |
| 170 | u64 bits, int limit, int delay, |
| 171 | const char *reg_name) |
| 172 | { |
| 173 | int err; |
| 174 | u64 val; |
| 175 | |
| 176 | val = nr64_ipp(reg); |
| 177 | val |= bits; |
| 178 | nw64_ipp(reg, val); |
| 179 | |
| 180 | err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay); |
| 181 | if (err) |
| 182 | dev_err(np->device, PFX "%s: bits (%llx) of register %s " |
| 183 | "would not clear, val[%llx]\n", |
| 184 | np->dev->name, (unsigned long long) bits, reg_name, |
| 185 | (unsigned long long) nr64_ipp(reg)); |
| 186 | return err; |
| 187 | } |
| 188 | |
| 189 | #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ |
| 190 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ |
| 191 | __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ |
| 192 | }) |
| 193 | |
| 194 | static int __niu_wait_bits_clear(struct niu *np, unsigned long reg, |
| 195 | u64 bits, int limit, int delay) |
| 196 | { |
| 197 | while (--limit >= 0) { |
| 198 | u64 val = nr64(reg); |
| 199 | |
| 200 | if (!(val & bits)) |
| 201 | break; |
| 202 | udelay(delay); |
| 203 | } |
| 204 | if (limit < 0) |
| 205 | return -ENODEV; |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ |
| 210 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ |
| 211 | __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \ |
| 212 | }) |
| 213 | |
| 214 | static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg, |
| 215 | u64 bits, int limit, int delay, |
| 216 | const char *reg_name) |
| 217 | { |
| 218 | int err; |
| 219 | |
| 220 | nw64(reg, bits); |
| 221 | err = __niu_wait_bits_clear(np, reg, bits, limit, delay); |
| 222 | if (err) |
| 223 | dev_err(np->device, PFX "%s: bits (%llx) of register %s " |
| 224 | "would not clear, val[%llx]\n", |
| 225 | np->dev->name, (unsigned long long) bits, reg_name, |
| 226 | (unsigned long long) nr64(reg)); |
| 227 | return err; |
| 228 | } |
| 229 | |
| 230 | #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ |
| 231 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ |
| 232 | __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ |
| 233 | }) |
| 234 | |
| 235 | static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on) |
| 236 | { |
| 237 | u64 val = (u64) lp->timer; |
| 238 | |
| 239 | if (on) |
| 240 | val |= LDG_IMGMT_ARM; |
| 241 | |
| 242 | nw64(LDG_IMGMT(lp->ldg_num), val); |
| 243 | } |
| 244 | |
| 245 | static int niu_ldn_irq_enable(struct niu *np, int ldn, int on) |
| 246 | { |
| 247 | unsigned long mask_reg, bits; |
| 248 | u64 val; |
| 249 | |
| 250 | if (ldn < 0 || ldn > LDN_MAX) |
| 251 | return -EINVAL; |
| 252 | |
| 253 | if (ldn < 64) { |
| 254 | mask_reg = LD_IM0(ldn); |
| 255 | bits = LD_IM0_MASK; |
| 256 | } else { |
| 257 | mask_reg = LD_IM1(ldn - 64); |
| 258 | bits = LD_IM1_MASK; |
| 259 | } |
| 260 | |
| 261 | val = nr64(mask_reg); |
| 262 | if (on) |
| 263 | val &= ~bits; |
| 264 | else |
| 265 | val |= bits; |
| 266 | nw64(mask_reg, val); |
| 267 | |
| 268 | return 0; |
| 269 | } |
| 270 | |
| 271 | static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on) |
| 272 | { |
| 273 | struct niu_parent *parent = np->parent; |
| 274 | int i; |
| 275 | |
| 276 | for (i = 0; i <= LDN_MAX; i++) { |
| 277 | int err; |
| 278 | |
| 279 | if (parent->ldg_map[i] != lp->ldg_num) |
| 280 | continue; |
| 281 | |
| 282 | err = niu_ldn_irq_enable(np, i, on); |
| 283 | if (err) |
| 284 | return err; |
| 285 | } |
| 286 | return 0; |
| 287 | } |
| 288 | |
| 289 | static int niu_enable_interrupts(struct niu *np, int on) |
| 290 | { |
| 291 | int i; |
| 292 | |
| 293 | for (i = 0; i < np->num_ldg; i++) { |
| 294 | struct niu_ldg *lp = &np->ldg[i]; |
| 295 | int err; |
| 296 | |
| 297 | err = niu_enable_ldn_in_ldg(np, lp, on); |
| 298 | if (err) |
| 299 | return err; |
| 300 | } |
| 301 | for (i = 0; i < np->num_ldg; i++) |
| 302 | niu_ldg_rearm(np, &np->ldg[i], on); |
| 303 | |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | static u32 phy_encode(u32 type, int port) |
| 308 | { |
| 309 | return (type << (port * 2)); |
| 310 | } |
| 311 | |
| 312 | static u32 phy_decode(u32 val, int port) |
| 313 | { |
| 314 | return (val >> (port * 2)) & PORT_TYPE_MASK; |
| 315 | } |
| 316 | |
| 317 | static int mdio_wait(struct niu *np) |
| 318 | { |
| 319 | int limit = 1000; |
| 320 | u64 val; |
| 321 | |
| 322 | while (--limit > 0) { |
| 323 | val = nr64(MIF_FRAME_OUTPUT); |
| 324 | if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1) |
| 325 | return val & MIF_FRAME_OUTPUT_DATA; |
| 326 | |
| 327 | udelay(10); |
| 328 | } |
| 329 | |
| 330 | return -ENODEV; |
| 331 | } |
| 332 | |
| 333 | static int mdio_read(struct niu *np, int port, int dev, int reg) |
| 334 | { |
| 335 | int err; |
| 336 | |
| 337 | nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); |
| 338 | err = mdio_wait(np); |
| 339 | if (err < 0) |
| 340 | return err; |
| 341 | |
| 342 | nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev)); |
| 343 | return mdio_wait(np); |
| 344 | } |
| 345 | |
| 346 | static int mdio_write(struct niu *np, int port, int dev, int reg, int data) |
| 347 | { |
| 348 | int err; |
| 349 | |
| 350 | nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); |
| 351 | err = mdio_wait(np); |
| 352 | if (err < 0) |
| 353 | return err; |
| 354 | |
| 355 | nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data)); |
| 356 | err = mdio_wait(np); |
| 357 | if (err < 0) |
| 358 | return err; |
| 359 | |
| 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | static int mii_read(struct niu *np, int port, int reg) |
| 364 | { |
| 365 | nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); |
| 366 | return mdio_wait(np); |
| 367 | } |
| 368 | |
| 369 | static int mii_write(struct niu *np, int port, int reg, int data) |
| 370 | { |
| 371 | int err; |
| 372 | |
| 373 | nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); |
| 374 | err = mdio_wait(np); |
| 375 | if (err < 0) |
| 376 | return err; |
| 377 | |
| 378 | return 0; |
| 379 | } |
| 380 | |
| 381 | static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val) |
| 382 | { |
| 383 | int err; |
| 384 | |
| 385 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 386 | ESR2_TI_PLL_TX_CFG_L(channel), |
| 387 | val & 0xffff); |
| 388 | if (!err) |
| 389 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 390 | ESR2_TI_PLL_TX_CFG_H(channel), |
| 391 | val >> 16); |
| 392 | return err; |
| 393 | } |
| 394 | |
| 395 | static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) |
| 396 | { |
| 397 | int err; |
| 398 | |
| 399 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 400 | ESR2_TI_PLL_RX_CFG_L(channel), |
| 401 | val & 0xffff); |
| 402 | if (!err) |
| 403 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 404 | ESR2_TI_PLL_RX_CFG_H(channel), |
| 405 | val >> 16); |
| 406 | return err; |
| 407 | } |
| 408 | |
| 409 | /* Mode is always 10G fiber. */ |
| 410 | static int serdes_init_niu_10g_fiber(struct niu *np) |
| 411 | { |
| 412 | struct niu_link_config *lp = &np->link_config; |
| 413 | u32 tx_cfg, rx_cfg; |
| 414 | unsigned long i; |
| 415 | |
| 416 | tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); |
| 417 | rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | |
| 418 | PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | |
| 419 | PLL_RX_CFG_EQ_LP_ADAPTIVE); |
| 420 | |
| 421 | if (lp->loopback_mode == LOOPBACK_PHY) { |
| 422 | u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; |
| 423 | |
| 424 | mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 425 | ESR2_TI_PLL_TEST_CFG_L, test_cfg); |
| 426 | |
| 427 | tx_cfg |= PLL_TX_CFG_ENTEST; |
| 428 | rx_cfg |= PLL_RX_CFG_ENTEST; |
| 429 | } |
| 430 | |
| 431 | /* Initialize all 4 lanes of the SERDES. */ |
| 432 | for (i = 0; i < 4; i++) { |
| 433 | int err = esr2_set_tx_cfg(np, i, tx_cfg); |
| 434 | if (err) |
| 435 | return err; |
| 436 | } |
| 437 | |
| 438 | for (i = 0; i < 4; i++) { |
| 439 | int err = esr2_set_rx_cfg(np, i, rx_cfg); |
| 440 | if (err) |
| 441 | return err; |
| 442 | } |
| 443 | |
| 444 | return 0; |
| 445 | } |
| 446 | |
| 447 | static int serdes_init_niu_1g_serdes(struct niu *np) |
| 448 | { |
| 449 | struct niu_link_config *lp = &np->link_config; |
| 450 | u16 pll_cfg, pll_sts; |
| 451 | int max_retry = 100; |
| 452 | u64 uninitialized_var(sig), mask, val; |
| 453 | u32 tx_cfg, rx_cfg; |
| 454 | unsigned long i; |
| 455 | int err; |
| 456 | |
| 457 | tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV | |
| 458 | PLL_TX_CFG_RATE_HALF); |
| 459 | rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | |
| 460 | PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | |
| 461 | PLL_RX_CFG_RATE_HALF); |
| 462 | |
| 463 | if (np->port == 0) |
| 464 | rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE; |
| 465 | |
| 466 | if (lp->loopback_mode == LOOPBACK_PHY) { |
| 467 | u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; |
| 468 | |
| 469 | mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 470 | ESR2_TI_PLL_TEST_CFG_L, test_cfg); |
| 471 | |
| 472 | tx_cfg |= PLL_TX_CFG_ENTEST; |
| 473 | rx_cfg |= PLL_RX_CFG_ENTEST; |
| 474 | } |
| 475 | |
| 476 | /* Initialize PLL for 1G */ |
| 477 | pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X); |
| 478 | |
| 479 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 480 | ESR2_TI_PLL_CFG_L, pll_cfg); |
| 481 | if (err) { |
| 482 | dev_err(np->device, PFX "NIU Port %d " |
| 483 | "serdes_init_niu_1g_serdes: " |
| 484 | "mdio write to ESR2_TI_PLL_CFG_L failed", np->port); |
| 485 | return err; |
| 486 | } |
| 487 | |
| 488 | pll_sts = PLL_CFG_ENPLL; |
| 489 | |
| 490 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 491 | ESR2_TI_PLL_STS_L, pll_sts); |
| 492 | if (err) { |
| 493 | dev_err(np->device, PFX "NIU Port %d " |
| 494 | "serdes_init_niu_1g_serdes: " |
| 495 | "mdio write to ESR2_TI_PLL_STS_L failed", np->port); |
| 496 | return err; |
| 497 | } |
| 498 | |
| 499 | udelay(200); |
| 500 | |
| 501 | /* Initialize all 4 lanes of the SERDES. */ |
| 502 | for (i = 0; i < 4; i++) { |
| 503 | err = esr2_set_tx_cfg(np, i, tx_cfg); |
| 504 | if (err) |
| 505 | return err; |
| 506 | } |
| 507 | |
| 508 | for (i = 0; i < 4; i++) { |
| 509 | err = esr2_set_rx_cfg(np, i, rx_cfg); |
| 510 | if (err) |
| 511 | return err; |
| 512 | } |
| 513 | |
| 514 | switch (np->port) { |
| 515 | case 0: |
| 516 | val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); |
| 517 | mask = val; |
| 518 | break; |
| 519 | |
| 520 | case 1: |
| 521 | val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); |
| 522 | mask = val; |
| 523 | break; |
| 524 | |
| 525 | default: |
| 526 | return -EINVAL; |
| 527 | } |
| 528 | |
| 529 | while (max_retry--) { |
| 530 | sig = nr64(ESR_INT_SIGNALS); |
| 531 | if ((sig & mask) == val) |
| 532 | break; |
| 533 | |
| 534 | mdelay(500); |
| 535 | } |
| 536 | |
| 537 | if ((sig & mask) != val) { |
| 538 | dev_err(np->device, PFX "Port %u signal bits [%08x] are not " |
| 539 | "[%08x]\n", np->port, (int) (sig & mask), (int) val); |
| 540 | return -ENODEV; |
| 541 | } |
| 542 | |
| 543 | return 0; |
| 544 | } |
| 545 | |
| 546 | static int serdes_init_niu_10g_serdes(struct niu *np) |
| 547 | { |
| 548 | struct niu_link_config *lp = &np->link_config; |
| 549 | u32 tx_cfg, rx_cfg, pll_cfg, pll_sts; |
| 550 | int max_retry = 100; |
| 551 | u64 uninitialized_var(sig), mask, val; |
| 552 | unsigned long i; |
| 553 | int err; |
| 554 | |
| 555 | tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); |
| 556 | rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | |
| 557 | PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | |
| 558 | PLL_RX_CFG_EQ_LP_ADAPTIVE); |
| 559 | |
| 560 | if (lp->loopback_mode == LOOPBACK_PHY) { |
| 561 | u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; |
| 562 | |
| 563 | mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 564 | ESR2_TI_PLL_TEST_CFG_L, test_cfg); |
| 565 | |
| 566 | tx_cfg |= PLL_TX_CFG_ENTEST; |
| 567 | rx_cfg |= PLL_RX_CFG_ENTEST; |
| 568 | } |
| 569 | |
| 570 | /* Initialize PLL for 10G */ |
| 571 | pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X); |
| 572 | |
| 573 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 574 | ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff); |
| 575 | if (err) { |
| 576 | dev_err(np->device, PFX "NIU Port %d " |
| 577 | "serdes_init_niu_10g_serdes: " |
| 578 | "mdio write to ESR2_TI_PLL_CFG_L failed", np->port); |
| 579 | return err; |
| 580 | } |
| 581 | |
| 582 | pll_sts = PLL_CFG_ENPLL; |
| 583 | |
| 584 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, |
| 585 | ESR2_TI_PLL_STS_L, pll_sts & 0xffff); |
| 586 | if (err) { |
| 587 | dev_err(np->device, PFX "NIU Port %d " |
| 588 | "serdes_init_niu_10g_serdes: " |
| 589 | "mdio write to ESR2_TI_PLL_STS_L failed", np->port); |
| 590 | return err; |
| 591 | } |
| 592 | |
| 593 | udelay(200); |
| 594 | |
| 595 | /* Initialize all 4 lanes of the SERDES. */ |
| 596 | for (i = 0; i < 4; i++) { |
| 597 | err = esr2_set_tx_cfg(np, i, tx_cfg); |
| 598 | if (err) |
| 599 | return err; |
| 600 | } |
| 601 | |
| 602 | for (i = 0; i < 4; i++) { |
| 603 | err = esr2_set_rx_cfg(np, i, rx_cfg); |
| 604 | if (err) |
| 605 | return err; |
| 606 | } |
| 607 | |
| 608 | /* check if serdes is ready */ |
| 609 | |
| 610 | switch (np->port) { |
| 611 | case 0: |
| 612 | mask = ESR_INT_SIGNALS_P0_BITS; |
| 613 | val = (ESR_INT_SRDY0_P0 | |
| 614 | ESR_INT_DET0_P0 | |
| 615 | ESR_INT_XSRDY_P0 | |
| 616 | ESR_INT_XDP_P0_CH3 | |
| 617 | ESR_INT_XDP_P0_CH2 | |
| 618 | ESR_INT_XDP_P0_CH1 | |
| 619 | ESR_INT_XDP_P0_CH0); |
| 620 | break; |
| 621 | |
| 622 | case 1: |
| 623 | mask = ESR_INT_SIGNALS_P1_BITS; |
| 624 | val = (ESR_INT_SRDY0_P1 | |
| 625 | ESR_INT_DET0_P1 | |
| 626 | ESR_INT_XSRDY_P1 | |
| 627 | ESR_INT_XDP_P1_CH3 | |
| 628 | ESR_INT_XDP_P1_CH2 | |
| 629 | ESR_INT_XDP_P1_CH1 | |
| 630 | ESR_INT_XDP_P1_CH0); |
| 631 | break; |
| 632 | |
| 633 | default: |
| 634 | return -EINVAL; |
| 635 | } |
| 636 | |
| 637 | while (max_retry--) { |
| 638 | sig = nr64(ESR_INT_SIGNALS); |
| 639 | if ((sig & mask) == val) |
| 640 | break; |
| 641 | |
| 642 | mdelay(500); |
| 643 | } |
| 644 | |
| 645 | if ((sig & mask) != val) { |
| 646 | pr_info(PFX "NIU Port %u signal bits [%08x] are not " |
| 647 | "[%08x] for 10G...trying 1G\n", |
| 648 | np->port, (int) (sig & mask), (int) val); |
| 649 | |
| 650 | /* 10G failed, try initializing at 1G */ |
| 651 | err = serdes_init_niu_1g_serdes(np); |
| 652 | if (!err) { |
| 653 | np->flags &= ~NIU_FLAGS_10G; |
| 654 | np->mac_xcvr = MAC_XCVR_PCS; |
| 655 | } else { |
| 656 | dev_err(np->device, PFX "Port %u 10G/1G SERDES " |
| 657 | "Link Failed \n", np->port); |
| 658 | return -ENODEV; |
| 659 | } |
| 660 | } |
| 661 | return 0; |
| 662 | } |
| 663 | |
| 664 | static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) |
| 665 | { |
| 666 | int err; |
| 667 | |
| 668 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan)); |
| 669 | if (err >= 0) { |
| 670 | *val = (err & 0xffff); |
| 671 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, |
| 672 | ESR_RXTX_CTRL_H(chan)); |
| 673 | if (err >= 0) |
| 674 | *val |= ((err & 0xffff) << 16); |
| 675 | err = 0; |
| 676 | } |
| 677 | return err; |
| 678 | } |
| 679 | |
| 680 | static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val) |
| 681 | { |
| 682 | int err; |
| 683 | |
| 684 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, |
| 685 | ESR_GLUE_CTRL0_L(chan)); |
| 686 | if (err >= 0) { |
| 687 | *val = (err & 0xffff); |
| 688 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, |
| 689 | ESR_GLUE_CTRL0_H(chan)); |
| 690 | if (err >= 0) { |
| 691 | *val |= ((err & 0xffff) << 16); |
| 692 | err = 0; |
| 693 | } |
| 694 | } |
| 695 | return err; |
| 696 | } |
| 697 | |
| 698 | static int esr_read_reset(struct niu *np, u32 *val) |
| 699 | { |
| 700 | int err; |
| 701 | |
| 702 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, |
| 703 | ESR_RXTX_RESET_CTRL_L); |
| 704 | if (err >= 0) { |
| 705 | *val = (err & 0xffff); |
| 706 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, |
| 707 | ESR_RXTX_RESET_CTRL_H); |
| 708 | if (err >= 0) { |
| 709 | *val |= ((err & 0xffff) << 16); |
| 710 | err = 0; |
| 711 | } |
| 712 | } |
| 713 | return err; |
| 714 | } |
| 715 | |
| 716 | static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val) |
| 717 | { |
| 718 | int err; |
| 719 | |
| 720 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, |
| 721 | ESR_RXTX_CTRL_L(chan), val & 0xffff); |
| 722 | if (!err) |
| 723 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, |
| 724 | ESR_RXTX_CTRL_H(chan), (val >> 16)); |
| 725 | return err; |
| 726 | } |
| 727 | |
| 728 | static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) |
| 729 | { |
| 730 | int err; |
| 731 | |
| 732 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, |
| 733 | ESR_GLUE_CTRL0_L(chan), val & 0xffff); |
| 734 | if (!err) |
| 735 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, |
| 736 | ESR_GLUE_CTRL0_H(chan), (val >> 16)); |
| 737 | return err; |
| 738 | } |
| 739 | |
| 740 | static int esr_reset(struct niu *np) |
| 741 | { |
| 742 | u32 uninitialized_var(reset); |
| 743 | int err; |
| 744 | |
| 745 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, |
| 746 | ESR_RXTX_RESET_CTRL_L, 0x0000); |
| 747 | if (err) |
| 748 | return err; |
| 749 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, |
| 750 | ESR_RXTX_RESET_CTRL_H, 0xffff); |
| 751 | if (err) |
| 752 | return err; |
| 753 | udelay(200); |
| 754 | |
| 755 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, |
| 756 | ESR_RXTX_RESET_CTRL_L, 0xffff); |
| 757 | if (err) |
| 758 | return err; |
| 759 | udelay(200); |
| 760 | |
| 761 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, |
| 762 | ESR_RXTX_RESET_CTRL_H, 0x0000); |
| 763 | if (err) |
| 764 | return err; |
| 765 | udelay(200); |
| 766 | |
| 767 | err = esr_read_reset(np, &reset); |
| 768 | if (err) |
| 769 | return err; |
| 770 | if (reset != 0) { |
| 771 | dev_err(np->device, PFX "Port %u ESR_RESET " |
| 772 | "did not clear [%08x]\n", |
| 773 | np->port, reset); |
| 774 | return -ENODEV; |
| 775 | } |
| 776 | |
| 777 | return 0; |
| 778 | } |
| 779 | |
| 780 | static int serdes_init_10g(struct niu *np) |
| 781 | { |
| 782 | struct niu_link_config *lp = &np->link_config; |
| 783 | unsigned long ctrl_reg, test_cfg_reg, i; |
| 784 | u64 ctrl_val, test_cfg_val, sig, mask, val; |
| 785 | int err; |
| 786 | |
| 787 | switch (np->port) { |
| 788 | case 0: |
| 789 | ctrl_reg = ENET_SERDES_0_CTRL_CFG; |
| 790 | test_cfg_reg = ENET_SERDES_0_TEST_CFG; |
| 791 | break; |
| 792 | case 1: |
| 793 | ctrl_reg = ENET_SERDES_1_CTRL_CFG; |
| 794 | test_cfg_reg = ENET_SERDES_1_TEST_CFG; |
| 795 | break; |
| 796 | |
| 797 | default: |
| 798 | return -EINVAL; |
| 799 | } |
| 800 | ctrl_val = (ENET_SERDES_CTRL_SDET_0 | |
| 801 | ENET_SERDES_CTRL_SDET_1 | |
| 802 | ENET_SERDES_CTRL_SDET_2 | |
| 803 | ENET_SERDES_CTRL_SDET_3 | |
| 804 | (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | |
| 805 | (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | |
| 806 | (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | |
| 807 | (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | |
| 808 | (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | |
| 809 | (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | |
| 810 | (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | |
| 811 | (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); |
| 812 | test_cfg_val = 0; |
| 813 | |
| 814 | if (lp->loopback_mode == LOOPBACK_PHY) { |
| 815 | test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << |
| 816 | ENET_SERDES_TEST_MD_0_SHIFT) | |
| 817 | (ENET_TEST_MD_PAD_LOOPBACK << |
| 818 | ENET_SERDES_TEST_MD_1_SHIFT) | |
| 819 | (ENET_TEST_MD_PAD_LOOPBACK << |
| 820 | ENET_SERDES_TEST_MD_2_SHIFT) | |
| 821 | (ENET_TEST_MD_PAD_LOOPBACK << |
| 822 | ENET_SERDES_TEST_MD_3_SHIFT)); |
| 823 | } |
| 824 | |
| 825 | nw64(ctrl_reg, ctrl_val); |
| 826 | nw64(test_cfg_reg, test_cfg_val); |
| 827 | |
| 828 | /* Initialize all 4 lanes of the SERDES. */ |
| 829 | for (i = 0; i < 4; i++) { |
| 830 | u32 rxtx_ctrl, glue0; |
| 831 | |
| 832 | err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); |
| 833 | if (err) |
| 834 | return err; |
| 835 | err = esr_read_glue0(np, i, &glue0); |
| 836 | if (err) |
| 837 | return err; |
| 838 | |
| 839 | rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); |
| 840 | rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | |
| 841 | (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); |
| 842 | |
| 843 | glue0 &= ~(ESR_GLUE_CTRL0_SRATE | |
| 844 | ESR_GLUE_CTRL0_THCNT | |
| 845 | ESR_GLUE_CTRL0_BLTIME); |
| 846 | glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | |
| 847 | (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | |
| 848 | (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | |
| 849 | (BLTIME_300_CYCLES << |
| 850 | ESR_GLUE_CTRL0_BLTIME_SHIFT)); |
| 851 | |
| 852 | err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); |
| 853 | if (err) |
| 854 | return err; |
| 855 | err = esr_write_glue0(np, i, glue0); |
| 856 | if (err) |
| 857 | return err; |
| 858 | } |
| 859 | |
| 860 | err = esr_reset(np); |
| 861 | if (err) |
| 862 | return err; |
| 863 | |
| 864 | sig = nr64(ESR_INT_SIGNALS); |
| 865 | switch (np->port) { |
| 866 | case 0: |
| 867 | mask = ESR_INT_SIGNALS_P0_BITS; |
| 868 | val = (ESR_INT_SRDY0_P0 | |
| 869 | ESR_INT_DET0_P0 | |
| 870 | ESR_INT_XSRDY_P0 | |
| 871 | ESR_INT_XDP_P0_CH3 | |
| 872 | ESR_INT_XDP_P0_CH2 | |
| 873 | ESR_INT_XDP_P0_CH1 | |
| 874 | ESR_INT_XDP_P0_CH0); |
| 875 | break; |
| 876 | |
| 877 | case 1: |
| 878 | mask = ESR_INT_SIGNALS_P1_BITS; |
| 879 | val = (ESR_INT_SRDY0_P1 | |
| 880 | ESR_INT_DET0_P1 | |
| 881 | ESR_INT_XSRDY_P1 | |
| 882 | ESR_INT_XDP_P1_CH3 | |
| 883 | ESR_INT_XDP_P1_CH2 | |
| 884 | ESR_INT_XDP_P1_CH1 | |
| 885 | ESR_INT_XDP_P1_CH0); |
| 886 | break; |
| 887 | |
| 888 | default: |
| 889 | return -EINVAL; |
| 890 | } |
| 891 | |
| 892 | if ((sig & mask) != val) { |
| 893 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { |
| 894 | np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; |
| 895 | return 0; |
| 896 | } |
| 897 | dev_err(np->device, PFX "Port %u signal bits [%08x] are not " |
| 898 | "[%08x]\n", np->port, (int) (sig & mask), (int) val); |
| 899 | return -ENODEV; |
| 900 | } |
| 901 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY) |
| 902 | np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; |
| 903 | return 0; |
| 904 | } |
| 905 | |
| 906 | static int serdes_init_1g(struct niu *np) |
| 907 | { |
| 908 | u64 val; |
| 909 | |
| 910 | val = nr64(ENET_SERDES_1_PLL_CFG); |
| 911 | val &= ~ENET_SERDES_PLL_FBDIV2; |
| 912 | switch (np->port) { |
| 913 | case 0: |
| 914 | val |= ENET_SERDES_PLL_HRATE0; |
| 915 | break; |
| 916 | case 1: |
| 917 | val |= ENET_SERDES_PLL_HRATE1; |
| 918 | break; |
| 919 | case 2: |
| 920 | val |= ENET_SERDES_PLL_HRATE2; |
| 921 | break; |
| 922 | case 3: |
| 923 | val |= ENET_SERDES_PLL_HRATE3; |
| 924 | break; |
| 925 | default: |
| 926 | return -EINVAL; |
| 927 | } |
| 928 | nw64(ENET_SERDES_1_PLL_CFG, val); |
| 929 | |
| 930 | return 0; |
| 931 | } |
| 932 | |
| 933 | static int serdes_init_1g_serdes(struct niu *np) |
| 934 | { |
| 935 | struct niu_link_config *lp = &np->link_config; |
| 936 | unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; |
| 937 | u64 ctrl_val, test_cfg_val, sig, mask, val; |
| 938 | int err; |
| 939 | u64 reset_val, val_rd; |
| 940 | |
| 941 | val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 | |
| 942 | ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 | |
| 943 | ENET_SERDES_PLL_FBDIV0; |
| 944 | switch (np->port) { |
| 945 | case 0: |
| 946 | reset_val = ENET_SERDES_RESET_0; |
| 947 | ctrl_reg = ENET_SERDES_0_CTRL_CFG; |
| 948 | test_cfg_reg = ENET_SERDES_0_TEST_CFG; |
| 949 | pll_cfg = ENET_SERDES_0_PLL_CFG; |
| 950 | break; |
| 951 | case 1: |
| 952 | reset_val = ENET_SERDES_RESET_1; |
| 953 | ctrl_reg = ENET_SERDES_1_CTRL_CFG; |
| 954 | test_cfg_reg = ENET_SERDES_1_TEST_CFG; |
| 955 | pll_cfg = ENET_SERDES_1_PLL_CFG; |
| 956 | break; |
| 957 | |
| 958 | default: |
| 959 | return -EINVAL; |
| 960 | } |
| 961 | ctrl_val = (ENET_SERDES_CTRL_SDET_0 | |
| 962 | ENET_SERDES_CTRL_SDET_1 | |
| 963 | ENET_SERDES_CTRL_SDET_2 | |
| 964 | ENET_SERDES_CTRL_SDET_3 | |
| 965 | (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | |
| 966 | (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | |
| 967 | (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | |
| 968 | (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | |
| 969 | (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | |
| 970 | (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | |
| 971 | (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | |
| 972 | (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); |
| 973 | test_cfg_val = 0; |
| 974 | |
| 975 | if (lp->loopback_mode == LOOPBACK_PHY) { |
| 976 | test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << |
| 977 | ENET_SERDES_TEST_MD_0_SHIFT) | |
| 978 | (ENET_TEST_MD_PAD_LOOPBACK << |
| 979 | ENET_SERDES_TEST_MD_1_SHIFT) | |
| 980 | (ENET_TEST_MD_PAD_LOOPBACK << |
| 981 | ENET_SERDES_TEST_MD_2_SHIFT) | |
| 982 | (ENET_TEST_MD_PAD_LOOPBACK << |
| 983 | ENET_SERDES_TEST_MD_3_SHIFT)); |
| 984 | } |
| 985 | |
| 986 | nw64(ENET_SERDES_RESET, reset_val); |
| 987 | mdelay(20); |
| 988 | val_rd = nr64(ENET_SERDES_RESET); |
| 989 | val_rd &= ~reset_val; |
| 990 | nw64(pll_cfg, val); |
| 991 | nw64(ctrl_reg, ctrl_val); |
| 992 | nw64(test_cfg_reg, test_cfg_val); |
| 993 | nw64(ENET_SERDES_RESET, val_rd); |
| 994 | mdelay(2000); |
| 995 | |
| 996 | /* Initialize all 4 lanes of the SERDES. */ |
| 997 | for (i = 0; i < 4; i++) { |
| 998 | u32 rxtx_ctrl, glue0; |
| 999 | |
| 1000 | err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); |
| 1001 | if (err) |
| 1002 | return err; |
| 1003 | err = esr_read_glue0(np, i, &glue0); |
| 1004 | if (err) |
| 1005 | return err; |
| 1006 | |
| 1007 | rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); |
| 1008 | rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | |
| 1009 | (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); |
| 1010 | |
| 1011 | glue0 &= ~(ESR_GLUE_CTRL0_SRATE | |
| 1012 | ESR_GLUE_CTRL0_THCNT | |
| 1013 | ESR_GLUE_CTRL0_BLTIME); |
| 1014 | glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | |
| 1015 | (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | |
| 1016 | (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | |
| 1017 | (BLTIME_300_CYCLES << |
| 1018 | ESR_GLUE_CTRL0_BLTIME_SHIFT)); |
| 1019 | |
| 1020 | err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); |
| 1021 | if (err) |
| 1022 | return err; |
| 1023 | err = esr_write_glue0(np, i, glue0); |
| 1024 | if (err) |
| 1025 | return err; |
| 1026 | } |
| 1027 | |
| 1028 | |
| 1029 | sig = nr64(ESR_INT_SIGNALS); |
| 1030 | switch (np->port) { |
| 1031 | case 0: |
| 1032 | val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); |
| 1033 | mask = val; |
| 1034 | break; |
| 1035 | |
| 1036 | case 1: |
| 1037 | val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); |
| 1038 | mask = val; |
| 1039 | break; |
| 1040 | |
| 1041 | default: |
| 1042 | return -EINVAL; |
| 1043 | } |
| 1044 | |
| 1045 | if ((sig & mask) != val) { |
| 1046 | dev_err(np->device, PFX "Port %u signal bits [%08x] are not " |
| 1047 | "[%08x]\n", np->port, (int) (sig & mask), (int) val); |
| 1048 | return -ENODEV; |
| 1049 | } |
| 1050 | |
| 1051 | return 0; |
| 1052 | } |
| 1053 | |
| 1054 | static int link_status_1g_serdes(struct niu *np, int *link_up_p) |
| 1055 | { |
| 1056 | struct niu_link_config *lp = &np->link_config; |
| 1057 | int link_up; |
| 1058 | u64 val; |
| 1059 | u16 current_speed; |
| 1060 | unsigned long flags; |
| 1061 | u8 current_duplex; |
| 1062 | |
| 1063 | link_up = 0; |
| 1064 | current_speed = SPEED_INVALID; |
| 1065 | current_duplex = DUPLEX_INVALID; |
| 1066 | |
| 1067 | spin_lock_irqsave(&np->lock, flags); |
| 1068 | |
| 1069 | val = nr64_pcs(PCS_MII_STAT); |
| 1070 | |
| 1071 | if (val & PCS_MII_STAT_LINK_STATUS) { |
| 1072 | link_up = 1; |
| 1073 | current_speed = SPEED_1000; |
| 1074 | current_duplex = DUPLEX_FULL; |
| 1075 | } |
| 1076 | |
| 1077 | lp->active_speed = current_speed; |
| 1078 | lp->active_duplex = current_duplex; |
| 1079 | spin_unlock_irqrestore(&np->lock, flags); |
| 1080 | |
| 1081 | *link_up_p = link_up; |
| 1082 | return 0; |
| 1083 | } |
| 1084 | |
| 1085 | static int link_status_10g_serdes(struct niu *np, int *link_up_p) |
| 1086 | { |
| 1087 | unsigned long flags; |
| 1088 | struct niu_link_config *lp = &np->link_config; |
| 1089 | int link_up = 0; |
| 1090 | int link_ok = 1; |
| 1091 | u64 val, val2; |
| 1092 | u16 current_speed; |
| 1093 | u8 current_duplex; |
| 1094 | |
| 1095 | if (!(np->flags & NIU_FLAGS_10G)) |
| 1096 | return link_status_1g_serdes(np, link_up_p); |
| 1097 | |
| 1098 | current_speed = SPEED_INVALID; |
| 1099 | current_duplex = DUPLEX_INVALID; |
| 1100 | spin_lock_irqsave(&np->lock, flags); |
| 1101 | |
| 1102 | val = nr64_xpcs(XPCS_STATUS(0)); |
| 1103 | val2 = nr64_mac(XMAC_INTER2); |
| 1104 | if (val2 & 0x01000000) |
| 1105 | link_ok = 0; |
| 1106 | |
| 1107 | if ((val & 0x1000ULL) && link_ok) { |
| 1108 | link_up = 1; |
| 1109 | current_speed = SPEED_10000; |
| 1110 | current_duplex = DUPLEX_FULL; |
| 1111 | } |
| 1112 | lp->active_speed = current_speed; |
| 1113 | lp->active_duplex = current_duplex; |
| 1114 | spin_unlock_irqrestore(&np->lock, flags); |
| 1115 | *link_up_p = link_up; |
| 1116 | return 0; |
| 1117 | } |
| 1118 | |
| 1119 | static int link_status_mii(struct niu *np, int *link_up_p) |
| 1120 | { |
| 1121 | struct niu_link_config *lp = &np->link_config; |
| 1122 | int err; |
| 1123 | int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus; |
| 1124 | int supported, advertising, active_speed, active_duplex; |
| 1125 | |
| 1126 | err = mii_read(np, np->phy_addr, MII_BMCR); |
| 1127 | if (unlikely(err < 0)) |
| 1128 | return err; |
| 1129 | bmcr = err; |
| 1130 | |
| 1131 | err = mii_read(np, np->phy_addr, MII_BMSR); |
| 1132 | if (unlikely(err < 0)) |
| 1133 | return err; |
| 1134 | bmsr = err; |
| 1135 | |
| 1136 | err = mii_read(np, np->phy_addr, MII_ADVERTISE); |
| 1137 | if (unlikely(err < 0)) |
| 1138 | return err; |
| 1139 | advert = err; |
| 1140 | |
| 1141 | err = mii_read(np, np->phy_addr, MII_LPA); |
| 1142 | if (unlikely(err < 0)) |
| 1143 | return err; |
| 1144 | lpa = err; |
| 1145 | |
| 1146 | if (likely(bmsr & BMSR_ESTATEN)) { |
| 1147 | err = mii_read(np, np->phy_addr, MII_ESTATUS); |
| 1148 | if (unlikely(err < 0)) |
| 1149 | return err; |
| 1150 | estatus = err; |
| 1151 | |
| 1152 | err = mii_read(np, np->phy_addr, MII_CTRL1000); |
| 1153 | if (unlikely(err < 0)) |
| 1154 | return err; |
| 1155 | ctrl1000 = err; |
| 1156 | |
| 1157 | err = mii_read(np, np->phy_addr, MII_STAT1000); |
| 1158 | if (unlikely(err < 0)) |
| 1159 | return err; |
| 1160 | stat1000 = err; |
| 1161 | } else |
| 1162 | estatus = ctrl1000 = stat1000 = 0; |
| 1163 | |
| 1164 | supported = 0; |
| 1165 | if (bmsr & BMSR_ANEGCAPABLE) |
| 1166 | supported |= SUPPORTED_Autoneg; |
| 1167 | if (bmsr & BMSR_10HALF) |
| 1168 | supported |= SUPPORTED_10baseT_Half; |
| 1169 | if (bmsr & BMSR_10FULL) |
| 1170 | supported |= SUPPORTED_10baseT_Full; |
| 1171 | if (bmsr & BMSR_100HALF) |
| 1172 | supported |= SUPPORTED_100baseT_Half; |
| 1173 | if (bmsr & BMSR_100FULL) |
| 1174 | supported |= SUPPORTED_100baseT_Full; |
| 1175 | if (estatus & ESTATUS_1000_THALF) |
| 1176 | supported |= SUPPORTED_1000baseT_Half; |
| 1177 | if (estatus & ESTATUS_1000_TFULL) |
| 1178 | supported |= SUPPORTED_1000baseT_Full; |
| 1179 | lp->supported = supported; |
| 1180 | |
| 1181 | advertising = 0; |
| 1182 | if (advert & ADVERTISE_10HALF) |
| 1183 | advertising |= ADVERTISED_10baseT_Half; |
| 1184 | if (advert & ADVERTISE_10FULL) |
| 1185 | advertising |= ADVERTISED_10baseT_Full; |
| 1186 | if (advert & ADVERTISE_100HALF) |
| 1187 | advertising |= ADVERTISED_100baseT_Half; |
| 1188 | if (advert & ADVERTISE_100FULL) |
| 1189 | advertising |= ADVERTISED_100baseT_Full; |
| 1190 | if (ctrl1000 & ADVERTISE_1000HALF) |
| 1191 | advertising |= ADVERTISED_1000baseT_Half; |
| 1192 | if (ctrl1000 & ADVERTISE_1000FULL) |
| 1193 | advertising |= ADVERTISED_1000baseT_Full; |
| 1194 | |
| 1195 | if (bmcr & BMCR_ANENABLE) { |
| 1196 | int neg, neg1000; |
| 1197 | |
| 1198 | lp->active_autoneg = 1; |
| 1199 | advertising |= ADVERTISED_Autoneg; |
| 1200 | |
| 1201 | neg = advert & lpa; |
| 1202 | neg1000 = (ctrl1000 << 2) & stat1000; |
| 1203 | |
| 1204 | if (neg1000 & (LPA_1000FULL | LPA_1000HALF)) |
| 1205 | active_speed = SPEED_1000; |
| 1206 | else if (neg & LPA_100) |
| 1207 | active_speed = SPEED_100; |
| 1208 | else if (neg & (LPA_10HALF | LPA_10FULL)) |
| 1209 | active_speed = SPEED_10; |
| 1210 | else |
| 1211 | active_speed = SPEED_INVALID; |
| 1212 | |
| 1213 | if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX)) |
| 1214 | active_duplex = DUPLEX_FULL; |
| 1215 | else if (active_speed != SPEED_INVALID) |
| 1216 | active_duplex = DUPLEX_HALF; |
| 1217 | else |
| 1218 | active_duplex = DUPLEX_INVALID; |
| 1219 | } else { |
| 1220 | lp->active_autoneg = 0; |
| 1221 | |
| 1222 | if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100)) |
| 1223 | active_speed = SPEED_1000; |
| 1224 | else if (bmcr & BMCR_SPEED100) |
| 1225 | active_speed = SPEED_100; |
| 1226 | else |
| 1227 | active_speed = SPEED_10; |
| 1228 | |
| 1229 | if (bmcr & BMCR_FULLDPLX) |
| 1230 | active_duplex = DUPLEX_FULL; |
| 1231 | else |
| 1232 | active_duplex = DUPLEX_HALF; |
| 1233 | } |
| 1234 | |
| 1235 | lp->active_advertising = advertising; |
| 1236 | lp->active_speed = active_speed; |
| 1237 | lp->active_duplex = active_duplex; |
| 1238 | *link_up_p = !!(bmsr & BMSR_LSTATUS); |
| 1239 | |
| 1240 | return 0; |
| 1241 | } |
| 1242 | |
| 1243 | static int link_status_1g_rgmii(struct niu *np, int *link_up_p) |
| 1244 | { |
| 1245 | struct niu_link_config *lp = &np->link_config; |
| 1246 | u16 current_speed, bmsr; |
| 1247 | unsigned long flags; |
| 1248 | u8 current_duplex; |
| 1249 | int err, link_up; |
| 1250 | |
| 1251 | link_up = 0; |
| 1252 | current_speed = SPEED_INVALID; |
| 1253 | current_duplex = DUPLEX_INVALID; |
| 1254 | |
| 1255 | spin_lock_irqsave(&np->lock, flags); |
| 1256 | |
| 1257 | err = -EINVAL; |
| 1258 | |
| 1259 | err = mii_read(np, np->phy_addr, MII_BMSR); |
| 1260 | if (err < 0) |
| 1261 | goto out; |
| 1262 | |
| 1263 | bmsr = err; |
| 1264 | if (bmsr & BMSR_LSTATUS) { |
| 1265 | u16 adv, lpa, common, estat; |
| 1266 | |
| 1267 | err = mii_read(np, np->phy_addr, MII_ADVERTISE); |
| 1268 | if (err < 0) |
| 1269 | goto out; |
| 1270 | adv = err; |
| 1271 | |
| 1272 | err = mii_read(np, np->phy_addr, MII_LPA); |
| 1273 | if (err < 0) |
| 1274 | goto out; |
| 1275 | lpa = err; |
| 1276 | |
| 1277 | common = adv & lpa; |
| 1278 | |
| 1279 | err = mii_read(np, np->phy_addr, MII_ESTATUS); |
| 1280 | if (err < 0) |
| 1281 | goto out; |
| 1282 | estat = err; |
| 1283 | link_up = 1; |
| 1284 | current_speed = SPEED_1000; |
| 1285 | current_duplex = DUPLEX_FULL; |
| 1286 | |
| 1287 | } |
| 1288 | lp->active_speed = current_speed; |
| 1289 | lp->active_duplex = current_duplex; |
| 1290 | err = 0; |
| 1291 | |
| 1292 | out: |
| 1293 | spin_unlock_irqrestore(&np->lock, flags); |
| 1294 | |
| 1295 | *link_up_p = link_up; |
| 1296 | return err; |
| 1297 | } |
| 1298 | |
| 1299 | static int link_status_1g(struct niu *np, int *link_up_p) |
| 1300 | { |
| 1301 | struct niu_link_config *lp = &np->link_config; |
| 1302 | unsigned long flags; |
| 1303 | int err; |
| 1304 | |
| 1305 | spin_lock_irqsave(&np->lock, flags); |
| 1306 | |
| 1307 | err = link_status_mii(np, link_up_p); |
| 1308 | lp->supported |= SUPPORTED_TP; |
| 1309 | lp->active_advertising |= ADVERTISED_TP; |
| 1310 | |
| 1311 | spin_unlock_irqrestore(&np->lock, flags); |
| 1312 | return err; |
| 1313 | } |
| 1314 | |
| 1315 | static int bcm8704_reset(struct niu *np) |
| 1316 | { |
| 1317 | int err, limit; |
| 1318 | |
| 1319 | err = mdio_read(np, np->phy_addr, |
| 1320 | BCM8704_PHYXS_DEV_ADDR, MII_BMCR); |
| 1321 | if (err < 0 || err == 0xffff) |
| 1322 | return err; |
| 1323 | err |= BMCR_RESET; |
| 1324 | err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, |
| 1325 | MII_BMCR, err); |
| 1326 | if (err) |
| 1327 | return err; |
| 1328 | |
| 1329 | limit = 1000; |
| 1330 | while (--limit >= 0) { |
| 1331 | err = mdio_read(np, np->phy_addr, |
| 1332 | BCM8704_PHYXS_DEV_ADDR, MII_BMCR); |
| 1333 | if (err < 0) |
| 1334 | return err; |
| 1335 | if (!(err & BMCR_RESET)) |
| 1336 | break; |
| 1337 | } |
| 1338 | if (limit < 0) { |
| 1339 | dev_err(np->device, PFX "Port %u PHY will not reset " |
| 1340 | "(bmcr=%04x)\n", np->port, (err & 0xffff)); |
| 1341 | return -ENODEV; |
| 1342 | } |
| 1343 | return 0; |
| 1344 | } |
| 1345 | |
| 1346 | /* When written, certain PHY registers need to be read back twice |
| 1347 | * in order for the bits to settle properly. |
| 1348 | */ |
| 1349 | static int bcm8704_user_dev3_readback(struct niu *np, int reg) |
| 1350 | { |
| 1351 | int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); |
| 1352 | if (err < 0) |
| 1353 | return err; |
| 1354 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); |
| 1355 | if (err < 0) |
| 1356 | return err; |
| 1357 | return 0; |
| 1358 | } |
| 1359 | |
| 1360 | static int bcm8706_init_user_dev3(struct niu *np) |
| 1361 | { |
| 1362 | int err; |
| 1363 | |
| 1364 | |
| 1365 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, |
| 1366 | BCM8704_USER_OPT_DIGITAL_CTRL); |
| 1367 | if (err < 0) |
| 1368 | return err; |
| 1369 | err &= ~USER_ODIG_CTRL_GPIOS; |
| 1370 | err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); |
| 1371 | err |= USER_ODIG_CTRL_RESV2; |
| 1372 | err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, |
| 1373 | BCM8704_USER_OPT_DIGITAL_CTRL, err); |
| 1374 | if (err) |
| 1375 | return err; |
| 1376 | |
| 1377 | mdelay(1000); |
| 1378 | |
| 1379 | return 0; |
| 1380 | } |
| 1381 | |
| 1382 | static int bcm8704_init_user_dev3(struct niu *np) |
| 1383 | { |
| 1384 | int err; |
| 1385 | |
| 1386 | err = mdio_write(np, np->phy_addr, |
| 1387 | BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL, |
| 1388 | (USER_CONTROL_OPTXRST_LVL | |
| 1389 | USER_CONTROL_OPBIASFLT_LVL | |
| 1390 | USER_CONTROL_OBTMPFLT_LVL | |
| 1391 | USER_CONTROL_OPPRFLT_LVL | |
| 1392 | USER_CONTROL_OPTXFLT_LVL | |
| 1393 | USER_CONTROL_OPRXLOS_LVL | |
| 1394 | USER_CONTROL_OPRXFLT_LVL | |
| 1395 | USER_CONTROL_OPTXON_LVL | |
| 1396 | (0x3f << USER_CONTROL_RES1_SHIFT))); |
| 1397 | if (err) |
| 1398 | return err; |
| 1399 | |
| 1400 | err = mdio_write(np, np->phy_addr, |
| 1401 | BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL, |
| 1402 | (USER_PMD_TX_CTL_XFP_CLKEN | |
| 1403 | (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) | |
| 1404 | (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) | |
| 1405 | USER_PMD_TX_CTL_TSCK_LPWREN)); |
| 1406 | if (err) |
| 1407 | return err; |
| 1408 | |
| 1409 | err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL); |
| 1410 | if (err) |
| 1411 | return err; |
| 1412 | err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL); |
| 1413 | if (err) |
| 1414 | return err; |
| 1415 | |
| 1416 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, |
| 1417 | BCM8704_USER_OPT_DIGITAL_CTRL); |
| 1418 | if (err < 0) |
| 1419 | return err; |
| 1420 | err &= ~USER_ODIG_CTRL_GPIOS; |
| 1421 | err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); |
| 1422 | err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, |
| 1423 | BCM8704_USER_OPT_DIGITAL_CTRL, err); |
| 1424 | if (err) |
| 1425 | return err; |
| 1426 | |
| 1427 | mdelay(1000); |
| 1428 | |
| 1429 | return 0; |
| 1430 | } |
| 1431 | |
| 1432 | static int mrvl88x2011_act_led(struct niu *np, int val) |
| 1433 | { |
| 1434 | int err; |
| 1435 | |
| 1436 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, |
| 1437 | MRVL88X2011_LED_8_TO_11_CTL); |
| 1438 | if (err < 0) |
| 1439 | return err; |
| 1440 | |
| 1441 | err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK); |
| 1442 | err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val); |
| 1443 | |
| 1444 | return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, |
| 1445 | MRVL88X2011_LED_8_TO_11_CTL, err); |
| 1446 | } |
| 1447 | |
| 1448 | static int mrvl88x2011_led_blink_rate(struct niu *np, int rate) |
| 1449 | { |
| 1450 | int err; |
| 1451 | |
| 1452 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, |
| 1453 | MRVL88X2011_LED_BLINK_CTL); |
| 1454 | if (err >= 0) { |
| 1455 | err &= ~MRVL88X2011_LED_BLKRATE_MASK; |
| 1456 | err |= (rate << 4); |
| 1457 | |
| 1458 | err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, |
| 1459 | MRVL88X2011_LED_BLINK_CTL, err); |
| 1460 | } |
| 1461 | |
| 1462 | return err; |
| 1463 | } |
| 1464 | |
| 1465 | static int xcvr_init_10g_mrvl88x2011(struct niu *np) |
| 1466 | { |
| 1467 | int err; |
| 1468 | |
| 1469 | /* Set LED functions */ |
| 1470 | err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS); |
| 1471 | if (err) |
| 1472 | return err; |
| 1473 | |
| 1474 | /* led activity */ |
| 1475 | err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF); |
| 1476 | if (err) |
| 1477 | return err; |
| 1478 | |
| 1479 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, |
| 1480 | MRVL88X2011_GENERAL_CTL); |
| 1481 | if (err < 0) |
| 1482 | return err; |
| 1483 | |
| 1484 | err |= MRVL88X2011_ENA_XFPREFCLK; |
| 1485 | |
| 1486 | err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, |
| 1487 | MRVL88X2011_GENERAL_CTL, err); |
| 1488 | if (err < 0) |
| 1489 | return err; |
| 1490 | |
| 1491 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, |
| 1492 | MRVL88X2011_PMA_PMD_CTL_1); |
| 1493 | if (err < 0) |
| 1494 | return err; |
| 1495 | |
| 1496 | if (np->link_config.loopback_mode == LOOPBACK_MAC) |
| 1497 | err |= MRVL88X2011_LOOPBACK; |
| 1498 | else |
| 1499 | err &= ~MRVL88X2011_LOOPBACK; |
| 1500 | |
| 1501 | err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, |
| 1502 | MRVL88X2011_PMA_PMD_CTL_1, err); |
| 1503 | if (err < 0) |
| 1504 | return err; |
| 1505 | |
| 1506 | /* Enable PMD */ |
| 1507 | return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, |
| 1508 | MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX); |
| 1509 | } |
| 1510 | |
| 1511 | |
| 1512 | static int xcvr_diag_bcm870x(struct niu *np) |
| 1513 | { |
| 1514 | u16 analog_stat0, tx_alarm_status; |
| 1515 | int err = 0; |
| 1516 | |
| 1517 | #if 1 |
| 1518 | err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, |
| 1519 | MII_STAT1000); |
| 1520 | if (err < 0) |
| 1521 | return err; |
| 1522 | pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n", |
| 1523 | np->port, err); |
| 1524 | |
| 1525 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20); |
| 1526 | if (err < 0) |
| 1527 | return err; |
| 1528 | pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n", |
| 1529 | np->port, err); |
| 1530 | |
| 1531 | err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, |
| 1532 | MII_NWAYTEST); |
| 1533 | if (err < 0) |
| 1534 | return err; |
| 1535 | pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n", |
| 1536 | np->port, err); |
| 1537 | #endif |
| 1538 | |
| 1539 | /* XXX dig this out it might not be so useful XXX */ |
| 1540 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, |
| 1541 | BCM8704_USER_ANALOG_STATUS0); |
| 1542 | if (err < 0) |
| 1543 | return err; |
| 1544 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, |
| 1545 | BCM8704_USER_ANALOG_STATUS0); |
| 1546 | if (err < 0) |
| 1547 | return err; |
| 1548 | analog_stat0 = err; |
| 1549 | |
| 1550 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, |
| 1551 | BCM8704_USER_TX_ALARM_STATUS); |
| 1552 | if (err < 0) |
| 1553 | return err; |
| 1554 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, |
| 1555 | BCM8704_USER_TX_ALARM_STATUS); |
| 1556 | if (err < 0) |
| 1557 | return err; |
| 1558 | tx_alarm_status = err; |
| 1559 | |
| 1560 | if (analog_stat0 != 0x03fc) { |
| 1561 | if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) { |
| 1562 | pr_info(PFX "Port %u cable not connected " |
| 1563 | "or bad cable.\n", np->port); |
| 1564 | } else if (analog_stat0 == 0x639c) { |
| 1565 | pr_info(PFX "Port %u optical module is bad " |
| 1566 | "or missing.\n", np->port); |
| 1567 | } |
| 1568 | } |
| 1569 | |
| 1570 | return 0; |
| 1571 | } |
| 1572 | |
| 1573 | static int xcvr_10g_set_lb_bcm870x(struct niu *np) |
| 1574 | { |
| 1575 | struct niu_link_config *lp = &np->link_config; |
| 1576 | int err; |
| 1577 | |
| 1578 | err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, |
| 1579 | MII_BMCR); |
| 1580 | if (err < 0) |
| 1581 | return err; |
| 1582 | |
| 1583 | err &= ~BMCR_LOOPBACK; |
| 1584 | |
| 1585 | if (lp->loopback_mode == LOOPBACK_MAC) |
| 1586 | err |= BMCR_LOOPBACK; |
| 1587 | |
| 1588 | err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, |
| 1589 | MII_BMCR, err); |
| 1590 | if (err) |
| 1591 | return err; |
| 1592 | |
| 1593 | return 0; |
| 1594 | } |
| 1595 | |
| 1596 | static int xcvr_init_10g_bcm8706(struct niu *np) |
| 1597 | { |
| 1598 | int err = 0; |
| 1599 | u64 val; |
| 1600 | |
| 1601 | if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) && |
| 1602 | (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0) |
| 1603 | return err; |
| 1604 | |
| 1605 | val = nr64_mac(XMAC_CONFIG); |
| 1606 | val &= ~XMAC_CONFIG_LED_POLARITY; |
| 1607 | val |= XMAC_CONFIG_FORCE_LED_ON; |
| 1608 | nw64_mac(XMAC_CONFIG, val); |
| 1609 | |
| 1610 | val = nr64(MIF_CONFIG); |
| 1611 | val |= MIF_CONFIG_INDIRECT_MODE; |
| 1612 | nw64(MIF_CONFIG, val); |
| 1613 | |
| 1614 | err = bcm8704_reset(np); |
| 1615 | if (err) |
| 1616 | return err; |
| 1617 | |
| 1618 | err = xcvr_10g_set_lb_bcm870x(np); |
| 1619 | if (err) |
| 1620 | return err; |
| 1621 | |
| 1622 | err = bcm8706_init_user_dev3(np); |
| 1623 | if (err) |
| 1624 | return err; |
| 1625 | |
| 1626 | err = xcvr_diag_bcm870x(np); |
| 1627 | if (err) |
| 1628 | return err; |
| 1629 | |
| 1630 | return 0; |
| 1631 | } |
| 1632 | |
| 1633 | static int xcvr_init_10g_bcm8704(struct niu *np) |
| 1634 | { |
| 1635 | int err; |
| 1636 | |
| 1637 | err = bcm8704_reset(np); |
| 1638 | if (err) |
| 1639 | return err; |
| 1640 | |
| 1641 | err = bcm8704_init_user_dev3(np); |
| 1642 | if (err) |
| 1643 | return err; |
| 1644 | |
| 1645 | err = xcvr_10g_set_lb_bcm870x(np); |
| 1646 | if (err) |
| 1647 | return err; |
| 1648 | |
| 1649 | err = xcvr_diag_bcm870x(np); |
| 1650 | if (err) |
| 1651 | return err; |
| 1652 | |
| 1653 | return 0; |
| 1654 | } |
| 1655 | |
| 1656 | static int xcvr_init_10g(struct niu *np) |
| 1657 | { |
| 1658 | int phy_id, err; |
| 1659 | u64 val; |
| 1660 | |
| 1661 | val = nr64_mac(XMAC_CONFIG); |
| 1662 | val &= ~XMAC_CONFIG_LED_POLARITY; |
| 1663 | val |= XMAC_CONFIG_FORCE_LED_ON; |
| 1664 | nw64_mac(XMAC_CONFIG, val); |
| 1665 | |
| 1666 | /* XXX shared resource, lock parent XXX */ |
| 1667 | val = nr64(MIF_CONFIG); |
| 1668 | val |= MIF_CONFIG_INDIRECT_MODE; |
| 1669 | nw64(MIF_CONFIG, val); |
| 1670 | |
| 1671 | phy_id = phy_decode(np->parent->port_phy, np->port); |
| 1672 | phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; |
| 1673 | |
| 1674 | /* handle different phy types */ |
| 1675 | switch (phy_id & NIU_PHY_ID_MASK) { |
| 1676 | case NIU_PHY_ID_MRVL88X2011: |
| 1677 | err = xcvr_init_10g_mrvl88x2011(np); |
| 1678 | break; |
| 1679 | |
| 1680 | default: /* bcom 8704 */ |
| 1681 | err = xcvr_init_10g_bcm8704(np); |
| 1682 | break; |
| 1683 | } |
| 1684 | |
| 1685 | return 0; |
| 1686 | } |
| 1687 | |
| 1688 | static int mii_reset(struct niu *np) |
| 1689 | { |
| 1690 | int limit, err; |
| 1691 | |
| 1692 | err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET); |
| 1693 | if (err) |
| 1694 | return err; |
| 1695 | |
| 1696 | limit = 1000; |
| 1697 | while (--limit >= 0) { |
| 1698 | udelay(500); |
| 1699 | err = mii_read(np, np->phy_addr, MII_BMCR); |
| 1700 | if (err < 0) |
| 1701 | return err; |
| 1702 | if (!(err & BMCR_RESET)) |
| 1703 | break; |
| 1704 | } |
| 1705 | if (limit < 0) { |
| 1706 | dev_err(np->device, PFX "Port %u MII would not reset, " |
| 1707 | "bmcr[%04x]\n", np->port, err); |
| 1708 | return -ENODEV; |
| 1709 | } |
| 1710 | |
| 1711 | return 0; |
| 1712 | } |
| 1713 | |
| 1714 | static int xcvr_init_1g_rgmii(struct niu *np) |
| 1715 | { |
| 1716 | int err; |
| 1717 | u64 val; |
| 1718 | u16 bmcr, bmsr, estat; |
| 1719 | |
| 1720 | val = nr64(MIF_CONFIG); |
| 1721 | val &= ~MIF_CONFIG_INDIRECT_MODE; |
| 1722 | nw64(MIF_CONFIG, val); |
| 1723 | |
| 1724 | err = mii_reset(np); |
| 1725 | if (err) |
| 1726 | return err; |
| 1727 | |
| 1728 | err = mii_read(np, np->phy_addr, MII_BMSR); |
| 1729 | if (err < 0) |
| 1730 | return err; |
| 1731 | bmsr = err; |
| 1732 | |
| 1733 | estat = 0; |
| 1734 | if (bmsr & BMSR_ESTATEN) { |
| 1735 | err = mii_read(np, np->phy_addr, MII_ESTATUS); |
| 1736 | if (err < 0) |
| 1737 | return err; |
| 1738 | estat = err; |
| 1739 | } |
| 1740 | |
| 1741 | bmcr = 0; |
| 1742 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); |
| 1743 | if (err) |
| 1744 | return err; |
| 1745 | |
| 1746 | if (bmsr & BMSR_ESTATEN) { |
| 1747 | u16 ctrl1000 = 0; |
| 1748 | |
| 1749 | if (estat & ESTATUS_1000_TFULL) |
| 1750 | ctrl1000 |= ADVERTISE_1000FULL; |
| 1751 | err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000); |
| 1752 | if (err) |
| 1753 | return err; |
| 1754 | } |
| 1755 | |
| 1756 | bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX); |
| 1757 | |
| 1758 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); |
| 1759 | if (err) |
| 1760 | return err; |
| 1761 | |
| 1762 | err = mii_read(np, np->phy_addr, MII_BMCR); |
| 1763 | if (err < 0) |
| 1764 | return err; |
| 1765 | bmcr = mii_read(np, np->phy_addr, MII_BMCR); |
| 1766 | |
| 1767 | err = mii_read(np, np->phy_addr, MII_BMSR); |
| 1768 | if (err < 0) |
| 1769 | return err; |
| 1770 | |
| 1771 | return 0; |
| 1772 | } |
| 1773 | |
| 1774 | static int mii_init_common(struct niu *np) |
| 1775 | { |
| 1776 | struct niu_link_config *lp = &np->link_config; |
| 1777 | u16 bmcr, bmsr, adv, estat; |
| 1778 | int err; |
| 1779 | |
| 1780 | err = mii_reset(np); |
| 1781 | if (err) |
| 1782 | return err; |
| 1783 | |
| 1784 | err = mii_read(np, np->phy_addr, MII_BMSR); |
| 1785 | if (err < 0) |
| 1786 | return err; |
| 1787 | bmsr = err; |
| 1788 | |
| 1789 | estat = 0; |
| 1790 | if (bmsr & BMSR_ESTATEN) { |
| 1791 | err = mii_read(np, np->phy_addr, MII_ESTATUS); |
| 1792 | if (err < 0) |
| 1793 | return err; |
| 1794 | estat = err; |
| 1795 | } |
| 1796 | |
| 1797 | bmcr = 0; |
| 1798 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); |
| 1799 | if (err) |
| 1800 | return err; |
| 1801 | |
| 1802 | if (lp->loopback_mode == LOOPBACK_MAC) { |
| 1803 | bmcr |= BMCR_LOOPBACK; |
| 1804 | if (lp->active_speed == SPEED_1000) |
| 1805 | bmcr |= BMCR_SPEED1000; |
| 1806 | if (lp->active_duplex == DUPLEX_FULL) |
| 1807 | bmcr |= BMCR_FULLDPLX; |
| 1808 | } |
| 1809 | |
| 1810 | if (lp->loopback_mode == LOOPBACK_PHY) { |
| 1811 | u16 aux; |
| 1812 | |
| 1813 | aux = (BCM5464R_AUX_CTL_EXT_LB | |
| 1814 | BCM5464R_AUX_CTL_WRITE_1); |
| 1815 | err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux); |
| 1816 | if (err) |
| 1817 | return err; |
| 1818 | } |
| 1819 | |
| 1820 | if (lp->autoneg) { |
| 1821 | u16 ctrl1000; |
| 1822 | |
| 1823 | adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP; |
| 1824 | if ((bmsr & BMSR_10HALF) && |
| 1825 | (lp->advertising & ADVERTISED_10baseT_Half)) |
| 1826 | adv |= ADVERTISE_10HALF; |
| 1827 | if ((bmsr & BMSR_10FULL) && |
| 1828 | (lp->advertising & ADVERTISED_10baseT_Full)) |
| 1829 | adv |= ADVERTISE_10FULL; |
| 1830 | if ((bmsr & BMSR_100HALF) && |
| 1831 | (lp->advertising & ADVERTISED_100baseT_Half)) |
| 1832 | adv |= ADVERTISE_100HALF; |
| 1833 | if ((bmsr & BMSR_100FULL) && |
| 1834 | (lp->advertising & ADVERTISED_100baseT_Full)) |
| 1835 | adv |= ADVERTISE_100FULL; |
| 1836 | err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv); |
| 1837 | if (err) |
| 1838 | return err; |
| 1839 | |
| 1840 | if (likely(bmsr & BMSR_ESTATEN)) { |
| 1841 | ctrl1000 = 0; |
| 1842 | if ((estat & ESTATUS_1000_THALF) && |
| 1843 | (lp->advertising & ADVERTISED_1000baseT_Half)) |
| 1844 | ctrl1000 |= ADVERTISE_1000HALF; |
| 1845 | if ((estat & ESTATUS_1000_TFULL) && |
| 1846 | (lp->advertising & ADVERTISED_1000baseT_Full)) |
| 1847 | ctrl1000 |= ADVERTISE_1000FULL; |
| 1848 | err = mii_write(np, np->phy_addr, |
| 1849 | MII_CTRL1000, ctrl1000); |
| 1850 | if (err) |
| 1851 | return err; |
| 1852 | } |
| 1853 | |
| 1854 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
| 1855 | } else { |
| 1856 | /* !lp->autoneg */ |
| 1857 | int fulldpx; |
| 1858 | |
| 1859 | if (lp->duplex == DUPLEX_FULL) { |
| 1860 | bmcr |= BMCR_FULLDPLX; |
| 1861 | fulldpx = 1; |
| 1862 | } else if (lp->duplex == DUPLEX_HALF) |
| 1863 | fulldpx = 0; |
| 1864 | else |
| 1865 | return -EINVAL; |
| 1866 | |
| 1867 | if (lp->speed == SPEED_1000) { |
| 1868 | /* if X-full requested while not supported, or |
| 1869 | X-half requested while not supported... */ |
| 1870 | if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) || |
| 1871 | (!fulldpx && !(estat & ESTATUS_1000_THALF))) |
| 1872 | return -EINVAL; |
| 1873 | bmcr |= BMCR_SPEED1000; |
| 1874 | } else if (lp->speed == SPEED_100) { |
| 1875 | if ((fulldpx && !(bmsr & BMSR_100FULL)) || |
| 1876 | (!fulldpx && !(bmsr & BMSR_100HALF))) |
| 1877 | return -EINVAL; |
| 1878 | bmcr |= BMCR_SPEED100; |
| 1879 | } else if (lp->speed == SPEED_10) { |
| 1880 | if ((fulldpx && !(bmsr & BMSR_10FULL)) || |
| 1881 | (!fulldpx && !(bmsr & BMSR_10HALF))) |
| 1882 | return -EINVAL; |
| 1883 | } else |
| 1884 | return -EINVAL; |
| 1885 | } |
| 1886 | |
| 1887 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); |
| 1888 | if (err) |
| 1889 | return err; |
| 1890 | |
| 1891 | #if 0 |
| 1892 | err = mii_read(np, np->phy_addr, MII_BMCR); |
| 1893 | if (err < 0) |
| 1894 | return err; |
| 1895 | bmcr = err; |
| 1896 | |
| 1897 | err = mii_read(np, np->phy_addr, MII_BMSR); |
| 1898 | if (err < 0) |
| 1899 | return err; |
| 1900 | bmsr = err; |
| 1901 | |
| 1902 | pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n", |
| 1903 | np->port, bmcr, bmsr); |
| 1904 | #endif |
| 1905 | |
| 1906 | return 0; |
| 1907 | } |
| 1908 | |
| 1909 | static int xcvr_init_1g(struct niu *np) |
| 1910 | { |
| 1911 | u64 val; |
| 1912 | |
| 1913 | /* XXX shared resource, lock parent XXX */ |
| 1914 | val = nr64(MIF_CONFIG); |
| 1915 | val &= ~MIF_CONFIG_INDIRECT_MODE; |
| 1916 | nw64(MIF_CONFIG, val); |
| 1917 | |
| 1918 | return mii_init_common(np); |
| 1919 | } |
| 1920 | |
| 1921 | static int niu_xcvr_init(struct niu *np) |
| 1922 | { |
| 1923 | const struct niu_phy_ops *ops = np->phy_ops; |
| 1924 | int err; |
| 1925 | |
| 1926 | err = 0; |
| 1927 | if (ops->xcvr_init) |
| 1928 | err = ops->xcvr_init(np); |
| 1929 | |
| 1930 | return err; |
| 1931 | } |
| 1932 | |
| 1933 | static int niu_serdes_init(struct niu *np) |
| 1934 | { |
| 1935 | const struct niu_phy_ops *ops = np->phy_ops; |
| 1936 | int err; |
| 1937 | |
| 1938 | err = 0; |
| 1939 | if (ops->serdes_init) |
| 1940 | err = ops->serdes_init(np); |
| 1941 | |
| 1942 | return err; |
| 1943 | } |
| 1944 | |
| 1945 | static void niu_init_xif(struct niu *); |
| 1946 | static void niu_handle_led(struct niu *, int status); |
| 1947 | |
| 1948 | static int niu_link_status_common(struct niu *np, int link_up) |
| 1949 | { |
| 1950 | struct niu_link_config *lp = &np->link_config; |
| 1951 | struct net_device *dev = np->dev; |
| 1952 | unsigned long flags; |
| 1953 | |
| 1954 | if (!netif_carrier_ok(dev) && link_up) { |
| 1955 | niuinfo(LINK, "%s: Link is up at %s, %s duplex\n", |
| 1956 | dev->name, |
| 1957 | (lp->active_speed == SPEED_10000 ? |
| 1958 | "10Gb/sec" : |
| 1959 | (lp->active_speed == SPEED_1000 ? |
| 1960 | "1Gb/sec" : |
| 1961 | (lp->active_speed == SPEED_100 ? |
| 1962 | "100Mbit/sec" : "10Mbit/sec"))), |
| 1963 | (lp->active_duplex == DUPLEX_FULL ? |
| 1964 | "full" : "half")); |
| 1965 | |
| 1966 | spin_lock_irqsave(&np->lock, flags); |
| 1967 | niu_init_xif(np); |
| 1968 | niu_handle_led(np, 1); |
| 1969 | spin_unlock_irqrestore(&np->lock, flags); |
| 1970 | |
| 1971 | netif_carrier_on(dev); |
| 1972 | } else if (netif_carrier_ok(dev) && !link_up) { |
| 1973 | niuwarn(LINK, "%s: Link is down\n", dev->name); |
| 1974 | spin_lock_irqsave(&np->lock, flags); |
| 1975 | niu_handle_led(np, 0); |
| 1976 | spin_unlock_irqrestore(&np->lock, flags); |
| 1977 | netif_carrier_off(dev); |
| 1978 | } |
| 1979 | |
| 1980 | return 0; |
| 1981 | } |
| 1982 | |
| 1983 | static int link_status_10g_mrvl(struct niu *np, int *link_up_p) |
| 1984 | { |
| 1985 | int err, link_up, pma_status, pcs_status; |
| 1986 | |
| 1987 | link_up = 0; |
| 1988 | |
| 1989 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, |
| 1990 | MRVL88X2011_10G_PMD_STATUS_2); |
| 1991 | if (err < 0) |
| 1992 | goto out; |
| 1993 | |
| 1994 | /* Check PMA/PMD Register: 1.0001.2 == 1 */ |
| 1995 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, |
| 1996 | MRVL88X2011_PMA_PMD_STATUS_1); |
| 1997 | if (err < 0) |
| 1998 | goto out; |
| 1999 | |
| 2000 | pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); |
| 2001 | |
| 2002 | /* Check PMC Register : 3.0001.2 == 1: read twice */ |
| 2003 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, |
| 2004 | MRVL88X2011_PMA_PMD_STATUS_1); |
| 2005 | if (err < 0) |
| 2006 | goto out; |
| 2007 | |
| 2008 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, |
| 2009 | MRVL88X2011_PMA_PMD_STATUS_1); |
| 2010 | if (err < 0) |
| 2011 | goto out; |
| 2012 | |
| 2013 | pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); |
| 2014 | |
| 2015 | /* Check XGXS Register : 4.0018.[0-3,12] */ |
| 2016 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR, |
| 2017 | MRVL88X2011_10G_XGXS_LANE_STAT); |
| 2018 | if (err < 0) |
| 2019 | goto out; |
| 2020 | |
| 2021 | if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 | |
| 2022 | PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 | |
| 2023 | PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC | |
| 2024 | 0x800)) |
| 2025 | link_up = (pma_status && pcs_status) ? 1 : 0; |
| 2026 | |
| 2027 | np->link_config.active_speed = SPEED_10000; |
| 2028 | np->link_config.active_duplex = DUPLEX_FULL; |
| 2029 | err = 0; |
| 2030 | out: |
| 2031 | mrvl88x2011_act_led(np, (link_up ? |
| 2032 | MRVL88X2011_LED_CTL_PCS_ACT : |
| 2033 | MRVL88X2011_LED_CTL_OFF)); |
| 2034 | |
| 2035 | *link_up_p = link_up; |
| 2036 | return err; |
| 2037 | } |
| 2038 | |
| 2039 | static int link_status_10g_bcm8706(struct niu *np, int *link_up_p) |
| 2040 | { |
| 2041 | int err, link_up; |
| 2042 | link_up = 0; |
| 2043 | |
| 2044 | err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, |
| 2045 | BCM8704_PMD_RCV_SIGDET); |
| 2046 | if (err < 0 || err == 0xffff) |
| 2047 | goto out; |
| 2048 | if (!(err & PMD_RCV_SIGDET_GLOBAL)) { |
| 2049 | err = 0; |
| 2050 | goto out; |
| 2051 | } |
| 2052 | |
| 2053 | err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, |
| 2054 | BCM8704_PCS_10G_R_STATUS); |
| 2055 | if (err < 0) |
| 2056 | goto out; |
| 2057 | |
| 2058 | if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { |
| 2059 | err = 0; |
| 2060 | goto out; |
| 2061 | } |
| 2062 | |
| 2063 | err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, |
| 2064 | BCM8704_PHYXS_XGXS_LANE_STAT); |
| 2065 | if (err < 0) |
| 2066 | goto out; |
| 2067 | if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | |
| 2068 | PHYXS_XGXS_LANE_STAT_MAGIC | |
| 2069 | PHYXS_XGXS_LANE_STAT_PATTEST | |
| 2070 | PHYXS_XGXS_LANE_STAT_LANE3 | |
| 2071 | PHYXS_XGXS_LANE_STAT_LANE2 | |
| 2072 | PHYXS_XGXS_LANE_STAT_LANE1 | |
| 2073 | PHYXS_XGXS_LANE_STAT_LANE0)) { |
| 2074 | err = 0; |
| 2075 | np->link_config.active_speed = SPEED_INVALID; |
| 2076 | np->link_config.active_duplex = DUPLEX_INVALID; |
| 2077 | goto out; |
| 2078 | } |
| 2079 | |
| 2080 | link_up = 1; |
| 2081 | np->link_config.active_speed = SPEED_10000; |
| 2082 | np->link_config.active_duplex = DUPLEX_FULL; |
| 2083 | err = 0; |
| 2084 | |
| 2085 | out: |
| 2086 | *link_up_p = link_up; |
| 2087 | return err; |
| 2088 | } |
| 2089 | |
| 2090 | static int link_status_10g_bcom(struct niu *np, int *link_up_p) |
| 2091 | { |
| 2092 | int err, link_up; |
| 2093 | |
| 2094 | link_up = 0; |
| 2095 | |
| 2096 | err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, |
| 2097 | BCM8704_PMD_RCV_SIGDET); |
| 2098 | if (err < 0) |
| 2099 | goto out; |
| 2100 | if (!(err & PMD_RCV_SIGDET_GLOBAL)) { |
| 2101 | err = 0; |
| 2102 | goto out; |
| 2103 | } |
| 2104 | |
| 2105 | err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, |
| 2106 | BCM8704_PCS_10G_R_STATUS); |
| 2107 | if (err < 0) |
| 2108 | goto out; |
| 2109 | if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { |
| 2110 | err = 0; |
| 2111 | goto out; |
| 2112 | } |
| 2113 | |
| 2114 | err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, |
| 2115 | BCM8704_PHYXS_XGXS_LANE_STAT); |
| 2116 | if (err < 0) |
| 2117 | goto out; |
| 2118 | |
| 2119 | if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | |
| 2120 | PHYXS_XGXS_LANE_STAT_MAGIC | |
| 2121 | PHYXS_XGXS_LANE_STAT_LANE3 | |
| 2122 | PHYXS_XGXS_LANE_STAT_LANE2 | |
| 2123 | PHYXS_XGXS_LANE_STAT_LANE1 | |
| 2124 | PHYXS_XGXS_LANE_STAT_LANE0)) { |
| 2125 | err = 0; |
| 2126 | goto out; |
| 2127 | } |
| 2128 | |
| 2129 | link_up = 1; |
| 2130 | np->link_config.active_speed = SPEED_10000; |
| 2131 | np->link_config.active_duplex = DUPLEX_FULL; |
| 2132 | err = 0; |
| 2133 | |
| 2134 | out: |
| 2135 | *link_up_p = link_up; |
| 2136 | return err; |
| 2137 | } |
| 2138 | |
| 2139 | static int link_status_10g(struct niu *np, int *link_up_p) |
| 2140 | { |
| 2141 | unsigned long flags; |
| 2142 | int err = -EINVAL; |
| 2143 | |
| 2144 | spin_lock_irqsave(&np->lock, flags); |
| 2145 | |
| 2146 | if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { |
| 2147 | int phy_id; |
| 2148 | |
| 2149 | phy_id = phy_decode(np->parent->port_phy, np->port); |
| 2150 | phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; |
| 2151 | |
| 2152 | /* handle different phy types */ |
| 2153 | switch (phy_id & NIU_PHY_ID_MASK) { |
| 2154 | case NIU_PHY_ID_MRVL88X2011: |
| 2155 | err = link_status_10g_mrvl(np, link_up_p); |
| 2156 | break; |
| 2157 | |
| 2158 | default: /* bcom 8704 */ |
| 2159 | err = link_status_10g_bcom(np, link_up_p); |
| 2160 | break; |
| 2161 | } |
| 2162 | } |
| 2163 | |
| 2164 | spin_unlock_irqrestore(&np->lock, flags); |
| 2165 | |
| 2166 | return err; |
| 2167 | } |
| 2168 | |
| 2169 | static int niu_10g_phy_present(struct niu *np) |
| 2170 | { |
| 2171 | u64 sig, mask, val; |
| 2172 | |
| 2173 | sig = nr64(ESR_INT_SIGNALS); |
| 2174 | switch (np->port) { |
| 2175 | case 0: |
| 2176 | mask = ESR_INT_SIGNALS_P0_BITS; |
| 2177 | val = (ESR_INT_SRDY0_P0 | |
| 2178 | ESR_INT_DET0_P0 | |
| 2179 | ESR_INT_XSRDY_P0 | |
| 2180 | ESR_INT_XDP_P0_CH3 | |
| 2181 | ESR_INT_XDP_P0_CH2 | |
| 2182 | ESR_INT_XDP_P0_CH1 | |
| 2183 | ESR_INT_XDP_P0_CH0); |
| 2184 | break; |
| 2185 | |
| 2186 | case 1: |
| 2187 | mask = ESR_INT_SIGNALS_P1_BITS; |
| 2188 | val = (ESR_INT_SRDY0_P1 | |
| 2189 | ESR_INT_DET0_P1 | |
| 2190 | ESR_INT_XSRDY_P1 | |
| 2191 | ESR_INT_XDP_P1_CH3 | |
| 2192 | ESR_INT_XDP_P1_CH2 | |
| 2193 | ESR_INT_XDP_P1_CH1 | |
| 2194 | ESR_INT_XDP_P1_CH0); |
| 2195 | break; |
| 2196 | |
| 2197 | default: |
| 2198 | return 0; |
| 2199 | } |
| 2200 | |
| 2201 | if ((sig & mask) != val) |
| 2202 | return 0; |
| 2203 | return 1; |
| 2204 | } |
| 2205 | |
| 2206 | static int link_status_10g_hotplug(struct niu *np, int *link_up_p) |
| 2207 | { |
| 2208 | unsigned long flags; |
| 2209 | int err = 0; |
| 2210 | int phy_present; |
| 2211 | int phy_present_prev; |
| 2212 | |
| 2213 | spin_lock_irqsave(&np->lock, flags); |
| 2214 | |
| 2215 | if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { |
| 2216 | phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ? |
| 2217 | 1 : 0; |
| 2218 | phy_present = niu_10g_phy_present(np); |
| 2219 | if (phy_present != phy_present_prev) { |
| 2220 | /* state change */ |
| 2221 | if (phy_present) { |
| 2222 | /* A NEM was just plugged in */ |
| 2223 | np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; |
| 2224 | if (np->phy_ops->xcvr_init) |
| 2225 | err = np->phy_ops->xcvr_init(np); |
| 2226 | if (err) { |
| 2227 | err = mdio_read(np, np->phy_addr, |
| 2228 | BCM8704_PHYXS_DEV_ADDR, MII_BMCR); |
| 2229 | if (err == 0xffff) { |
| 2230 | /* No mdio, back-to-back XAUI */ |
| 2231 | goto out; |
| 2232 | } |
| 2233 | /* debounce */ |
| 2234 | np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; |
| 2235 | } |
| 2236 | } else { |
| 2237 | np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; |
| 2238 | *link_up_p = 0; |
| 2239 | niuwarn(LINK, "%s: Hotplug PHY Removed\n", |
| 2240 | np->dev->name); |
| 2241 | } |
| 2242 | } |
| 2243 | out: |
| 2244 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) { |
| 2245 | err = link_status_10g_bcm8706(np, link_up_p); |
| 2246 | if (err == 0xffff) { |
| 2247 | /* No mdio, back-to-back XAUI: it is C10NEM */ |
| 2248 | *link_up_p = 1; |
| 2249 | np->link_config.active_speed = SPEED_10000; |
| 2250 | np->link_config.active_duplex = DUPLEX_FULL; |
| 2251 | } |
| 2252 | } |
| 2253 | } |
| 2254 | |
| 2255 | spin_unlock_irqrestore(&np->lock, flags); |
| 2256 | |
| 2257 | return 0; |
| 2258 | } |
| 2259 | |
| 2260 | static int niu_link_status(struct niu *np, int *link_up_p) |
| 2261 | { |
| 2262 | const struct niu_phy_ops *ops = np->phy_ops; |
| 2263 | int err; |
| 2264 | |
| 2265 | err = 0; |
| 2266 | if (ops->link_status) |
| 2267 | err = ops->link_status(np, link_up_p); |
| 2268 | |
| 2269 | return err; |
| 2270 | } |
| 2271 | |
| 2272 | static void niu_timer(unsigned long __opaque) |
| 2273 | { |
| 2274 | struct niu *np = (struct niu *) __opaque; |
| 2275 | unsigned long off; |
| 2276 | int err, link_up; |
| 2277 | |
| 2278 | err = niu_link_status(np, &link_up); |
| 2279 | if (!err) |
| 2280 | niu_link_status_common(np, link_up); |
| 2281 | |
| 2282 | if (netif_carrier_ok(np->dev)) |
| 2283 | off = 5 * HZ; |
| 2284 | else |
| 2285 | off = 1 * HZ; |
| 2286 | np->timer.expires = jiffies + off; |
| 2287 | |
| 2288 | add_timer(&np->timer); |
| 2289 | } |
| 2290 | |
| 2291 | static const struct niu_phy_ops phy_ops_10g_serdes = { |
| 2292 | .serdes_init = serdes_init_10g_serdes, |
| 2293 | .link_status = link_status_10g_serdes, |
| 2294 | }; |
| 2295 | |
| 2296 | static const struct niu_phy_ops phy_ops_10g_serdes_niu = { |
| 2297 | .serdes_init = serdes_init_niu_10g_serdes, |
| 2298 | .link_status = link_status_10g_serdes, |
| 2299 | }; |
| 2300 | |
| 2301 | static const struct niu_phy_ops phy_ops_1g_serdes_niu = { |
| 2302 | .serdes_init = serdes_init_niu_1g_serdes, |
| 2303 | .link_status = link_status_1g_serdes, |
| 2304 | }; |
| 2305 | |
| 2306 | static const struct niu_phy_ops phy_ops_1g_rgmii = { |
| 2307 | .xcvr_init = xcvr_init_1g_rgmii, |
| 2308 | .link_status = link_status_1g_rgmii, |
| 2309 | }; |
| 2310 | |
| 2311 | static const struct niu_phy_ops phy_ops_10g_fiber_niu = { |
| 2312 | .serdes_init = serdes_init_niu_10g_fiber, |
| 2313 | .xcvr_init = xcvr_init_10g, |
| 2314 | .link_status = link_status_10g, |
| 2315 | }; |
| 2316 | |
| 2317 | static const struct niu_phy_ops phy_ops_10g_fiber = { |
| 2318 | .serdes_init = serdes_init_10g, |
| 2319 | .xcvr_init = xcvr_init_10g, |
| 2320 | .link_status = link_status_10g, |
| 2321 | }; |
| 2322 | |
| 2323 | static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = { |
| 2324 | .serdes_init = serdes_init_10g, |
| 2325 | .xcvr_init = xcvr_init_10g_bcm8706, |
| 2326 | .link_status = link_status_10g_hotplug, |
| 2327 | }; |
| 2328 | |
| 2329 | static const struct niu_phy_ops phy_ops_niu_10g_hotplug = { |
| 2330 | .serdes_init = serdes_init_niu_10g_fiber, |
| 2331 | .xcvr_init = xcvr_init_10g_bcm8706, |
| 2332 | .link_status = link_status_10g_hotplug, |
| 2333 | }; |
| 2334 | |
| 2335 | static const struct niu_phy_ops phy_ops_10g_copper = { |
| 2336 | .serdes_init = serdes_init_10g, |
| 2337 | .link_status = link_status_10g, /* XXX */ |
| 2338 | }; |
| 2339 | |
| 2340 | static const struct niu_phy_ops phy_ops_1g_fiber = { |
| 2341 | .serdes_init = serdes_init_1g, |
| 2342 | .xcvr_init = xcvr_init_1g, |
| 2343 | .link_status = link_status_1g, |
| 2344 | }; |
| 2345 | |
| 2346 | static const struct niu_phy_ops phy_ops_1g_copper = { |
| 2347 | .xcvr_init = xcvr_init_1g, |
| 2348 | .link_status = link_status_1g, |
| 2349 | }; |
| 2350 | |
| 2351 | struct niu_phy_template { |
| 2352 | const struct niu_phy_ops *ops; |
| 2353 | u32 phy_addr_base; |
| 2354 | }; |
| 2355 | |
| 2356 | static const struct niu_phy_template phy_template_niu_10g_fiber = { |
| 2357 | .ops = &phy_ops_10g_fiber_niu, |
| 2358 | .phy_addr_base = 16, |
| 2359 | }; |
| 2360 | |
| 2361 | static const struct niu_phy_template phy_template_niu_10g_serdes = { |
| 2362 | .ops = &phy_ops_10g_serdes_niu, |
| 2363 | .phy_addr_base = 0, |
| 2364 | }; |
| 2365 | |
| 2366 | static const struct niu_phy_template phy_template_niu_1g_serdes = { |
| 2367 | .ops = &phy_ops_1g_serdes_niu, |
| 2368 | .phy_addr_base = 0, |
| 2369 | }; |
| 2370 | |
| 2371 | static const struct niu_phy_template phy_template_10g_fiber = { |
| 2372 | .ops = &phy_ops_10g_fiber, |
| 2373 | .phy_addr_base = 8, |
| 2374 | }; |
| 2375 | |
| 2376 | static const struct niu_phy_template phy_template_10g_fiber_hotplug = { |
| 2377 | .ops = &phy_ops_10g_fiber_hotplug, |
| 2378 | .phy_addr_base = 8, |
| 2379 | }; |
| 2380 | |
| 2381 | static const struct niu_phy_template phy_template_niu_10g_hotplug = { |
| 2382 | .ops = &phy_ops_niu_10g_hotplug, |
| 2383 | .phy_addr_base = 8, |
| 2384 | }; |
| 2385 | |
| 2386 | static const struct niu_phy_template phy_template_10g_copper = { |
| 2387 | .ops = &phy_ops_10g_copper, |
| 2388 | .phy_addr_base = 10, |
| 2389 | }; |
| 2390 | |
| 2391 | static const struct niu_phy_template phy_template_1g_fiber = { |
| 2392 | .ops = &phy_ops_1g_fiber, |
| 2393 | .phy_addr_base = 0, |
| 2394 | }; |
| 2395 | |
| 2396 | static const struct niu_phy_template phy_template_1g_copper = { |
| 2397 | .ops = &phy_ops_1g_copper, |
| 2398 | .phy_addr_base = 0, |
| 2399 | }; |
| 2400 | |
| 2401 | static const struct niu_phy_template phy_template_1g_rgmii = { |
| 2402 | .ops = &phy_ops_1g_rgmii, |
| 2403 | .phy_addr_base = 0, |
| 2404 | }; |
| 2405 | |
| 2406 | static const struct niu_phy_template phy_template_10g_serdes = { |
| 2407 | .ops = &phy_ops_10g_serdes, |
| 2408 | .phy_addr_base = 0, |
| 2409 | }; |
| 2410 | |
| 2411 | static int niu_atca_port_num[4] = { |
| 2412 | 0, 0, 11, 10 |
| 2413 | }; |
| 2414 | |
| 2415 | static int serdes_init_10g_serdes(struct niu *np) |
| 2416 | { |
| 2417 | struct niu_link_config *lp = &np->link_config; |
| 2418 | unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; |
| 2419 | u64 ctrl_val, test_cfg_val, sig, mask, val; |
| 2420 | u64 reset_val; |
| 2421 | |
| 2422 | switch (np->port) { |
| 2423 | case 0: |
| 2424 | reset_val = ENET_SERDES_RESET_0; |
| 2425 | ctrl_reg = ENET_SERDES_0_CTRL_CFG; |
| 2426 | test_cfg_reg = ENET_SERDES_0_TEST_CFG; |
| 2427 | pll_cfg = ENET_SERDES_0_PLL_CFG; |
| 2428 | break; |
| 2429 | case 1: |
| 2430 | reset_val = ENET_SERDES_RESET_1; |
| 2431 | ctrl_reg = ENET_SERDES_1_CTRL_CFG; |
| 2432 | test_cfg_reg = ENET_SERDES_1_TEST_CFG; |
| 2433 | pll_cfg = ENET_SERDES_1_PLL_CFG; |
| 2434 | break; |
| 2435 | |
| 2436 | default: |
| 2437 | return -EINVAL; |
| 2438 | } |
| 2439 | ctrl_val = (ENET_SERDES_CTRL_SDET_0 | |
| 2440 | ENET_SERDES_CTRL_SDET_1 | |
| 2441 | ENET_SERDES_CTRL_SDET_2 | |
| 2442 | ENET_SERDES_CTRL_SDET_3 | |
| 2443 | (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | |
| 2444 | (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | |
| 2445 | (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | |
| 2446 | (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | |
| 2447 | (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | |
| 2448 | (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | |
| 2449 | (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | |
| 2450 | (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); |
| 2451 | test_cfg_val = 0; |
| 2452 | |
| 2453 | if (lp->loopback_mode == LOOPBACK_PHY) { |
| 2454 | test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << |
| 2455 | ENET_SERDES_TEST_MD_0_SHIFT) | |
| 2456 | (ENET_TEST_MD_PAD_LOOPBACK << |
| 2457 | ENET_SERDES_TEST_MD_1_SHIFT) | |
| 2458 | (ENET_TEST_MD_PAD_LOOPBACK << |
| 2459 | ENET_SERDES_TEST_MD_2_SHIFT) | |
| 2460 | (ENET_TEST_MD_PAD_LOOPBACK << |
| 2461 | ENET_SERDES_TEST_MD_3_SHIFT)); |
| 2462 | } |
| 2463 | |
| 2464 | esr_reset(np); |
| 2465 | nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2); |
| 2466 | nw64(ctrl_reg, ctrl_val); |
| 2467 | nw64(test_cfg_reg, test_cfg_val); |
| 2468 | |
| 2469 | /* Initialize all 4 lanes of the SERDES. */ |
| 2470 | for (i = 0; i < 4; i++) { |
| 2471 | u32 rxtx_ctrl, glue0; |
| 2472 | int err; |
| 2473 | |
| 2474 | err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); |
| 2475 | if (err) |
| 2476 | return err; |
| 2477 | err = esr_read_glue0(np, i, &glue0); |
| 2478 | if (err) |
| 2479 | return err; |
| 2480 | |
| 2481 | rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); |
| 2482 | rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | |
| 2483 | (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); |
| 2484 | |
| 2485 | glue0 &= ~(ESR_GLUE_CTRL0_SRATE | |
| 2486 | ESR_GLUE_CTRL0_THCNT | |
| 2487 | ESR_GLUE_CTRL0_BLTIME); |
| 2488 | glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | |
| 2489 | (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | |
| 2490 | (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | |
| 2491 | (BLTIME_300_CYCLES << |
| 2492 | ESR_GLUE_CTRL0_BLTIME_SHIFT)); |
| 2493 | |
| 2494 | err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); |
| 2495 | if (err) |
| 2496 | return err; |
| 2497 | err = esr_write_glue0(np, i, glue0); |
| 2498 | if (err) |
| 2499 | return err; |
| 2500 | } |
| 2501 | |
| 2502 | |
| 2503 | sig = nr64(ESR_INT_SIGNALS); |
| 2504 | switch (np->port) { |
| 2505 | case 0: |
| 2506 | mask = ESR_INT_SIGNALS_P0_BITS; |
| 2507 | val = (ESR_INT_SRDY0_P0 | |
| 2508 | ESR_INT_DET0_P0 | |
| 2509 | ESR_INT_XSRDY_P0 | |
| 2510 | ESR_INT_XDP_P0_CH3 | |
| 2511 | ESR_INT_XDP_P0_CH2 | |
| 2512 | ESR_INT_XDP_P0_CH1 | |
| 2513 | ESR_INT_XDP_P0_CH0); |
| 2514 | break; |
| 2515 | |
| 2516 | case 1: |
| 2517 | mask = ESR_INT_SIGNALS_P1_BITS; |
| 2518 | val = (ESR_INT_SRDY0_P1 | |
| 2519 | ESR_INT_DET0_P1 | |
| 2520 | ESR_INT_XSRDY_P1 | |
| 2521 | ESR_INT_XDP_P1_CH3 | |
| 2522 | ESR_INT_XDP_P1_CH2 | |
| 2523 | ESR_INT_XDP_P1_CH1 | |
| 2524 | ESR_INT_XDP_P1_CH0); |
| 2525 | break; |
| 2526 | |
| 2527 | default: |
| 2528 | return -EINVAL; |
| 2529 | } |
| 2530 | |
| 2531 | if ((sig & mask) != val) { |
| 2532 | int err; |
| 2533 | err = serdes_init_1g_serdes(np); |
| 2534 | if (!err) { |
| 2535 | np->flags &= ~NIU_FLAGS_10G; |
| 2536 | np->mac_xcvr = MAC_XCVR_PCS; |
| 2537 | } else { |
| 2538 | dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n", |
| 2539 | np->port); |
| 2540 | return -ENODEV; |
| 2541 | } |
| 2542 | } |
| 2543 | |
| 2544 | return 0; |
| 2545 | } |
| 2546 | |
| 2547 | static int niu_determine_phy_disposition(struct niu *np) |
| 2548 | { |
| 2549 | struct niu_parent *parent = np->parent; |
| 2550 | u8 plat_type = parent->plat_type; |
| 2551 | const struct niu_phy_template *tp; |
| 2552 | u32 phy_addr_off = 0; |
| 2553 | |
| 2554 | if (plat_type == PLAT_TYPE_NIU) { |
| 2555 | switch (np->flags & |
| 2556 | (NIU_FLAGS_10G | |
| 2557 | NIU_FLAGS_FIBER | |
| 2558 | NIU_FLAGS_XCVR_SERDES)) { |
| 2559 | case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: |
| 2560 | /* 10G Serdes */ |
| 2561 | tp = &phy_template_niu_10g_serdes; |
| 2562 | break; |
| 2563 | case NIU_FLAGS_XCVR_SERDES: |
| 2564 | /* 1G Serdes */ |
| 2565 | tp = &phy_template_niu_1g_serdes; |
| 2566 | break; |
| 2567 | case NIU_FLAGS_10G | NIU_FLAGS_FIBER: |
| 2568 | /* 10G Fiber */ |
| 2569 | default: |
| 2570 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { |
| 2571 | tp = &phy_template_niu_10g_hotplug; |
| 2572 | if (np->port == 0) |
| 2573 | phy_addr_off = 8; |
| 2574 | if (np->port == 1) |
| 2575 | phy_addr_off = 12; |
| 2576 | } else { |
| 2577 | tp = &phy_template_niu_10g_fiber; |
| 2578 | phy_addr_off += np->port; |
| 2579 | } |
| 2580 | break; |
| 2581 | } |
| 2582 | } else { |
| 2583 | switch (np->flags & |
| 2584 | (NIU_FLAGS_10G | |
| 2585 | NIU_FLAGS_FIBER | |
| 2586 | NIU_FLAGS_XCVR_SERDES)) { |
| 2587 | case 0: |
| 2588 | /* 1G copper */ |
| 2589 | tp = &phy_template_1g_copper; |
| 2590 | if (plat_type == PLAT_TYPE_VF_P0) |
| 2591 | phy_addr_off = 10; |
| 2592 | else if (plat_type == PLAT_TYPE_VF_P1) |
| 2593 | phy_addr_off = 26; |
| 2594 | |
| 2595 | phy_addr_off += (np->port ^ 0x3); |
| 2596 | break; |
| 2597 | |
| 2598 | case NIU_FLAGS_10G: |
| 2599 | /* 10G copper */ |
| 2600 | tp = &phy_template_10g_copper; |
| 2601 | break; |
| 2602 | |
| 2603 | case NIU_FLAGS_FIBER: |
| 2604 | /* 1G fiber */ |
| 2605 | tp = &phy_template_1g_fiber; |
| 2606 | break; |
| 2607 | |
| 2608 | case NIU_FLAGS_10G | NIU_FLAGS_FIBER: |
| 2609 | /* 10G fiber */ |
| 2610 | tp = &phy_template_10g_fiber; |
| 2611 | if (plat_type == PLAT_TYPE_VF_P0 || |
| 2612 | plat_type == PLAT_TYPE_VF_P1) |
| 2613 | phy_addr_off = 8; |
| 2614 | phy_addr_off += np->port; |
| 2615 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { |
| 2616 | tp = &phy_template_10g_fiber_hotplug; |
| 2617 | if (np->port == 0) |
| 2618 | phy_addr_off = 8; |
| 2619 | if (np->port == 1) |
| 2620 | phy_addr_off = 12; |
| 2621 | } |
| 2622 | break; |
| 2623 | |
| 2624 | case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: |
| 2625 | case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: |
| 2626 | case NIU_FLAGS_XCVR_SERDES: |
| 2627 | switch(np->port) { |
| 2628 | case 0: |
| 2629 | case 1: |
| 2630 | tp = &phy_template_10g_serdes; |
| 2631 | break; |
| 2632 | case 2: |
| 2633 | case 3: |
| 2634 | tp = &phy_template_1g_rgmii; |
| 2635 | break; |
| 2636 | default: |
| 2637 | return -EINVAL; |
| 2638 | break; |
| 2639 | } |
| 2640 | phy_addr_off = niu_atca_port_num[np->port]; |
| 2641 | break; |
| 2642 | |
| 2643 | default: |
| 2644 | return -EINVAL; |
| 2645 | } |
| 2646 | } |
| 2647 | |
| 2648 | np->phy_ops = tp->ops; |
| 2649 | np->phy_addr = tp->phy_addr_base + phy_addr_off; |
| 2650 | |
| 2651 | return 0; |
| 2652 | } |
| 2653 | |
| 2654 | static int niu_init_link(struct niu *np) |
| 2655 | { |
| 2656 | struct niu_parent *parent = np->parent; |
| 2657 | int err, ignore; |
| 2658 | |
| 2659 | if (parent->plat_type == PLAT_TYPE_NIU) { |
| 2660 | err = niu_xcvr_init(np); |
| 2661 | if (err) |
| 2662 | return err; |
| 2663 | msleep(200); |
| 2664 | } |
| 2665 | err = niu_serdes_init(np); |
| 2666 | if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY)) |
| 2667 | return err; |
| 2668 | msleep(200); |
| 2669 | err = niu_xcvr_init(np); |
| 2670 | if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY)) |
| 2671 | niu_link_status(np, &ignore); |
| 2672 | return 0; |
| 2673 | } |
| 2674 | |
| 2675 | static void niu_set_primary_mac(struct niu *np, unsigned char *addr) |
| 2676 | { |
| 2677 | u16 reg0 = addr[4] << 8 | addr[5]; |
| 2678 | u16 reg1 = addr[2] << 8 | addr[3]; |
| 2679 | u16 reg2 = addr[0] << 8 | addr[1]; |
| 2680 | |
| 2681 | if (np->flags & NIU_FLAGS_XMAC) { |
| 2682 | nw64_mac(XMAC_ADDR0, reg0); |
| 2683 | nw64_mac(XMAC_ADDR1, reg1); |
| 2684 | nw64_mac(XMAC_ADDR2, reg2); |
| 2685 | } else { |
| 2686 | nw64_mac(BMAC_ADDR0, reg0); |
| 2687 | nw64_mac(BMAC_ADDR1, reg1); |
| 2688 | nw64_mac(BMAC_ADDR2, reg2); |
| 2689 | } |
| 2690 | } |
| 2691 | |
| 2692 | static int niu_num_alt_addr(struct niu *np) |
| 2693 | { |
| 2694 | if (np->flags & NIU_FLAGS_XMAC) |
| 2695 | return XMAC_NUM_ALT_ADDR; |
| 2696 | else |
| 2697 | return BMAC_NUM_ALT_ADDR; |
| 2698 | } |
| 2699 | |
| 2700 | static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr) |
| 2701 | { |
| 2702 | u16 reg0 = addr[4] << 8 | addr[5]; |
| 2703 | u16 reg1 = addr[2] << 8 | addr[3]; |
| 2704 | u16 reg2 = addr[0] << 8 | addr[1]; |
| 2705 | |
| 2706 | if (index >= niu_num_alt_addr(np)) |
| 2707 | return -EINVAL; |
| 2708 | |
| 2709 | if (np->flags & NIU_FLAGS_XMAC) { |
| 2710 | nw64_mac(XMAC_ALT_ADDR0(index), reg0); |
| 2711 | nw64_mac(XMAC_ALT_ADDR1(index), reg1); |
| 2712 | nw64_mac(XMAC_ALT_ADDR2(index), reg2); |
| 2713 | } else { |
| 2714 | nw64_mac(BMAC_ALT_ADDR0(index), reg0); |
| 2715 | nw64_mac(BMAC_ALT_ADDR1(index), reg1); |
| 2716 | nw64_mac(BMAC_ALT_ADDR2(index), reg2); |
| 2717 | } |
| 2718 | |
| 2719 | return 0; |
| 2720 | } |
| 2721 | |
| 2722 | static int niu_enable_alt_mac(struct niu *np, int index, int on) |
| 2723 | { |
| 2724 | unsigned long reg; |
| 2725 | u64 val, mask; |
| 2726 | |
| 2727 | if (index >= niu_num_alt_addr(np)) |
| 2728 | return -EINVAL; |
| 2729 | |
| 2730 | if (np->flags & NIU_FLAGS_XMAC) { |
| 2731 | reg = XMAC_ADDR_CMPEN; |
| 2732 | mask = 1 << index; |
| 2733 | } else { |
| 2734 | reg = BMAC_ADDR_CMPEN; |
| 2735 | mask = 1 << (index + 1); |
| 2736 | } |
| 2737 | |
| 2738 | val = nr64_mac(reg); |
| 2739 | if (on) |
| 2740 | val |= mask; |
| 2741 | else |
| 2742 | val &= ~mask; |
| 2743 | nw64_mac(reg, val); |
| 2744 | |
| 2745 | return 0; |
| 2746 | } |
| 2747 | |
| 2748 | static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg, |
| 2749 | int num, int mac_pref) |
| 2750 | { |
| 2751 | u64 val = nr64_mac(reg); |
| 2752 | val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR); |
| 2753 | val |= num; |
| 2754 | if (mac_pref) |
| 2755 | val |= HOST_INFO_MPR; |
| 2756 | nw64_mac(reg, val); |
| 2757 | } |
| 2758 | |
| 2759 | static int __set_rdc_table_num(struct niu *np, |
| 2760 | int xmac_index, int bmac_index, |
| 2761 | int rdc_table_num, int mac_pref) |
| 2762 | { |
| 2763 | unsigned long reg; |
| 2764 | |
| 2765 | if (rdc_table_num & ~HOST_INFO_MACRDCTBLN) |
| 2766 | return -EINVAL; |
| 2767 | if (np->flags & NIU_FLAGS_XMAC) |
| 2768 | reg = XMAC_HOST_INFO(xmac_index); |
| 2769 | else |
| 2770 | reg = BMAC_HOST_INFO(bmac_index); |
| 2771 | __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref); |
| 2772 | return 0; |
| 2773 | } |
| 2774 | |
| 2775 | static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num, |
| 2776 | int mac_pref) |
| 2777 | { |
| 2778 | return __set_rdc_table_num(np, 17, 0, table_num, mac_pref); |
| 2779 | } |
| 2780 | |
| 2781 | static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num, |
| 2782 | int mac_pref) |
| 2783 | { |
| 2784 | return __set_rdc_table_num(np, 16, 8, table_num, mac_pref); |
| 2785 | } |
| 2786 | |
| 2787 | static int niu_set_alt_mac_rdc_table(struct niu *np, int idx, |
| 2788 | int table_num, int mac_pref) |
| 2789 | { |
| 2790 | if (idx >= niu_num_alt_addr(np)) |
| 2791 | return -EINVAL; |
| 2792 | return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref); |
| 2793 | } |
| 2794 | |
| 2795 | static u64 vlan_entry_set_parity(u64 reg_val) |
| 2796 | { |
| 2797 | u64 port01_mask; |
| 2798 | u64 port23_mask; |
| 2799 | |
| 2800 | port01_mask = 0x00ff; |
| 2801 | port23_mask = 0xff00; |
| 2802 | |
| 2803 | if (hweight64(reg_val & port01_mask) & 1) |
| 2804 | reg_val |= ENET_VLAN_TBL_PARITY0; |
| 2805 | else |
| 2806 | reg_val &= ~ENET_VLAN_TBL_PARITY0; |
| 2807 | |
| 2808 | if (hweight64(reg_val & port23_mask) & 1) |
| 2809 | reg_val |= ENET_VLAN_TBL_PARITY1; |
| 2810 | else |
| 2811 | reg_val &= ~ENET_VLAN_TBL_PARITY1; |
| 2812 | |
| 2813 | return reg_val; |
| 2814 | } |
| 2815 | |
| 2816 | static void vlan_tbl_write(struct niu *np, unsigned long index, |
| 2817 | int port, int vpr, int rdc_table) |
| 2818 | { |
| 2819 | u64 reg_val = nr64(ENET_VLAN_TBL(index)); |
| 2820 | |
| 2821 | reg_val &= ~((ENET_VLAN_TBL_VPR | |
| 2822 | ENET_VLAN_TBL_VLANRDCTBLN) << |
| 2823 | ENET_VLAN_TBL_SHIFT(port)); |
| 2824 | if (vpr) |
| 2825 | reg_val |= (ENET_VLAN_TBL_VPR << |
| 2826 | ENET_VLAN_TBL_SHIFT(port)); |
| 2827 | reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port)); |
| 2828 | |
| 2829 | reg_val = vlan_entry_set_parity(reg_val); |
| 2830 | |
| 2831 | nw64(ENET_VLAN_TBL(index), reg_val); |
| 2832 | } |
| 2833 | |
| 2834 | static void vlan_tbl_clear(struct niu *np) |
| 2835 | { |
| 2836 | int i; |
| 2837 | |
| 2838 | for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) |
| 2839 | nw64(ENET_VLAN_TBL(i), 0); |
| 2840 | } |
| 2841 | |
| 2842 | static int tcam_wait_bit(struct niu *np, u64 bit) |
| 2843 | { |
| 2844 | int limit = 1000; |
| 2845 | |
| 2846 | while (--limit > 0) { |
| 2847 | if (nr64(TCAM_CTL) & bit) |
| 2848 | break; |
| 2849 | udelay(1); |
| 2850 | } |
| 2851 | if (limit < 0) |
| 2852 | return -ENODEV; |
| 2853 | |
| 2854 | return 0; |
| 2855 | } |
| 2856 | |
| 2857 | static int tcam_flush(struct niu *np, int index) |
| 2858 | { |
| 2859 | nw64(TCAM_KEY_0, 0x00); |
| 2860 | nw64(TCAM_KEY_MASK_0, 0xff); |
| 2861 | nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); |
| 2862 | |
| 2863 | return tcam_wait_bit(np, TCAM_CTL_STAT); |
| 2864 | } |
| 2865 | |
| 2866 | #if 0 |
| 2867 | static int tcam_read(struct niu *np, int index, |
| 2868 | u64 *key, u64 *mask) |
| 2869 | { |
| 2870 | int err; |
| 2871 | |
| 2872 | nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index)); |
| 2873 | err = tcam_wait_bit(np, TCAM_CTL_STAT); |
| 2874 | if (!err) { |
| 2875 | key[0] = nr64(TCAM_KEY_0); |
| 2876 | key[1] = nr64(TCAM_KEY_1); |
| 2877 | key[2] = nr64(TCAM_KEY_2); |
| 2878 | key[3] = nr64(TCAM_KEY_3); |
| 2879 | mask[0] = nr64(TCAM_KEY_MASK_0); |
| 2880 | mask[1] = nr64(TCAM_KEY_MASK_1); |
| 2881 | mask[2] = nr64(TCAM_KEY_MASK_2); |
| 2882 | mask[3] = nr64(TCAM_KEY_MASK_3); |
| 2883 | } |
| 2884 | return err; |
| 2885 | } |
| 2886 | #endif |
| 2887 | |
| 2888 | static int tcam_write(struct niu *np, int index, |
| 2889 | u64 *key, u64 *mask) |
| 2890 | { |
| 2891 | nw64(TCAM_KEY_0, key[0]); |
| 2892 | nw64(TCAM_KEY_1, key[1]); |
| 2893 | nw64(TCAM_KEY_2, key[2]); |
| 2894 | nw64(TCAM_KEY_3, key[3]); |
| 2895 | nw64(TCAM_KEY_MASK_0, mask[0]); |
| 2896 | nw64(TCAM_KEY_MASK_1, mask[1]); |
| 2897 | nw64(TCAM_KEY_MASK_2, mask[2]); |
| 2898 | nw64(TCAM_KEY_MASK_3, mask[3]); |
| 2899 | nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); |
| 2900 | |
| 2901 | return tcam_wait_bit(np, TCAM_CTL_STAT); |
| 2902 | } |
| 2903 | |
| 2904 | #if 0 |
| 2905 | static int tcam_assoc_read(struct niu *np, int index, u64 *data) |
| 2906 | { |
| 2907 | int err; |
| 2908 | |
| 2909 | nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index)); |
| 2910 | err = tcam_wait_bit(np, TCAM_CTL_STAT); |
| 2911 | if (!err) |
| 2912 | *data = nr64(TCAM_KEY_1); |
| 2913 | |
| 2914 | return err; |
| 2915 | } |
| 2916 | #endif |
| 2917 | |
| 2918 | static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data) |
| 2919 | { |
| 2920 | nw64(TCAM_KEY_1, assoc_data); |
| 2921 | nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index)); |
| 2922 | |
| 2923 | return tcam_wait_bit(np, TCAM_CTL_STAT); |
| 2924 | } |
| 2925 | |
| 2926 | static void tcam_enable(struct niu *np, int on) |
| 2927 | { |
| 2928 | u64 val = nr64(FFLP_CFG_1); |
| 2929 | |
| 2930 | if (on) |
| 2931 | val &= ~FFLP_CFG_1_TCAM_DIS; |
| 2932 | else |
| 2933 | val |= FFLP_CFG_1_TCAM_DIS; |
| 2934 | nw64(FFLP_CFG_1, val); |
| 2935 | } |
| 2936 | |
| 2937 | static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio) |
| 2938 | { |
| 2939 | u64 val = nr64(FFLP_CFG_1); |
| 2940 | |
| 2941 | val &= ~(FFLP_CFG_1_FFLPINITDONE | |
| 2942 | FFLP_CFG_1_CAMLAT | |
| 2943 | FFLP_CFG_1_CAMRATIO); |
| 2944 | val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT); |
| 2945 | val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT); |
| 2946 | nw64(FFLP_CFG_1, val); |
| 2947 | |
| 2948 | val = nr64(FFLP_CFG_1); |
| 2949 | val |= FFLP_CFG_1_FFLPINITDONE; |
| 2950 | nw64(FFLP_CFG_1, val); |
| 2951 | } |
| 2952 | |
| 2953 | static int tcam_user_eth_class_enable(struct niu *np, unsigned long class, |
| 2954 | int on) |
| 2955 | { |
| 2956 | unsigned long reg; |
| 2957 | u64 val; |
| 2958 | |
| 2959 | if (class < CLASS_CODE_ETHERTYPE1 || |
| 2960 | class > CLASS_CODE_ETHERTYPE2) |
| 2961 | return -EINVAL; |
| 2962 | |
| 2963 | reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); |
| 2964 | val = nr64(reg); |
| 2965 | if (on) |
| 2966 | val |= L2_CLS_VLD; |
| 2967 | else |
| 2968 | val &= ~L2_CLS_VLD; |
| 2969 | nw64(reg, val); |
| 2970 | |
| 2971 | return 0; |
| 2972 | } |
| 2973 | |
| 2974 | #if 0 |
| 2975 | static int tcam_user_eth_class_set(struct niu *np, unsigned long class, |
| 2976 | u64 ether_type) |
| 2977 | { |
| 2978 | unsigned long reg; |
| 2979 | u64 val; |
| 2980 | |
| 2981 | if (class < CLASS_CODE_ETHERTYPE1 || |
| 2982 | class > CLASS_CODE_ETHERTYPE2 || |
| 2983 | (ether_type & ~(u64)0xffff) != 0) |
| 2984 | return -EINVAL; |
| 2985 | |
| 2986 | reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); |
| 2987 | val = nr64(reg); |
| 2988 | val &= ~L2_CLS_ETYPE; |
| 2989 | val |= (ether_type << L2_CLS_ETYPE_SHIFT); |
| 2990 | nw64(reg, val); |
| 2991 | |
| 2992 | return 0; |
| 2993 | } |
| 2994 | #endif |
| 2995 | |
| 2996 | static int tcam_user_ip_class_enable(struct niu *np, unsigned long class, |
| 2997 | int on) |
| 2998 | { |
| 2999 | unsigned long reg; |
| 3000 | u64 val; |
| 3001 | |
| 3002 | if (class < CLASS_CODE_USER_PROG1 || |
| 3003 | class > CLASS_CODE_USER_PROG4) |
| 3004 | return -EINVAL; |
| 3005 | |
| 3006 | reg = L3_CLS(class - CLASS_CODE_USER_PROG1); |
| 3007 | val = nr64(reg); |
| 3008 | if (on) |
| 3009 | val |= L3_CLS_VALID; |
| 3010 | else |
| 3011 | val &= ~L3_CLS_VALID; |
| 3012 | nw64(reg, val); |
| 3013 | |
| 3014 | return 0; |
| 3015 | } |
| 3016 | |
| 3017 | static int tcam_user_ip_class_set(struct niu *np, unsigned long class, |
| 3018 | int ipv6, u64 protocol_id, |
| 3019 | u64 tos_mask, u64 tos_val) |
| 3020 | { |
| 3021 | unsigned long reg; |
| 3022 | u64 val; |
| 3023 | |
| 3024 | if (class < CLASS_CODE_USER_PROG1 || |
| 3025 | class > CLASS_CODE_USER_PROG4 || |
| 3026 | (protocol_id & ~(u64)0xff) != 0 || |
| 3027 | (tos_mask & ~(u64)0xff) != 0 || |
| 3028 | (tos_val & ~(u64)0xff) != 0) |
| 3029 | return -EINVAL; |
| 3030 | |
| 3031 | reg = L3_CLS(class - CLASS_CODE_USER_PROG1); |
| 3032 | val = nr64(reg); |
| 3033 | val &= ~(L3_CLS_IPVER | L3_CLS_PID | |
| 3034 | L3_CLS_TOSMASK | L3_CLS_TOS); |
| 3035 | if (ipv6) |
| 3036 | val |= L3_CLS_IPVER; |
| 3037 | val |= (protocol_id << L3_CLS_PID_SHIFT); |
| 3038 | val |= (tos_mask << L3_CLS_TOSMASK_SHIFT); |
| 3039 | val |= (tos_val << L3_CLS_TOS_SHIFT); |
| 3040 | nw64(reg, val); |
| 3041 | |
| 3042 | return 0; |
| 3043 | } |
| 3044 | |
| 3045 | static int tcam_early_init(struct niu *np) |
| 3046 | { |
| 3047 | unsigned long i; |
| 3048 | int err; |
| 3049 | |
| 3050 | tcam_enable(np, 0); |
| 3051 | tcam_set_lat_and_ratio(np, |
| 3052 | DEFAULT_TCAM_LATENCY, |
| 3053 | DEFAULT_TCAM_ACCESS_RATIO); |
| 3054 | for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) { |
| 3055 | err = tcam_user_eth_class_enable(np, i, 0); |
| 3056 | if (err) |
| 3057 | return err; |
| 3058 | } |
| 3059 | for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) { |
| 3060 | err = tcam_user_ip_class_enable(np, i, 0); |
| 3061 | if (err) |
| 3062 | return err; |
| 3063 | } |
| 3064 | |
| 3065 | return 0; |
| 3066 | } |
| 3067 | |
| 3068 | static int tcam_flush_all(struct niu *np) |
| 3069 | { |
| 3070 | unsigned long i; |
| 3071 | |
| 3072 | for (i = 0; i < np->parent->tcam_num_entries; i++) { |
| 3073 | int err = tcam_flush(np, i); |
| 3074 | if (err) |
| 3075 | return err; |
| 3076 | } |
| 3077 | return 0; |
| 3078 | } |
| 3079 | |
| 3080 | static u64 hash_addr_regval(unsigned long index, unsigned long num_entries) |
| 3081 | { |
| 3082 | return ((u64)index | (num_entries == 1 ? |
| 3083 | HASH_TBL_ADDR_AUTOINC : 0)); |
| 3084 | } |
| 3085 | |
| 3086 | #if 0 |
| 3087 | static int hash_read(struct niu *np, unsigned long partition, |
| 3088 | unsigned long index, unsigned long num_entries, |
| 3089 | u64 *data) |
| 3090 | { |
| 3091 | u64 val = hash_addr_regval(index, num_entries); |
| 3092 | unsigned long i; |
| 3093 | |
| 3094 | if (partition >= FCRAM_NUM_PARTITIONS || |
| 3095 | index + num_entries > FCRAM_SIZE) |
| 3096 | return -EINVAL; |
| 3097 | |
| 3098 | nw64(HASH_TBL_ADDR(partition), val); |
| 3099 | for (i = 0; i < num_entries; i++) |
| 3100 | data[i] = nr64(HASH_TBL_DATA(partition)); |
| 3101 | |
| 3102 | return 0; |
| 3103 | } |
| 3104 | #endif |
| 3105 | |
| 3106 | static int hash_write(struct niu *np, unsigned long partition, |
| 3107 | unsigned long index, unsigned long num_entries, |
| 3108 | u64 *data) |
| 3109 | { |
| 3110 | u64 val = hash_addr_regval(index, num_entries); |
| 3111 | unsigned long i; |
| 3112 | |
| 3113 | if (partition >= FCRAM_NUM_PARTITIONS || |
| 3114 | index + (num_entries * 8) > FCRAM_SIZE) |
| 3115 | return -EINVAL; |
| 3116 | |
| 3117 | nw64(HASH_TBL_ADDR(partition), val); |
| 3118 | for (i = 0; i < num_entries; i++) |
| 3119 | nw64(HASH_TBL_DATA(partition), data[i]); |
| 3120 | |
| 3121 | return 0; |
| 3122 | } |
| 3123 | |
| 3124 | static void fflp_reset(struct niu *np) |
| 3125 | { |
| 3126 | u64 val; |
| 3127 | |
| 3128 | nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST); |
| 3129 | udelay(10); |
| 3130 | nw64(FFLP_CFG_1, 0); |
| 3131 | |
| 3132 | val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE; |
| 3133 | nw64(FFLP_CFG_1, val); |
| 3134 | } |
| 3135 | |
| 3136 | static void fflp_set_timings(struct niu *np) |
| 3137 | { |
| 3138 | u64 val = nr64(FFLP_CFG_1); |
| 3139 | |
| 3140 | val &= ~FFLP_CFG_1_FFLPINITDONE; |
| 3141 | val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT); |
| 3142 | nw64(FFLP_CFG_1, val); |
| 3143 | |
| 3144 | val = nr64(FFLP_CFG_1); |
| 3145 | val |= FFLP_CFG_1_FFLPINITDONE; |
| 3146 | nw64(FFLP_CFG_1, val); |
| 3147 | |
| 3148 | val = nr64(FCRAM_REF_TMR); |
| 3149 | val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN); |
| 3150 | val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT); |
| 3151 | val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT); |
| 3152 | nw64(FCRAM_REF_TMR, val); |
| 3153 | } |
| 3154 | |
| 3155 | static int fflp_set_partition(struct niu *np, u64 partition, |
| 3156 | u64 mask, u64 base, int enable) |
| 3157 | { |
| 3158 | unsigned long reg; |
| 3159 | u64 val; |
| 3160 | |
| 3161 | if (partition >= FCRAM_NUM_PARTITIONS || |
| 3162 | (mask & ~(u64)0x1f) != 0 || |
| 3163 | (base & ~(u64)0x1f) != 0) |
| 3164 | return -EINVAL; |
| 3165 | |
| 3166 | reg = FLW_PRT_SEL(partition); |
| 3167 | |
| 3168 | val = nr64(reg); |
| 3169 | val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE); |
| 3170 | val |= (mask << FLW_PRT_SEL_MASK_SHIFT); |
| 3171 | val |= (base << FLW_PRT_SEL_BASE_SHIFT); |
| 3172 | if (enable) |
| 3173 | val |= FLW_PRT_SEL_EXT; |
| 3174 | nw64(reg, val); |
| 3175 | |
| 3176 | return 0; |
| 3177 | } |
| 3178 | |
| 3179 | static int fflp_disable_all_partitions(struct niu *np) |
| 3180 | { |
| 3181 | unsigned long i; |
| 3182 | |
| 3183 | for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) { |
| 3184 | int err = fflp_set_partition(np, 0, 0, 0, 0); |
| 3185 | if (err) |
| 3186 | return err; |
| 3187 | } |
| 3188 | return 0; |
| 3189 | } |
| 3190 | |
| 3191 | static void fflp_llcsnap_enable(struct niu *np, int on) |
| 3192 | { |
| 3193 | u64 val = nr64(FFLP_CFG_1); |
| 3194 | |
| 3195 | if (on) |
| 3196 | val |= FFLP_CFG_1_LLCSNAP; |
| 3197 | else |
| 3198 | val &= ~FFLP_CFG_1_LLCSNAP; |
| 3199 | nw64(FFLP_CFG_1, val); |
| 3200 | } |
| 3201 | |
| 3202 | static void fflp_errors_enable(struct niu *np, int on) |
| 3203 | { |
| 3204 | u64 val = nr64(FFLP_CFG_1); |
| 3205 | |
| 3206 | if (on) |
| 3207 | val &= ~FFLP_CFG_1_ERRORDIS; |
| 3208 | else |
| 3209 | val |= FFLP_CFG_1_ERRORDIS; |
| 3210 | nw64(FFLP_CFG_1, val); |
| 3211 | } |
| 3212 | |
| 3213 | static int fflp_hash_clear(struct niu *np) |
| 3214 | { |
| 3215 | struct fcram_hash_ipv4 ent; |
| 3216 | unsigned long i; |
| 3217 | |
| 3218 | /* IPV4 hash entry with valid bit clear, rest is don't care. */ |
| 3219 | memset(&ent, 0, sizeof(ent)); |
| 3220 | ent.header = HASH_HEADER_EXT; |
| 3221 | |
| 3222 | for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) { |
| 3223 | int err = hash_write(np, 0, i, 1, (u64 *) &ent); |
| 3224 | if (err) |
| 3225 | return err; |
| 3226 | } |
| 3227 | return 0; |
| 3228 | } |
| 3229 | |
| 3230 | static int fflp_early_init(struct niu *np) |
| 3231 | { |
| 3232 | struct niu_parent *parent; |
| 3233 | unsigned long flags; |
| 3234 | int err; |
| 3235 | |
| 3236 | niu_lock_parent(np, flags); |
| 3237 | |
| 3238 | parent = np->parent; |
| 3239 | err = 0; |
| 3240 | if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) { |
| 3241 | niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n", |
| 3242 | np->port); |
| 3243 | if (np->parent->plat_type != PLAT_TYPE_NIU) { |
| 3244 | fflp_reset(np); |
| 3245 | fflp_set_timings(np); |
| 3246 | err = fflp_disable_all_partitions(np); |
| 3247 | if (err) { |
| 3248 | niudbg(PROBE, "fflp_disable_all_partitions " |
| 3249 | "failed, err=%d\n", err); |
| 3250 | goto out; |
| 3251 | } |
| 3252 | } |
| 3253 | |
| 3254 | err = tcam_early_init(np); |
| 3255 | if (err) { |
| 3256 | niudbg(PROBE, "tcam_early_init failed, err=%d\n", |
| 3257 | err); |
| 3258 | goto out; |
| 3259 | } |
| 3260 | fflp_llcsnap_enable(np, 1); |
| 3261 | fflp_errors_enable(np, 0); |
| 3262 | nw64(H1POLY, 0); |
| 3263 | nw64(H2POLY, 0); |
| 3264 | |
| 3265 | err = tcam_flush_all(np); |
| 3266 | if (err) { |
| 3267 | niudbg(PROBE, "tcam_flush_all failed, err=%d\n", |
| 3268 | err); |
| 3269 | goto out; |
| 3270 | } |
| 3271 | if (np->parent->plat_type != PLAT_TYPE_NIU) { |
| 3272 | err = fflp_hash_clear(np); |
| 3273 | if (err) { |
| 3274 | niudbg(PROBE, "fflp_hash_clear failed, " |
| 3275 | "err=%d\n", err); |
| 3276 | goto out; |
| 3277 | } |
| 3278 | } |
| 3279 | |
| 3280 | vlan_tbl_clear(np); |
| 3281 | |
| 3282 | niudbg(PROBE, "fflp_early_init: Success\n"); |
| 3283 | parent->flags |= PARENT_FLGS_CLS_HWINIT; |
| 3284 | } |
| 3285 | out: |
| 3286 | niu_unlock_parent(np, flags); |
| 3287 | return err; |
| 3288 | } |
| 3289 | |
| 3290 | static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key) |
| 3291 | { |
| 3292 | if (class_code < CLASS_CODE_USER_PROG1 || |
| 3293 | class_code > CLASS_CODE_SCTP_IPV6) |
| 3294 | return -EINVAL; |
| 3295 | |
| 3296 | nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key); |
| 3297 | return 0; |
| 3298 | } |
| 3299 | |
| 3300 | static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key) |
| 3301 | { |
| 3302 | if (class_code < CLASS_CODE_USER_PROG1 || |
| 3303 | class_code > CLASS_CODE_SCTP_IPV6) |
| 3304 | return -EINVAL; |
| 3305 | |
| 3306 | nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key); |
| 3307 | return 0; |
| 3308 | } |
| 3309 | |
| 3310 | /* Entries for the ports are interleaved in the TCAM */ |
| 3311 | static u16 tcam_get_index(struct niu *np, u16 idx) |
| 3312 | { |
| 3313 | /* One entry reserved for IP fragment rule */ |
| 3314 | if (idx >= (np->clas.tcam_sz - 1)) |
| 3315 | idx = 0; |
| 3316 | return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports)); |
| 3317 | } |
| 3318 | |
| 3319 | static u16 tcam_get_size(struct niu *np) |
| 3320 | { |
| 3321 | /* One entry reserved for IP fragment rule */ |
| 3322 | return np->clas.tcam_sz - 1; |
| 3323 | } |
| 3324 | |
| 3325 | static u16 tcam_get_valid_entry_cnt(struct niu *np) |
| 3326 | { |
| 3327 | /* One entry reserved for IP fragment rule */ |
| 3328 | return np->clas.tcam_valid_entries - 1; |
| 3329 | } |
| 3330 | |
| 3331 | static void niu_rx_skb_append(struct sk_buff *skb, struct page *page, |
| 3332 | u32 offset, u32 size) |
| 3333 | { |
| 3334 | int i = skb_shinfo(skb)->nr_frags; |
| 3335 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 3336 | |
| 3337 | frag->page = page; |
| 3338 | frag->page_offset = offset; |
| 3339 | frag->size = size; |
| 3340 | |
| 3341 | skb->len += size; |
| 3342 | skb->data_len += size; |
| 3343 | skb->truesize += size; |
| 3344 | |
| 3345 | skb_shinfo(skb)->nr_frags = i + 1; |
| 3346 | } |
| 3347 | |
| 3348 | static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a) |
| 3349 | { |
| 3350 | a >>= PAGE_SHIFT; |
| 3351 | a ^= (a >> ilog2(MAX_RBR_RING_SIZE)); |
| 3352 | |
| 3353 | return (a & (MAX_RBR_RING_SIZE - 1)); |
| 3354 | } |
| 3355 | |
| 3356 | static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr, |
| 3357 | struct page ***link) |
| 3358 | { |
| 3359 | unsigned int h = niu_hash_rxaddr(rp, addr); |
| 3360 | struct page *p, **pp; |
| 3361 | |
| 3362 | addr &= PAGE_MASK; |
| 3363 | pp = &rp->rxhash[h]; |
| 3364 | for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) { |
| 3365 | if (p->index == addr) { |
| 3366 | *link = pp; |
| 3367 | break; |
| 3368 | } |
| 3369 | } |
| 3370 | |
| 3371 | return p; |
| 3372 | } |
| 3373 | |
| 3374 | static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base) |
| 3375 | { |
| 3376 | unsigned int h = niu_hash_rxaddr(rp, base); |
| 3377 | |
| 3378 | page->index = base; |
| 3379 | page->mapping = (struct address_space *) rp->rxhash[h]; |
| 3380 | rp->rxhash[h] = page; |
| 3381 | } |
| 3382 | |
| 3383 | static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp, |
| 3384 | gfp_t mask, int start_index) |
| 3385 | { |
| 3386 | struct page *page; |
| 3387 | u64 addr; |
| 3388 | int i; |
| 3389 | |
| 3390 | page = alloc_page(mask); |
| 3391 | if (!page) |
| 3392 | return -ENOMEM; |
| 3393 | |
| 3394 | addr = np->ops->map_page(np->device, page, 0, |
| 3395 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 3396 | |
| 3397 | niu_hash_page(rp, page, addr); |
| 3398 | if (rp->rbr_blocks_per_page > 1) |
| 3399 | atomic_add(rp->rbr_blocks_per_page - 1, |
| 3400 | &compound_head(page)->_count); |
| 3401 | |
| 3402 | for (i = 0; i < rp->rbr_blocks_per_page; i++) { |
| 3403 | __le32 *rbr = &rp->rbr[start_index + i]; |
| 3404 | |
| 3405 | *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT); |
| 3406 | addr += rp->rbr_block_size; |
| 3407 | } |
| 3408 | |
| 3409 | return 0; |
| 3410 | } |
| 3411 | |
| 3412 | static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) |
| 3413 | { |
| 3414 | int index = rp->rbr_index; |
| 3415 | |
| 3416 | rp->rbr_pending++; |
| 3417 | if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) { |
| 3418 | int err = niu_rbr_add_page(np, rp, mask, index); |
| 3419 | |
| 3420 | if (unlikely(err)) { |
| 3421 | rp->rbr_pending--; |
| 3422 | return; |
| 3423 | } |
| 3424 | |
| 3425 | rp->rbr_index += rp->rbr_blocks_per_page; |
| 3426 | BUG_ON(rp->rbr_index > rp->rbr_table_size); |
| 3427 | if (rp->rbr_index == rp->rbr_table_size) |
| 3428 | rp->rbr_index = 0; |
| 3429 | |
| 3430 | if (rp->rbr_pending >= rp->rbr_kick_thresh) { |
| 3431 | nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending); |
| 3432 | rp->rbr_pending = 0; |
| 3433 | } |
| 3434 | } |
| 3435 | } |
| 3436 | |
| 3437 | static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp) |
| 3438 | { |
| 3439 | unsigned int index = rp->rcr_index; |
| 3440 | int num_rcr = 0; |
| 3441 | |
| 3442 | rp->rx_dropped++; |
| 3443 | while (1) { |
| 3444 | struct page *page, **link; |
| 3445 | u64 addr, val; |
| 3446 | u32 rcr_size; |
| 3447 | |
| 3448 | num_rcr++; |
| 3449 | |
| 3450 | val = le64_to_cpup(&rp->rcr[index]); |
| 3451 | addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << |
| 3452 | RCR_ENTRY_PKT_BUF_ADDR_SHIFT; |
| 3453 | page = niu_find_rxpage(rp, addr, &link); |
| 3454 | |
| 3455 | rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> |
| 3456 | RCR_ENTRY_PKTBUFSZ_SHIFT]; |
| 3457 | if ((page->index + PAGE_SIZE) - rcr_size == addr) { |
| 3458 | *link = (struct page *) page->mapping; |
| 3459 | np->ops->unmap_page(np->device, page->index, |
| 3460 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 3461 | page->index = 0; |
| 3462 | page->mapping = NULL; |
| 3463 | __free_page(page); |
| 3464 | rp->rbr_refill_pending++; |
| 3465 | } |
| 3466 | |
| 3467 | index = NEXT_RCR(rp, index); |
| 3468 | if (!(val & RCR_ENTRY_MULTI)) |
| 3469 | break; |
| 3470 | |
| 3471 | } |
| 3472 | rp->rcr_index = index; |
| 3473 | |
| 3474 | return num_rcr; |
| 3475 | } |
| 3476 | |
| 3477 | static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np, |
| 3478 | struct rx_ring_info *rp) |
| 3479 | { |
| 3480 | unsigned int index = rp->rcr_index; |
| 3481 | struct sk_buff *skb; |
| 3482 | int len, num_rcr; |
| 3483 | |
| 3484 | skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE); |
| 3485 | if (unlikely(!skb)) |
| 3486 | return niu_rx_pkt_ignore(np, rp); |
| 3487 | |
| 3488 | num_rcr = 0; |
| 3489 | while (1) { |
| 3490 | struct page *page, **link; |
| 3491 | u32 rcr_size, append_size; |
| 3492 | u64 addr, val, off; |
| 3493 | |
| 3494 | num_rcr++; |
| 3495 | |
| 3496 | val = le64_to_cpup(&rp->rcr[index]); |
| 3497 | |
| 3498 | len = (val & RCR_ENTRY_L2_LEN) >> |
| 3499 | RCR_ENTRY_L2_LEN_SHIFT; |
| 3500 | len -= ETH_FCS_LEN; |
| 3501 | |
| 3502 | addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << |
| 3503 | RCR_ENTRY_PKT_BUF_ADDR_SHIFT; |
| 3504 | page = niu_find_rxpage(rp, addr, &link); |
| 3505 | |
| 3506 | rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> |
| 3507 | RCR_ENTRY_PKTBUFSZ_SHIFT]; |
| 3508 | |
| 3509 | off = addr & ~PAGE_MASK; |
| 3510 | append_size = rcr_size; |
| 3511 | if (num_rcr == 1) { |
| 3512 | int ptype; |
| 3513 | |
| 3514 | off += 2; |
| 3515 | append_size -= 2; |
| 3516 | |
| 3517 | ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT); |
| 3518 | if ((ptype == RCR_PKT_TYPE_TCP || |
| 3519 | ptype == RCR_PKT_TYPE_UDP) && |
| 3520 | !(val & (RCR_ENTRY_NOPORT | |
| 3521 | RCR_ENTRY_ERROR))) |
| 3522 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 3523 | else |
| 3524 | skb->ip_summed = CHECKSUM_NONE; |
| 3525 | } |
| 3526 | if (!(val & RCR_ENTRY_MULTI)) |
| 3527 | append_size = len - skb->len; |
| 3528 | |
| 3529 | niu_rx_skb_append(skb, page, off, append_size); |
| 3530 | if ((page->index + rp->rbr_block_size) - rcr_size == addr) { |
| 3531 | *link = (struct page *) page->mapping; |
| 3532 | np->ops->unmap_page(np->device, page->index, |
| 3533 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 3534 | page->index = 0; |
| 3535 | page->mapping = NULL; |
| 3536 | rp->rbr_refill_pending++; |
| 3537 | } else |
| 3538 | get_page(page); |
| 3539 | |
| 3540 | index = NEXT_RCR(rp, index); |
| 3541 | if (!(val & RCR_ENTRY_MULTI)) |
| 3542 | break; |
| 3543 | |
| 3544 | } |
| 3545 | rp->rcr_index = index; |
| 3546 | |
| 3547 | skb_reserve(skb, NET_IP_ALIGN); |
| 3548 | __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX)); |
| 3549 | |
| 3550 | rp->rx_packets++; |
| 3551 | rp->rx_bytes += skb->len; |
| 3552 | |
| 3553 | skb->protocol = eth_type_trans(skb, np->dev); |
| 3554 | skb_record_rx_queue(skb, rp->rx_channel); |
| 3555 | napi_gro_receive(napi, skb); |
| 3556 | |
| 3557 | return num_rcr; |
| 3558 | } |
| 3559 | |
| 3560 | static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) |
| 3561 | { |
| 3562 | int blocks_per_page = rp->rbr_blocks_per_page; |
| 3563 | int err, index = rp->rbr_index; |
| 3564 | |
| 3565 | err = 0; |
| 3566 | while (index < (rp->rbr_table_size - blocks_per_page)) { |
| 3567 | err = niu_rbr_add_page(np, rp, mask, index); |
| 3568 | if (err) |
| 3569 | break; |
| 3570 | |
| 3571 | index += blocks_per_page; |
| 3572 | } |
| 3573 | |
| 3574 | rp->rbr_index = index; |
| 3575 | return err; |
| 3576 | } |
| 3577 | |
| 3578 | static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp) |
| 3579 | { |
| 3580 | int i; |
| 3581 | |
| 3582 | for (i = 0; i < MAX_RBR_RING_SIZE; i++) { |
| 3583 | struct page *page; |
| 3584 | |
| 3585 | page = rp->rxhash[i]; |
| 3586 | while (page) { |
| 3587 | struct page *next = (struct page *) page->mapping; |
| 3588 | u64 base = page->index; |
| 3589 | |
| 3590 | np->ops->unmap_page(np->device, base, PAGE_SIZE, |
| 3591 | DMA_FROM_DEVICE); |
| 3592 | page->index = 0; |
| 3593 | page->mapping = NULL; |
| 3594 | |
| 3595 | __free_page(page); |
| 3596 | |
| 3597 | page = next; |
| 3598 | } |
| 3599 | } |
| 3600 | |
| 3601 | for (i = 0; i < rp->rbr_table_size; i++) |
| 3602 | rp->rbr[i] = cpu_to_le32(0); |
| 3603 | rp->rbr_index = 0; |
| 3604 | } |
| 3605 | |
| 3606 | static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx) |
| 3607 | { |
| 3608 | struct tx_buff_info *tb = &rp->tx_buffs[idx]; |
| 3609 | struct sk_buff *skb = tb->skb; |
| 3610 | struct tx_pkt_hdr *tp; |
| 3611 | u64 tx_flags; |
| 3612 | int i, len; |
| 3613 | |
| 3614 | tp = (struct tx_pkt_hdr *) skb->data; |
| 3615 | tx_flags = le64_to_cpup(&tp->flags); |
| 3616 | |
| 3617 | rp->tx_packets++; |
| 3618 | rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) - |
| 3619 | ((tx_flags & TXHDR_PAD) / 2)); |
| 3620 | |
| 3621 | len = skb_headlen(skb); |
| 3622 | np->ops->unmap_single(np->device, tb->mapping, |
| 3623 | len, DMA_TO_DEVICE); |
| 3624 | |
| 3625 | if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK) |
| 3626 | rp->mark_pending--; |
| 3627 | |
| 3628 | tb->skb = NULL; |
| 3629 | do { |
| 3630 | idx = NEXT_TX(rp, idx); |
| 3631 | len -= MAX_TX_DESC_LEN; |
| 3632 | } while (len > 0); |
| 3633 | |
| 3634 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
| 3635 | tb = &rp->tx_buffs[idx]; |
| 3636 | BUG_ON(tb->skb != NULL); |
| 3637 | np->ops->unmap_page(np->device, tb->mapping, |
| 3638 | skb_shinfo(skb)->frags[i].size, |
| 3639 | DMA_TO_DEVICE); |
| 3640 | idx = NEXT_TX(rp, idx); |
| 3641 | } |
| 3642 | |
| 3643 | dev_kfree_skb(skb); |
| 3644 | |
| 3645 | return idx; |
| 3646 | } |
| 3647 | |
| 3648 | #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4) |
| 3649 | |
| 3650 | static void niu_tx_work(struct niu *np, struct tx_ring_info *rp) |
| 3651 | { |
| 3652 | struct netdev_queue *txq; |
| 3653 | u16 pkt_cnt, tmp; |
| 3654 | int cons, index; |
| 3655 | u64 cs; |
| 3656 | |
| 3657 | index = (rp - np->tx_rings); |
| 3658 | txq = netdev_get_tx_queue(np->dev, index); |
| 3659 | |
| 3660 | cs = rp->tx_cs; |
| 3661 | if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK)))) |
| 3662 | goto out; |
| 3663 | |
| 3664 | tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT; |
| 3665 | pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) & |
| 3666 | (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT); |
| 3667 | |
| 3668 | rp->last_pkt_cnt = tmp; |
| 3669 | |
| 3670 | cons = rp->cons; |
| 3671 | |
| 3672 | niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n", |
| 3673 | np->dev->name, pkt_cnt, cons); |
| 3674 | |
| 3675 | while (pkt_cnt--) |
| 3676 | cons = release_tx_packet(np, rp, cons); |
| 3677 | |
| 3678 | rp->cons = cons; |
| 3679 | smp_mb(); |
| 3680 | |
| 3681 | out: |
| 3682 | if (unlikely(netif_tx_queue_stopped(txq) && |
| 3683 | (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) { |
| 3684 | __netif_tx_lock(txq, smp_processor_id()); |
| 3685 | if (netif_tx_queue_stopped(txq) && |
| 3686 | (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))) |
| 3687 | netif_tx_wake_queue(txq); |
| 3688 | __netif_tx_unlock(txq); |
| 3689 | } |
| 3690 | } |
| 3691 | |
| 3692 | static inline void niu_sync_rx_discard_stats(struct niu *np, |
| 3693 | struct rx_ring_info *rp, |
| 3694 | const int limit) |
| 3695 | { |
| 3696 | /* This elaborate scheme is needed for reading the RX discard |
| 3697 | * counters, as they are only 16-bit and can overflow quickly, |
| 3698 | * and because the overflow indication bit is not usable as |
| 3699 | * the counter value does not wrap, but remains at max value |
| 3700 | * 0xFFFF. |
| 3701 | * |
| 3702 | * In theory and in practice counters can be lost in between |
| 3703 | * reading nr64() and clearing the counter nw64(). For this |
| 3704 | * reason, the number of counter clearings nw64() is |
| 3705 | * limited/reduced though the limit parameter. |
| 3706 | */ |
| 3707 | int rx_channel = rp->rx_channel; |
| 3708 | u32 misc, wred; |
| 3709 | |
| 3710 | /* RXMISC (Receive Miscellaneous Discard Count), covers the |
| 3711 | * following discard events: IPP (Input Port Process), |
| 3712 | * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive |
| 3713 | * Block Ring) prefetch buffer is empty. |
| 3714 | */ |
| 3715 | misc = nr64(RXMISC(rx_channel)); |
| 3716 | if (unlikely((misc & RXMISC_COUNT) > limit)) { |
| 3717 | nw64(RXMISC(rx_channel), 0); |
| 3718 | rp->rx_errors += misc & RXMISC_COUNT; |
| 3719 | |
| 3720 | if (unlikely(misc & RXMISC_OFLOW)) |
| 3721 | dev_err(np->device, "rx-%d: Counter overflow " |
| 3722 | "RXMISC discard\n", rx_channel); |
| 3723 | |
| 3724 | niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n", |
| 3725 | np->dev->name, rx_channel, misc, misc-limit); |
| 3726 | } |
| 3727 | |
| 3728 | /* WRED (Weighted Random Early Discard) by hardware */ |
| 3729 | wred = nr64(RED_DIS_CNT(rx_channel)); |
| 3730 | if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) { |
| 3731 | nw64(RED_DIS_CNT(rx_channel), 0); |
| 3732 | rp->rx_dropped += wred & RED_DIS_CNT_COUNT; |
| 3733 | |
| 3734 | if (unlikely(wred & RED_DIS_CNT_OFLOW)) |
| 3735 | dev_err(np->device, "rx-%d: Counter overflow " |
| 3736 | "WRED discard\n", rx_channel); |
| 3737 | |
| 3738 | niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n", |
| 3739 | np->dev->name, rx_channel, wred, wred-limit); |
| 3740 | } |
| 3741 | } |
| 3742 | |
| 3743 | static int niu_rx_work(struct napi_struct *napi, struct niu *np, |
| 3744 | struct rx_ring_info *rp, int budget) |
| 3745 | { |
| 3746 | int qlen, rcr_done = 0, work_done = 0; |
| 3747 | struct rxdma_mailbox *mbox = rp->mbox; |
| 3748 | u64 stat; |
| 3749 | |
| 3750 | #if 1 |
| 3751 | stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); |
| 3752 | qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN; |
| 3753 | #else |
| 3754 | stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); |
| 3755 | qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN); |
| 3756 | #endif |
| 3757 | mbox->rx_dma_ctl_stat = 0; |
| 3758 | mbox->rcrstat_a = 0; |
| 3759 | |
| 3760 | niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n", |
| 3761 | np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen); |
| 3762 | |
| 3763 | rcr_done = work_done = 0; |
| 3764 | qlen = min(qlen, budget); |
| 3765 | while (work_done < qlen) { |
| 3766 | rcr_done += niu_process_rx_pkt(napi, np, rp); |
| 3767 | work_done++; |
| 3768 | } |
| 3769 | |
| 3770 | if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) { |
| 3771 | unsigned int i; |
| 3772 | |
| 3773 | for (i = 0; i < rp->rbr_refill_pending; i++) |
| 3774 | niu_rbr_refill(np, rp, GFP_ATOMIC); |
| 3775 | rp->rbr_refill_pending = 0; |
| 3776 | } |
| 3777 | |
| 3778 | stat = (RX_DMA_CTL_STAT_MEX | |
| 3779 | ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) | |
| 3780 | ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT)); |
| 3781 | |
| 3782 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat); |
| 3783 | |
| 3784 | /* Only sync discards stats when qlen indicate potential for drops */ |
| 3785 | if (qlen > 10) |
| 3786 | niu_sync_rx_discard_stats(np, rp, 0x7FFF); |
| 3787 | |
| 3788 | return work_done; |
| 3789 | } |
| 3790 | |
| 3791 | static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget) |
| 3792 | { |
| 3793 | u64 v0 = lp->v0; |
| 3794 | u32 tx_vec = (v0 >> 32); |
| 3795 | u32 rx_vec = (v0 & 0xffffffff); |
| 3796 | int i, work_done = 0; |
| 3797 | |
| 3798 | niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n", |
| 3799 | np->dev->name, (unsigned long long) v0); |
| 3800 | |
| 3801 | for (i = 0; i < np->num_tx_rings; i++) { |
| 3802 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 3803 | if (tx_vec & (1 << rp->tx_channel)) |
| 3804 | niu_tx_work(np, rp); |
| 3805 | nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0); |
| 3806 | } |
| 3807 | |
| 3808 | for (i = 0; i < np->num_rx_rings; i++) { |
| 3809 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 3810 | |
| 3811 | if (rx_vec & (1 << rp->rx_channel)) { |
| 3812 | int this_work_done; |
| 3813 | |
| 3814 | this_work_done = niu_rx_work(&lp->napi, np, rp, |
| 3815 | budget); |
| 3816 | |
| 3817 | budget -= this_work_done; |
| 3818 | work_done += this_work_done; |
| 3819 | } |
| 3820 | nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0); |
| 3821 | } |
| 3822 | |
| 3823 | return work_done; |
| 3824 | } |
| 3825 | |
| 3826 | static int niu_poll(struct napi_struct *napi, int budget) |
| 3827 | { |
| 3828 | struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi); |
| 3829 | struct niu *np = lp->np; |
| 3830 | int work_done; |
| 3831 | |
| 3832 | work_done = niu_poll_core(np, lp, budget); |
| 3833 | |
| 3834 | if (work_done < budget) { |
| 3835 | napi_complete(napi); |
| 3836 | niu_ldg_rearm(np, lp, 1); |
| 3837 | } |
| 3838 | return work_done; |
| 3839 | } |
| 3840 | |
| 3841 | static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp, |
| 3842 | u64 stat) |
| 3843 | { |
| 3844 | dev_err(np->device, PFX "%s: RX channel %u errors ( ", |
| 3845 | np->dev->name, rp->rx_channel); |
| 3846 | |
| 3847 | if (stat & RX_DMA_CTL_STAT_RBR_TMOUT) |
| 3848 | printk("RBR_TMOUT "); |
| 3849 | if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR) |
| 3850 | printk("RSP_CNT "); |
| 3851 | if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS) |
| 3852 | printk("BYTE_EN_BUS "); |
| 3853 | if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR) |
| 3854 | printk("RSP_DAT "); |
| 3855 | if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR) |
| 3856 | printk("RCR_ACK "); |
| 3857 | if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR) |
| 3858 | printk("RCR_SHA_PAR "); |
| 3859 | if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR) |
| 3860 | printk("RBR_PRE_PAR "); |
| 3861 | if (stat & RX_DMA_CTL_STAT_CONFIG_ERR) |
| 3862 | printk("CONFIG "); |
| 3863 | if (stat & RX_DMA_CTL_STAT_RCRINCON) |
| 3864 | printk("RCRINCON "); |
| 3865 | if (stat & RX_DMA_CTL_STAT_RCRFULL) |
| 3866 | printk("RCRFULL "); |
| 3867 | if (stat & RX_DMA_CTL_STAT_RBRFULL) |
| 3868 | printk("RBRFULL "); |
| 3869 | if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE) |
| 3870 | printk("RBRLOGPAGE "); |
| 3871 | if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE) |
| 3872 | printk("CFIGLOGPAGE "); |
| 3873 | if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR) |
| 3874 | printk("DC_FIDO "); |
| 3875 | |
| 3876 | printk(")\n"); |
| 3877 | } |
| 3878 | |
| 3879 | static int niu_rx_error(struct niu *np, struct rx_ring_info *rp) |
| 3880 | { |
| 3881 | u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); |
| 3882 | int err = 0; |
| 3883 | |
| 3884 | |
| 3885 | if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL | |
| 3886 | RX_DMA_CTL_STAT_PORT_FATAL)) |
| 3887 | err = -EINVAL; |
| 3888 | |
| 3889 | if (err) { |
| 3890 | dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n", |
| 3891 | np->dev->name, rp->rx_channel, |
| 3892 | (unsigned long long) stat); |
| 3893 | |
| 3894 | niu_log_rxchan_errors(np, rp, stat); |
| 3895 | } |
| 3896 | |
| 3897 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), |
| 3898 | stat & RX_DMA_CTL_WRITE_CLEAR_ERRS); |
| 3899 | |
| 3900 | return err; |
| 3901 | } |
| 3902 | |
| 3903 | static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp, |
| 3904 | u64 cs) |
| 3905 | { |
| 3906 | dev_err(np->device, PFX "%s: TX channel %u errors ( ", |
| 3907 | np->dev->name, rp->tx_channel); |
| 3908 | |
| 3909 | if (cs & TX_CS_MBOX_ERR) |
| 3910 | printk("MBOX "); |
| 3911 | if (cs & TX_CS_PKT_SIZE_ERR) |
| 3912 | printk("PKT_SIZE "); |
| 3913 | if (cs & TX_CS_TX_RING_OFLOW) |
| 3914 | printk("TX_RING_OFLOW "); |
| 3915 | if (cs & TX_CS_PREF_BUF_PAR_ERR) |
| 3916 | printk("PREF_BUF_PAR "); |
| 3917 | if (cs & TX_CS_NACK_PREF) |
| 3918 | printk("NACK_PREF "); |
| 3919 | if (cs & TX_CS_NACK_PKT_RD) |
| 3920 | printk("NACK_PKT_RD "); |
| 3921 | if (cs & TX_CS_CONF_PART_ERR) |
| 3922 | printk("CONF_PART "); |
| 3923 | if (cs & TX_CS_PKT_PRT_ERR) |
| 3924 | printk("PKT_PTR "); |
| 3925 | |
| 3926 | printk(")\n"); |
| 3927 | } |
| 3928 | |
| 3929 | static int niu_tx_error(struct niu *np, struct tx_ring_info *rp) |
| 3930 | { |
| 3931 | u64 cs, logh, logl; |
| 3932 | |
| 3933 | cs = nr64(TX_CS(rp->tx_channel)); |
| 3934 | logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel)); |
| 3935 | logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel)); |
| 3936 | |
| 3937 | dev_err(np->device, PFX "%s: TX channel %u error, " |
| 3938 | "cs[%llx] logh[%llx] logl[%llx]\n", |
| 3939 | np->dev->name, rp->tx_channel, |
| 3940 | (unsigned long long) cs, |
| 3941 | (unsigned long long) logh, |
| 3942 | (unsigned long long) logl); |
| 3943 | |
| 3944 | niu_log_txchan_errors(np, rp, cs); |
| 3945 | |
| 3946 | return -ENODEV; |
| 3947 | } |
| 3948 | |
| 3949 | static int niu_mif_interrupt(struct niu *np) |
| 3950 | { |
| 3951 | u64 mif_status = nr64(MIF_STATUS); |
| 3952 | int phy_mdint = 0; |
| 3953 | |
| 3954 | if (np->flags & NIU_FLAGS_XMAC) { |
| 3955 | u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS); |
| 3956 | |
| 3957 | if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT) |
| 3958 | phy_mdint = 1; |
| 3959 | } |
| 3960 | |
| 3961 | dev_err(np->device, PFX "%s: MIF interrupt, " |
| 3962 | "stat[%llx] phy_mdint(%d)\n", |
| 3963 | np->dev->name, (unsigned long long) mif_status, phy_mdint); |
| 3964 | |
| 3965 | return -ENODEV; |
| 3966 | } |
| 3967 | |
| 3968 | static void niu_xmac_interrupt(struct niu *np) |
| 3969 | { |
| 3970 | struct niu_xmac_stats *mp = &np->mac_stats.xmac; |
| 3971 | u64 val; |
| 3972 | |
| 3973 | val = nr64_mac(XTXMAC_STATUS); |
| 3974 | if (val & XTXMAC_STATUS_FRAME_CNT_EXP) |
| 3975 | mp->tx_frames += TXMAC_FRM_CNT_COUNT; |
| 3976 | if (val & XTXMAC_STATUS_BYTE_CNT_EXP) |
| 3977 | mp->tx_bytes += TXMAC_BYTE_CNT_COUNT; |
| 3978 | if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR) |
| 3979 | mp->tx_fifo_errors++; |
| 3980 | if (val & XTXMAC_STATUS_TXMAC_OFLOW) |
| 3981 | mp->tx_overflow_errors++; |
| 3982 | if (val & XTXMAC_STATUS_MAX_PSIZE_ERR) |
| 3983 | mp->tx_max_pkt_size_errors++; |
| 3984 | if (val & XTXMAC_STATUS_TXMAC_UFLOW) |
| 3985 | mp->tx_underflow_errors++; |
| 3986 | |
| 3987 | val = nr64_mac(XRXMAC_STATUS); |
| 3988 | if (val & XRXMAC_STATUS_LCL_FLT_STATUS) |
| 3989 | mp->rx_local_faults++; |
| 3990 | if (val & XRXMAC_STATUS_RFLT_DET) |
| 3991 | mp->rx_remote_faults++; |
| 3992 | if (val & XRXMAC_STATUS_LFLT_CNT_EXP) |
| 3993 | mp->rx_link_faults += LINK_FAULT_CNT_COUNT; |
| 3994 | if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP) |
| 3995 | mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT; |
| 3996 | if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP) |
| 3997 | mp->rx_frags += RXMAC_FRAG_CNT_COUNT; |
| 3998 | if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP) |
| 3999 | mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT; |
| 4000 | if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) |
| 4001 | mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; |
| 4002 | if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) |
| 4003 | mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; |
| 4004 | if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP) |
| 4005 | mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT; |
| 4006 | if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP) |
| 4007 | mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT; |
| 4008 | if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP) |
| 4009 | mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT; |
| 4010 | if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP) |
| 4011 | mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT; |
| 4012 | if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP) |
| 4013 | mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT; |
| 4014 | if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP) |
| 4015 | mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT; |
| 4016 | if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP) |
| 4017 | mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT; |
| 4018 | if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP) |
| 4019 | mp->rx_octets += RXMAC_BT_CNT_COUNT; |
| 4020 | if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP) |
| 4021 | mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT; |
| 4022 | if (val & XRXMAC_STATUS_LENERR_CNT_EXP) |
| 4023 | mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT; |
| 4024 | if (val & XRXMAC_STATUS_CRCERR_CNT_EXP) |
| 4025 | mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT; |
| 4026 | if (val & XRXMAC_STATUS_RXUFLOW) |
| 4027 | mp->rx_underflows++; |
| 4028 | if (val & XRXMAC_STATUS_RXOFLOW) |
| 4029 | mp->rx_overflows++; |
| 4030 | |
| 4031 | val = nr64_mac(XMAC_FC_STAT); |
| 4032 | if (val & XMAC_FC_STAT_TX_MAC_NPAUSE) |
| 4033 | mp->pause_off_state++; |
| 4034 | if (val & XMAC_FC_STAT_TX_MAC_PAUSE) |
| 4035 | mp->pause_on_state++; |
| 4036 | if (val & XMAC_FC_STAT_RX_MAC_RPAUSE) |
| 4037 | mp->pause_received++; |
| 4038 | } |
| 4039 | |
| 4040 | static void niu_bmac_interrupt(struct niu *np) |
| 4041 | { |
| 4042 | struct niu_bmac_stats *mp = &np->mac_stats.bmac; |
| 4043 | u64 val; |
| 4044 | |
| 4045 | val = nr64_mac(BTXMAC_STATUS); |
| 4046 | if (val & BTXMAC_STATUS_UNDERRUN) |
| 4047 | mp->tx_underflow_errors++; |
| 4048 | if (val & BTXMAC_STATUS_MAX_PKT_ERR) |
| 4049 | mp->tx_max_pkt_size_errors++; |
| 4050 | if (val & BTXMAC_STATUS_BYTE_CNT_EXP) |
| 4051 | mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT; |
| 4052 | if (val & BTXMAC_STATUS_FRAME_CNT_EXP) |
| 4053 | mp->tx_frames += BTXMAC_FRM_CNT_COUNT; |
| 4054 | |
| 4055 | val = nr64_mac(BRXMAC_STATUS); |
| 4056 | if (val & BRXMAC_STATUS_OVERFLOW) |
| 4057 | mp->rx_overflows++; |
| 4058 | if (val & BRXMAC_STATUS_FRAME_CNT_EXP) |
| 4059 | mp->rx_frames += BRXMAC_FRAME_CNT_COUNT; |
| 4060 | if (val & BRXMAC_STATUS_ALIGN_ERR_EXP) |
| 4061 | mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; |
| 4062 | if (val & BRXMAC_STATUS_CRC_ERR_EXP) |
| 4063 | mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; |
| 4064 | if (val & BRXMAC_STATUS_LEN_ERR_EXP) |
| 4065 | mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT; |
| 4066 | |
| 4067 | val = nr64_mac(BMAC_CTRL_STATUS); |
| 4068 | if (val & BMAC_CTRL_STATUS_NOPAUSE) |
| 4069 | mp->pause_off_state++; |
| 4070 | if (val & BMAC_CTRL_STATUS_PAUSE) |
| 4071 | mp->pause_on_state++; |
| 4072 | if (val & BMAC_CTRL_STATUS_PAUSE_RECV) |
| 4073 | mp->pause_received++; |
| 4074 | } |
| 4075 | |
| 4076 | static int niu_mac_interrupt(struct niu *np) |
| 4077 | { |
| 4078 | if (np->flags & NIU_FLAGS_XMAC) |
| 4079 | niu_xmac_interrupt(np); |
| 4080 | else |
| 4081 | niu_bmac_interrupt(np); |
| 4082 | |
| 4083 | return 0; |
| 4084 | } |
| 4085 | |
| 4086 | static void niu_log_device_error(struct niu *np, u64 stat) |
| 4087 | { |
| 4088 | dev_err(np->device, PFX "%s: Core device errors ( ", |
| 4089 | np->dev->name); |
| 4090 | |
| 4091 | if (stat & SYS_ERR_MASK_META2) |
| 4092 | printk("META2 "); |
| 4093 | if (stat & SYS_ERR_MASK_META1) |
| 4094 | printk("META1 "); |
| 4095 | if (stat & SYS_ERR_MASK_PEU) |
| 4096 | printk("PEU "); |
| 4097 | if (stat & SYS_ERR_MASK_TXC) |
| 4098 | printk("TXC "); |
| 4099 | if (stat & SYS_ERR_MASK_RDMC) |
| 4100 | printk("RDMC "); |
| 4101 | if (stat & SYS_ERR_MASK_TDMC) |
| 4102 | printk("TDMC "); |
| 4103 | if (stat & SYS_ERR_MASK_ZCP) |
| 4104 | printk("ZCP "); |
| 4105 | if (stat & SYS_ERR_MASK_FFLP) |
| 4106 | printk("FFLP "); |
| 4107 | if (stat & SYS_ERR_MASK_IPP) |
| 4108 | printk("IPP "); |
| 4109 | if (stat & SYS_ERR_MASK_MAC) |
| 4110 | printk("MAC "); |
| 4111 | if (stat & SYS_ERR_MASK_SMX) |
| 4112 | printk("SMX "); |
| 4113 | |
| 4114 | printk(")\n"); |
| 4115 | } |
| 4116 | |
| 4117 | static int niu_device_error(struct niu *np) |
| 4118 | { |
| 4119 | u64 stat = nr64(SYS_ERR_STAT); |
| 4120 | |
| 4121 | dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n", |
| 4122 | np->dev->name, (unsigned long long) stat); |
| 4123 | |
| 4124 | niu_log_device_error(np, stat); |
| 4125 | |
| 4126 | return -ENODEV; |
| 4127 | } |
| 4128 | |
| 4129 | static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp, |
| 4130 | u64 v0, u64 v1, u64 v2) |
| 4131 | { |
| 4132 | |
| 4133 | int i, err = 0; |
| 4134 | |
| 4135 | lp->v0 = v0; |
| 4136 | lp->v1 = v1; |
| 4137 | lp->v2 = v2; |
| 4138 | |
| 4139 | if (v1 & 0x00000000ffffffffULL) { |
| 4140 | u32 rx_vec = (v1 & 0xffffffff); |
| 4141 | |
| 4142 | for (i = 0; i < np->num_rx_rings; i++) { |
| 4143 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 4144 | |
| 4145 | if (rx_vec & (1 << rp->rx_channel)) { |
| 4146 | int r = niu_rx_error(np, rp); |
| 4147 | if (r) { |
| 4148 | err = r; |
| 4149 | } else { |
| 4150 | if (!v0) |
| 4151 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), |
| 4152 | RX_DMA_CTL_STAT_MEX); |
| 4153 | } |
| 4154 | } |
| 4155 | } |
| 4156 | } |
| 4157 | if (v1 & 0x7fffffff00000000ULL) { |
| 4158 | u32 tx_vec = (v1 >> 32) & 0x7fffffff; |
| 4159 | |
| 4160 | for (i = 0; i < np->num_tx_rings; i++) { |
| 4161 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 4162 | |
| 4163 | if (tx_vec & (1 << rp->tx_channel)) { |
| 4164 | int r = niu_tx_error(np, rp); |
| 4165 | if (r) |
| 4166 | err = r; |
| 4167 | } |
| 4168 | } |
| 4169 | } |
| 4170 | if ((v0 | v1) & 0x8000000000000000ULL) { |
| 4171 | int r = niu_mif_interrupt(np); |
| 4172 | if (r) |
| 4173 | err = r; |
| 4174 | } |
| 4175 | if (v2) { |
| 4176 | if (v2 & 0x01ef) { |
| 4177 | int r = niu_mac_interrupt(np); |
| 4178 | if (r) |
| 4179 | err = r; |
| 4180 | } |
| 4181 | if (v2 & 0x0210) { |
| 4182 | int r = niu_device_error(np); |
| 4183 | if (r) |
| 4184 | err = r; |
| 4185 | } |
| 4186 | } |
| 4187 | |
| 4188 | if (err) |
| 4189 | niu_enable_interrupts(np, 0); |
| 4190 | |
| 4191 | return err; |
| 4192 | } |
| 4193 | |
| 4194 | static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp, |
| 4195 | int ldn) |
| 4196 | { |
| 4197 | struct rxdma_mailbox *mbox = rp->mbox; |
| 4198 | u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); |
| 4199 | |
| 4200 | stat_write = (RX_DMA_CTL_STAT_RCRTHRES | |
| 4201 | RX_DMA_CTL_STAT_RCRTO); |
| 4202 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write); |
| 4203 | |
| 4204 | niudbg(INTR, "%s: rxchan_intr stat[%llx]\n", |
| 4205 | np->dev->name, (unsigned long long) stat); |
| 4206 | } |
| 4207 | |
| 4208 | static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp, |
| 4209 | int ldn) |
| 4210 | { |
| 4211 | rp->tx_cs = nr64(TX_CS(rp->tx_channel)); |
| 4212 | |
| 4213 | niudbg(INTR, "%s: txchan_intr cs[%llx]\n", |
| 4214 | np->dev->name, (unsigned long long) rp->tx_cs); |
| 4215 | } |
| 4216 | |
| 4217 | static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0) |
| 4218 | { |
| 4219 | struct niu_parent *parent = np->parent; |
| 4220 | u32 rx_vec, tx_vec; |
| 4221 | int i; |
| 4222 | |
| 4223 | tx_vec = (v0 >> 32); |
| 4224 | rx_vec = (v0 & 0xffffffff); |
| 4225 | |
| 4226 | for (i = 0; i < np->num_rx_rings; i++) { |
| 4227 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 4228 | int ldn = LDN_RXDMA(rp->rx_channel); |
| 4229 | |
| 4230 | if (parent->ldg_map[ldn] != ldg) |
| 4231 | continue; |
| 4232 | |
| 4233 | nw64(LD_IM0(ldn), LD_IM0_MASK); |
| 4234 | if (rx_vec & (1 << rp->rx_channel)) |
| 4235 | niu_rxchan_intr(np, rp, ldn); |
| 4236 | } |
| 4237 | |
| 4238 | for (i = 0; i < np->num_tx_rings; i++) { |
| 4239 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 4240 | int ldn = LDN_TXDMA(rp->tx_channel); |
| 4241 | |
| 4242 | if (parent->ldg_map[ldn] != ldg) |
| 4243 | continue; |
| 4244 | |
| 4245 | nw64(LD_IM0(ldn), LD_IM0_MASK); |
| 4246 | if (tx_vec & (1 << rp->tx_channel)) |
| 4247 | niu_txchan_intr(np, rp, ldn); |
| 4248 | } |
| 4249 | } |
| 4250 | |
| 4251 | static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp, |
| 4252 | u64 v0, u64 v1, u64 v2) |
| 4253 | { |
| 4254 | if (likely(napi_schedule_prep(&lp->napi))) { |
| 4255 | lp->v0 = v0; |
| 4256 | lp->v1 = v1; |
| 4257 | lp->v2 = v2; |
| 4258 | __niu_fastpath_interrupt(np, lp->ldg_num, v0); |
| 4259 | __napi_schedule(&lp->napi); |
| 4260 | } |
| 4261 | } |
| 4262 | |
| 4263 | static irqreturn_t niu_interrupt(int irq, void *dev_id) |
| 4264 | { |
| 4265 | struct niu_ldg *lp = dev_id; |
| 4266 | struct niu *np = lp->np; |
| 4267 | int ldg = lp->ldg_num; |
| 4268 | unsigned long flags; |
| 4269 | u64 v0, v1, v2; |
| 4270 | |
| 4271 | if (netif_msg_intr(np)) |
| 4272 | printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ", |
| 4273 | lp, ldg); |
| 4274 | |
| 4275 | spin_lock_irqsave(&np->lock, flags); |
| 4276 | |
| 4277 | v0 = nr64(LDSV0(ldg)); |
| 4278 | v1 = nr64(LDSV1(ldg)); |
| 4279 | v2 = nr64(LDSV2(ldg)); |
| 4280 | |
| 4281 | if (netif_msg_intr(np)) |
| 4282 | printk("v0[%llx] v1[%llx] v2[%llx]\n", |
| 4283 | (unsigned long long) v0, |
| 4284 | (unsigned long long) v1, |
| 4285 | (unsigned long long) v2); |
| 4286 | |
| 4287 | if (unlikely(!v0 && !v1 && !v2)) { |
| 4288 | spin_unlock_irqrestore(&np->lock, flags); |
| 4289 | return IRQ_NONE; |
| 4290 | } |
| 4291 | |
| 4292 | if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) { |
| 4293 | int err = niu_slowpath_interrupt(np, lp, v0, v1, v2); |
| 4294 | if (err) |
| 4295 | goto out; |
| 4296 | } |
| 4297 | if (likely(v0 & ~((u64)1 << LDN_MIF))) |
| 4298 | niu_schedule_napi(np, lp, v0, v1, v2); |
| 4299 | else |
| 4300 | niu_ldg_rearm(np, lp, 1); |
| 4301 | out: |
| 4302 | spin_unlock_irqrestore(&np->lock, flags); |
| 4303 | |
| 4304 | return IRQ_HANDLED; |
| 4305 | } |
| 4306 | |
| 4307 | static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp) |
| 4308 | { |
| 4309 | if (rp->mbox) { |
| 4310 | np->ops->free_coherent(np->device, |
| 4311 | sizeof(struct rxdma_mailbox), |
| 4312 | rp->mbox, rp->mbox_dma); |
| 4313 | rp->mbox = NULL; |
| 4314 | } |
| 4315 | if (rp->rcr) { |
| 4316 | np->ops->free_coherent(np->device, |
| 4317 | MAX_RCR_RING_SIZE * sizeof(__le64), |
| 4318 | rp->rcr, rp->rcr_dma); |
| 4319 | rp->rcr = NULL; |
| 4320 | rp->rcr_table_size = 0; |
| 4321 | rp->rcr_index = 0; |
| 4322 | } |
| 4323 | if (rp->rbr) { |
| 4324 | niu_rbr_free(np, rp); |
| 4325 | |
| 4326 | np->ops->free_coherent(np->device, |
| 4327 | MAX_RBR_RING_SIZE * sizeof(__le32), |
| 4328 | rp->rbr, rp->rbr_dma); |
| 4329 | rp->rbr = NULL; |
| 4330 | rp->rbr_table_size = 0; |
| 4331 | rp->rbr_index = 0; |
| 4332 | } |
| 4333 | kfree(rp->rxhash); |
| 4334 | rp->rxhash = NULL; |
| 4335 | } |
| 4336 | |
| 4337 | static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp) |
| 4338 | { |
| 4339 | if (rp->mbox) { |
| 4340 | np->ops->free_coherent(np->device, |
| 4341 | sizeof(struct txdma_mailbox), |
| 4342 | rp->mbox, rp->mbox_dma); |
| 4343 | rp->mbox = NULL; |
| 4344 | } |
| 4345 | if (rp->descr) { |
| 4346 | int i; |
| 4347 | |
| 4348 | for (i = 0; i < MAX_TX_RING_SIZE; i++) { |
| 4349 | if (rp->tx_buffs[i].skb) |
| 4350 | (void) release_tx_packet(np, rp, i); |
| 4351 | } |
| 4352 | |
| 4353 | np->ops->free_coherent(np->device, |
| 4354 | MAX_TX_RING_SIZE * sizeof(__le64), |
| 4355 | rp->descr, rp->descr_dma); |
| 4356 | rp->descr = NULL; |
| 4357 | rp->pending = 0; |
| 4358 | rp->prod = 0; |
| 4359 | rp->cons = 0; |
| 4360 | rp->wrap_bit = 0; |
| 4361 | } |
| 4362 | } |
| 4363 | |
| 4364 | static void niu_free_channels(struct niu *np) |
| 4365 | { |
| 4366 | int i; |
| 4367 | |
| 4368 | if (np->rx_rings) { |
| 4369 | for (i = 0; i < np->num_rx_rings; i++) { |
| 4370 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 4371 | |
| 4372 | niu_free_rx_ring_info(np, rp); |
| 4373 | } |
| 4374 | kfree(np->rx_rings); |
| 4375 | np->rx_rings = NULL; |
| 4376 | np->num_rx_rings = 0; |
| 4377 | } |
| 4378 | |
| 4379 | if (np->tx_rings) { |
| 4380 | for (i = 0; i < np->num_tx_rings; i++) { |
| 4381 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 4382 | |
| 4383 | niu_free_tx_ring_info(np, rp); |
| 4384 | } |
| 4385 | kfree(np->tx_rings); |
| 4386 | np->tx_rings = NULL; |
| 4387 | np->num_tx_rings = 0; |
| 4388 | } |
| 4389 | } |
| 4390 | |
| 4391 | static int niu_alloc_rx_ring_info(struct niu *np, |
| 4392 | struct rx_ring_info *rp) |
| 4393 | { |
| 4394 | BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64); |
| 4395 | |
| 4396 | rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *), |
| 4397 | GFP_KERNEL); |
| 4398 | if (!rp->rxhash) |
| 4399 | return -ENOMEM; |
| 4400 | |
| 4401 | rp->mbox = np->ops->alloc_coherent(np->device, |
| 4402 | sizeof(struct rxdma_mailbox), |
| 4403 | &rp->mbox_dma, GFP_KERNEL); |
| 4404 | if (!rp->mbox) |
| 4405 | return -ENOMEM; |
| 4406 | if ((unsigned long)rp->mbox & (64UL - 1)) { |
| 4407 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " |
| 4408 | "RXDMA mailbox %p\n", np->dev->name, rp->mbox); |
| 4409 | return -EINVAL; |
| 4410 | } |
| 4411 | |
| 4412 | rp->rcr = np->ops->alloc_coherent(np->device, |
| 4413 | MAX_RCR_RING_SIZE * sizeof(__le64), |
| 4414 | &rp->rcr_dma, GFP_KERNEL); |
| 4415 | if (!rp->rcr) |
| 4416 | return -ENOMEM; |
| 4417 | if ((unsigned long)rp->rcr & (64UL - 1)) { |
| 4418 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " |
| 4419 | "RXDMA RCR table %p\n", np->dev->name, rp->rcr); |
| 4420 | return -EINVAL; |
| 4421 | } |
| 4422 | rp->rcr_table_size = MAX_RCR_RING_SIZE; |
| 4423 | rp->rcr_index = 0; |
| 4424 | |
| 4425 | rp->rbr = np->ops->alloc_coherent(np->device, |
| 4426 | MAX_RBR_RING_SIZE * sizeof(__le32), |
| 4427 | &rp->rbr_dma, GFP_KERNEL); |
| 4428 | if (!rp->rbr) |
| 4429 | return -ENOMEM; |
| 4430 | if ((unsigned long)rp->rbr & (64UL - 1)) { |
| 4431 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " |
| 4432 | "RXDMA RBR table %p\n", np->dev->name, rp->rbr); |
| 4433 | return -EINVAL; |
| 4434 | } |
| 4435 | rp->rbr_table_size = MAX_RBR_RING_SIZE; |
| 4436 | rp->rbr_index = 0; |
| 4437 | rp->rbr_pending = 0; |
| 4438 | |
| 4439 | return 0; |
| 4440 | } |
| 4441 | |
| 4442 | static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp) |
| 4443 | { |
| 4444 | int mtu = np->dev->mtu; |
| 4445 | |
| 4446 | /* These values are recommended by the HW designers for fair |
| 4447 | * utilization of DRR amongst the rings. |
| 4448 | */ |
| 4449 | rp->max_burst = mtu + 32; |
| 4450 | if (rp->max_burst > 4096) |
| 4451 | rp->max_burst = 4096; |
| 4452 | } |
| 4453 | |
| 4454 | static int niu_alloc_tx_ring_info(struct niu *np, |
| 4455 | struct tx_ring_info *rp) |
| 4456 | { |
| 4457 | BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64); |
| 4458 | |
| 4459 | rp->mbox = np->ops->alloc_coherent(np->device, |
| 4460 | sizeof(struct txdma_mailbox), |
| 4461 | &rp->mbox_dma, GFP_KERNEL); |
| 4462 | if (!rp->mbox) |
| 4463 | return -ENOMEM; |
| 4464 | if ((unsigned long)rp->mbox & (64UL - 1)) { |
| 4465 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " |
| 4466 | "TXDMA mailbox %p\n", np->dev->name, rp->mbox); |
| 4467 | return -EINVAL; |
| 4468 | } |
| 4469 | |
| 4470 | rp->descr = np->ops->alloc_coherent(np->device, |
| 4471 | MAX_TX_RING_SIZE * sizeof(__le64), |
| 4472 | &rp->descr_dma, GFP_KERNEL); |
| 4473 | if (!rp->descr) |
| 4474 | return -ENOMEM; |
| 4475 | if ((unsigned long)rp->descr & (64UL - 1)) { |
| 4476 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " |
| 4477 | "TXDMA descr table %p\n", np->dev->name, rp->descr); |
| 4478 | return -EINVAL; |
| 4479 | } |
| 4480 | |
| 4481 | rp->pending = MAX_TX_RING_SIZE; |
| 4482 | rp->prod = 0; |
| 4483 | rp->cons = 0; |
| 4484 | rp->wrap_bit = 0; |
| 4485 | |
| 4486 | /* XXX make these configurable... XXX */ |
| 4487 | rp->mark_freq = rp->pending / 4; |
| 4488 | |
| 4489 | niu_set_max_burst(np, rp); |
| 4490 | |
| 4491 | return 0; |
| 4492 | } |
| 4493 | |
| 4494 | static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp) |
| 4495 | { |
| 4496 | u16 bss; |
| 4497 | |
| 4498 | bss = min(PAGE_SHIFT, 15); |
| 4499 | |
| 4500 | rp->rbr_block_size = 1 << bss; |
| 4501 | rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss); |
| 4502 | |
| 4503 | rp->rbr_sizes[0] = 256; |
| 4504 | rp->rbr_sizes[1] = 1024; |
| 4505 | if (np->dev->mtu > ETH_DATA_LEN) { |
| 4506 | switch (PAGE_SIZE) { |
| 4507 | case 4 * 1024: |
| 4508 | rp->rbr_sizes[2] = 4096; |
| 4509 | break; |
| 4510 | |
| 4511 | default: |
| 4512 | rp->rbr_sizes[2] = 8192; |
| 4513 | break; |
| 4514 | } |
| 4515 | } else { |
| 4516 | rp->rbr_sizes[2] = 2048; |
| 4517 | } |
| 4518 | rp->rbr_sizes[3] = rp->rbr_block_size; |
| 4519 | } |
| 4520 | |
| 4521 | static int niu_alloc_channels(struct niu *np) |
| 4522 | { |
| 4523 | struct niu_parent *parent = np->parent; |
| 4524 | int first_rx_channel, first_tx_channel; |
| 4525 | int i, port, err; |
| 4526 | |
| 4527 | port = np->port; |
| 4528 | first_rx_channel = first_tx_channel = 0; |
| 4529 | for (i = 0; i < port; i++) { |
| 4530 | first_rx_channel += parent->rxchan_per_port[i]; |
| 4531 | first_tx_channel += parent->txchan_per_port[i]; |
| 4532 | } |
| 4533 | |
| 4534 | np->num_rx_rings = parent->rxchan_per_port[port]; |
| 4535 | np->num_tx_rings = parent->txchan_per_port[port]; |
| 4536 | |
| 4537 | np->dev->real_num_tx_queues = np->num_tx_rings; |
| 4538 | |
| 4539 | np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info), |
| 4540 | GFP_KERNEL); |
| 4541 | err = -ENOMEM; |
| 4542 | if (!np->rx_rings) |
| 4543 | goto out_err; |
| 4544 | |
| 4545 | for (i = 0; i < np->num_rx_rings; i++) { |
| 4546 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 4547 | |
| 4548 | rp->np = np; |
| 4549 | rp->rx_channel = first_rx_channel + i; |
| 4550 | |
| 4551 | err = niu_alloc_rx_ring_info(np, rp); |
| 4552 | if (err) |
| 4553 | goto out_err; |
| 4554 | |
| 4555 | niu_size_rbr(np, rp); |
| 4556 | |
| 4557 | /* XXX better defaults, configurable, etc... XXX */ |
| 4558 | rp->nonsyn_window = 64; |
| 4559 | rp->nonsyn_threshold = rp->rcr_table_size - 64; |
| 4560 | rp->syn_window = 64; |
| 4561 | rp->syn_threshold = rp->rcr_table_size - 64; |
| 4562 | rp->rcr_pkt_threshold = 16; |
| 4563 | rp->rcr_timeout = 8; |
| 4564 | rp->rbr_kick_thresh = RBR_REFILL_MIN; |
| 4565 | if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page) |
| 4566 | rp->rbr_kick_thresh = rp->rbr_blocks_per_page; |
| 4567 | |
| 4568 | err = niu_rbr_fill(np, rp, GFP_KERNEL); |
| 4569 | if (err) |
| 4570 | return err; |
| 4571 | } |
| 4572 | |
| 4573 | np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info), |
| 4574 | GFP_KERNEL); |
| 4575 | err = -ENOMEM; |
| 4576 | if (!np->tx_rings) |
| 4577 | goto out_err; |
| 4578 | |
| 4579 | for (i = 0; i < np->num_tx_rings; i++) { |
| 4580 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 4581 | |
| 4582 | rp->np = np; |
| 4583 | rp->tx_channel = first_tx_channel + i; |
| 4584 | |
| 4585 | err = niu_alloc_tx_ring_info(np, rp); |
| 4586 | if (err) |
| 4587 | goto out_err; |
| 4588 | } |
| 4589 | |
| 4590 | return 0; |
| 4591 | |
| 4592 | out_err: |
| 4593 | niu_free_channels(np); |
| 4594 | return err; |
| 4595 | } |
| 4596 | |
| 4597 | static int niu_tx_cs_sng_poll(struct niu *np, int channel) |
| 4598 | { |
| 4599 | int limit = 1000; |
| 4600 | |
| 4601 | while (--limit > 0) { |
| 4602 | u64 val = nr64(TX_CS(channel)); |
| 4603 | if (val & TX_CS_SNG_STATE) |
| 4604 | return 0; |
| 4605 | } |
| 4606 | return -ENODEV; |
| 4607 | } |
| 4608 | |
| 4609 | static int niu_tx_channel_stop(struct niu *np, int channel) |
| 4610 | { |
| 4611 | u64 val = nr64(TX_CS(channel)); |
| 4612 | |
| 4613 | val |= TX_CS_STOP_N_GO; |
| 4614 | nw64(TX_CS(channel), val); |
| 4615 | |
| 4616 | return niu_tx_cs_sng_poll(np, channel); |
| 4617 | } |
| 4618 | |
| 4619 | static int niu_tx_cs_reset_poll(struct niu *np, int channel) |
| 4620 | { |
| 4621 | int limit = 1000; |
| 4622 | |
| 4623 | while (--limit > 0) { |
| 4624 | u64 val = nr64(TX_CS(channel)); |
| 4625 | if (!(val & TX_CS_RST)) |
| 4626 | return 0; |
| 4627 | } |
| 4628 | return -ENODEV; |
| 4629 | } |
| 4630 | |
| 4631 | static int niu_tx_channel_reset(struct niu *np, int channel) |
| 4632 | { |
| 4633 | u64 val = nr64(TX_CS(channel)); |
| 4634 | int err; |
| 4635 | |
| 4636 | val |= TX_CS_RST; |
| 4637 | nw64(TX_CS(channel), val); |
| 4638 | |
| 4639 | err = niu_tx_cs_reset_poll(np, channel); |
| 4640 | if (!err) |
| 4641 | nw64(TX_RING_KICK(channel), 0); |
| 4642 | |
| 4643 | return err; |
| 4644 | } |
| 4645 | |
| 4646 | static int niu_tx_channel_lpage_init(struct niu *np, int channel) |
| 4647 | { |
| 4648 | u64 val; |
| 4649 | |
| 4650 | nw64(TX_LOG_MASK1(channel), 0); |
| 4651 | nw64(TX_LOG_VAL1(channel), 0); |
| 4652 | nw64(TX_LOG_MASK2(channel), 0); |
| 4653 | nw64(TX_LOG_VAL2(channel), 0); |
| 4654 | nw64(TX_LOG_PAGE_RELO1(channel), 0); |
| 4655 | nw64(TX_LOG_PAGE_RELO2(channel), 0); |
| 4656 | nw64(TX_LOG_PAGE_HDL(channel), 0); |
| 4657 | |
| 4658 | val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT; |
| 4659 | val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1); |
| 4660 | nw64(TX_LOG_PAGE_VLD(channel), val); |
| 4661 | |
| 4662 | /* XXX TXDMA 32bit mode? XXX */ |
| 4663 | |
| 4664 | return 0; |
| 4665 | } |
| 4666 | |
| 4667 | static void niu_txc_enable_port(struct niu *np, int on) |
| 4668 | { |
| 4669 | unsigned long flags; |
| 4670 | u64 val, mask; |
| 4671 | |
| 4672 | niu_lock_parent(np, flags); |
| 4673 | val = nr64(TXC_CONTROL); |
| 4674 | mask = (u64)1 << np->port; |
| 4675 | if (on) { |
| 4676 | val |= TXC_CONTROL_ENABLE | mask; |
| 4677 | } else { |
| 4678 | val &= ~mask; |
| 4679 | if ((val & ~TXC_CONTROL_ENABLE) == 0) |
| 4680 | val &= ~TXC_CONTROL_ENABLE; |
| 4681 | } |
| 4682 | nw64(TXC_CONTROL, val); |
| 4683 | niu_unlock_parent(np, flags); |
| 4684 | } |
| 4685 | |
| 4686 | static void niu_txc_set_imask(struct niu *np, u64 imask) |
| 4687 | { |
| 4688 | unsigned long flags; |
| 4689 | u64 val; |
| 4690 | |
| 4691 | niu_lock_parent(np, flags); |
| 4692 | val = nr64(TXC_INT_MASK); |
| 4693 | val &= ~TXC_INT_MASK_VAL(np->port); |
| 4694 | val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port)); |
| 4695 | niu_unlock_parent(np, flags); |
| 4696 | } |
| 4697 | |
| 4698 | static void niu_txc_port_dma_enable(struct niu *np, int on) |
| 4699 | { |
| 4700 | u64 val = 0; |
| 4701 | |
| 4702 | if (on) { |
| 4703 | int i; |
| 4704 | |
| 4705 | for (i = 0; i < np->num_tx_rings; i++) |
| 4706 | val |= (1 << np->tx_rings[i].tx_channel); |
| 4707 | } |
| 4708 | nw64(TXC_PORT_DMA(np->port), val); |
| 4709 | } |
| 4710 | |
| 4711 | static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp) |
| 4712 | { |
| 4713 | int err, channel = rp->tx_channel; |
| 4714 | u64 val, ring_len; |
| 4715 | |
| 4716 | err = niu_tx_channel_stop(np, channel); |
| 4717 | if (err) |
| 4718 | return err; |
| 4719 | |
| 4720 | err = niu_tx_channel_reset(np, channel); |
| 4721 | if (err) |
| 4722 | return err; |
| 4723 | |
| 4724 | err = niu_tx_channel_lpage_init(np, channel); |
| 4725 | if (err) |
| 4726 | return err; |
| 4727 | |
| 4728 | nw64(TXC_DMA_MAX(channel), rp->max_burst); |
| 4729 | nw64(TX_ENT_MSK(channel), 0); |
| 4730 | |
| 4731 | if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE | |
| 4732 | TX_RNG_CFIG_STADDR)) { |
| 4733 | dev_err(np->device, PFX "%s: TX ring channel %d " |
| 4734 | "DMA addr (%llx) is not aligned.\n", |
| 4735 | np->dev->name, channel, |
| 4736 | (unsigned long long) rp->descr_dma); |
| 4737 | return -EINVAL; |
| 4738 | } |
| 4739 | |
| 4740 | /* The length field in TX_RNG_CFIG is measured in 64-byte |
| 4741 | * blocks. rp->pending is the number of TX descriptors in |
| 4742 | * our ring, 8 bytes each, thus we divide by 8 bytes more |
| 4743 | * to get the proper value the chip wants. |
| 4744 | */ |
| 4745 | ring_len = (rp->pending / 8); |
| 4746 | |
| 4747 | val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) | |
| 4748 | rp->descr_dma); |
| 4749 | nw64(TX_RNG_CFIG(channel), val); |
| 4750 | |
| 4751 | if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) || |
| 4752 | ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) { |
| 4753 | dev_err(np->device, PFX "%s: TX ring channel %d " |
| 4754 | "MBOX addr (%llx) is has illegal bits.\n", |
| 4755 | np->dev->name, channel, |
| 4756 | (unsigned long long) rp->mbox_dma); |
| 4757 | return -EINVAL; |
| 4758 | } |
| 4759 | nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32); |
| 4760 | nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR); |
| 4761 | |
| 4762 | nw64(TX_CS(channel), 0); |
| 4763 | |
| 4764 | rp->last_pkt_cnt = 0; |
| 4765 | |
| 4766 | return 0; |
| 4767 | } |
| 4768 | |
| 4769 | static void niu_init_rdc_groups(struct niu *np) |
| 4770 | { |
| 4771 | struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port]; |
| 4772 | int i, first_table_num = tp->first_table_num; |
| 4773 | |
| 4774 | for (i = 0; i < tp->num_tables; i++) { |
| 4775 | struct rdc_table *tbl = &tp->tables[i]; |
| 4776 | int this_table = first_table_num + i; |
| 4777 | int slot; |
| 4778 | |
| 4779 | for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) |
| 4780 | nw64(RDC_TBL(this_table, slot), |
| 4781 | tbl->rxdma_channel[slot]); |
| 4782 | } |
| 4783 | |
| 4784 | nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]); |
| 4785 | } |
| 4786 | |
| 4787 | static void niu_init_drr_weight(struct niu *np) |
| 4788 | { |
| 4789 | int type = phy_decode(np->parent->port_phy, np->port); |
| 4790 | u64 val; |
| 4791 | |
| 4792 | switch (type) { |
| 4793 | case PORT_TYPE_10G: |
| 4794 | val = PT_DRR_WEIGHT_DEFAULT_10G; |
| 4795 | break; |
| 4796 | |
| 4797 | case PORT_TYPE_1G: |
| 4798 | default: |
| 4799 | val = PT_DRR_WEIGHT_DEFAULT_1G; |
| 4800 | break; |
| 4801 | } |
| 4802 | nw64(PT_DRR_WT(np->port), val); |
| 4803 | } |
| 4804 | |
| 4805 | static int niu_init_hostinfo(struct niu *np) |
| 4806 | { |
| 4807 | struct niu_parent *parent = np->parent; |
| 4808 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; |
| 4809 | int i, err, num_alt = niu_num_alt_addr(np); |
| 4810 | int first_rdc_table = tp->first_table_num; |
| 4811 | |
| 4812 | err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); |
| 4813 | if (err) |
| 4814 | return err; |
| 4815 | |
| 4816 | err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); |
| 4817 | if (err) |
| 4818 | return err; |
| 4819 | |
| 4820 | for (i = 0; i < num_alt; i++) { |
| 4821 | err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1); |
| 4822 | if (err) |
| 4823 | return err; |
| 4824 | } |
| 4825 | |
| 4826 | return 0; |
| 4827 | } |
| 4828 | |
| 4829 | static int niu_rx_channel_reset(struct niu *np, int channel) |
| 4830 | { |
| 4831 | return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel), |
| 4832 | RXDMA_CFIG1_RST, 1000, 10, |
| 4833 | "RXDMA_CFIG1"); |
| 4834 | } |
| 4835 | |
| 4836 | static int niu_rx_channel_lpage_init(struct niu *np, int channel) |
| 4837 | { |
| 4838 | u64 val; |
| 4839 | |
| 4840 | nw64(RX_LOG_MASK1(channel), 0); |
| 4841 | nw64(RX_LOG_VAL1(channel), 0); |
| 4842 | nw64(RX_LOG_MASK2(channel), 0); |
| 4843 | nw64(RX_LOG_VAL2(channel), 0); |
| 4844 | nw64(RX_LOG_PAGE_RELO1(channel), 0); |
| 4845 | nw64(RX_LOG_PAGE_RELO2(channel), 0); |
| 4846 | nw64(RX_LOG_PAGE_HDL(channel), 0); |
| 4847 | |
| 4848 | val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT; |
| 4849 | val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1); |
| 4850 | nw64(RX_LOG_PAGE_VLD(channel), val); |
| 4851 | |
| 4852 | return 0; |
| 4853 | } |
| 4854 | |
| 4855 | static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp) |
| 4856 | { |
| 4857 | u64 val; |
| 4858 | |
| 4859 | val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) | |
| 4860 | ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) | |
| 4861 | ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) | |
| 4862 | ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT)); |
| 4863 | nw64(RDC_RED_PARA(rp->rx_channel), val); |
| 4864 | } |
| 4865 | |
| 4866 | static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret) |
| 4867 | { |
| 4868 | u64 val = 0; |
| 4869 | |
| 4870 | *ret = 0; |
| 4871 | switch (rp->rbr_block_size) { |
| 4872 | case 4 * 1024: |
| 4873 | val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT); |
| 4874 | break; |
| 4875 | case 8 * 1024: |
| 4876 | val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT); |
| 4877 | break; |
| 4878 | case 16 * 1024: |
| 4879 | val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT); |
| 4880 | break; |
| 4881 | case 32 * 1024: |
| 4882 | val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT); |
| 4883 | break; |
| 4884 | default: |
| 4885 | return -EINVAL; |
| 4886 | } |
| 4887 | val |= RBR_CFIG_B_VLD2; |
| 4888 | switch (rp->rbr_sizes[2]) { |
| 4889 | case 2 * 1024: |
| 4890 | val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT); |
| 4891 | break; |
| 4892 | case 4 * 1024: |
| 4893 | val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT); |
| 4894 | break; |
| 4895 | case 8 * 1024: |
| 4896 | val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT); |
| 4897 | break; |
| 4898 | case 16 * 1024: |
| 4899 | val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT); |
| 4900 | break; |
| 4901 | |
| 4902 | default: |
| 4903 | return -EINVAL; |
| 4904 | } |
| 4905 | val |= RBR_CFIG_B_VLD1; |
| 4906 | switch (rp->rbr_sizes[1]) { |
| 4907 | case 1 * 1024: |
| 4908 | val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT); |
| 4909 | break; |
| 4910 | case 2 * 1024: |
| 4911 | val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT); |
| 4912 | break; |
| 4913 | case 4 * 1024: |
| 4914 | val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT); |
| 4915 | break; |
| 4916 | case 8 * 1024: |
| 4917 | val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT); |
| 4918 | break; |
| 4919 | |
| 4920 | default: |
| 4921 | return -EINVAL; |
| 4922 | } |
| 4923 | val |= RBR_CFIG_B_VLD0; |
| 4924 | switch (rp->rbr_sizes[0]) { |
| 4925 | case 256: |
| 4926 | val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT); |
| 4927 | break; |
| 4928 | case 512: |
| 4929 | val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT); |
| 4930 | break; |
| 4931 | case 1 * 1024: |
| 4932 | val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT); |
| 4933 | break; |
| 4934 | case 2 * 1024: |
| 4935 | val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT); |
| 4936 | break; |
| 4937 | |
| 4938 | default: |
| 4939 | return -EINVAL; |
| 4940 | } |
| 4941 | |
| 4942 | *ret = val; |
| 4943 | return 0; |
| 4944 | } |
| 4945 | |
| 4946 | static int niu_enable_rx_channel(struct niu *np, int channel, int on) |
| 4947 | { |
| 4948 | u64 val = nr64(RXDMA_CFIG1(channel)); |
| 4949 | int limit; |
| 4950 | |
| 4951 | if (on) |
| 4952 | val |= RXDMA_CFIG1_EN; |
| 4953 | else |
| 4954 | val &= ~RXDMA_CFIG1_EN; |
| 4955 | nw64(RXDMA_CFIG1(channel), val); |
| 4956 | |
| 4957 | limit = 1000; |
| 4958 | while (--limit > 0) { |
| 4959 | if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST) |
| 4960 | break; |
| 4961 | udelay(10); |
| 4962 | } |
| 4963 | if (limit <= 0) |
| 4964 | return -ENODEV; |
| 4965 | return 0; |
| 4966 | } |
| 4967 | |
| 4968 | static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp) |
| 4969 | { |
| 4970 | int err, channel = rp->rx_channel; |
| 4971 | u64 val; |
| 4972 | |
| 4973 | err = niu_rx_channel_reset(np, channel); |
| 4974 | if (err) |
| 4975 | return err; |
| 4976 | |
| 4977 | err = niu_rx_channel_lpage_init(np, channel); |
| 4978 | if (err) |
| 4979 | return err; |
| 4980 | |
| 4981 | niu_rx_channel_wred_init(np, rp); |
| 4982 | |
| 4983 | nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY); |
| 4984 | nw64(RX_DMA_CTL_STAT(channel), |
| 4985 | (RX_DMA_CTL_STAT_MEX | |
| 4986 | RX_DMA_CTL_STAT_RCRTHRES | |
| 4987 | RX_DMA_CTL_STAT_RCRTO | |
| 4988 | RX_DMA_CTL_STAT_RBR_EMPTY)); |
| 4989 | nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32); |
| 4990 | nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0)); |
| 4991 | nw64(RBR_CFIG_A(channel), |
| 4992 | ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) | |
| 4993 | (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR))); |
| 4994 | err = niu_compute_rbr_cfig_b(rp, &val); |
| 4995 | if (err) |
| 4996 | return err; |
| 4997 | nw64(RBR_CFIG_B(channel), val); |
| 4998 | nw64(RCRCFIG_A(channel), |
| 4999 | ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) | |
| 5000 | (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR))); |
| 5001 | nw64(RCRCFIG_B(channel), |
| 5002 | ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) | |
| 5003 | RCRCFIG_B_ENTOUT | |
| 5004 | ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT)); |
| 5005 | |
| 5006 | err = niu_enable_rx_channel(np, channel, 1); |
| 5007 | if (err) |
| 5008 | return err; |
| 5009 | |
| 5010 | nw64(RBR_KICK(channel), rp->rbr_index); |
| 5011 | |
| 5012 | val = nr64(RX_DMA_CTL_STAT(channel)); |
| 5013 | val |= RX_DMA_CTL_STAT_RBR_EMPTY; |
| 5014 | nw64(RX_DMA_CTL_STAT(channel), val); |
| 5015 | |
| 5016 | return 0; |
| 5017 | } |
| 5018 | |
| 5019 | static int niu_init_rx_channels(struct niu *np) |
| 5020 | { |
| 5021 | unsigned long flags; |
| 5022 | u64 seed = jiffies_64; |
| 5023 | int err, i; |
| 5024 | |
| 5025 | niu_lock_parent(np, flags); |
| 5026 | nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider); |
| 5027 | nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL)); |
| 5028 | niu_unlock_parent(np, flags); |
| 5029 | |
| 5030 | /* XXX RXDMA 32bit mode? XXX */ |
| 5031 | |
| 5032 | niu_init_rdc_groups(np); |
| 5033 | niu_init_drr_weight(np); |
| 5034 | |
| 5035 | err = niu_init_hostinfo(np); |
| 5036 | if (err) |
| 5037 | return err; |
| 5038 | |
| 5039 | for (i = 0; i < np->num_rx_rings; i++) { |
| 5040 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 5041 | |
| 5042 | err = niu_init_one_rx_channel(np, rp); |
| 5043 | if (err) |
| 5044 | return err; |
| 5045 | } |
| 5046 | |
| 5047 | return 0; |
| 5048 | } |
| 5049 | |
| 5050 | static int niu_set_ip_frag_rule(struct niu *np) |
| 5051 | { |
| 5052 | struct niu_parent *parent = np->parent; |
| 5053 | struct niu_classifier *cp = &np->clas; |
| 5054 | struct niu_tcam_entry *tp; |
| 5055 | int index, err; |
| 5056 | |
| 5057 | index = cp->tcam_top; |
| 5058 | tp = &parent->tcam[index]; |
| 5059 | |
| 5060 | /* Note that the noport bit is the same in both ipv4 and |
| 5061 | * ipv6 format TCAM entries. |
| 5062 | */ |
| 5063 | memset(tp, 0, sizeof(*tp)); |
| 5064 | tp->key[1] = TCAM_V4KEY1_NOPORT; |
| 5065 | tp->key_mask[1] = TCAM_V4KEY1_NOPORT; |
| 5066 | tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | |
| 5067 | ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT)); |
| 5068 | err = tcam_write(np, index, tp->key, tp->key_mask); |
| 5069 | if (err) |
| 5070 | return err; |
| 5071 | err = tcam_assoc_write(np, index, tp->assoc_data); |
| 5072 | if (err) |
| 5073 | return err; |
| 5074 | tp->valid = 1; |
| 5075 | cp->tcam_valid_entries++; |
| 5076 | |
| 5077 | return 0; |
| 5078 | } |
| 5079 | |
| 5080 | static int niu_init_classifier_hw(struct niu *np) |
| 5081 | { |
| 5082 | struct niu_parent *parent = np->parent; |
| 5083 | struct niu_classifier *cp = &np->clas; |
| 5084 | int i, err; |
| 5085 | |
| 5086 | nw64(H1POLY, cp->h1_init); |
| 5087 | nw64(H2POLY, cp->h2_init); |
| 5088 | |
| 5089 | err = niu_init_hostinfo(np); |
| 5090 | if (err) |
| 5091 | return err; |
| 5092 | |
| 5093 | for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) { |
| 5094 | struct niu_vlan_rdc *vp = &cp->vlan_mappings[i]; |
| 5095 | |
| 5096 | vlan_tbl_write(np, i, np->port, |
| 5097 | vp->vlan_pref, vp->rdc_num); |
| 5098 | } |
| 5099 | |
| 5100 | for (i = 0; i < cp->num_alt_mac_mappings; i++) { |
| 5101 | struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i]; |
| 5102 | |
| 5103 | err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num, |
| 5104 | ap->rdc_num, ap->mac_pref); |
| 5105 | if (err) |
| 5106 | return err; |
| 5107 | } |
| 5108 | |
| 5109 | for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { |
| 5110 | int index = i - CLASS_CODE_USER_PROG1; |
| 5111 | |
| 5112 | err = niu_set_tcam_key(np, i, parent->tcam_key[index]); |
| 5113 | if (err) |
| 5114 | return err; |
| 5115 | err = niu_set_flow_key(np, i, parent->flow_key[index]); |
| 5116 | if (err) |
| 5117 | return err; |
| 5118 | } |
| 5119 | |
| 5120 | err = niu_set_ip_frag_rule(np); |
| 5121 | if (err) |
| 5122 | return err; |
| 5123 | |
| 5124 | tcam_enable(np, 1); |
| 5125 | |
| 5126 | return 0; |
| 5127 | } |
| 5128 | |
| 5129 | static int niu_zcp_write(struct niu *np, int index, u64 *data) |
| 5130 | { |
| 5131 | nw64(ZCP_RAM_DATA0, data[0]); |
| 5132 | nw64(ZCP_RAM_DATA1, data[1]); |
| 5133 | nw64(ZCP_RAM_DATA2, data[2]); |
| 5134 | nw64(ZCP_RAM_DATA3, data[3]); |
| 5135 | nw64(ZCP_RAM_DATA4, data[4]); |
| 5136 | nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL); |
| 5137 | nw64(ZCP_RAM_ACC, |
| 5138 | (ZCP_RAM_ACC_WRITE | |
| 5139 | (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | |
| 5140 | (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); |
| 5141 | |
| 5142 | return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, |
| 5143 | 1000, 100); |
| 5144 | } |
| 5145 | |
| 5146 | static int niu_zcp_read(struct niu *np, int index, u64 *data) |
| 5147 | { |
| 5148 | int err; |
| 5149 | |
| 5150 | err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, |
| 5151 | 1000, 100); |
| 5152 | if (err) { |
| 5153 | dev_err(np->device, PFX "%s: ZCP read busy won't clear, " |
| 5154 | "ZCP_RAM_ACC[%llx]\n", np->dev->name, |
| 5155 | (unsigned long long) nr64(ZCP_RAM_ACC)); |
| 5156 | return err; |
| 5157 | } |
| 5158 | |
| 5159 | nw64(ZCP_RAM_ACC, |
| 5160 | (ZCP_RAM_ACC_READ | |
| 5161 | (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | |
| 5162 | (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); |
| 5163 | |
| 5164 | err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, |
| 5165 | 1000, 100); |
| 5166 | if (err) { |
| 5167 | dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, " |
| 5168 | "ZCP_RAM_ACC[%llx]\n", np->dev->name, |
| 5169 | (unsigned long long) nr64(ZCP_RAM_ACC)); |
| 5170 | return err; |
| 5171 | } |
| 5172 | |
| 5173 | data[0] = nr64(ZCP_RAM_DATA0); |
| 5174 | data[1] = nr64(ZCP_RAM_DATA1); |
| 5175 | data[2] = nr64(ZCP_RAM_DATA2); |
| 5176 | data[3] = nr64(ZCP_RAM_DATA3); |
| 5177 | data[4] = nr64(ZCP_RAM_DATA4); |
| 5178 | |
| 5179 | return 0; |
| 5180 | } |
| 5181 | |
| 5182 | static void niu_zcp_cfifo_reset(struct niu *np) |
| 5183 | { |
| 5184 | u64 val = nr64(RESET_CFIFO); |
| 5185 | |
| 5186 | val |= RESET_CFIFO_RST(np->port); |
| 5187 | nw64(RESET_CFIFO, val); |
| 5188 | udelay(10); |
| 5189 | |
| 5190 | val &= ~RESET_CFIFO_RST(np->port); |
| 5191 | nw64(RESET_CFIFO, val); |
| 5192 | } |
| 5193 | |
| 5194 | static int niu_init_zcp(struct niu *np) |
| 5195 | { |
| 5196 | u64 data[5], rbuf[5]; |
| 5197 | int i, max, err; |
| 5198 | |
| 5199 | if (np->parent->plat_type != PLAT_TYPE_NIU) { |
| 5200 | if (np->port == 0 || np->port == 1) |
| 5201 | max = ATLAS_P0_P1_CFIFO_ENTRIES; |
| 5202 | else |
| 5203 | max = ATLAS_P2_P3_CFIFO_ENTRIES; |
| 5204 | } else |
| 5205 | max = NIU_CFIFO_ENTRIES; |
| 5206 | |
| 5207 | data[0] = 0; |
| 5208 | data[1] = 0; |
| 5209 | data[2] = 0; |
| 5210 | data[3] = 0; |
| 5211 | data[4] = 0; |
| 5212 | |
| 5213 | for (i = 0; i < max; i++) { |
| 5214 | err = niu_zcp_write(np, i, data); |
| 5215 | if (err) |
| 5216 | return err; |
| 5217 | err = niu_zcp_read(np, i, rbuf); |
| 5218 | if (err) |
| 5219 | return err; |
| 5220 | } |
| 5221 | |
| 5222 | niu_zcp_cfifo_reset(np); |
| 5223 | nw64(CFIFO_ECC(np->port), 0); |
| 5224 | nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL); |
| 5225 | (void) nr64(ZCP_INT_STAT); |
| 5226 | nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL); |
| 5227 | |
| 5228 | return 0; |
| 5229 | } |
| 5230 | |
| 5231 | static void niu_ipp_write(struct niu *np, int index, u64 *data) |
| 5232 | { |
| 5233 | u64 val = nr64_ipp(IPP_CFIG); |
| 5234 | |
| 5235 | nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W); |
| 5236 | nw64_ipp(IPP_DFIFO_WR_PTR, index); |
| 5237 | nw64_ipp(IPP_DFIFO_WR0, data[0]); |
| 5238 | nw64_ipp(IPP_DFIFO_WR1, data[1]); |
| 5239 | nw64_ipp(IPP_DFIFO_WR2, data[2]); |
| 5240 | nw64_ipp(IPP_DFIFO_WR3, data[3]); |
| 5241 | nw64_ipp(IPP_DFIFO_WR4, data[4]); |
| 5242 | nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W); |
| 5243 | } |
| 5244 | |
| 5245 | static void niu_ipp_read(struct niu *np, int index, u64 *data) |
| 5246 | { |
| 5247 | nw64_ipp(IPP_DFIFO_RD_PTR, index); |
| 5248 | data[0] = nr64_ipp(IPP_DFIFO_RD0); |
| 5249 | data[1] = nr64_ipp(IPP_DFIFO_RD1); |
| 5250 | data[2] = nr64_ipp(IPP_DFIFO_RD2); |
| 5251 | data[3] = nr64_ipp(IPP_DFIFO_RD3); |
| 5252 | data[4] = nr64_ipp(IPP_DFIFO_RD4); |
| 5253 | } |
| 5254 | |
| 5255 | static int niu_ipp_reset(struct niu *np) |
| 5256 | { |
| 5257 | return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST, |
| 5258 | 1000, 100, "IPP_CFIG"); |
| 5259 | } |
| 5260 | |
| 5261 | static int niu_init_ipp(struct niu *np) |
| 5262 | { |
| 5263 | u64 data[5], rbuf[5], val; |
| 5264 | int i, max, err; |
| 5265 | |
| 5266 | if (np->parent->plat_type != PLAT_TYPE_NIU) { |
| 5267 | if (np->port == 0 || np->port == 1) |
| 5268 | max = ATLAS_P0_P1_DFIFO_ENTRIES; |
| 5269 | else |
| 5270 | max = ATLAS_P2_P3_DFIFO_ENTRIES; |
| 5271 | } else |
| 5272 | max = NIU_DFIFO_ENTRIES; |
| 5273 | |
| 5274 | data[0] = 0; |
| 5275 | data[1] = 0; |
| 5276 | data[2] = 0; |
| 5277 | data[3] = 0; |
| 5278 | data[4] = 0; |
| 5279 | |
| 5280 | for (i = 0; i < max; i++) { |
| 5281 | niu_ipp_write(np, i, data); |
| 5282 | niu_ipp_read(np, i, rbuf); |
| 5283 | } |
| 5284 | |
| 5285 | (void) nr64_ipp(IPP_INT_STAT); |
| 5286 | (void) nr64_ipp(IPP_INT_STAT); |
| 5287 | |
| 5288 | err = niu_ipp_reset(np); |
| 5289 | if (err) |
| 5290 | return err; |
| 5291 | |
| 5292 | (void) nr64_ipp(IPP_PKT_DIS); |
| 5293 | (void) nr64_ipp(IPP_BAD_CS_CNT); |
| 5294 | (void) nr64_ipp(IPP_ECC); |
| 5295 | |
| 5296 | (void) nr64_ipp(IPP_INT_STAT); |
| 5297 | |
| 5298 | nw64_ipp(IPP_MSK, ~IPP_MSK_ALL); |
| 5299 | |
| 5300 | val = nr64_ipp(IPP_CFIG); |
| 5301 | val &= ~IPP_CFIG_IP_MAX_PKT; |
| 5302 | val |= (IPP_CFIG_IPP_ENABLE | |
| 5303 | IPP_CFIG_DFIFO_ECC_EN | |
| 5304 | IPP_CFIG_DROP_BAD_CRC | |
| 5305 | IPP_CFIG_CKSUM_EN | |
| 5306 | (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT)); |
| 5307 | nw64_ipp(IPP_CFIG, val); |
| 5308 | |
| 5309 | return 0; |
| 5310 | } |
| 5311 | |
| 5312 | static void niu_handle_led(struct niu *np, int status) |
| 5313 | { |
| 5314 | u64 val; |
| 5315 | val = nr64_mac(XMAC_CONFIG); |
| 5316 | |
| 5317 | if ((np->flags & NIU_FLAGS_10G) != 0 && |
| 5318 | (np->flags & NIU_FLAGS_FIBER) != 0) { |
| 5319 | if (status) { |
| 5320 | val |= XMAC_CONFIG_LED_POLARITY; |
| 5321 | val &= ~XMAC_CONFIG_FORCE_LED_ON; |
| 5322 | } else { |
| 5323 | val |= XMAC_CONFIG_FORCE_LED_ON; |
| 5324 | val &= ~XMAC_CONFIG_LED_POLARITY; |
| 5325 | } |
| 5326 | } |
| 5327 | |
| 5328 | nw64_mac(XMAC_CONFIG, val); |
| 5329 | } |
| 5330 | |
| 5331 | static void niu_init_xif_xmac(struct niu *np) |
| 5332 | { |
| 5333 | struct niu_link_config *lp = &np->link_config; |
| 5334 | u64 val; |
| 5335 | |
| 5336 | if (np->flags & NIU_FLAGS_XCVR_SERDES) { |
| 5337 | val = nr64(MIF_CONFIG); |
| 5338 | val |= MIF_CONFIG_ATCA_GE; |
| 5339 | nw64(MIF_CONFIG, val); |
| 5340 | } |
| 5341 | |
| 5342 | val = nr64_mac(XMAC_CONFIG); |
| 5343 | val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; |
| 5344 | |
| 5345 | val |= XMAC_CONFIG_TX_OUTPUT_EN; |
| 5346 | |
| 5347 | if (lp->loopback_mode == LOOPBACK_MAC) { |
| 5348 | val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; |
| 5349 | val |= XMAC_CONFIG_LOOPBACK; |
| 5350 | } else { |
| 5351 | val &= ~XMAC_CONFIG_LOOPBACK; |
| 5352 | } |
| 5353 | |
| 5354 | if (np->flags & NIU_FLAGS_10G) { |
| 5355 | val &= ~XMAC_CONFIG_LFS_DISABLE; |
| 5356 | } else { |
| 5357 | val |= XMAC_CONFIG_LFS_DISABLE; |
| 5358 | if (!(np->flags & NIU_FLAGS_FIBER) && |
| 5359 | !(np->flags & NIU_FLAGS_XCVR_SERDES)) |
| 5360 | val |= XMAC_CONFIG_1G_PCS_BYPASS; |
| 5361 | else |
| 5362 | val &= ~XMAC_CONFIG_1G_PCS_BYPASS; |
| 5363 | } |
| 5364 | |
| 5365 | val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; |
| 5366 | |
| 5367 | if (lp->active_speed == SPEED_100) |
| 5368 | val |= XMAC_CONFIG_SEL_CLK_25MHZ; |
| 5369 | else |
| 5370 | val &= ~XMAC_CONFIG_SEL_CLK_25MHZ; |
| 5371 | |
| 5372 | nw64_mac(XMAC_CONFIG, val); |
| 5373 | |
| 5374 | val = nr64_mac(XMAC_CONFIG); |
| 5375 | val &= ~XMAC_CONFIG_MODE_MASK; |
| 5376 | if (np->flags & NIU_FLAGS_10G) { |
| 5377 | val |= XMAC_CONFIG_MODE_XGMII; |
| 5378 | } else { |
| 5379 | if (lp->active_speed == SPEED_1000) |
| 5380 | val |= XMAC_CONFIG_MODE_GMII; |
| 5381 | else |
| 5382 | val |= XMAC_CONFIG_MODE_MII; |
| 5383 | } |
| 5384 | |
| 5385 | nw64_mac(XMAC_CONFIG, val); |
| 5386 | } |
| 5387 | |
| 5388 | static void niu_init_xif_bmac(struct niu *np) |
| 5389 | { |
| 5390 | struct niu_link_config *lp = &np->link_config; |
| 5391 | u64 val; |
| 5392 | |
| 5393 | val = BMAC_XIF_CONFIG_TX_OUTPUT_EN; |
| 5394 | |
| 5395 | if (lp->loopback_mode == LOOPBACK_MAC) |
| 5396 | val |= BMAC_XIF_CONFIG_MII_LOOPBACK; |
| 5397 | else |
| 5398 | val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK; |
| 5399 | |
| 5400 | if (lp->active_speed == SPEED_1000) |
| 5401 | val |= BMAC_XIF_CONFIG_GMII_MODE; |
| 5402 | else |
| 5403 | val &= ~BMAC_XIF_CONFIG_GMII_MODE; |
| 5404 | |
| 5405 | val &= ~(BMAC_XIF_CONFIG_LINK_LED | |
| 5406 | BMAC_XIF_CONFIG_LED_POLARITY); |
| 5407 | |
| 5408 | if (!(np->flags & NIU_FLAGS_10G) && |
| 5409 | !(np->flags & NIU_FLAGS_FIBER) && |
| 5410 | lp->active_speed == SPEED_100) |
| 5411 | val |= BMAC_XIF_CONFIG_25MHZ_CLOCK; |
| 5412 | else |
| 5413 | val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK; |
| 5414 | |
| 5415 | nw64_mac(BMAC_XIF_CONFIG, val); |
| 5416 | } |
| 5417 | |
| 5418 | static void niu_init_xif(struct niu *np) |
| 5419 | { |
| 5420 | if (np->flags & NIU_FLAGS_XMAC) |
| 5421 | niu_init_xif_xmac(np); |
| 5422 | else |
| 5423 | niu_init_xif_bmac(np); |
| 5424 | } |
| 5425 | |
| 5426 | static void niu_pcs_mii_reset(struct niu *np) |
| 5427 | { |
| 5428 | int limit = 1000; |
| 5429 | u64 val = nr64_pcs(PCS_MII_CTL); |
| 5430 | val |= PCS_MII_CTL_RST; |
| 5431 | nw64_pcs(PCS_MII_CTL, val); |
| 5432 | while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) { |
| 5433 | udelay(100); |
| 5434 | val = nr64_pcs(PCS_MII_CTL); |
| 5435 | } |
| 5436 | } |
| 5437 | |
| 5438 | static void niu_xpcs_reset(struct niu *np) |
| 5439 | { |
| 5440 | int limit = 1000; |
| 5441 | u64 val = nr64_xpcs(XPCS_CONTROL1); |
| 5442 | val |= XPCS_CONTROL1_RESET; |
| 5443 | nw64_xpcs(XPCS_CONTROL1, val); |
| 5444 | while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) { |
| 5445 | udelay(100); |
| 5446 | val = nr64_xpcs(XPCS_CONTROL1); |
| 5447 | } |
| 5448 | } |
| 5449 | |
| 5450 | static int niu_init_pcs(struct niu *np) |
| 5451 | { |
| 5452 | struct niu_link_config *lp = &np->link_config; |
| 5453 | u64 val; |
| 5454 | |
| 5455 | switch (np->flags & (NIU_FLAGS_10G | |
| 5456 | NIU_FLAGS_FIBER | |
| 5457 | NIU_FLAGS_XCVR_SERDES)) { |
| 5458 | case NIU_FLAGS_FIBER: |
| 5459 | /* 1G fiber */ |
| 5460 | nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); |
| 5461 | nw64_pcs(PCS_DPATH_MODE, 0); |
| 5462 | niu_pcs_mii_reset(np); |
| 5463 | break; |
| 5464 | |
| 5465 | case NIU_FLAGS_10G: |
| 5466 | case NIU_FLAGS_10G | NIU_FLAGS_FIBER: |
| 5467 | case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: |
| 5468 | /* 10G SERDES */ |
| 5469 | if (!(np->flags & NIU_FLAGS_XMAC)) |
| 5470 | return -EINVAL; |
| 5471 | |
| 5472 | /* 10G copper or fiber */ |
| 5473 | val = nr64_mac(XMAC_CONFIG); |
| 5474 | val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; |
| 5475 | nw64_mac(XMAC_CONFIG, val); |
| 5476 | |
| 5477 | niu_xpcs_reset(np); |
| 5478 | |
| 5479 | val = nr64_xpcs(XPCS_CONTROL1); |
| 5480 | if (lp->loopback_mode == LOOPBACK_PHY) |
| 5481 | val |= XPCS_CONTROL1_LOOPBACK; |
| 5482 | else |
| 5483 | val &= ~XPCS_CONTROL1_LOOPBACK; |
| 5484 | nw64_xpcs(XPCS_CONTROL1, val); |
| 5485 | |
| 5486 | nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0); |
| 5487 | (void) nr64_xpcs(XPCS_SYMERR_CNT01); |
| 5488 | (void) nr64_xpcs(XPCS_SYMERR_CNT23); |
| 5489 | break; |
| 5490 | |
| 5491 | |
| 5492 | case NIU_FLAGS_XCVR_SERDES: |
| 5493 | /* 1G SERDES */ |
| 5494 | niu_pcs_mii_reset(np); |
| 5495 | nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); |
| 5496 | nw64_pcs(PCS_DPATH_MODE, 0); |
| 5497 | break; |
| 5498 | |
| 5499 | case 0: |
| 5500 | /* 1G copper */ |
| 5501 | case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: |
| 5502 | /* 1G RGMII FIBER */ |
| 5503 | nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII); |
| 5504 | niu_pcs_mii_reset(np); |
| 5505 | break; |
| 5506 | |
| 5507 | default: |
| 5508 | return -EINVAL; |
| 5509 | } |
| 5510 | |
| 5511 | return 0; |
| 5512 | } |
| 5513 | |
| 5514 | static int niu_reset_tx_xmac(struct niu *np) |
| 5515 | { |
| 5516 | return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST, |
| 5517 | (XTXMAC_SW_RST_REG_RS | |
| 5518 | XTXMAC_SW_RST_SOFT_RST), |
| 5519 | 1000, 100, "XTXMAC_SW_RST"); |
| 5520 | } |
| 5521 | |
| 5522 | static int niu_reset_tx_bmac(struct niu *np) |
| 5523 | { |
| 5524 | int limit; |
| 5525 | |
| 5526 | nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET); |
| 5527 | limit = 1000; |
| 5528 | while (--limit >= 0) { |
| 5529 | if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET)) |
| 5530 | break; |
| 5531 | udelay(100); |
| 5532 | } |
| 5533 | if (limit < 0) { |
| 5534 | dev_err(np->device, PFX "Port %u TX BMAC would not reset, " |
| 5535 | "BTXMAC_SW_RST[%llx]\n", |
| 5536 | np->port, |
| 5537 | (unsigned long long) nr64_mac(BTXMAC_SW_RST)); |
| 5538 | return -ENODEV; |
| 5539 | } |
| 5540 | |
| 5541 | return 0; |
| 5542 | } |
| 5543 | |
| 5544 | static int niu_reset_tx_mac(struct niu *np) |
| 5545 | { |
| 5546 | if (np->flags & NIU_FLAGS_XMAC) |
| 5547 | return niu_reset_tx_xmac(np); |
| 5548 | else |
| 5549 | return niu_reset_tx_bmac(np); |
| 5550 | } |
| 5551 | |
| 5552 | static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max) |
| 5553 | { |
| 5554 | u64 val; |
| 5555 | |
| 5556 | val = nr64_mac(XMAC_MIN); |
| 5557 | val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE | |
| 5558 | XMAC_MIN_RX_MIN_PKT_SIZE); |
| 5559 | val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT); |
| 5560 | val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT); |
| 5561 | nw64_mac(XMAC_MIN, val); |
| 5562 | |
| 5563 | nw64_mac(XMAC_MAX, max); |
| 5564 | |
| 5565 | nw64_mac(XTXMAC_STAT_MSK, ~(u64)0); |
| 5566 | |
| 5567 | val = nr64_mac(XMAC_IPG); |
| 5568 | if (np->flags & NIU_FLAGS_10G) { |
| 5569 | val &= ~XMAC_IPG_IPG_XGMII; |
| 5570 | val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT); |
| 5571 | } else { |
| 5572 | val &= ~XMAC_IPG_IPG_MII_GMII; |
| 5573 | val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT); |
| 5574 | } |
| 5575 | nw64_mac(XMAC_IPG, val); |
| 5576 | |
| 5577 | val = nr64_mac(XMAC_CONFIG); |
| 5578 | val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC | |
| 5579 | XMAC_CONFIG_STRETCH_MODE | |
| 5580 | XMAC_CONFIG_VAR_MIN_IPG_EN | |
| 5581 | XMAC_CONFIG_TX_ENABLE); |
| 5582 | nw64_mac(XMAC_CONFIG, val); |
| 5583 | |
| 5584 | nw64_mac(TXMAC_FRM_CNT, 0); |
| 5585 | nw64_mac(TXMAC_BYTE_CNT, 0); |
| 5586 | } |
| 5587 | |
| 5588 | static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max) |
| 5589 | { |
| 5590 | u64 val; |
| 5591 | |
| 5592 | nw64_mac(BMAC_MIN_FRAME, min); |
| 5593 | nw64_mac(BMAC_MAX_FRAME, max); |
| 5594 | |
| 5595 | nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0); |
| 5596 | nw64_mac(BMAC_CTRL_TYPE, 0x8808); |
| 5597 | nw64_mac(BMAC_PREAMBLE_SIZE, 7); |
| 5598 | |
| 5599 | val = nr64_mac(BTXMAC_CONFIG); |
| 5600 | val &= ~(BTXMAC_CONFIG_FCS_DISABLE | |
| 5601 | BTXMAC_CONFIG_ENABLE); |
| 5602 | nw64_mac(BTXMAC_CONFIG, val); |
| 5603 | } |
| 5604 | |
| 5605 | static void niu_init_tx_mac(struct niu *np) |
| 5606 | { |
| 5607 | u64 min, max; |
| 5608 | |
| 5609 | min = 64; |
| 5610 | if (np->dev->mtu > ETH_DATA_LEN) |
| 5611 | max = 9216; |
| 5612 | else |
| 5613 | max = 1522; |
| 5614 | |
| 5615 | /* The XMAC_MIN register only accepts values for TX min which |
| 5616 | * have the low 3 bits cleared. |
| 5617 | */ |
| 5618 | BUILD_BUG_ON(min & 0x7); |
| 5619 | |
| 5620 | if (np->flags & NIU_FLAGS_XMAC) |
| 5621 | niu_init_tx_xmac(np, min, max); |
| 5622 | else |
| 5623 | niu_init_tx_bmac(np, min, max); |
| 5624 | } |
| 5625 | |
| 5626 | static int niu_reset_rx_xmac(struct niu *np) |
| 5627 | { |
| 5628 | int limit; |
| 5629 | |
| 5630 | nw64_mac(XRXMAC_SW_RST, |
| 5631 | XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST); |
| 5632 | limit = 1000; |
| 5633 | while (--limit >= 0) { |
| 5634 | if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS | |
| 5635 | XRXMAC_SW_RST_SOFT_RST))) |
| 5636 | break; |
| 5637 | udelay(100); |
| 5638 | } |
| 5639 | if (limit < 0) { |
| 5640 | dev_err(np->device, PFX "Port %u RX XMAC would not reset, " |
| 5641 | "XRXMAC_SW_RST[%llx]\n", |
| 5642 | np->port, |
| 5643 | (unsigned long long) nr64_mac(XRXMAC_SW_RST)); |
| 5644 | return -ENODEV; |
| 5645 | } |
| 5646 | |
| 5647 | return 0; |
| 5648 | } |
| 5649 | |
| 5650 | static int niu_reset_rx_bmac(struct niu *np) |
| 5651 | { |
| 5652 | int limit; |
| 5653 | |
| 5654 | nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET); |
| 5655 | limit = 1000; |
| 5656 | while (--limit >= 0) { |
| 5657 | if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET)) |
| 5658 | break; |
| 5659 | udelay(100); |
| 5660 | } |
| 5661 | if (limit < 0) { |
| 5662 | dev_err(np->device, PFX "Port %u RX BMAC would not reset, " |
| 5663 | "BRXMAC_SW_RST[%llx]\n", |
| 5664 | np->port, |
| 5665 | (unsigned long long) nr64_mac(BRXMAC_SW_RST)); |
| 5666 | return -ENODEV; |
| 5667 | } |
| 5668 | |
| 5669 | return 0; |
| 5670 | } |
| 5671 | |
| 5672 | static int niu_reset_rx_mac(struct niu *np) |
| 5673 | { |
| 5674 | if (np->flags & NIU_FLAGS_XMAC) |
| 5675 | return niu_reset_rx_xmac(np); |
| 5676 | else |
| 5677 | return niu_reset_rx_bmac(np); |
| 5678 | } |
| 5679 | |
| 5680 | static void niu_init_rx_xmac(struct niu *np) |
| 5681 | { |
| 5682 | struct niu_parent *parent = np->parent; |
| 5683 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; |
| 5684 | int first_rdc_table = tp->first_table_num; |
| 5685 | unsigned long i; |
| 5686 | u64 val; |
| 5687 | |
| 5688 | nw64_mac(XMAC_ADD_FILT0, 0); |
| 5689 | nw64_mac(XMAC_ADD_FILT1, 0); |
| 5690 | nw64_mac(XMAC_ADD_FILT2, 0); |
| 5691 | nw64_mac(XMAC_ADD_FILT12_MASK, 0); |
| 5692 | nw64_mac(XMAC_ADD_FILT00_MASK, 0); |
| 5693 | for (i = 0; i < MAC_NUM_HASH; i++) |
| 5694 | nw64_mac(XMAC_HASH_TBL(i), 0); |
| 5695 | nw64_mac(XRXMAC_STAT_MSK, ~(u64)0); |
| 5696 | niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); |
| 5697 | niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); |
| 5698 | |
| 5699 | val = nr64_mac(XMAC_CONFIG); |
| 5700 | val &= ~(XMAC_CONFIG_RX_MAC_ENABLE | |
| 5701 | XMAC_CONFIG_PROMISCUOUS | |
| 5702 | XMAC_CONFIG_PROMISC_GROUP | |
| 5703 | XMAC_CONFIG_ERR_CHK_DIS | |
| 5704 | XMAC_CONFIG_RX_CRC_CHK_DIS | |
| 5705 | XMAC_CONFIG_RESERVED_MULTICAST | |
| 5706 | XMAC_CONFIG_RX_CODEV_CHK_DIS | |
| 5707 | XMAC_CONFIG_ADDR_FILTER_EN | |
| 5708 | XMAC_CONFIG_RCV_PAUSE_ENABLE | |
| 5709 | XMAC_CONFIG_STRIP_CRC | |
| 5710 | XMAC_CONFIG_PASS_FLOW_CTRL | |
| 5711 | XMAC_CONFIG_MAC2IPP_PKT_CNT_EN); |
| 5712 | val |= (XMAC_CONFIG_HASH_FILTER_EN); |
| 5713 | nw64_mac(XMAC_CONFIG, val); |
| 5714 | |
| 5715 | nw64_mac(RXMAC_BT_CNT, 0); |
| 5716 | nw64_mac(RXMAC_BC_FRM_CNT, 0); |
| 5717 | nw64_mac(RXMAC_MC_FRM_CNT, 0); |
| 5718 | nw64_mac(RXMAC_FRAG_CNT, 0); |
| 5719 | nw64_mac(RXMAC_HIST_CNT1, 0); |
| 5720 | nw64_mac(RXMAC_HIST_CNT2, 0); |
| 5721 | nw64_mac(RXMAC_HIST_CNT3, 0); |
| 5722 | nw64_mac(RXMAC_HIST_CNT4, 0); |
| 5723 | nw64_mac(RXMAC_HIST_CNT5, 0); |
| 5724 | nw64_mac(RXMAC_HIST_CNT6, 0); |
| 5725 | nw64_mac(RXMAC_HIST_CNT7, 0); |
| 5726 | nw64_mac(RXMAC_MPSZER_CNT, 0); |
| 5727 | nw64_mac(RXMAC_CRC_ER_CNT, 0); |
| 5728 | nw64_mac(RXMAC_CD_VIO_CNT, 0); |
| 5729 | nw64_mac(LINK_FAULT_CNT, 0); |
| 5730 | } |
| 5731 | |
| 5732 | static void niu_init_rx_bmac(struct niu *np) |
| 5733 | { |
| 5734 | struct niu_parent *parent = np->parent; |
| 5735 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; |
| 5736 | int first_rdc_table = tp->first_table_num; |
| 5737 | unsigned long i; |
| 5738 | u64 val; |
| 5739 | |
| 5740 | nw64_mac(BMAC_ADD_FILT0, 0); |
| 5741 | nw64_mac(BMAC_ADD_FILT1, 0); |
| 5742 | nw64_mac(BMAC_ADD_FILT2, 0); |
| 5743 | nw64_mac(BMAC_ADD_FILT12_MASK, 0); |
| 5744 | nw64_mac(BMAC_ADD_FILT00_MASK, 0); |
| 5745 | for (i = 0; i < MAC_NUM_HASH; i++) |
| 5746 | nw64_mac(BMAC_HASH_TBL(i), 0); |
| 5747 | niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); |
| 5748 | niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); |
| 5749 | nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0); |
| 5750 | |
| 5751 | val = nr64_mac(BRXMAC_CONFIG); |
| 5752 | val &= ~(BRXMAC_CONFIG_ENABLE | |
| 5753 | BRXMAC_CONFIG_STRIP_PAD | |
| 5754 | BRXMAC_CONFIG_STRIP_FCS | |
| 5755 | BRXMAC_CONFIG_PROMISC | |
| 5756 | BRXMAC_CONFIG_PROMISC_GRP | |
| 5757 | BRXMAC_CONFIG_ADDR_FILT_EN | |
| 5758 | BRXMAC_CONFIG_DISCARD_DIS); |
| 5759 | val |= (BRXMAC_CONFIG_HASH_FILT_EN); |
| 5760 | nw64_mac(BRXMAC_CONFIG, val); |
| 5761 | |
| 5762 | val = nr64_mac(BMAC_ADDR_CMPEN); |
| 5763 | val |= BMAC_ADDR_CMPEN_EN0; |
| 5764 | nw64_mac(BMAC_ADDR_CMPEN, val); |
| 5765 | } |
| 5766 | |
| 5767 | static void niu_init_rx_mac(struct niu *np) |
| 5768 | { |
| 5769 | niu_set_primary_mac(np, np->dev->dev_addr); |
| 5770 | |
| 5771 | if (np->flags & NIU_FLAGS_XMAC) |
| 5772 | niu_init_rx_xmac(np); |
| 5773 | else |
| 5774 | niu_init_rx_bmac(np); |
| 5775 | } |
| 5776 | |
| 5777 | static void niu_enable_tx_xmac(struct niu *np, int on) |
| 5778 | { |
| 5779 | u64 val = nr64_mac(XMAC_CONFIG); |
| 5780 | |
| 5781 | if (on) |
| 5782 | val |= XMAC_CONFIG_TX_ENABLE; |
| 5783 | else |
| 5784 | val &= ~XMAC_CONFIG_TX_ENABLE; |
| 5785 | nw64_mac(XMAC_CONFIG, val); |
| 5786 | } |
| 5787 | |
| 5788 | static void niu_enable_tx_bmac(struct niu *np, int on) |
| 5789 | { |
| 5790 | u64 val = nr64_mac(BTXMAC_CONFIG); |
| 5791 | |
| 5792 | if (on) |
| 5793 | val |= BTXMAC_CONFIG_ENABLE; |
| 5794 | else |
| 5795 | val &= ~BTXMAC_CONFIG_ENABLE; |
| 5796 | nw64_mac(BTXMAC_CONFIG, val); |
| 5797 | } |
| 5798 | |
| 5799 | static void niu_enable_tx_mac(struct niu *np, int on) |
| 5800 | { |
| 5801 | if (np->flags & NIU_FLAGS_XMAC) |
| 5802 | niu_enable_tx_xmac(np, on); |
| 5803 | else |
| 5804 | niu_enable_tx_bmac(np, on); |
| 5805 | } |
| 5806 | |
| 5807 | static void niu_enable_rx_xmac(struct niu *np, int on) |
| 5808 | { |
| 5809 | u64 val = nr64_mac(XMAC_CONFIG); |
| 5810 | |
| 5811 | val &= ~(XMAC_CONFIG_HASH_FILTER_EN | |
| 5812 | XMAC_CONFIG_PROMISCUOUS); |
| 5813 | |
| 5814 | if (np->flags & NIU_FLAGS_MCAST) |
| 5815 | val |= XMAC_CONFIG_HASH_FILTER_EN; |
| 5816 | if (np->flags & NIU_FLAGS_PROMISC) |
| 5817 | val |= XMAC_CONFIG_PROMISCUOUS; |
| 5818 | |
| 5819 | if (on) |
| 5820 | val |= XMAC_CONFIG_RX_MAC_ENABLE; |
| 5821 | else |
| 5822 | val &= ~XMAC_CONFIG_RX_MAC_ENABLE; |
| 5823 | nw64_mac(XMAC_CONFIG, val); |
| 5824 | } |
| 5825 | |
| 5826 | static void niu_enable_rx_bmac(struct niu *np, int on) |
| 5827 | { |
| 5828 | u64 val = nr64_mac(BRXMAC_CONFIG); |
| 5829 | |
| 5830 | val &= ~(BRXMAC_CONFIG_HASH_FILT_EN | |
| 5831 | BRXMAC_CONFIG_PROMISC); |
| 5832 | |
| 5833 | if (np->flags & NIU_FLAGS_MCAST) |
| 5834 | val |= BRXMAC_CONFIG_HASH_FILT_EN; |
| 5835 | if (np->flags & NIU_FLAGS_PROMISC) |
| 5836 | val |= BRXMAC_CONFIG_PROMISC; |
| 5837 | |
| 5838 | if (on) |
| 5839 | val |= BRXMAC_CONFIG_ENABLE; |
| 5840 | else |
| 5841 | val &= ~BRXMAC_CONFIG_ENABLE; |
| 5842 | nw64_mac(BRXMAC_CONFIG, val); |
| 5843 | } |
| 5844 | |
| 5845 | static void niu_enable_rx_mac(struct niu *np, int on) |
| 5846 | { |
| 5847 | if (np->flags & NIU_FLAGS_XMAC) |
| 5848 | niu_enable_rx_xmac(np, on); |
| 5849 | else |
| 5850 | niu_enable_rx_bmac(np, on); |
| 5851 | } |
| 5852 | |
| 5853 | static int niu_init_mac(struct niu *np) |
| 5854 | { |
| 5855 | int err; |
| 5856 | |
| 5857 | niu_init_xif(np); |
| 5858 | err = niu_init_pcs(np); |
| 5859 | if (err) |
| 5860 | return err; |
| 5861 | |
| 5862 | err = niu_reset_tx_mac(np); |
| 5863 | if (err) |
| 5864 | return err; |
| 5865 | niu_init_tx_mac(np); |
| 5866 | err = niu_reset_rx_mac(np); |
| 5867 | if (err) |
| 5868 | return err; |
| 5869 | niu_init_rx_mac(np); |
| 5870 | |
| 5871 | /* This looks hookey but the RX MAC reset we just did will |
| 5872 | * undo some of the state we setup in niu_init_tx_mac() so we |
| 5873 | * have to call it again. In particular, the RX MAC reset will |
| 5874 | * set the XMAC_MAX register back to it's default value. |
| 5875 | */ |
| 5876 | niu_init_tx_mac(np); |
| 5877 | niu_enable_tx_mac(np, 1); |
| 5878 | |
| 5879 | niu_enable_rx_mac(np, 1); |
| 5880 | |
| 5881 | return 0; |
| 5882 | } |
| 5883 | |
| 5884 | static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp) |
| 5885 | { |
| 5886 | (void) niu_tx_channel_stop(np, rp->tx_channel); |
| 5887 | } |
| 5888 | |
| 5889 | static void niu_stop_tx_channels(struct niu *np) |
| 5890 | { |
| 5891 | int i; |
| 5892 | |
| 5893 | for (i = 0; i < np->num_tx_rings; i++) { |
| 5894 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 5895 | |
| 5896 | niu_stop_one_tx_channel(np, rp); |
| 5897 | } |
| 5898 | } |
| 5899 | |
| 5900 | static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp) |
| 5901 | { |
| 5902 | (void) niu_tx_channel_reset(np, rp->tx_channel); |
| 5903 | } |
| 5904 | |
| 5905 | static void niu_reset_tx_channels(struct niu *np) |
| 5906 | { |
| 5907 | int i; |
| 5908 | |
| 5909 | for (i = 0; i < np->num_tx_rings; i++) { |
| 5910 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 5911 | |
| 5912 | niu_reset_one_tx_channel(np, rp); |
| 5913 | } |
| 5914 | } |
| 5915 | |
| 5916 | static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp) |
| 5917 | { |
| 5918 | (void) niu_enable_rx_channel(np, rp->rx_channel, 0); |
| 5919 | } |
| 5920 | |
| 5921 | static void niu_stop_rx_channels(struct niu *np) |
| 5922 | { |
| 5923 | int i; |
| 5924 | |
| 5925 | for (i = 0; i < np->num_rx_rings; i++) { |
| 5926 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 5927 | |
| 5928 | niu_stop_one_rx_channel(np, rp); |
| 5929 | } |
| 5930 | } |
| 5931 | |
| 5932 | static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp) |
| 5933 | { |
| 5934 | int channel = rp->rx_channel; |
| 5935 | |
| 5936 | (void) niu_rx_channel_reset(np, channel); |
| 5937 | nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL); |
| 5938 | nw64(RX_DMA_CTL_STAT(channel), 0); |
| 5939 | (void) niu_enable_rx_channel(np, channel, 0); |
| 5940 | } |
| 5941 | |
| 5942 | static void niu_reset_rx_channels(struct niu *np) |
| 5943 | { |
| 5944 | int i; |
| 5945 | |
| 5946 | for (i = 0; i < np->num_rx_rings; i++) { |
| 5947 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 5948 | |
| 5949 | niu_reset_one_rx_channel(np, rp); |
| 5950 | } |
| 5951 | } |
| 5952 | |
| 5953 | static void niu_disable_ipp(struct niu *np) |
| 5954 | { |
| 5955 | u64 rd, wr, val; |
| 5956 | int limit; |
| 5957 | |
| 5958 | rd = nr64_ipp(IPP_DFIFO_RD_PTR); |
| 5959 | wr = nr64_ipp(IPP_DFIFO_WR_PTR); |
| 5960 | limit = 100; |
| 5961 | while (--limit >= 0 && (rd != wr)) { |
| 5962 | rd = nr64_ipp(IPP_DFIFO_RD_PTR); |
| 5963 | wr = nr64_ipp(IPP_DFIFO_WR_PTR); |
| 5964 | } |
| 5965 | if (limit < 0 && |
| 5966 | (rd != 0 && wr != 1)) { |
| 5967 | dev_err(np->device, PFX "%s: IPP would not quiesce, " |
| 5968 | "rd_ptr[%llx] wr_ptr[%llx]\n", |
| 5969 | np->dev->name, |
| 5970 | (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR), |
| 5971 | (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR)); |
| 5972 | } |
| 5973 | |
| 5974 | val = nr64_ipp(IPP_CFIG); |
| 5975 | val &= ~(IPP_CFIG_IPP_ENABLE | |
| 5976 | IPP_CFIG_DFIFO_ECC_EN | |
| 5977 | IPP_CFIG_DROP_BAD_CRC | |
| 5978 | IPP_CFIG_CKSUM_EN); |
| 5979 | nw64_ipp(IPP_CFIG, val); |
| 5980 | |
| 5981 | (void) niu_ipp_reset(np); |
| 5982 | } |
| 5983 | |
| 5984 | static int niu_init_hw(struct niu *np) |
| 5985 | { |
| 5986 | int i, err; |
| 5987 | |
| 5988 | niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name); |
| 5989 | niu_txc_enable_port(np, 1); |
| 5990 | niu_txc_port_dma_enable(np, 1); |
| 5991 | niu_txc_set_imask(np, 0); |
| 5992 | |
| 5993 | niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name); |
| 5994 | for (i = 0; i < np->num_tx_rings; i++) { |
| 5995 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 5996 | |
| 5997 | err = niu_init_one_tx_channel(np, rp); |
| 5998 | if (err) |
| 5999 | return err; |
| 6000 | } |
| 6001 | |
| 6002 | niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name); |
| 6003 | err = niu_init_rx_channels(np); |
| 6004 | if (err) |
| 6005 | goto out_uninit_tx_channels; |
| 6006 | |
| 6007 | niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name); |
| 6008 | err = niu_init_classifier_hw(np); |
| 6009 | if (err) |
| 6010 | goto out_uninit_rx_channels; |
| 6011 | |
| 6012 | niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name); |
| 6013 | err = niu_init_zcp(np); |
| 6014 | if (err) |
| 6015 | goto out_uninit_rx_channels; |
| 6016 | |
| 6017 | niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name); |
| 6018 | err = niu_init_ipp(np); |
| 6019 | if (err) |
| 6020 | goto out_uninit_rx_channels; |
| 6021 | |
| 6022 | niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name); |
| 6023 | err = niu_init_mac(np); |
| 6024 | if (err) |
| 6025 | goto out_uninit_ipp; |
| 6026 | |
| 6027 | return 0; |
| 6028 | |
| 6029 | out_uninit_ipp: |
| 6030 | niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name); |
| 6031 | niu_disable_ipp(np); |
| 6032 | |
| 6033 | out_uninit_rx_channels: |
| 6034 | niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name); |
| 6035 | niu_stop_rx_channels(np); |
| 6036 | niu_reset_rx_channels(np); |
| 6037 | |
| 6038 | out_uninit_tx_channels: |
| 6039 | niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name); |
| 6040 | niu_stop_tx_channels(np); |
| 6041 | niu_reset_tx_channels(np); |
| 6042 | |
| 6043 | return err; |
| 6044 | } |
| 6045 | |
| 6046 | static void niu_stop_hw(struct niu *np) |
| 6047 | { |
| 6048 | niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name); |
| 6049 | niu_enable_interrupts(np, 0); |
| 6050 | |
| 6051 | niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name); |
| 6052 | niu_enable_rx_mac(np, 0); |
| 6053 | |
| 6054 | niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name); |
| 6055 | niu_disable_ipp(np); |
| 6056 | |
| 6057 | niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name); |
| 6058 | niu_stop_tx_channels(np); |
| 6059 | |
| 6060 | niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name); |
| 6061 | niu_stop_rx_channels(np); |
| 6062 | |
| 6063 | niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name); |
| 6064 | niu_reset_tx_channels(np); |
| 6065 | |
| 6066 | niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name); |
| 6067 | niu_reset_rx_channels(np); |
| 6068 | } |
| 6069 | |
| 6070 | static void niu_set_irq_name(struct niu *np) |
| 6071 | { |
| 6072 | int port = np->port; |
| 6073 | int i, j = 1; |
| 6074 | |
| 6075 | sprintf(np->irq_name[0], "%s:MAC", np->dev->name); |
| 6076 | |
| 6077 | if (port == 0) { |
| 6078 | sprintf(np->irq_name[1], "%s:MIF", np->dev->name); |
| 6079 | sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name); |
| 6080 | j = 3; |
| 6081 | } |
| 6082 | |
| 6083 | for (i = 0; i < np->num_ldg - j; i++) { |
| 6084 | if (i < np->num_rx_rings) |
| 6085 | sprintf(np->irq_name[i+j], "%s-rx-%d", |
| 6086 | np->dev->name, i); |
| 6087 | else if (i < np->num_tx_rings + np->num_rx_rings) |
| 6088 | sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name, |
| 6089 | i - np->num_rx_rings); |
| 6090 | } |
| 6091 | } |
| 6092 | |
| 6093 | static int niu_request_irq(struct niu *np) |
| 6094 | { |
| 6095 | int i, j, err; |
| 6096 | |
| 6097 | niu_set_irq_name(np); |
| 6098 | |
| 6099 | err = 0; |
| 6100 | for (i = 0; i < np->num_ldg; i++) { |
| 6101 | struct niu_ldg *lp = &np->ldg[i]; |
| 6102 | |
| 6103 | err = request_irq(lp->irq, niu_interrupt, |
| 6104 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, |
| 6105 | np->irq_name[i], lp); |
| 6106 | if (err) |
| 6107 | goto out_free_irqs; |
| 6108 | |
| 6109 | } |
| 6110 | |
| 6111 | return 0; |
| 6112 | |
| 6113 | out_free_irqs: |
| 6114 | for (j = 0; j < i; j++) { |
| 6115 | struct niu_ldg *lp = &np->ldg[j]; |
| 6116 | |
| 6117 | free_irq(lp->irq, lp); |
| 6118 | } |
| 6119 | return err; |
| 6120 | } |
| 6121 | |
| 6122 | static void niu_free_irq(struct niu *np) |
| 6123 | { |
| 6124 | int i; |
| 6125 | |
| 6126 | for (i = 0; i < np->num_ldg; i++) { |
| 6127 | struct niu_ldg *lp = &np->ldg[i]; |
| 6128 | |
| 6129 | free_irq(lp->irq, lp); |
| 6130 | } |
| 6131 | } |
| 6132 | |
| 6133 | static void niu_enable_napi(struct niu *np) |
| 6134 | { |
| 6135 | int i; |
| 6136 | |
| 6137 | for (i = 0; i < np->num_ldg; i++) |
| 6138 | napi_enable(&np->ldg[i].napi); |
| 6139 | } |
| 6140 | |
| 6141 | static void niu_disable_napi(struct niu *np) |
| 6142 | { |
| 6143 | int i; |
| 6144 | |
| 6145 | for (i = 0; i < np->num_ldg; i++) |
| 6146 | napi_disable(&np->ldg[i].napi); |
| 6147 | } |
| 6148 | |
| 6149 | static int niu_open(struct net_device *dev) |
| 6150 | { |
| 6151 | struct niu *np = netdev_priv(dev); |
| 6152 | int err; |
| 6153 | |
| 6154 | netif_carrier_off(dev); |
| 6155 | |
| 6156 | err = niu_alloc_channels(np); |
| 6157 | if (err) |
| 6158 | goto out_err; |
| 6159 | |
| 6160 | err = niu_enable_interrupts(np, 0); |
| 6161 | if (err) |
| 6162 | goto out_free_channels; |
| 6163 | |
| 6164 | err = niu_request_irq(np); |
| 6165 | if (err) |
| 6166 | goto out_free_channels; |
| 6167 | |
| 6168 | niu_enable_napi(np); |
| 6169 | |
| 6170 | spin_lock_irq(&np->lock); |
| 6171 | |
| 6172 | err = niu_init_hw(np); |
| 6173 | if (!err) { |
| 6174 | init_timer(&np->timer); |
| 6175 | np->timer.expires = jiffies + HZ; |
| 6176 | np->timer.data = (unsigned long) np; |
| 6177 | np->timer.function = niu_timer; |
| 6178 | |
| 6179 | err = niu_enable_interrupts(np, 1); |
| 6180 | if (err) |
| 6181 | niu_stop_hw(np); |
| 6182 | } |
| 6183 | |
| 6184 | spin_unlock_irq(&np->lock); |
| 6185 | |
| 6186 | if (err) { |
| 6187 | niu_disable_napi(np); |
| 6188 | goto out_free_irq; |
| 6189 | } |
| 6190 | |
| 6191 | netif_tx_start_all_queues(dev); |
| 6192 | |
| 6193 | if (np->link_config.loopback_mode != LOOPBACK_DISABLED) |
| 6194 | netif_carrier_on(dev); |
| 6195 | |
| 6196 | add_timer(&np->timer); |
| 6197 | |
| 6198 | return 0; |
| 6199 | |
| 6200 | out_free_irq: |
| 6201 | niu_free_irq(np); |
| 6202 | |
| 6203 | out_free_channels: |
| 6204 | niu_free_channels(np); |
| 6205 | |
| 6206 | out_err: |
| 6207 | return err; |
| 6208 | } |
| 6209 | |
| 6210 | static void niu_full_shutdown(struct niu *np, struct net_device *dev) |
| 6211 | { |
| 6212 | cancel_work_sync(&np->reset_task); |
| 6213 | |
| 6214 | niu_disable_napi(np); |
| 6215 | netif_tx_stop_all_queues(dev); |
| 6216 | |
| 6217 | del_timer_sync(&np->timer); |
| 6218 | |
| 6219 | spin_lock_irq(&np->lock); |
| 6220 | |
| 6221 | niu_stop_hw(np); |
| 6222 | |
| 6223 | spin_unlock_irq(&np->lock); |
| 6224 | } |
| 6225 | |
| 6226 | static int niu_close(struct net_device *dev) |
| 6227 | { |
| 6228 | struct niu *np = netdev_priv(dev); |
| 6229 | |
| 6230 | niu_full_shutdown(np, dev); |
| 6231 | |
| 6232 | niu_free_irq(np); |
| 6233 | |
| 6234 | niu_free_channels(np); |
| 6235 | |
| 6236 | niu_handle_led(np, 0); |
| 6237 | |
| 6238 | return 0; |
| 6239 | } |
| 6240 | |
| 6241 | static void niu_sync_xmac_stats(struct niu *np) |
| 6242 | { |
| 6243 | struct niu_xmac_stats *mp = &np->mac_stats.xmac; |
| 6244 | |
| 6245 | mp->tx_frames += nr64_mac(TXMAC_FRM_CNT); |
| 6246 | mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT); |
| 6247 | |
| 6248 | mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT); |
| 6249 | mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT); |
| 6250 | mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT); |
| 6251 | mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT); |
| 6252 | mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT); |
| 6253 | mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1); |
| 6254 | mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2); |
| 6255 | mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3); |
| 6256 | mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4); |
| 6257 | mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5); |
| 6258 | mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6); |
| 6259 | mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7); |
| 6260 | mp->rx_octets += nr64_mac(RXMAC_BT_CNT); |
| 6261 | mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT); |
| 6262 | mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT); |
| 6263 | mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT); |
| 6264 | } |
| 6265 | |
| 6266 | static void niu_sync_bmac_stats(struct niu *np) |
| 6267 | { |
| 6268 | struct niu_bmac_stats *mp = &np->mac_stats.bmac; |
| 6269 | |
| 6270 | mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT); |
| 6271 | mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT); |
| 6272 | |
| 6273 | mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT); |
| 6274 | mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); |
| 6275 | mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); |
| 6276 | mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT); |
| 6277 | } |
| 6278 | |
| 6279 | static void niu_sync_mac_stats(struct niu *np) |
| 6280 | { |
| 6281 | if (np->flags & NIU_FLAGS_XMAC) |
| 6282 | niu_sync_xmac_stats(np); |
| 6283 | else |
| 6284 | niu_sync_bmac_stats(np); |
| 6285 | } |
| 6286 | |
| 6287 | static void niu_get_rx_stats(struct niu *np) |
| 6288 | { |
| 6289 | unsigned long pkts, dropped, errors, bytes; |
| 6290 | int i; |
| 6291 | |
| 6292 | pkts = dropped = errors = bytes = 0; |
| 6293 | for (i = 0; i < np->num_rx_rings; i++) { |
| 6294 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 6295 | |
| 6296 | niu_sync_rx_discard_stats(np, rp, 0); |
| 6297 | |
| 6298 | pkts += rp->rx_packets; |
| 6299 | bytes += rp->rx_bytes; |
| 6300 | dropped += rp->rx_dropped; |
| 6301 | errors += rp->rx_errors; |
| 6302 | } |
| 6303 | np->dev->stats.rx_packets = pkts; |
| 6304 | np->dev->stats.rx_bytes = bytes; |
| 6305 | np->dev->stats.rx_dropped = dropped; |
| 6306 | np->dev->stats.rx_errors = errors; |
| 6307 | } |
| 6308 | |
| 6309 | static void niu_get_tx_stats(struct niu *np) |
| 6310 | { |
| 6311 | unsigned long pkts, errors, bytes; |
| 6312 | int i; |
| 6313 | |
| 6314 | pkts = errors = bytes = 0; |
| 6315 | for (i = 0; i < np->num_tx_rings; i++) { |
| 6316 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 6317 | |
| 6318 | pkts += rp->tx_packets; |
| 6319 | bytes += rp->tx_bytes; |
| 6320 | errors += rp->tx_errors; |
| 6321 | } |
| 6322 | np->dev->stats.tx_packets = pkts; |
| 6323 | np->dev->stats.tx_bytes = bytes; |
| 6324 | np->dev->stats.tx_errors = errors; |
| 6325 | } |
| 6326 | |
| 6327 | static struct net_device_stats *niu_get_stats(struct net_device *dev) |
| 6328 | { |
| 6329 | struct niu *np = netdev_priv(dev); |
| 6330 | |
| 6331 | niu_get_rx_stats(np); |
| 6332 | niu_get_tx_stats(np); |
| 6333 | |
| 6334 | return &dev->stats; |
| 6335 | } |
| 6336 | |
| 6337 | static void niu_load_hash_xmac(struct niu *np, u16 *hash) |
| 6338 | { |
| 6339 | int i; |
| 6340 | |
| 6341 | for (i = 0; i < 16; i++) |
| 6342 | nw64_mac(XMAC_HASH_TBL(i), hash[i]); |
| 6343 | } |
| 6344 | |
| 6345 | static void niu_load_hash_bmac(struct niu *np, u16 *hash) |
| 6346 | { |
| 6347 | int i; |
| 6348 | |
| 6349 | for (i = 0; i < 16; i++) |
| 6350 | nw64_mac(BMAC_HASH_TBL(i), hash[i]); |
| 6351 | } |
| 6352 | |
| 6353 | static void niu_load_hash(struct niu *np, u16 *hash) |
| 6354 | { |
| 6355 | if (np->flags & NIU_FLAGS_XMAC) |
| 6356 | niu_load_hash_xmac(np, hash); |
| 6357 | else |
| 6358 | niu_load_hash_bmac(np, hash); |
| 6359 | } |
| 6360 | |
| 6361 | static void niu_set_rx_mode(struct net_device *dev) |
| 6362 | { |
| 6363 | struct niu *np = netdev_priv(dev); |
| 6364 | int i, alt_cnt, err; |
| 6365 | struct dev_addr_list *addr; |
| 6366 | struct netdev_hw_addr *ha; |
| 6367 | unsigned long flags; |
| 6368 | u16 hash[16] = { 0, }; |
| 6369 | |
| 6370 | spin_lock_irqsave(&np->lock, flags); |
| 6371 | niu_enable_rx_mac(np, 0); |
| 6372 | |
| 6373 | np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC); |
| 6374 | if (dev->flags & IFF_PROMISC) |
| 6375 | np->flags |= NIU_FLAGS_PROMISC; |
| 6376 | if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0)) |
| 6377 | np->flags |= NIU_FLAGS_MCAST; |
| 6378 | |
| 6379 | alt_cnt = dev->uc.count; |
| 6380 | if (alt_cnt > niu_num_alt_addr(np)) { |
| 6381 | alt_cnt = 0; |
| 6382 | np->flags |= NIU_FLAGS_PROMISC; |
| 6383 | } |
| 6384 | |
| 6385 | if (alt_cnt) { |
| 6386 | int index = 0; |
| 6387 | |
| 6388 | list_for_each_entry(ha, &dev->uc.list, list) { |
| 6389 | err = niu_set_alt_mac(np, index, ha->addr); |
| 6390 | if (err) |
| 6391 | printk(KERN_WARNING PFX "%s: Error %d " |
| 6392 | "adding alt mac %d\n", |
| 6393 | dev->name, err, index); |
| 6394 | err = niu_enable_alt_mac(np, index, 1); |
| 6395 | if (err) |
| 6396 | printk(KERN_WARNING PFX "%s: Error %d " |
| 6397 | "enabling alt mac %d\n", |
| 6398 | dev->name, err, index); |
| 6399 | |
| 6400 | index++; |
| 6401 | } |
| 6402 | } else { |
| 6403 | int alt_start; |
| 6404 | if (np->flags & NIU_FLAGS_XMAC) |
| 6405 | alt_start = 0; |
| 6406 | else |
| 6407 | alt_start = 1; |
| 6408 | for (i = alt_start; i < niu_num_alt_addr(np); i++) { |
| 6409 | err = niu_enable_alt_mac(np, i, 0); |
| 6410 | if (err) |
| 6411 | printk(KERN_WARNING PFX "%s: Error %d " |
| 6412 | "disabling alt mac %d\n", |
| 6413 | dev->name, err, i); |
| 6414 | } |
| 6415 | } |
| 6416 | if (dev->flags & IFF_ALLMULTI) { |
| 6417 | for (i = 0; i < 16; i++) |
| 6418 | hash[i] = 0xffff; |
| 6419 | } else if (dev->mc_count > 0) { |
| 6420 | for (addr = dev->mc_list; addr; addr = addr->next) { |
| 6421 | u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr); |
| 6422 | |
| 6423 | crc >>= 24; |
| 6424 | hash[crc >> 4] |= (1 << (15 - (crc & 0xf))); |
| 6425 | } |
| 6426 | } |
| 6427 | |
| 6428 | if (np->flags & NIU_FLAGS_MCAST) |
| 6429 | niu_load_hash(np, hash); |
| 6430 | |
| 6431 | niu_enable_rx_mac(np, 1); |
| 6432 | spin_unlock_irqrestore(&np->lock, flags); |
| 6433 | } |
| 6434 | |
| 6435 | static int niu_set_mac_addr(struct net_device *dev, void *p) |
| 6436 | { |
| 6437 | struct niu *np = netdev_priv(dev); |
| 6438 | struct sockaddr *addr = p; |
| 6439 | unsigned long flags; |
| 6440 | |
| 6441 | if (!is_valid_ether_addr(addr->sa_data)) |
| 6442 | return -EINVAL; |
| 6443 | |
| 6444 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
| 6445 | |
| 6446 | if (!netif_running(dev)) |
| 6447 | return 0; |
| 6448 | |
| 6449 | spin_lock_irqsave(&np->lock, flags); |
| 6450 | niu_enable_rx_mac(np, 0); |
| 6451 | niu_set_primary_mac(np, dev->dev_addr); |
| 6452 | niu_enable_rx_mac(np, 1); |
| 6453 | spin_unlock_irqrestore(&np->lock, flags); |
| 6454 | |
| 6455 | return 0; |
| 6456 | } |
| 6457 | |
| 6458 | static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 6459 | { |
| 6460 | return -EOPNOTSUPP; |
| 6461 | } |
| 6462 | |
| 6463 | static void niu_netif_stop(struct niu *np) |
| 6464 | { |
| 6465 | np->dev->trans_start = jiffies; /* prevent tx timeout */ |
| 6466 | |
| 6467 | niu_disable_napi(np); |
| 6468 | |
| 6469 | netif_tx_disable(np->dev); |
| 6470 | } |
| 6471 | |
| 6472 | static void niu_netif_start(struct niu *np) |
| 6473 | { |
| 6474 | /* NOTE: unconditional netif_wake_queue is only appropriate |
| 6475 | * so long as all callers are assured to have free tx slots |
| 6476 | * (such as after niu_init_hw). |
| 6477 | */ |
| 6478 | netif_tx_wake_all_queues(np->dev); |
| 6479 | |
| 6480 | niu_enable_napi(np); |
| 6481 | |
| 6482 | niu_enable_interrupts(np, 1); |
| 6483 | } |
| 6484 | |
| 6485 | static void niu_reset_buffers(struct niu *np) |
| 6486 | { |
| 6487 | int i, j, k, err; |
| 6488 | |
| 6489 | if (np->rx_rings) { |
| 6490 | for (i = 0; i < np->num_rx_rings; i++) { |
| 6491 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 6492 | |
| 6493 | for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) { |
| 6494 | struct page *page; |
| 6495 | |
| 6496 | page = rp->rxhash[j]; |
| 6497 | while (page) { |
| 6498 | struct page *next = |
| 6499 | (struct page *) page->mapping; |
| 6500 | u64 base = page->index; |
| 6501 | base = base >> RBR_DESCR_ADDR_SHIFT; |
| 6502 | rp->rbr[k++] = cpu_to_le32(base); |
| 6503 | page = next; |
| 6504 | } |
| 6505 | } |
| 6506 | for (; k < MAX_RBR_RING_SIZE; k++) { |
| 6507 | err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k); |
| 6508 | if (unlikely(err)) |
| 6509 | break; |
| 6510 | } |
| 6511 | |
| 6512 | rp->rbr_index = rp->rbr_table_size - 1; |
| 6513 | rp->rcr_index = 0; |
| 6514 | rp->rbr_pending = 0; |
| 6515 | rp->rbr_refill_pending = 0; |
| 6516 | } |
| 6517 | } |
| 6518 | if (np->tx_rings) { |
| 6519 | for (i = 0; i < np->num_tx_rings; i++) { |
| 6520 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 6521 | |
| 6522 | for (j = 0; j < MAX_TX_RING_SIZE; j++) { |
| 6523 | if (rp->tx_buffs[j].skb) |
| 6524 | (void) release_tx_packet(np, rp, j); |
| 6525 | } |
| 6526 | |
| 6527 | rp->pending = MAX_TX_RING_SIZE; |
| 6528 | rp->prod = 0; |
| 6529 | rp->cons = 0; |
| 6530 | rp->wrap_bit = 0; |
| 6531 | } |
| 6532 | } |
| 6533 | } |
| 6534 | |
| 6535 | static void niu_reset_task(struct work_struct *work) |
| 6536 | { |
| 6537 | struct niu *np = container_of(work, struct niu, reset_task); |
| 6538 | unsigned long flags; |
| 6539 | int err; |
| 6540 | |
| 6541 | spin_lock_irqsave(&np->lock, flags); |
| 6542 | if (!netif_running(np->dev)) { |
| 6543 | spin_unlock_irqrestore(&np->lock, flags); |
| 6544 | return; |
| 6545 | } |
| 6546 | |
| 6547 | spin_unlock_irqrestore(&np->lock, flags); |
| 6548 | |
| 6549 | del_timer_sync(&np->timer); |
| 6550 | |
| 6551 | niu_netif_stop(np); |
| 6552 | |
| 6553 | spin_lock_irqsave(&np->lock, flags); |
| 6554 | |
| 6555 | niu_stop_hw(np); |
| 6556 | |
| 6557 | spin_unlock_irqrestore(&np->lock, flags); |
| 6558 | |
| 6559 | niu_reset_buffers(np); |
| 6560 | |
| 6561 | spin_lock_irqsave(&np->lock, flags); |
| 6562 | |
| 6563 | err = niu_init_hw(np); |
| 6564 | if (!err) { |
| 6565 | np->timer.expires = jiffies + HZ; |
| 6566 | add_timer(&np->timer); |
| 6567 | niu_netif_start(np); |
| 6568 | } |
| 6569 | |
| 6570 | spin_unlock_irqrestore(&np->lock, flags); |
| 6571 | } |
| 6572 | |
| 6573 | static void niu_tx_timeout(struct net_device *dev) |
| 6574 | { |
| 6575 | struct niu *np = netdev_priv(dev); |
| 6576 | |
| 6577 | dev_err(np->device, PFX "%s: Transmit timed out, resetting\n", |
| 6578 | dev->name); |
| 6579 | |
| 6580 | schedule_work(&np->reset_task); |
| 6581 | } |
| 6582 | |
| 6583 | static void niu_set_txd(struct tx_ring_info *rp, int index, |
| 6584 | u64 mapping, u64 len, u64 mark, |
| 6585 | u64 n_frags) |
| 6586 | { |
| 6587 | __le64 *desc = &rp->descr[index]; |
| 6588 | |
| 6589 | *desc = cpu_to_le64(mark | |
| 6590 | (n_frags << TX_DESC_NUM_PTR_SHIFT) | |
| 6591 | (len << TX_DESC_TR_LEN_SHIFT) | |
| 6592 | (mapping & TX_DESC_SAD)); |
| 6593 | } |
| 6594 | |
| 6595 | static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr, |
| 6596 | u64 pad_bytes, u64 len) |
| 6597 | { |
| 6598 | u16 eth_proto, eth_proto_inner; |
| 6599 | u64 csum_bits, l3off, ihl, ret; |
| 6600 | u8 ip_proto; |
| 6601 | int ipv6; |
| 6602 | |
| 6603 | eth_proto = be16_to_cpu(ehdr->h_proto); |
| 6604 | eth_proto_inner = eth_proto; |
| 6605 | if (eth_proto == ETH_P_8021Q) { |
| 6606 | struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr; |
| 6607 | __be16 val = vp->h_vlan_encapsulated_proto; |
| 6608 | |
| 6609 | eth_proto_inner = be16_to_cpu(val); |
| 6610 | } |
| 6611 | |
| 6612 | ipv6 = ihl = 0; |
| 6613 | switch (skb->protocol) { |
| 6614 | case cpu_to_be16(ETH_P_IP): |
| 6615 | ip_proto = ip_hdr(skb)->protocol; |
| 6616 | ihl = ip_hdr(skb)->ihl; |
| 6617 | break; |
| 6618 | case cpu_to_be16(ETH_P_IPV6): |
| 6619 | ip_proto = ipv6_hdr(skb)->nexthdr; |
| 6620 | ihl = (40 >> 2); |
| 6621 | ipv6 = 1; |
| 6622 | break; |
| 6623 | default: |
| 6624 | ip_proto = ihl = 0; |
| 6625 | break; |
| 6626 | } |
| 6627 | |
| 6628 | csum_bits = TXHDR_CSUM_NONE; |
| 6629 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
| 6630 | u64 start, stuff; |
| 6631 | |
| 6632 | csum_bits = (ip_proto == IPPROTO_TCP ? |
| 6633 | TXHDR_CSUM_TCP : |
| 6634 | (ip_proto == IPPROTO_UDP ? |
| 6635 | TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP)); |
| 6636 | |
| 6637 | start = skb_transport_offset(skb) - |
| 6638 | (pad_bytes + sizeof(struct tx_pkt_hdr)); |
| 6639 | stuff = start + skb->csum_offset; |
| 6640 | |
| 6641 | csum_bits |= (start / 2) << TXHDR_L4START_SHIFT; |
| 6642 | csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT; |
| 6643 | } |
| 6644 | |
| 6645 | l3off = skb_network_offset(skb) - |
| 6646 | (pad_bytes + sizeof(struct tx_pkt_hdr)); |
| 6647 | |
| 6648 | ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) | |
| 6649 | (len << TXHDR_LEN_SHIFT) | |
| 6650 | ((l3off / 2) << TXHDR_L3START_SHIFT) | |
| 6651 | (ihl << TXHDR_IHL_SHIFT) | |
| 6652 | ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) | |
| 6653 | ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) | |
| 6654 | (ipv6 ? TXHDR_IP_VER : 0) | |
| 6655 | csum_bits); |
| 6656 | |
| 6657 | return ret; |
| 6658 | } |
| 6659 | |
| 6660 | static netdev_tx_t niu_start_xmit(struct sk_buff *skb, |
| 6661 | struct net_device *dev) |
| 6662 | { |
| 6663 | struct niu *np = netdev_priv(dev); |
| 6664 | unsigned long align, headroom; |
| 6665 | struct netdev_queue *txq; |
| 6666 | struct tx_ring_info *rp; |
| 6667 | struct tx_pkt_hdr *tp; |
| 6668 | unsigned int len, nfg; |
| 6669 | struct ethhdr *ehdr; |
| 6670 | int prod, i, tlen; |
| 6671 | u64 mapping, mrk; |
| 6672 | |
| 6673 | i = skb_get_queue_mapping(skb); |
| 6674 | rp = &np->tx_rings[i]; |
| 6675 | txq = netdev_get_tx_queue(dev, i); |
| 6676 | |
| 6677 | if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) { |
| 6678 | netif_tx_stop_queue(txq); |
| 6679 | dev_err(np->device, PFX "%s: BUG! Tx ring full when " |
| 6680 | "queue awake!\n", dev->name); |
| 6681 | rp->tx_errors++; |
| 6682 | return NETDEV_TX_BUSY; |
| 6683 | } |
| 6684 | |
| 6685 | if (skb->len < ETH_ZLEN) { |
| 6686 | unsigned int pad_bytes = ETH_ZLEN - skb->len; |
| 6687 | |
| 6688 | if (skb_pad(skb, pad_bytes)) |
| 6689 | goto out; |
| 6690 | skb_put(skb, pad_bytes); |
| 6691 | } |
| 6692 | |
| 6693 | len = sizeof(struct tx_pkt_hdr) + 15; |
| 6694 | if (skb_headroom(skb) < len) { |
| 6695 | struct sk_buff *skb_new; |
| 6696 | |
| 6697 | skb_new = skb_realloc_headroom(skb, len); |
| 6698 | if (!skb_new) { |
| 6699 | rp->tx_errors++; |
| 6700 | goto out_drop; |
| 6701 | } |
| 6702 | kfree_skb(skb); |
| 6703 | skb = skb_new; |
| 6704 | } else |
| 6705 | skb_orphan(skb); |
| 6706 | |
| 6707 | align = ((unsigned long) skb->data & (16 - 1)); |
| 6708 | headroom = align + sizeof(struct tx_pkt_hdr); |
| 6709 | |
| 6710 | ehdr = (struct ethhdr *) skb->data; |
| 6711 | tp = (struct tx_pkt_hdr *) skb_push(skb, headroom); |
| 6712 | |
| 6713 | len = skb->len - sizeof(struct tx_pkt_hdr); |
| 6714 | tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len)); |
| 6715 | tp->resv = 0; |
| 6716 | |
| 6717 | len = skb_headlen(skb); |
| 6718 | mapping = np->ops->map_single(np->device, skb->data, |
| 6719 | len, DMA_TO_DEVICE); |
| 6720 | |
| 6721 | prod = rp->prod; |
| 6722 | |
| 6723 | rp->tx_buffs[prod].skb = skb; |
| 6724 | rp->tx_buffs[prod].mapping = mapping; |
| 6725 | |
| 6726 | mrk = TX_DESC_SOP; |
| 6727 | if (++rp->mark_counter == rp->mark_freq) { |
| 6728 | rp->mark_counter = 0; |
| 6729 | mrk |= TX_DESC_MARK; |
| 6730 | rp->mark_pending++; |
| 6731 | } |
| 6732 | |
| 6733 | tlen = len; |
| 6734 | nfg = skb_shinfo(skb)->nr_frags; |
| 6735 | while (tlen > 0) { |
| 6736 | tlen -= MAX_TX_DESC_LEN; |
| 6737 | nfg++; |
| 6738 | } |
| 6739 | |
| 6740 | while (len > 0) { |
| 6741 | unsigned int this_len = len; |
| 6742 | |
| 6743 | if (this_len > MAX_TX_DESC_LEN) |
| 6744 | this_len = MAX_TX_DESC_LEN; |
| 6745 | |
| 6746 | niu_set_txd(rp, prod, mapping, this_len, mrk, nfg); |
| 6747 | mrk = nfg = 0; |
| 6748 | |
| 6749 | prod = NEXT_TX(rp, prod); |
| 6750 | mapping += this_len; |
| 6751 | len -= this_len; |
| 6752 | } |
| 6753 | |
| 6754 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
| 6755 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 6756 | |
| 6757 | len = frag->size; |
| 6758 | mapping = np->ops->map_page(np->device, frag->page, |
| 6759 | frag->page_offset, len, |
| 6760 | DMA_TO_DEVICE); |
| 6761 | |
| 6762 | rp->tx_buffs[prod].skb = NULL; |
| 6763 | rp->tx_buffs[prod].mapping = mapping; |
| 6764 | |
| 6765 | niu_set_txd(rp, prod, mapping, len, 0, 0); |
| 6766 | |
| 6767 | prod = NEXT_TX(rp, prod); |
| 6768 | } |
| 6769 | |
| 6770 | if (prod < rp->prod) |
| 6771 | rp->wrap_bit ^= TX_RING_KICK_WRAP; |
| 6772 | rp->prod = prod; |
| 6773 | |
| 6774 | nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3)); |
| 6775 | |
| 6776 | if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) { |
| 6777 | netif_tx_stop_queue(txq); |
| 6778 | if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)) |
| 6779 | netif_tx_wake_queue(txq); |
| 6780 | } |
| 6781 | |
| 6782 | out: |
| 6783 | return NETDEV_TX_OK; |
| 6784 | |
| 6785 | out_drop: |
| 6786 | rp->tx_errors++; |
| 6787 | kfree_skb(skb); |
| 6788 | goto out; |
| 6789 | } |
| 6790 | |
| 6791 | static int niu_change_mtu(struct net_device *dev, int new_mtu) |
| 6792 | { |
| 6793 | struct niu *np = netdev_priv(dev); |
| 6794 | int err, orig_jumbo, new_jumbo; |
| 6795 | |
| 6796 | if (new_mtu < 68 || new_mtu > NIU_MAX_MTU) |
| 6797 | return -EINVAL; |
| 6798 | |
| 6799 | orig_jumbo = (dev->mtu > ETH_DATA_LEN); |
| 6800 | new_jumbo = (new_mtu > ETH_DATA_LEN); |
| 6801 | |
| 6802 | dev->mtu = new_mtu; |
| 6803 | |
| 6804 | if (!netif_running(dev) || |
| 6805 | (orig_jumbo == new_jumbo)) |
| 6806 | return 0; |
| 6807 | |
| 6808 | niu_full_shutdown(np, dev); |
| 6809 | |
| 6810 | niu_free_channels(np); |
| 6811 | |
| 6812 | niu_enable_napi(np); |
| 6813 | |
| 6814 | err = niu_alloc_channels(np); |
| 6815 | if (err) |
| 6816 | return err; |
| 6817 | |
| 6818 | spin_lock_irq(&np->lock); |
| 6819 | |
| 6820 | err = niu_init_hw(np); |
| 6821 | if (!err) { |
| 6822 | init_timer(&np->timer); |
| 6823 | np->timer.expires = jiffies + HZ; |
| 6824 | np->timer.data = (unsigned long) np; |
| 6825 | np->timer.function = niu_timer; |
| 6826 | |
| 6827 | err = niu_enable_interrupts(np, 1); |
| 6828 | if (err) |
| 6829 | niu_stop_hw(np); |
| 6830 | } |
| 6831 | |
| 6832 | spin_unlock_irq(&np->lock); |
| 6833 | |
| 6834 | if (!err) { |
| 6835 | netif_tx_start_all_queues(dev); |
| 6836 | if (np->link_config.loopback_mode != LOOPBACK_DISABLED) |
| 6837 | netif_carrier_on(dev); |
| 6838 | |
| 6839 | add_timer(&np->timer); |
| 6840 | } |
| 6841 | |
| 6842 | return err; |
| 6843 | } |
| 6844 | |
| 6845 | static void niu_get_drvinfo(struct net_device *dev, |
| 6846 | struct ethtool_drvinfo *info) |
| 6847 | { |
| 6848 | struct niu *np = netdev_priv(dev); |
| 6849 | struct niu_vpd *vpd = &np->vpd; |
| 6850 | |
| 6851 | strcpy(info->driver, DRV_MODULE_NAME); |
| 6852 | strcpy(info->version, DRV_MODULE_VERSION); |
| 6853 | sprintf(info->fw_version, "%d.%d", |
| 6854 | vpd->fcode_major, vpd->fcode_minor); |
| 6855 | if (np->parent->plat_type != PLAT_TYPE_NIU) |
| 6856 | strcpy(info->bus_info, pci_name(np->pdev)); |
| 6857 | } |
| 6858 | |
| 6859 | static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 6860 | { |
| 6861 | struct niu *np = netdev_priv(dev); |
| 6862 | struct niu_link_config *lp; |
| 6863 | |
| 6864 | lp = &np->link_config; |
| 6865 | |
| 6866 | memset(cmd, 0, sizeof(*cmd)); |
| 6867 | cmd->phy_address = np->phy_addr; |
| 6868 | cmd->supported = lp->supported; |
| 6869 | cmd->advertising = lp->active_advertising; |
| 6870 | cmd->autoneg = lp->active_autoneg; |
| 6871 | cmd->speed = lp->active_speed; |
| 6872 | cmd->duplex = lp->active_duplex; |
| 6873 | cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP; |
| 6874 | cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ? |
| 6875 | XCVR_EXTERNAL : XCVR_INTERNAL; |
| 6876 | |
| 6877 | return 0; |
| 6878 | } |
| 6879 | |
| 6880 | static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 6881 | { |
| 6882 | struct niu *np = netdev_priv(dev); |
| 6883 | struct niu_link_config *lp = &np->link_config; |
| 6884 | |
| 6885 | lp->advertising = cmd->advertising; |
| 6886 | lp->speed = cmd->speed; |
| 6887 | lp->duplex = cmd->duplex; |
| 6888 | lp->autoneg = cmd->autoneg; |
| 6889 | return niu_init_link(np); |
| 6890 | } |
| 6891 | |
| 6892 | static u32 niu_get_msglevel(struct net_device *dev) |
| 6893 | { |
| 6894 | struct niu *np = netdev_priv(dev); |
| 6895 | return np->msg_enable; |
| 6896 | } |
| 6897 | |
| 6898 | static void niu_set_msglevel(struct net_device *dev, u32 value) |
| 6899 | { |
| 6900 | struct niu *np = netdev_priv(dev); |
| 6901 | np->msg_enable = value; |
| 6902 | } |
| 6903 | |
| 6904 | static int niu_nway_reset(struct net_device *dev) |
| 6905 | { |
| 6906 | struct niu *np = netdev_priv(dev); |
| 6907 | |
| 6908 | if (np->link_config.autoneg) |
| 6909 | return niu_init_link(np); |
| 6910 | |
| 6911 | return 0; |
| 6912 | } |
| 6913 | |
| 6914 | static int niu_get_eeprom_len(struct net_device *dev) |
| 6915 | { |
| 6916 | struct niu *np = netdev_priv(dev); |
| 6917 | |
| 6918 | return np->eeprom_len; |
| 6919 | } |
| 6920 | |
| 6921 | static int niu_get_eeprom(struct net_device *dev, |
| 6922 | struct ethtool_eeprom *eeprom, u8 *data) |
| 6923 | { |
| 6924 | struct niu *np = netdev_priv(dev); |
| 6925 | u32 offset, len, val; |
| 6926 | |
| 6927 | offset = eeprom->offset; |
| 6928 | len = eeprom->len; |
| 6929 | |
| 6930 | if (offset + len < offset) |
| 6931 | return -EINVAL; |
| 6932 | if (offset >= np->eeprom_len) |
| 6933 | return -EINVAL; |
| 6934 | if (offset + len > np->eeprom_len) |
| 6935 | len = eeprom->len = np->eeprom_len - offset; |
| 6936 | |
| 6937 | if (offset & 3) { |
| 6938 | u32 b_offset, b_count; |
| 6939 | |
| 6940 | b_offset = offset & 3; |
| 6941 | b_count = 4 - b_offset; |
| 6942 | if (b_count > len) |
| 6943 | b_count = len; |
| 6944 | |
| 6945 | val = nr64(ESPC_NCR((offset - b_offset) / 4)); |
| 6946 | memcpy(data, ((char *)&val) + b_offset, b_count); |
| 6947 | data += b_count; |
| 6948 | len -= b_count; |
| 6949 | offset += b_count; |
| 6950 | } |
| 6951 | while (len >= 4) { |
| 6952 | val = nr64(ESPC_NCR(offset / 4)); |
| 6953 | memcpy(data, &val, 4); |
| 6954 | data += 4; |
| 6955 | len -= 4; |
| 6956 | offset += 4; |
| 6957 | } |
| 6958 | if (len) { |
| 6959 | val = nr64(ESPC_NCR(offset / 4)); |
| 6960 | memcpy(data, &val, len); |
| 6961 | } |
| 6962 | return 0; |
| 6963 | } |
| 6964 | |
| 6965 | static void niu_ethflow_to_l3proto(int flow_type, u8 *pid) |
| 6966 | { |
| 6967 | switch (flow_type) { |
| 6968 | case TCP_V4_FLOW: |
| 6969 | case TCP_V6_FLOW: |
| 6970 | *pid = IPPROTO_TCP; |
| 6971 | break; |
| 6972 | case UDP_V4_FLOW: |
| 6973 | case UDP_V6_FLOW: |
| 6974 | *pid = IPPROTO_UDP; |
| 6975 | break; |
| 6976 | case SCTP_V4_FLOW: |
| 6977 | case SCTP_V6_FLOW: |
| 6978 | *pid = IPPROTO_SCTP; |
| 6979 | break; |
| 6980 | case AH_V4_FLOW: |
| 6981 | case AH_V6_FLOW: |
| 6982 | *pid = IPPROTO_AH; |
| 6983 | break; |
| 6984 | case ESP_V4_FLOW: |
| 6985 | case ESP_V6_FLOW: |
| 6986 | *pid = IPPROTO_ESP; |
| 6987 | break; |
| 6988 | default: |
| 6989 | *pid = 0; |
| 6990 | break; |
| 6991 | } |
| 6992 | } |
| 6993 | |
| 6994 | static int niu_class_to_ethflow(u64 class, int *flow_type) |
| 6995 | { |
| 6996 | switch (class) { |
| 6997 | case CLASS_CODE_TCP_IPV4: |
| 6998 | *flow_type = TCP_V4_FLOW; |
| 6999 | break; |
| 7000 | case CLASS_CODE_UDP_IPV4: |
| 7001 | *flow_type = UDP_V4_FLOW; |
| 7002 | break; |
| 7003 | case CLASS_CODE_AH_ESP_IPV4: |
| 7004 | *flow_type = AH_V4_FLOW; |
| 7005 | break; |
| 7006 | case CLASS_CODE_SCTP_IPV4: |
| 7007 | *flow_type = SCTP_V4_FLOW; |
| 7008 | break; |
| 7009 | case CLASS_CODE_TCP_IPV6: |
| 7010 | *flow_type = TCP_V6_FLOW; |
| 7011 | break; |
| 7012 | case CLASS_CODE_UDP_IPV6: |
| 7013 | *flow_type = UDP_V6_FLOW; |
| 7014 | break; |
| 7015 | case CLASS_CODE_AH_ESP_IPV6: |
| 7016 | *flow_type = AH_V6_FLOW; |
| 7017 | break; |
| 7018 | case CLASS_CODE_SCTP_IPV6: |
| 7019 | *flow_type = SCTP_V6_FLOW; |
| 7020 | break; |
| 7021 | case CLASS_CODE_USER_PROG1: |
| 7022 | case CLASS_CODE_USER_PROG2: |
| 7023 | case CLASS_CODE_USER_PROG3: |
| 7024 | case CLASS_CODE_USER_PROG4: |
| 7025 | *flow_type = IP_USER_FLOW; |
| 7026 | break; |
| 7027 | default: |
| 7028 | return 0; |
| 7029 | } |
| 7030 | |
| 7031 | return 1; |
| 7032 | } |
| 7033 | |
| 7034 | static int niu_ethflow_to_class(int flow_type, u64 *class) |
| 7035 | { |
| 7036 | switch (flow_type) { |
| 7037 | case TCP_V4_FLOW: |
| 7038 | *class = CLASS_CODE_TCP_IPV4; |
| 7039 | break; |
| 7040 | case UDP_V4_FLOW: |
| 7041 | *class = CLASS_CODE_UDP_IPV4; |
| 7042 | break; |
| 7043 | case AH_V4_FLOW: |
| 7044 | case ESP_V4_FLOW: |
| 7045 | *class = CLASS_CODE_AH_ESP_IPV4; |
| 7046 | break; |
| 7047 | case SCTP_V4_FLOW: |
| 7048 | *class = CLASS_CODE_SCTP_IPV4; |
| 7049 | break; |
| 7050 | case TCP_V6_FLOW: |
| 7051 | *class = CLASS_CODE_TCP_IPV6; |
| 7052 | break; |
| 7053 | case UDP_V6_FLOW: |
| 7054 | *class = CLASS_CODE_UDP_IPV6; |
| 7055 | break; |
| 7056 | case AH_V6_FLOW: |
| 7057 | case ESP_V6_FLOW: |
| 7058 | *class = CLASS_CODE_AH_ESP_IPV6; |
| 7059 | break; |
| 7060 | case SCTP_V6_FLOW: |
| 7061 | *class = CLASS_CODE_SCTP_IPV6; |
| 7062 | break; |
| 7063 | default: |
| 7064 | return 0; |
| 7065 | } |
| 7066 | |
| 7067 | return 1; |
| 7068 | } |
| 7069 | |
| 7070 | static u64 niu_flowkey_to_ethflow(u64 flow_key) |
| 7071 | { |
| 7072 | u64 ethflow = 0; |
| 7073 | |
| 7074 | if (flow_key & FLOW_KEY_L2DA) |
| 7075 | ethflow |= RXH_L2DA; |
| 7076 | if (flow_key & FLOW_KEY_VLAN) |
| 7077 | ethflow |= RXH_VLAN; |
| 7078 | if (flow_key & FLOW_KEY_IPSA) |
| 7079 | ethflow |= RXH_IP_SRC; |
| 7080 | if (flow_key & FLOW_KEY_IPDA) |
| 7081 | ethflow |= RXH_IP_DST; |
| 7082 | if (flow_key & FLOW_KEY_PROTO) |
| 7083 | ethflow |= RXH_L3_PROTO; |
| 7084 | if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT)) |
| 7085 | ethflow |= RXH_L4_B_0_1; |
| 7086 | if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT)) |
| 7087 | ethflow |= RXH_L4_B_2_3; |
| 7088 | |
| 7089 | return ethflow; |
| 7090 | |
| 7091 | } |
| 7092 | |
| 7093 | static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key) |
| 7094 | { |
| 7095 | u64 key = 0; |
| 7096 | |
| 7097 | if (ethflow & RXH_L2DA) |
| 7098 | key |= FLOW_KEY_L2DA; |
| 7099 | if (ethflow & RXH_VLAN) |
| 7100 | key |= FLOW_KEY_VLAN; |
| 7101 | if (ethflow & RXH_IP_SRC) |
| 7102 | key |= FLOW_KEY_IPSA; |
| 7103 | if (ethflow & RXH_IP_DST) |
| 7104 | key |= FLOW_KEY_IPDA; |
| 7105 | if (ethflow & RXH_L3_PROTO) |
| 7106 | key |= FLOW_KEY_PROTO; |
| 7107 | if (ethflow & RXH_L4_B_0_1) |
| 7108 | key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT); |
| 7109 | if (ethflow & RXH_L4_B_2_3) |
| 7110 | key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT); |
| 7111 | |
| 7112 | *flow_key = key; |
| 7113 | |
| 7114 | return 1; |
| 7115 | |
| 7116 | } |
| 7117 | |
| 7118 | static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc) |
| 7119 | { |
| 7120 | u64 class; |
| 7121 | |
| 7122 | nfc->data = 0; |
| 7123 | |
| 7124 | if (!niu_ethflow_to_class(nfc->flow_type, &class)) |
| 7125 | return -EINVAL; |
| 7126 | |
| 7127 | if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & |
| 7128 | TCAM_KEY_DISC) |
| 7129 | nfc->data = RXH_DISCARD; |
| 7130 | else |
| 7131 | nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class - |
| 7132 | CLASS_CODE_USER_PROG1]); |
| 7133 | return 0; |
| 7134 | } |
| 7135 | |
| 7136 | static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp, |
| 7137 | struct ethtool_rx_flow_spec *fsp) |
| 7138 | { |
| 7139 | |
| 7140 | fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >> |
| 7141 | TCAM_V4KEY3_SADDR_SHIFT; |
| 7142 | fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >> |
| 7143 | TCAM_V4KEY3_DADDR_SHIFT; |
| 7144 | fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> |
| 7145 | TCAM_V4KEY3_SADDR_SHIFT; |
| 7146 | fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> |
| 7147 | TCAM_V4KEY3_DADDR_SHIFT; |
| 7148 | |
| 7149 | fsp->h_u.tcp_ip4_spec.ip4src = |
| 7150 | cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src); |
| 7151 | fsp->m_u.tcp_ip4_spec.ip4src = |
| 7152 | cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src); |
| 7153 | fsp->h_u.tcp_ip4_spec.ip4dst = |
| 7154 | cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst); |
| 7155 | fsp->m_u.tcp_ip4_spec.ip4dst = |
| 7156 | cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst); |
| 7157 | |
| 7158 | fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >> |
| 7159 | TCAM_V4KEY2_TOS_SHIFT; |
| 7160 | fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >> |
| 7161 | TCAM_V4KEY2_TOS_SHIFT; |
| 7162 | |
| 7163 | switch (fsp->flow_type) { |
| 7164 | case TCP_V4_FLOW: |
| 7165 | case UDP_V4_FLOW: |
| 7166 | case SCTP_V4_FLOW: |
| 7167 | fsp->h_u.tcp_ip4_spec.psrc = |
| 7168 | ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> |
| 7169 | TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; |
| 7170 | fsp->h_u.tcp_ip4_spec.pdst = |
| 7171 | ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> |
| 7172 | TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; |
| 7173 | fsp->m_u.tcp_ip4_spec.psrc = |
| 7174 | ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> |
| 7175 | TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; |
| 7176 | fsp->m_u.tcp_ip4_spec.pdst = |
| 7177 | ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> |
| 7178 | TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; |
| 7179 | |
| 7180 | fsp->h_u.tcp_ip4_spec.psrc = |
| 7181 | cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc); |
| 7182 | fsp->h_u.tcp_ip4_spec.pdst = |
| 7183 | cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst); |
| 7184 | fsp->m_u.tcp_ip4_spec.psrc = |
| 7185 | cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc); |
| 7186 | fsp->m_u.tcp_ip4_spec.pdst = |
| 7187 | cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst); |
| 7188 | break; |
| 7189 | case AH_V4_FLOW: |
| 7190 | case ESP_V4_FLOW: |
| 7191 | fsp->h_u.ah_ip4_spec.spi = |
| 7192 | (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> |
| 7193 | TCAM_V4KEY2_PORT_SPI_SHIFT; |
| 7194 | fsp->m_u.ah_ip4_spec.spi = |
| 7195 | (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> |
| 7196 | TCAM_V4KEY2_PORT_SPI_SHIFT; |
| 7197 | |
| 7198 | fsp->h_u.ah_ip4_spec.spi = |
| 7199 | cpu_to_be32(fsp->h_u.ah_ip4_spec.spi); |
| 7200 | fsp->m_u.ah_ip4_spec.spi = |
| 7201 | cpu_to_be32(fsp->m_u.ah_ip4_spec.spi); |
| 7202 | break; |
| 7203 | case IP_USER_FLOW: |
| 7204 | fsp->h_u.usr_ip4_spec.l4_4_bytes = |
| 7205 | (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> |
| 7206 | TCAM_V4KEY2_PORT_SPI_SHIFT; |
| 7207 | fsp->m_u.usr_ip4_spec.l4_4_bytes = |
| 7208 | (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> |
| 7209 | TCAM_V4KEY2_PORT_SPI_SHIFT; |
| 7210 | |
| 7211 | fsp->h_u.usr_ip4_spec.l4_4_bytes = |
| 7212 | cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes); |
| 7213 | fsp->m_u.usr_ip4_spec.l4_4_bytes = |
| 7214 | cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes); |
| 7215 | |
| 7216 | fsp->h_u.usr_ip4_spec.proto = |
| 7217 | (tp->key[2] & TCAM_V4KEY2_PROTO) >> |
| 7218 | TCAM_V4KEY2_PROTO_SHIFT; |
| 7219 | fsp->m_u.usr_ip4_spec.proto = |
| 7220 | (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >> |
| 7221 | TCAM_V4KEY2_PROTO_SHIFT; |
| 7222 | |
| 7223 | fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; |
| 7224 | break; |
| 7225 | default: |
| 7226 | break; |
| 7227 | } |
| 7228 | } |
| 7229 | |
| 7230 | static int niu_get_ethtool_tcam_entry(struct niu *np, |
| 7231 | struct ethtool_rxnfc *nfc) |
| 7232 | { |
| 7233 | struct niu_parent *parent = np->parent; |
| 7234 | struct niu_tcam_entry *tp; |
| 7235 | struct ethtool_rx_flow_spec *fsp = &nfc->fs; |
| 7236 | u16 idx; |
| 7237 | u64 class; |
| 7238 | int ret = 0; |
| 7239 | |
| 7240 | idx = tcam_get_index(np, (u16)nfc->fs.location); |
| 7241 | |
| 7242 | tp = &parent->tcam[idx]; |
| 7243 | if (!tp->valid) { |
| 7244 | pr_info(PFX "niu%d: %s entry [%d] invalid for idx[%d]\n", |
| 7245 | parent->index, np->dev->name, (u16)nfc->fs.location, idx); |
| 7246 | return -EINVAL; |
| 7247 | } |
| 7248 | |
| 7249 | /* fill the flow spec entry */ |
| 7250 | class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> |
| 7251 | TCAM_V4KEY0_CLASS_CODE_SHIFT; |
| 7252 | ret = niu_class_to_ethflow(class, &fsp->flow_type); |
| 7253 | |
| 7254 | if (ret < 0) { |
| 7255 | pr_info(PFX "niu%d: %s niu_class_to_ethflow failed\n", |
| 7256 | parent->index, np->dev->name); |
| 7257 | ret = -EINVAL; |
| 7258 | goto out; |
| 7259 | } |
| 7260 | |
| 7261 | if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) { |
| 7262 | u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >> |
| 7263 | TCAM_V4KEY2_PROTO_SHIFT; |
| 7264 | if (proto == IPPROTO_ESP) { |
| 7265 | if (fsp->flow_type == AH_V4_FLOW) |
| 7266 | fsp->flow_type = ESP_V4_FLOW; |
| 7267 | else |
| 7268 | fsp->flow_type = ESP_V6_FLOW; |
| 7269 | } |
| 7270 | } |
| 7271 | |
| 7272 | switch (fsp->flow_type) { |
| 7273 | case TCP_V4_FLOW: |
| 7274 | case UDP_V4_FLOW: |
| 7275 | case SCTP_V4_FLOW: |
| 7276 | case AH_V4_FLOW: |
| 7277 | case ESP_V4_FLOW: |
| 7278 | niu_get_ip4fs_from_tcam_key(tp, fsp); |
| 7279 | break; |
| 7280 | case TCP_V6_FLOW: |
| 7281 | case UDP_V6_FLOW: |
| 7282 | case SCTP_V6_FLOW: |
| 7283 | case AH_V6_FLOW: |
| 7284 | case ESP_V6_FLOW: |
| 7285 | /* Not yet implemented */ |
| 7286 | ret = -EINVAL; |
| 7287 | break; |
| 7288 | case IP_USER_FLOW: |
| 7289 | niu_get_ip4fs_from_tcam_key(tp, fsp); |
| 7290 | break; |
| 7291 | default: |
| 7292 | ret = -EINVAL; |
| 7293 | break; |
| 7294 | } |
| 7295 | |
| 7296 | if (ret < 0) |
| 7297 | goto out; |
| 7298 | |
| 7299 | if (tp->assoc_data & TCAM_ASSOCDATA_DISC) |
| 7300 | fsp->ring_cookie = RX_CLS_FLOW_DISC; |
| 7301 | else |
| 7302 | fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >> |
| 7303 | TCAM_ASSOCDATA_OFFSET_SHIFT; |
| 7304 | |
| 7305 | /* put the tcam size here */ |
| 7306 | nfc->data = tcam_get_size(np); |
| 7307 | out: |
| 7308 | return ret; |
| 7309 | } |
| 7310 | |
| 7311 | static int niu_get_ethtool_tcam_all(struct niu *np, |
| 7312 | struct ethtool_rxnfc *nfc, |
| 7313 | u32 *rule_locs) |
| 7314 | { |
| 7315 | struct niu_parent *parent = np->parent; |
| 7316 | struct niu_tcam_entry *tp; |
| 7317 | int i, idx, cnt; |
| 7318 | u16 n_entries; |
| 7319 | unsigned long flags; |
| 7320 | |
| 7321 | |
| 7322 | /* put the tcam size here */ |
| 7323 | nfc->data = tcam_get_size(np); |
| 7324 | |
| 7325 | niu_lock_parent(np, flags); |
| 7326 | n_entries = nfc->rule_cnt; |
| 7327 | for (cnt = 0, i = 0; i < nfc->data; i++) { |
| 7328 | idx = tcam_get_index(np, i); |
| 7329 | tp = &parent->tcam[idx]; |
| 7330 | if (!tp->valid) |
| 7331 | continue; |
| 7332 | rule_locs[cnt] = i; |
| 7333 | cnt++; |
| 7334 | } |
| 7335 | niu_unlock_parent(np, flags); |
| 7336 | |
| 7337 | if (n_entries != cnt) { |
| 7338 | /* print warning, this should not happen */ |
| 7339 | pr_info(PFX "niu%d: %s In niu_get_ethtool_tcam_all, " |
| 7340 | "n_entries[%d] != cnt[%d]!!!\n\n", |
| 7341 | np->parent->index, np->dev->name, n_entries, cnt); |
| 7342 | } |
| 7343 | |
| 7344 | return 0; |
| 7345 | } |
| 7346 | |
| 7347 | static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd, |
| 7348 | void *rule_locs) |
| 7349 | { |
| 7350 | struct niu *np = netdev_priv(dev); |
| 7351 | int ret = 0; |
| 7352 | |
| 7353 | switch (cmd->cmd) { |
| 7354 | case ETHTOOL_GRXFH: |
| 7355 | ret = niu_get_hash_opts(np, cmd); |
| 7356 | break; |
| 7357 | case ETHTOOL_GRXRINGS: |
| 7358 | cmd->data = np->num_rx_rings; |
| 7359 | break; |
| 7360 | case ETHTOOL_GRXCLSRLCNT: |
| 7361 | cmd->rule_cnt = tcam_get_valid_entry_cnt(np); |
| 7362 | break; |
| 7363 | case ETHTOOL_GRXCLSRULE: |
| 7364 | ret = niu_get_ethtool_tcam_entry(np, cmd); |
| 7365 | break; |
| 7366 | case ETHTOOL_GRXCLSRLALL: |
| 7367 | ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs); |
| 7368 | break; |
| 7369 | default: |
| 7370 | ret = -EINVAL; |
| 7371 | break; |
| 7372 | } |
| 7373 | |
| 7374 | return ret; |
| 7375 | } |
| 7376 | |
| 7377 | static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc) |
| 7378 | { |
| 7379 | u64 class; |
| 7380 | u64 flow_key = 0; |
| 7381 | unsigned long flags; |
| 7382 | |
| 7383 | if (!niu_ethflow_to_class(nfc->flow_type, &class)) |
| 7384 | return -EINVAL; |
| 7385 | |
| 7386 | if (class < CLASS_CODE_USER_PROG1 || |
| 7387 | class > CLASS_CODE_SCTP_IPV6) |
| 7388 | return -EINVAL; |
| 7389 | |
| 7390 | if (nfc->data & RXH_DISCARD) { |
| 7391 | niu_lock_parent(np, flags); |
| 7392 | flow_key = np->parent->tcam_key[class - |
| 7393 | CLASS_CODE_USER_PROG1]; |
| 7394 | flow_key |= TCAM_KEY_DISC; |
| 7395 | nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key); |
| 7396 | np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key; |
| 7397 | niu_unlock_parent(np, flags); |
| 7398 | return 0; |
| 7399 | } else { |
| 7400 | /* Discard was set before, but is not set now */ |
| 7401 | if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & |
| 7402 | TCAM_KEY_DISC) { |
| 7403 | niu_lock_parent(np, flags); |
| 7404 | flow_key = np->parent->tcam_key[class - |
| 7405 | CLASS_CODE_USER_PROG1]; |
| 7406 | flow_key &= ~TCAM_KEY_DISC; |
| 7407 | nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), |
| 7408 | flow_key); |
| 7409 | np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = |
| 7410 | flow_key; |
| 7411 | niu_unlock_parent(np, flags); |
| 7412 | } |
| 7413 | } |
| 7414 | |
| 7415 | if (!niu_ethflow_to_flowkey(nfc->data, &flow_key)) |
| 7416 | return -EINVAL; |
| 7417 | |
| 7418 | niu_lock_parent(np, flags); |
| 7419 | nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key); |
| 7420 | np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key; |
| 7421 | niu_unlock_parent(np, flags); |
| 7422 | |
| 7423 | return 0; |
| 7424 | } |
| 7425 | |
| 7426 | static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp, |
| 7427 | struct niu_tcam_entry *tp, |
| 7428 | int l2_rdc_tab, u64 class) |
| 7429 | { |
| 7430 | u8 pid = 0; |
| 7431 | u32 sip, dip, sipm, dipm, spi, spim; |
| 7432 | u16 sport, dport, spm, dpm; |
| 7433 | |
| 7434 | sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src); |
| 7435 | sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src); |
| 7436 | dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst); |
| 7437 | dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst); |
| 7438 | |
| 7439 | tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT; |
| 7440 | tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE; |
| 7441 | tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT; |
| 7442 | tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM; |
| 7443 | |
| 7444 | tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT; |
| 7445 | tp->key[3] |= dip; |
| 7446 | |
| 7447 | tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT; |
| 7448 | tp->key_mask[3] |= dipm; |
| 7449 | |
| 7450 | tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos << |
| 7451 | TCAM_V4KEY2_TOS_SHIFT); |
| 7452 | tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos << |
| 7453 | TCAM_V4KEY2_TOS_SHIFT); |
| 7454 | switch (fsp->flow_type) { |
| 7455 | case TCP_V4_FLOW: |
| 7456 | case UDP_V4_FLOW: |
| 7457 | case SCTP_V4_FLOW: |
| 7458 | sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc); |
| 7459 | spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc); |
| 7460 | dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst); |
| 7461 | dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst); |
| 7462 | |
| 7463 | tp->key[2] |= (((u64)sport << 16) | dport); |
| 7464 | tp->key_mask[2] |= (((u64)spm << 16) | dpm); |
| 7465 | niu_ethflow_to_l3proto(fsp->flow_type, &pid); |
| 7466 | break; |
| 7467 | case AH_V4_FLOW: |
| 7468 | case ESP_V4_FLOW: |
| 7469 | spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi); |
| 7470 | spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi); |
| 7471 | |
| 7472 | tp->key[2] |= spi; |
| 7473 | tp->key_mask[2] |= spim; |
| 7474 | niu_ethflow_to_l3proto(fsp->flow_type, &pid); |
| 7475 | break; |
| 7476 | case IP_USER_FLOW: |
| 7477 | spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes); |
| 7478 | spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes); |
| 7479 | |
| 7480 | tp->key[2] |= spi; |
| 7481 | tp->key_mask[2] |= spim; |
| 7482 | pid = fsp->h_u.usr_ip4_spec.proto; |
| 7483 | break; |
| 7484 | default: |
| 7485 | break; |
| 7486 | } |
| 7487 | |
| 7488 | tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT); |
| 7489 | if (pid) { |
| 7490 | tp->key_mask[2] |= TCAM_V4KEY2_PROTO; |
| 7491 | } |
| 7492 | } |
| 7493 | |
| 7494 | static int niu_add_ethtool_tcam_entry(struct niu *np, |
| 7495 | struct ethtool_rxnfc *nfc) |
| 7496 | { |
| 7497 | struct niu_parent *parent = np->parent; |
| 7498 | struct niu_tcam_entry *tp; |
| 7499 | struct ethtool_rx_flow_spec *fsp = &nfc->fs; |
| 7500 | struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port]; |
| 7501 | int l2_rdc_table = rdc_table->first_table_num; |
| 7502 | u16 idx; |
| 7503 | u64 class; |
| 7504 | unsigned long flags; |
| 7505 | int err, ret; |
| 7506 | |
| 7507 | ret = 0; |
| 7508 | |
| 7509 | idx = nfc->fs.location; |
| 7510 | if (idx >= tcam_get_size(np)) |
| 7511 | return -EINVAL; |
| 7512 | |
| 7513 | if (fsp->flow_type == IP_USER_FLOW) { |
| 7514 | int i; |
| 7515 | int add_usr_cls = 0; |
| 7516 | int ipv6 = 0; |
| 7517 | struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec; |
| 7518 | struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec; |
| 7519 | |
| 7520 | niu_lock_parent(np, flags); |
| 7521 | |
| 7522 | for (i = 0; i < NIU_L3_PROG_CLS; i++) { |
| 7523 | if (parent->l3_cls[i]) { |
| 7524 | if (uspec->proto == parent->l3_cls_pid[i]) { |
| 7525 | class = parent->l3_cls[i]; |
| 7526 | parent->l3_cls_refcnt[i]++; |
| 7527 | add_usr_cls = 1; |
| 7528 | break; |
| 7529 | } |
| 7530 | } else { |
| 7531 | /* Program new user IP class */ |
| 7532 | switch (i) { |
| 7533 | case 0: |
| 7534 | class = CLASS_CODE_USER_PROG1; |
| 7535 | break; |
| 7536 | case 1: |
| 7537 | class = CLASS_CODE_USER_PROG2; |
| 7538 | break; |
| 7539 | case 2: |
| 7540 | class = CLASS_CODE_USER_PROG3; |
| 7541 | break; |
| 7542 | case 3: |
| 7543 | class = CLASS_CODE_USER_PROG4; |
| 7544 | break; |
| 7545 | default: |
| 7546 | break; |
| 7547 | } |
| 7548 | if (uspec->ip_ver == ETH_RX_NFC_IP6) |
| 7549 | ipv6 = 1; |
| 7550 | ret = tcam_user_ip_class_set(np, class, ipv6, |
| 7551 | uspec->proto, |
| 7552 | uspec->tos, |
| 7553 | umask->tos); |
| 7554 | if (ret) |
| 7555 | goto out; |
| 7556 | |
| 7557 | ret = tcam_user_ip_class_enable(np, class, 1); |
| 7558 | if (ret) |
| 7559 | goto out; |
| 7560 | parent->l3_cls[i] = class; |
| 7561 | parent->l3_cls_pid[i] = uspec->proto; |
| 7562 | parent->l3_cls_refcnt[i]++; |
| 7563 | add_usr_cls = 1; |
| 7564 | break; |
| 7565 | } |
| 7566 | } |
| 7567 | if (!add_usr_cls) { |
| 7568 | pr_info(PFX "niu%d: %s niu_add_ethtool_tcam_entry: " |
| 7569 | "Could not find/insert class for pid %d\n", |
| 7570 | parent->index, np->dev->name, uspec->proto); |
| 7571 | ret = -EINVAL; |
| 7572 | goto out; |
| 7573 | } |
| 7574 | niu_unlock_parent(np, flags); |
| 7575 | } else { |
| 7576 | if (!niu_ethflow_to_class(fsp->flow_type, &class)) { |
| 7577 | return -EINVAL; |
| 7578 | } |
| 7579 | } |
| 7580 | |
| 7581 | niu_lock_parent(np, flags); |
| 7582 | |
| 7583 | idx = tcam_get_index(np, idx); |
| 7584 | tp = &parent->tcam[idx]; |
| 7585 | |
| 7586 | memset(tp, 0, sizeof(*tp)); |
| 7587 | |
| 7588 | /* fill in the tcam key and mask */ |
| 7589 | switch (fsp->flow_type) { |
| 7590 | case TCP_V4_FLOW: |
| 7591 | case UDP_V4_FLOW: |
| 7592 | case SCTP_V4_FLOW: |
| 7593 | case AH_V4_FLOW: |
| 7594 | case ESP_V4_FLOW: |
| 7595 | niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class); |
| 7596 | break; |
| 7597 | case TCP_V6_FLOW: |
| 7598 | case UDP_V6_FLOW: |
| 7599 | case SCTP_V6_FLOW: |
| 7600 | case AH_V6_FLOW: |
| 7601 | case ESP_V6_FLOW: |
| 7602 | /* Not yet implemented */ |
| 7603 | pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: " |
| 7604 | "flow %d for IPv6 not implemented\n\n", |
| 7605 | parent->index, np->dev->name, fsp->flow_type); |
| 7606 | ret = -EINVAL; |
| 7607 | goto out; |
| 7608 | case IP_USER_FLOW: |
| 7609 | if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) { |
| 7610 | niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, |
| 7611 | class); |
| 7612 | } else { |
| 7613 | /* Not yet implemented */ |
| 7614 | pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: " |
| 7615 | "usr flow for IPv6 not implemented\n\n", |
| 7616 | parent->index, np->dev->name); |
| 7617 | ret = -EINVAL; |
| 7618 | goto out; |
| 7619 | } |
| 7620 | break; |
| 7621 | default: |
| 7622 | pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: " |
| 7623 | "Unknown flow type %d\n\n", |
| 7624 | parent->index, np->dev->name, fsp->flow_type); |
| 7625 | ret = -EINVAL; |
| 7626 | goto out; |
| 7627 | } |
| 7628 | |
| 7629 | /* fill in the assoc data */ |
| 7630 | if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { |
| 7631 | tp->assoc_data = TCAM_ASSOCDATA_DISC; |
| 7632 | } else { |
| 7633 | if (fsp->ring_cookie >= np->num_rx_rings) { |
| 7634 | pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: " |
| 7635 | "Invalid RX ring %lld\n\n", |
| 7636 | parent->index, np->dev->name, |
| 7637 | (long long) fsp->ring_cookie); |
| 7638 | ret = -EINVAL; |
| 7639 | goto out; |
| 7640 | } |
| 7641 | tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | |
| 7642 | (fsp->ring_cookie << |
| 7643 | TCAM_ASSOCDATA_OFFSET_SHIFT)); |
| 7644 | } |
| 7645 | |
| 7646 | err = tcam_write(np, idx, tp->key, tp->key_mask); |
| 7647 | if (err) { |
| 7648 | ret = -EINVAL; |
| 7649 | goto out; |
| 7650 | } |
| 7651 | err = tcam_assoc_write(np, idx, tp->assoc_data); |
| 7652 | if (err) { |
| 7653 | ret = -EINVAL; |
| 7654 | goto out; |
| 7655 | } |
| 7656 | |
| 7657 | /* validate the entry */ |
| 7658 | tp->valid = 1; |
| 7659 | np->clas.tcam_valid_entries++; |
| 7660 | out: |
| 7661 | niu_unlock_parent(np, flags); |
| 7662 | |
| 7663 | return ret; |
| 7664 | } |
| 7665 | |
| 7666 | static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc) |
| 7667 | { |
| 7668 | struct niu_parent *parent = np->parent; |
| 7669 | struct niu_tcam_entry *tp; |
| 7670 | u16 idx; |
| 7671 | unsigned long flags; |
| 7672 | u64 class; |
| 7673 | int ret = 0; |
| 7674 | |
| 7675 | if (loc >= tcam_get_size(np)) |
| 7676 | return -EINVAL; |
| 7677 | |
| 7678 | niu_lock_parent(np, flags); |
| 7679 | |
| 7680 | idx = tcam_get_index(np, loc); |
| 7681 | tp = &parent->tcam[idx]; |
| 7682 | |
| 7683 | /* if the entry is of a user defined class, then update*/ |
| 7684 | class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> |
| 7685 | TCAM_V4KEY0_CLASS_CODE_SHIFT; |
| 7686 | |
| 7687 | if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) { |
| 7688 | int i; |
| 7689 | for (i = 0; i < NIU_L3_PROG_CLS; i++) { |
| 7690 | if (parent->l3_cls[i] == class) { |
| 7691 | parent->l3_cls_refcnt[i]--; |
| 7692 | if (!parent->l3_cls_refcnt[i]) { |
| 7693 | /* disable class */ |
| 7694 | ret = tcam_user_ip_class_enable(np, |
| 7695 | class, |
| 7696 | 0); |
| 7697 | if (ret) |
| 7698 | goto out; |
| 7699 | parent->l3_cls[i] = 0; |
| 7700 | parent->l3_cls_pid[i] = 0; |
| 7701 | } |
| 7702 | break; |
| 7703 | } |
| 7704 | } |
| 7705 | if (i == NIU_L3_PROG_CLS) { |
| 7706 | pr_info(PFX "niu%d: %s In niu_del_ethtool_tcam_entry," |
| 7707 | "Usr class 0x%llx not found \n", |
| 7708 | parent->index, np->dev->name, |
| 7709 | (unsigned long long) class); |
| 7710 | ret = -EINVAL; |
| 7711 | goto out; |
| 7712 | } |
| 7713 | } |
| 7714 | |
| 7715 | ret = tcam_flush(np, idx); |
| 7716 | if (ret) |
| 7717 | goto out; |
| 7718 | |
| 7719 | /* invalidate the entry */ |
| 7720 | tp->valid = 0; |
| 7721 | np->clas.tcam_valid_entries--; |
| 7722 | out: |
| 7723 | niu_unlock_parent(np, flags); |
| 7724 | |
| 7725 | return ret; |
| 7726 | } |
| 7727 | |
| 7728 | static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd) |
| 7729 | { |
| 7730 | struct niu *np = netdev_priv(dev); |
| 7731 | int ret = 0; |
| 7732 | |
| 7733 | switch (cmd->cmd) { |
| 7734 | case ETHTOOL_SRXFH: |
| 7735 | ret = niu_set_hash_opts(np, cmd); |
| 7736 | break; |
| 7737 | case ETHTOOL_SRXCLSRLINS: |
| 7738 | ret = niu_add_ethtool_tcam_entry(np, cmd); |
| 7739 | break; |
| 7740 | case ETHTOOL_SRXCLSRLDEL: |
| 7741 | ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location); |
| 7742 | break; |
| 7743 | default: |
| 7744 | ret = -EINVAL; |
| 7745 | break; |
| 7746 | } |
| 7747 | |
| 7748 | return ret; |
| 7749 | } |
| 7750 | |
| 7751 | static const struct { |
| 7752 | const char string[ETH_GSTRING_LEN]; |
| 7753 | } niu_xmac_stat_keys[] = { |
| 7754 | { "tx_frames" }, |
| 7755 | { "tx_bytes" }, |
| 7756 | { "tx_fifo_errors" }, |
| 7757 | { "tx_overflow_errors" }, |
| 7758 | { "tx_max_pkt_size_errors" }, |
| 7759 | { "tx_underflow_errors" }, |
| 7760 | { "rx_local_faults" }, |
| 7761 | { "rx_remote_faults" }, |
| 7762 | { "rx_link_faults" }, |
| 7763 | { "rx_align_errors" }, |
| 7764 | { "rx_frags" }, |
| 7765 | { "rx_mcasts" }, |
| 7766 | { "rx_bcasts" }, |
| 7767 | { "rx_hist_cnt1" }, |
| 7768 | { "rx_hist_cnt2" }, |
| 7769 | { "rx_hist_cnt3" }, |
| 7770 | { "rx_hist_cnt4" }, |
| 7771 | { "rx_hist_cnt5" }, |
| 7772 | { "rx_hist_cnt6" }, |
| 7773 | { "rx_hist_cnt7" }, |
| 7774 | { "rx_octets" }, |
| 7775 | { "rx_code_violations" }, |
| 7776 | { "rx_len_errors" }, |
| 7777 | { "rx_crc_errors" }, |
| 7778 | { "rx_underflows" }, |
| 7779 | { "rx_overflows" }, |
| 7780 | { "pause_off_state" }, |
| 7781 | { "pause_on_state" }, |
| 7782 | { "pause_received" }, |
| 7783 | }; |
| 7784 | |
| 7785 | #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys) |
| 7786 | |
| 7787 | static const struct { |
| 7788 | const char string[ETH_GSTRING_LEN]; |
| 7789 | } niu_bmac_stat_keys[] = { |
| 7790 | { "tx_underflow_errors" }, |
| 7791 | { "tx_max_pkt_size_errors" }, |
| 7792 | { "tx_bytes" }, |
| 7793 | { "tx_frames" }, |
| 7794 | { "rx_overflows" }, |
| 7795 | { "rx_frames" }, |
| 7796 | { "rx_align_errors" }, |
| 7797 | { "rx_crc_errors" }, |
| 7798 | { "rx_len_errors" }, |
| 7799 | { "pause_off_state" }, |
| 7800 | { "pause_on_state" }, |
| 7801 | { "pause_received" }, |
| 7802 | }; |
| 7803 | |
| 7804 | #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys) |
| 7805 | |
| 7806 | static const struct { |
| 7807 | const char string[ETH_GSTRING_LEN]; |
| 7808 | } niu_rxchan_stat_keys[] = { |
| 7809 | { "rx_channel" }, |
| 7810 | { "rx_packets" }, |
| 7811 | { "rx_bytes" }, |
| 7812 | { "rx_dropped" }, |
| 7813 | { "rx_errors" }, |
| 7814 | }; |
| 7815 | |
| 7816 | #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys) |
| 7817 | |
| 7818 | static const struct { |
| 7819 | const char string[ETH_GSTRING_LEN]; |
| 7820 | } niu_txchan_stat_keys[] = { |
| 7821 | { "tx_channel" }, |
| 7822 | { "tx_packets" }, |
| 7823 | { "tx_bytes" }, |
| 7824 | { "tx_errors" }, |
| 7825 | }; |
| 7826 | |
| 7827 | #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys) |
| 7828 | |
| 7829 | static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
| 7830 | { |
| 7831 | struct niu *np = netdev_priv(dev); |
| 7832 | int i; |
| 7833 | |
| 7834 | if (stringset != ETH_SS_STATS) |
| 7835 | return; |
| 7836 | |
| 7837 | if (np->flags & NIU_FLAGS_XMAC) { |
| 7838 | memcpy(data, niu_xmac_stat_keys, |
| 7839 | sizeof(niu_xmac_stat_keys)); |
| 7840 | data += sizeof(niu_xmac_stat_keys); |
| 7841 | } else { |
| 7842 | memcpy(data, niu_bmac_stat_keys, |
| 7843 | sizeof(niu_bmac_stat_keys)); |
| 7844 | data += sizeof(niu_bmac_stat_keys); |
| 7845 | } |
| 7846 | for (i = 0; i < np->num_rx_rings; i++) { |
| 7847 | memcpy(data, niu_rxchan_stat_keys, |
| 7848 | sizeof(niu_rxchan_stat_keys)); |
| 7849 | data += sizeof(niu_rxchan_stat_keys); |
| 7850 | } |
| 7851 | for (i = 0; i < np->num_tx_rings; i++) { |
| 7852 | memcpy(data, niu_txchan_stat_keys, |
| 7853 | sizeof(niu_txchan_stat_keys)); |
| 7854 | data += sizeof(niu_txchan_stat_keys); |
| 7855 | } |
| 7856 | } |
| 7857 | |
| 7858 | static int niu_get_stats_count(struct net_device *dev) |
| 7859 | { |
| 7860 | struct niu *np = netdev_priv(dev); |
| 7861 | |
| 7862 | return ((np->flags & NIU_FLAGS_XMAC ? |
| 7863 | NUM_XMAC_STAT_KEYS : |
| 7864 | NUM_BMAC_STAT_KEYS) + |
| 7865 | (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) + |
| 7866 | (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS)); |
| 7867 | } |
| 7868 | |
| 7869 | static void niu_get_ethtool_stats(struct net_device *dev, |
| 7870 | struct ethtool_stats *stats, u64 *data) |
| 7871 | { |
| 7872 | struct niu *np = netdev_priv(dev); |
| 7873 | int i; |
| 7874 | |
| 7875 | niu_sync_mac_stats(np); |
| 7876 | if (np->flags & NIU_FLAGS_XMAC) { |
| 7877 | memcpy(data, &np->mac_stats.xmac, |
| 7878 | sizeof(struct niu_xmac_stats)); |
| 7879 | data += (sizeof(struct niu_xmac_stats) / sizeof(u64)); |
| 7880 | } else { |
| 7881 | memcpy(data, &np->mac_stats.bmac, |
| 7882 | sizeof(struct niu_bmac_stats)); |
| 7883 | data += (sizeof(struct niu_bmac_stats) / sizeof(u64)); |
| 7884 | } |
| 7885 | for (i = 0; i < np->num_rx_rings; i++) { |
| 7886 | struct rx_ring_info *rp = &np->rx_rings[i]; |
| 7887 | |
| 7888 | niu_sync_rx_discard_stats(np, rp, 0); |
| 7889 | |
| 7890 | data[0] = rp->rx_channel; |
| 7891 | data[1] = rp->rx_packets; |
| 7892 | data[2] = rp->rx_bytes; |
| 7893 | data[3] = rp->rx_dropped; |
| 7894 | data[4] = rp->rx_errors; |
| 7895 | data += 5; |
| 7896 | } |
| 7897 | for (i = 0; i < np->num_tx_rings; i++) { |
| 7898 | struct tx_ring_info *rp = &np->tx_rings[i]; |
| 7899 | |
| 7900 | data[0] = rp->tx_channel; |
| 7901 | data[1] = rp->tx_packets; |
| 7902 | data[2] = rp->tx_bytes; |
| 7903 | data[3] = rp->tx_errors; |
| 7904 | data += 4; |
| 7905 | } |
| 7906 | } |
| 7907 | |
| 7908 | static u64 niu_led_state_save(struct niu *np) |
| 7909 | { |
| 7910 | if (np->flags & NIU_FLAGS_XMAC) |
| 7911 | return nr64_mac(XMAC_CONFIG); |
| 7912 | else |
| 7913 | return nr64_mac(BMAC_XIF_CONFIG); |
| 7914 | } |
| 7915 | |
| 7916 | static void niu_led_state_restore(struct niu *np, u64 val) |
| 7917 | { |
| 7918 | if (np->flags & NIU_FLAGS_XMAC) |
| 7919 | nw64_mac(XMAC_CONFIG, val); |
| 7920 | else |
| 7921 | nw64_mac(BMAC_XIF_CONFIG, val); |
| 7922 | } |
| 7923 | |
| 7924 | static void niu_force_led(struct niu *np, int on) |
| 7925 | { |
| 7926 | u64 val, reg, bit; |
| 7927 | |
| 7928 | if (np->flags & NIU_FLAGS_XMAC) { |
| 7929 | reg = XMAC_CONFIG; |
| 7930 | bit = XMAC_CONFIG_FORCE_LED_ON; |
| 7931 | } else { |
| 7932 | reg = BMAC_XIF_CONFIG; |
| 7933 | bit = BMAC_XIF_CONFIG_LINK_LED; |
| 7934 | } |
| 7935 | |
| 7936 | val = nr64_mac(reg); |
| 7937 | if (on) |
| 7938 | val |= bit; |
| 7939 | else |
| 7940 | val &= ~bit; |
| 7941 | nw64_mac(reg, val); |
| 7942 | } |
| 7943 | |
| 7944 | static int niu_phys_id(struct net_device *dev, u32 data) |
| 7945 | { |
| 7946 | struct niu *np = netdev_priv(dev); |
| 7947 | u64 orig_led_state; |
| 7948 | int i; |
| 7949 | |
| 7950 | if (!netif_running(dev)) |
| 7951 | return -EAGAIN; |
| 7952 | |
| 7953 | if (data == 0) |
| 7954 | data = 2; |
| 7955 | |
| 7956 | orig_led_state = niu_led_state_save(np); |
| 7957 | for (i = 0; i < (data * 2); i++) { |
| 7958 | int on = ((i % 2) == 0); |
| 7959 | |
| 7960 | niu_force_led(np, on); |
| 7961 | |
| 7962 | if (msleep_interruptible(500)) |
| 7963 | break; |
| 7964 | } |
| 7965 | niu_led_state_restore(np, orig_led_state); |
| 7966 | |
| 7967 | return 0; |
| 7968 | } |
| 7969 | |
| 7970 | static const struct ethtool_ops niu_ethtool_ops = { |
| 7971 | .get_drvinfo = niu_get_drvinfo, |
| 7972 | .get_link = ethtool_op_get_link, |
| 7973 | .get_msglevel = niu_get_msglevel, |
| 7974 | .set_msglevel = niu_set_msglevel, |
| 7975 | .nway_reset = niu_nway_reset, |
| 7976 | .get_eeprom_len = niu_get_eeprom_len, |
| 7977 | .get_eeprom = niu_get_eeprom, |
| 7978 | .get_settings = niu_get_settings, |
| 7979 | .set_settings = niu_set_settings, |
| 7980 | .get_strings = niu_get_strings, |
| 7981 | .get_stats_count = niu_get_stats_count, |
| 7982 | .get_ethtool_stats = niu_get_ethtool_stats, |
| 7983 | .phys_id = niu_phys_id, |
| 7984 | .get_rxnfc = niu_get_nfc, |
| 7985 | .set_rxnfc = niu_set_nfc, |
| 7986 | }; |
| 7987 | |
| 7988 | static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent, |
| 7989 | int ldg, int ldn) |
| 7990 | { |
| 7991 | if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) |
| 7992 | return -EINVAL; |
| 7993 | if (ldn < 0 || ldn > LDN_MAX) |
| 7994 | return -EINVAL; |
| 7995 | |
| 7996 | parent->ldg_map[ldn] = ldg; |
| 7997 | |
| 7998 | if (np->parent->plat_type == PLAT_TYPE_NIU) { |
| 7999 | /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by |
| 8000 | * the firmware, and we're not supposed to change them. |
| 8001 | * Validate the mapping, because if it's wrong we probably |
| 8002 | * won't get any interrupts and that's painful to debug. |
| 8003 | */ |
| 8004 | if (nr64(LDG_NUM(ldn)) != ldg) { |
| 8005 | dev_err(np->device, PFX "Port %u, mis-matched " |
| 8006 | "LDG assignment " |
| 8007 | "for ldn %d, should be %d is %llu\n", |
| 8008 | np->port, ldn, ldg, |
| 8009 | (unsigned long long) nr64(LDG_NUM(ldn))); |
| 8010 | return -EINVAL; |
| 8011 | } |
| 8012 | } else |
| 8013 | nw64(LDG_NUM(ldn), ldg); |
| 8014 | |
| 8015 | return 0; |
| 8016 | } |
| 8017 | |
| 8018 | static int niu_set_ldg_timer_res(struct niu *np, int res) |
| 8019 | { |
| 8020 | if (res < 0 || res > LDG_TIMER_RES_VAL) |
| 8021 | return -EINVAL; |
| 8022 | |
| 8023 | |
| 8024 | nw64(LDG_TIMER_RES, res); |
| 8025 | |
| 8026 | return 0; |
| 8027 | } |
| 8028 | |
| 8029 | static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector) |
| 8030 | { |
| 8031 | if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) || |
| 8032 | (func < 0 || func > 3) || |
| 8033 | (vector < 0 || vector > 0x1f)) |
| 8034 | return -EINVAL; |
| 8035 | |
| 8036 | nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector); |
| 8037 | |
| 8038 | return 0; |
| 8039 | } |
| 8040 | |
| 8041 | static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr) |
| 8042 | { |
| 8043 | u64 frame, frame_base = (ESPC_PIO_STAT_READ_START | |
| 8044 | (addr << ESPC_PIO_STAT_ADDR_SHIFT)); |
| 8045 | int limit; |
| 8046 | |
| 8047 | if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT)) |
| 8048 | return -EINVAL; |
| 8049 | |
| 8050 | frame = frame_base; |
| 8051 | nw64(ESPC_PIO_STAT, frame); |
| 8052 | limit = 64; |
| 8053 | do { |
| 8054 | udelay(5); |
| 8055 | frame = nr64(ESPC_PIO_STAT); |
| 8056 | if (frame & ESPC_PIO_STAT_READ_END) |
| 8057 | break; |
| 8058 | } while (limit--); |
| 8059 | if (!(frame & ESPC_PIO_STAT_READ_END)) { |
| 8060 | dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n", |
| 8061 | (unsigned long long) frame); |
| 8062 | return -ENODEV; |
| 8063 | } |
| 8064 | |
| 8065 | frame = frame_base; |
| 8066 | nw64(ESPC_PIO_STAT, frame); |
| 8067 | limit = 64; |
| 8068 | do { |
| 8069 | udelay(5); |
| 8070 | frame = nr64(ESPC_PIO_STAT); |
| 8071 | if (frame & ESPC_PIO_STAT_READ_END) |
| 8072 | break; |
| 8073 | } while (limit--); |
| 8074 | if (!(frame & ESPC_PIO_STAT_READ_END)) { |
| 8075 | dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n", |
| 8076 | (unsigned long long) frame); |
| 8077 | return -ENODEV; |
| 8078 | } |
| 8079 | |
| 8080 | frame = nr64(ESPC_PIO_STAT); |
| 8081 | return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT; |
| 8082 | } |
| 8083 | |
| 8084 | static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off) |
| 8085 | { |
| 8086 | int err = niu_pci_eeprom_read(np, off); |
| 8087 | u16 val; |
| 8088 | |
| 8089 | if (err < 0) |
| 8090 | return err; |
| 8091 | val = (err << 8); |
| 8092 | err = niu_pci_eeprom_read(np, off + 1); |
| 8093 | if (err < 0) |
| 8094 | return err; |
| 8095 | val |= (err & 0xff); |
| 8096 | |
| 8097 | return val; |
| 8098 | } |
| 8099 | |
| 8100 | static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off) |
| 8101 | { |
| 8102 | int err = niu_pci_eeprom_read(np, off); |
| 8103 | u16 val; |
| 8104 | |
| 8105 | if (err < 0) |
| 8106 | return err; |
| 8107 | |
| 8108 | val = (err & 0xff); |
| 8109 | err = niu_pci_eeprom_read(np, off + 1); |
| 8110 | if (err < 0) |
| 8111 | return err; |
| 8112 | |
| 8113 | val |= (err & 0xff) << 8; |
| 8114 | |
| 8115 | return val; |
| 8116 | } |
| 8117 | |
| 8118 | static int __devinit niu_pci_vpd_get_propname(struct niu *np, |
| 8119 | u32 off, |
| 8120 | char *namebuf, |
| 8121 | int namebuf_len) |
| 8122 | { |
| 8123 | int i; |
| 8124 | |
| 8125 | for (i = 0; i < namebuf_len; i++) { |
| 8126 | int err = niu_pci_eeprom_read(np, off + i); |
| 8127 | if (err < 0) |
| 8128 | return err; |
| 8129 | *namebuf++ = err; |
| 8130 | if (!err) |
| 8131 | break; |
| 8132 | } |
| 8133 | if (i >= namebuf_len) |
| 8134 | return -EINVAL; |
| 8135 | |
| 8136 | return i + 1; |
| 8137 | } |
| 8138 | |
| 8139 | static void __devinit niu_vpd_parse_version(struct niu *np) |
| 8140 | { |
| 8141 | struct niu_vpd *vpd = &np->vpd; |
| 8142 | int len = strlen(vpd->version) + 1; |
| 8143 | const char *s = vpd->version; |
| 8144 | int i; |
| 8145 | |
| 8146 | for (i = 0; i < len - 5; i++) { |
| 8147 | if (!strncmp(s + i, "FCode ", 5)) |
| 8148 | break; |
| 8149 | } |
| 8150 | if (i >= len - 5) |
| 8151 | return; |
| 8152 | |
| 8153 | s += i + 5; |
| 8154 | sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor); |
| 8155 | |
| 8156 | niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n", |
| 8157 | vpd->fcode_major, vpd->fcode_minor); |
| 8158 | if (vpd->fcode_major > NIU_VPD_MIN_MAJOR || |
| 8159 | (vpd->fcode_major == NIU_VPD_MIN_MAJOR && |
| 8160 | vpd->fcode_minor >= NIU_VPD_MIN_MINOR)) |
| 8161 | np->flags |= NIU_FLAGS_VPD_VALID; |
| 8162 | } |
| 8163 | |
| 8164 | /* ESPC_PIO_EN_ENABLE must be set */ |
| 8165 | static int __devinit niu_pci_vpd_scan_props(struct niu *np, |
| 8166 | u32 start, u32 end) |
| 8167 | { |
| 8168 | unsigned int found_mask = 0; |
| 8169 | #define FOUND_MASK_MODEL 0x00000001 |
| 8170 | #define FOUND_MASK_BMODEL 0x00000002 |
| 8171 | #define FOUND_MASK_VERS 0x00000004 |
| 8172 | #define FOUND_MASK_MAC 0x00000008 |
| 8173 | #define FOUND_MASK_NMAC 0x00000010 |
| 8174 | #define FOUND_MASK_PHY 0x00000020 |
| 8175 | #define FOUND_MASK_ALL 0x0000003f |
| 8176 | |
| 8177 | niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n", |
| 8178 | start, end); |
| 8179 | while (start < end) { |
| 8180 | int len, err, instance, type, prop_len; |
| 8181 | char namebuf[64]; |
| 8182 | u8 *prop_buf; |
| 8183 | int max_len; |
| 8184 | |
| 8185 | if (found_mask == FOUND_MASK_ALL) { |
| 8186 | niu_vpd_parse_version(np); |
| 8187 | return 1; |
| 8188 | } |
| 8189 | |
| 8190 | err = niu_pci_eeprom_read(np, start + 2); |
| 8191 | if (err < 0) |
| 8192 | return err; |
| 8193 | len = err; |
| 8194 | start += 3; |
| 8195 | |
| 8196 | instance = niu_pci_eeprom_read(np, start); |
| 8197 | type = niu_pci_eeprom_read(np, start + 3); |
| 8198 | prop_len = niu_pci_eeprom_read(np, start + 4); |
| 8199 | err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64); |
| 8200 | if (err < 0) |
| 8201 | return err; |
| 8202 | |
| 8203 | prop_buf = NULL; |
| 8204 | max_len = 0; |
| 8205 | if (!strcmp(namebuf, "model")) { |
| 8206 | prop_buf = np->vpd.model; |
| 8207 | max_len = NIU_VPD_MODEL_MAX; |
| 8208 | found_mask |= FOUND_MASK_MODEL; |
| 8209 | } else if (!strcmp(namebuf, "board-model")) { |
| 8210 | prop_buf = np->vpd.board_model; |
| 8211 | max_len = NIU_VPD_BD_MODEL_MAX; |
| 8212 | found_mask |= FOUND_MASK_BMODEL; |
| 8213 | } else if (!strcmp(namebuf, "version")) { |
| 8214 | prop_buf = np->vpd.version; |
| 8215 | max_len = NIU_VPD_VERSION_MAX; |
| 8216 | found_mask |= FOUND_MASK_VERS; |
| 8217 | } else if (!strcmp(namebuf, "local-mac-address")) { |
| 8218 | prop_buf = np->vpd.local_mac; |
| 8219 | max_len = ETH_ALEN; |
| 8220 | found_mask |= FOUND_MASK_MAC; |
| 8221 | } else if (!strcmp(namebuf, "num-mac-addresses")) { |
| 8222 | prop_buf = &np->vpd.mac_num; |
| 8223 | max_len = 1; |
| 8224 | found_mask |= FOUND_MASK_NMAC; |
| 8225 | } else if (!strcmp(namebuf, "phy-type")) { |
| 8226 | prop_buf = np->vpd.phy_type; |
| 8227 | max_len = NIU_VPD_PHY_TYPE_MAX; |
| 8228 | found_mask |= FOUND_MASK_PHY; |
| 8229 | } |
| 8230 | |
| 8231 | if (max_len && prop_len > max_len) { |
| 8232 | dev_err(np->device, PFX "Property '%s' length (%d) is " |
| 8233 | "too long.\n", namebuf, prop_len); |
| 8234 | return -EINVAL; |
| 8235 | } |
| 8236 | |
| 8237 | if (prop_buf) { |
| 8238 | u32 off = start + 5 + err; |
| 8239 | int i; |
| 8240 | |
| 8241 | niudbg(PROBE, "VPD_SCAN: Reading in property [%s] " |
| 8242 | "len[%d]\n", namebuf, prop_len); |
| 8243 | for (i = 0; i < prop_len; i++) |
| 8244 | *prop_buf++ = niu_pci_eeprom_read(np, off + i); |
| 8245 | } |
| 8246 | |
| 8247 | start += len; |
| 8248 | } |
| 8249 | |
| 8250 | return 0; |
| 8251 | } |
| 8252 | |
| 8253 | /* ESPC_PIO_EN_ENABLE must be set */ |
| 8254 | static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start) |
| 8255 | { |
| 8256 | u32 offset; |
| 8257 | int err; |
| 8258 | |
| 8259 | err = niu_pci_eeprom_read16_swp(np, start + 1); |
| 8260 | if (err < 0) |
| 8261 | return; |
| 8262 | |
| 8263 | offset = err + 3; |
| 8264 | |
| 8265 | while (start + offset < ESPC_EEPROM_SIZE) { |
| 8266 | u32 here = start + offset; |
| 8267 | u32 end; |
| 8268 | |
| 8269 | err = niu_pci_eeprom_read(np, here); |
| 8270 | if (err != 0x90) |
| 8271 | return; |
| 8272 | |
| 8273 | err = niu_pci_eeprom_read16_swp(np, here + 1); |
| 8274 | if (err < 0) |
| 8275 | return; |
| 8276 | |
| 8277 | here = start + offset + 3; |
| 8278 | end = start + offset + err; |
| 8279 | |
| 8280 | offset += err; |
| 8281 | |
| 8282 | err = niu_pci_vpd_scan_props(np, here, end); |
| 8283 | if (err < 0 || err == 1) |
| 8284 | return; |
| 8285 | } |
| 8286 | } |
| 8287 | |
| 8288 | /* ESPC_PIO_EN_ENABLE must be set */ |
| 8289 | static u32 __devinit niu_pci_vpd_offset(struct niu *np) |
| 8290 | { |
| 8291 | u32 start = 0, end = ESPC_EEPROM_SIZE, ret; |
| 8292 | int err; |
| 8293 | |
| 8294 | while (start < end) { |
| 8295 | ret = start; |
| 8296 | |
| 8297 | /* ROM header signature? */ |
| 8298 | err = niu_pci_eeprom_read16(np, start + 0); |
| 8299 | if (err != 0x55aa) |
| 8300 | return 0; |
| 8301 | |
| 8302 | /* Apply offset to PCI data structure. */ |
| 8303 | err = niu_pci_eeprom_read16(np, start + 23); |
| 8304 | if (err < 0) |
| 8305 | return 0; |
| 8306 | start += err; |
| 8307 | |
| 8308 | /* Check for "PCIR" signature. */ |
| 8309 | err = niu_pci_eeprom_read16(np, start + 0); |
| 8310 | if (err != 0x5043) |
| 8311 | return 0; |
| 8312 | err = niu_pci_eeprom_read16(np, start + 2); |
| 8313 | if (err != 0x4952) |
| 8314 | return 0; |
| 8315 | |
| 8316 | /* Check for OBP image type. */ |
| 8317 | err = niu_pci_eeprom_read(np, start + 20); |
| 8318 | if (err < 0) |
| 8319 | return 0; |
| 8320 | if (err != 0x01) { |
| 8321 | err = niu_pci_eeprom_read(np, ret + 2); |
| 8322 | if (err < 0) |
| 8323 | return 0; |
| 8324 | |
| 8325 | start = ret + (err * 512); |
| 8326 | continue; |
| 8327 | } |
| 8328 | |
| 8329 | err = niu_pci_eeprom_read16_swp(np, start + 8); |
| 8330 | if (err < 0) |
| 8331 | return err; |
| 8332 | ret += err; |
| 8333 | |
| 8334 | err = niu_pci_eeprom_read(np, ret + 0); |
| 8335 | if (err != 0x82) |
| 8336 | return 0; |
| 8337 | |
| 8338 | return ret; |
| 8339 | } |
| 8340 | |
| 8341 | return 0; |
| 8342 | } |
| 8343 | |
| 8344 | static int __devinit niu_phy_type_prop_decode(struct niu *np, |
| 8345 | const char *phy_prop) |
| 8346 | { |
| 8347 | if (!strcmp(phy_prop, "mif")) { |
| 8348 | /* 1G copper, MII */ |
| 8349 | np->flags &= ~(NIU_FLAGS_FIBER | |
| 8350 | NIU_FLAGS_10G); |
| 8351 | np->mac_xcvr = MAC_XCVR_MII; |
| 8352 | } else if (!strcmp(phy_prop, "xgf")) { |
| 8353 | /* 10G fiber, XPCS */ |
| 8354 | np->flags |= (NIU_FLAGS_10G | |
| 8355 | NIU_FLAGS_FIBER); |
| 8356 | np->mac_xcvr = MAC_XCVR_XPCS; |
| 8357 | } else if (!strcmp(phy_prop, "pcs")) { |
| 8358 | /* 1G fiber, PCS */ |
| 8359 | np->flags &= ~NIU_FLAGS_10G; |
| 8360 | np->flags |= NIU_FLAGS_FIBER; |
| 8361 | np->mac_xcvr = MAC_XCVR_PCS; |
| 8362 | } else if (!strcmp(phy_prop, "xgc")) { |
| 8363 | /* 10G copper, XPCS */ |
| 8364 | np->flags |= NIU_FLAGS_10G; |
| 8365 | np->flags &= ~NIU_FLAGS_FIBER; |
| 8366 | np->mac_xcvr = MAC_XCVR_XPCS; |
| 8367 | } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) { |
| 8368 | /* 10G Serdes or 1G Serdes, default to 10G */ |
| 8369 | np->flags |= NIU_FLAGS_10G; |
| 8370 | np->flags &= ~NIU_FLAGS_FIBER; |
| 8371 | np->flags |= NIU_FLAGS_XCVR_SERDES; |
| 8372 | np->mac_xcvr = MAC_XCVR_XPCS; |
| 8373 | } else { |
| 8374 | return -EINVAL; |
| 8375 | } |
| 8376 | return 0; |
| 8377 | } |
| 8378 | |
| 8379 | static int niu_pci_vpd_get_nports(struct niu *np) |
| 8380 | { |
| 8381 | int ports = 0; |
| 8382 | |
| 8383 | if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) || |
| 8384 | (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) || |
| 8385 | (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) || |
| 8386 | (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) || |
| 8387 | (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) { |
| 8388 | ports = 4; |
| 8389 | } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) || |
| 8390 | (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) || |
| 8391 | (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) || |
| 8392 | (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) { |
| 8393 | ports = 2; |
| 8394 | } |
| 8395 | |
| 8396 | return ports; |
| 8397 | } |
| 8398 | |
| 8399 | static void __devinit niu_pci_vpd_validate(struct niu *np) |
| 8400 | { |
| 8401 | struct net_device *dev = np->dev; |
| 8402 | struct niu_vpd *vpd = &np->vpd; |
| 8403 | u8 val8; |
| 8404 | |
| 8405 | if (!is_valid_ether_addr(&vpd->local_mac[0])) { |
| 8406 | dev_err(np->device, PFX "VPD MAC invalid, " |
| 8407 | "falling back to SPROM.\n"); |
| 8408 | |
| 8409 | np->flags &= ~NIU_FLAGS_VPD_VALID; |
| 8410 | return; |
| 8411 | } |
| 8412 | |
| 8413 | if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || |
| 8414 | !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { |
| 8415 | np->flags |= NIU_FLAGS_10G; |
| 8416 | np->flags &= ~NIU_FLAGS_FIBER; |
| 8417 | np->flags |= NIU_FLAGS_XCVR_SERDES; |
| 8418 | np->mac_xcvr = MAC_XCVR_PCS; |
| 8419 | if (np->port > 1) { |
| 8420 | np->flags |= NIU_FLAGS_FIBER; |
| 8421 | np->flags &= ~NIU_FLAGS_10G; |
| 8422 | } |
| 8423 | if (np->flags & NIU_FLAGS_10G) |
| 8424 | np->mac_xcvr = MAC_XCVR_XPCS; |
| 8425 | } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { |
| 8426 | np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | |
| 8427 | NIU_FLAGS_HOTPLUG_PHY); |
| 8428 | } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { |
| 8429 | dev_err(np->device, PFX "Illegal phy string [%s].\n", |
| 8430 | np->vpd.phy_type); |
| 8431 | dev_err(np->device, PFX "Falling back to SPROM.\n"); |
| 8432 | np->flags &= ~NIU_FLAGS_VPD_VALID; |
| 8433 | return; |
| 8434 | } |
| 8435 | |
| 8436 | memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN); |
| 8437 | |
| 8438 | val8 = dev->perm_addr[5]; |
| 8439 | dev->perm_addr[5] += np->port; |
| 8440 | if (dev->perm_addr[5] < val8) |
| 8441 | dev->perm_addr[4]++; |
| 8442 | |
| 8443 | memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); |
| 8444 | } |
| 8445 | |
| 8446 | static int __devinit niu_pci_probe_sprom(struct niu *np) |
| 8447 | { |
| 8448 | struct net_device *dev = np->dev; |
| 8449 | int len, i; |
| 8450 | u64 val, sum; |
| 8451 | u8 val8; |
| 8452 | |
| 8453 | val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ); |
| 8454 | val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT; |
| 8455 | len = val / 4; |
| 8456 | |
| 8457 | np->eeprom_len = len; |
| 8458 | |
| 8459 | niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val); |
| 8460 | |
| 8461 | sum = 0; |
| 8462 | for (i = 0; i < len; i++) { |
| 8463 | val = nr64(ESPC_NCR(i)); |
| 8464 | sum += (val >> 0) & 0xff; |
| 8465 | sum += (val >> 8) & 0xff; |
| 8466 | sum += (val >> 16) & 0xff; |
| 8467 | sum += (val >> 24) & 0xff; |
| 8468 | } |
| 8469 | niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff)); |
| 8470 | if ((sum & 0xff) != 0xab) { |
| 8471 | dev_err(np->device, PFX "Bad SPROM checksum " |
| 8472 | "(%x, should be 0xab)\n", (int) (sum & 0xff)); |
| 8473 | return -EINVAL; |
| 8474 | } |
| 8475 | |
| 8476 | val = nr64(ESPC_PHY_TYPE); |
| 8477 | switch (np->port) { |
| 8478 | case 0: |
| 8479 | val8 = (val & ESPC_PHY_TYPE_PORT0) >> |
| 8480 | ESPC_PHY_TYPE_PORT0_SHIFT; |
| 8481 | break; |
| 8482 | case 1: |
| 8483 | val8 = (val & ESPC_PHY_TYPE_PORT1) >> |
| 8484 | ESPC_PHY_TYPE_PORT1_SHIFT; |
| 8485 | break; |
| 8486 | case 2: |
| 8487 | val8 = (val & ESPC_PHY_TYPE_PORT2) >> |
| 8488 | ESPC_PHY_TYPE_PORT2_SHIFT; |
| 8489 | break; |
| 8490 | case 3: |
| 8491 | val8 = (val & ESPC_PHY_TYPE_PORT3) >> |
| 8492 | ESPC_PHY_TYPE_PORT3_SHIFT; |
| 8493 | break; |
| 8494 | default: |
| 8495 | dev_err(np->device, PFX "Bogus port number %u\n", |
| 8496 | np->port); |
| 8497 | return -EINVAL; |
| 8498 | } |
| 8499 | niudbg(PROBE, "SPROM: PHY type %x\n", val8); |
| 8500 | |
| 8501 | switch (val8) { |
| 8502 | case ESPC_PHY_TYPE_1G_COPPER: |
| 8503 | /* 1G copper, MII */ |
| 8504 | np->flags &= ~(NIU_FLAGS_FIBER | |
| 8505 | NIU_FLAGS_10G); |
| 8506 | np->mac_xcvr = MAC_XCVR_MII; |
| 8507 | break; |
| 8508 | |
| 8509 | case ESPC_PHY_TYPE_1G_FIBER: |
| 8510 | /* 1G fiber, PCS */ |
| 8511 | np->flags &= ~NIU_FLAGS_10G; |
| 8512 | np->flags |= NIU_FLAGS_FIBER; |
| 8513 | np->mac_xcvr = MAC_XCVR_PCS; |
| 8514 | break; |
| 8515 | |
| 8516 | case ESPC_PHY_TYPE_10G_COPPER: |
| 8517 | /* 10G copper, XPCS */ |
| 8518 | np->flags |= NIU_FLAGS_10G; |
| 8519 | np->flags &= ~NIU_FLAGS_FIBER; |
| 8520 | np->mac_xcvr = MAC_XCVR_XPCS; |
| 8521 | break; |
| 8522 | |
| 8523 | case ESPC_PHY_TYPE_10G_FIBER: |
| 8524 | /* 10G fiber, XPCS */ |
| 8525 | np->flags |= (NIU_FLAGS_10G | |
| 8526 | NIU_FLAGS_FIBER); |
| 8527 | np->mac_xcvr = MAC_XCVR_XPCS; |
| 8528 | break; |
| 8529 | |
| 8530 | default: |
| 8531 | dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8); |
| 8532 | return -EINVAL; |
| 8533 | } |
| 8534 | |
| 8535 | val = nr64(ESPC_MAC_ADDR0); |
| 8536 | niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n", |
| 8537 | (unsigned long long) val); |
| 8538 | dev->perm_addr[0] = (val >> 0) & 0xff; |
| 8539 | dev->perm_addr[1] = (val >> 8) & 0xff; |
| 8540 | dev->perm_addr[2] = (val >> 16) & 0xff; |
| 8541 | dev->perm_addr[3] = (val >> 24) & 0xff; |
| 8542 | |
| 8543 | val = nr64(ESPC_MAC_ADDR1); |
| 8544 | niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n", |
| 8545 | (unsigned long long) val); |
| 8546 | dev->perm_addr[4] = (val >> 0) & 0xff; |
| 8547 | dev->perm_addr[5] = (val >> 8) & 0xff; |
| 8548 | |
| 8549 | if (!is_valid_ether_addr(&dev->perm_addr[0])) { |
| 8550 | dev_err(np->device, PFX "SPROM MAC address invalid\n"); |
| 8551 | dev_err(np->device, PFX "[ \n"); |
| 8552 | for (i = 0; i < 6; i++) |
| 8553 | printk("%02x ", dev->perm_addr[i]); |
| 8554 | printk("]\n"); |
| 8555 | return -EINVAL; |
| 8556 | } |
| 8557 | |
| 8558 | val8 = dev->perm_addr[5]; |
| 8559 | dev->perm_addr[5] += np->port; |
| 8560 | if (dev->perm_addr[5] < val8) |
| 8561 | dev->perm_addr[4]++; |
| 8562 | |
| 8563 | memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); |
| 8564 | |
| 8565 | val = nr64(ESPC_MOD_STR_LEN); |
| 8566 | niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n", |
| 8567 | (unsigned long long) val); |
| 8568 | if (val >= 8 * 4) |
| 8569 | return -EINVAL; |
| 8570 | |
| 8571 | for (i = 0; i < val; i += 4) { |
| 8572 | u64 tmp = nr64(ESPC_NCR(5 + (i / 4))); |
| 8573 | |
| 8574 | np->vpd.model[i + 3] = (tmp >> 0) & 0xff; |
| 8575 | np->vpd.model[i + 2] = (tmp >> 8) & 0xff; |
| 8576 | np->vpd.model[i + 1] = (tmp >> 16) & 0xff; |
| 8577 | np->vpd.model[i + 0] = (tmp >> 24) & 0xff; |
| 8578 | } |
| 8579 | np->vpd.model[val] = '\0'; |
| 8580 | |
| 8581 | val = nr64(ESPC_BD_MOD_STR_LEN); |
| 8582 | niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n", |
| 8583 | (unsigned long long) val); |
| 8584 | if (val >= 4 * 4) |
| 8585 | return -EINVAL; |
| 8586 | |
| 8587 | for (i = 0; i < val; i += 4) { |
| 8588 | u64 tmp = nr64(ESPC_NCR(14 + (i / 4))); |
| 8589 | |
| 8590 | np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff; |
| 8591 | np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff; |
| 8592 | np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff; |
| 8593 | np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff; |
| 8594 | } |
| 8595 | np->vpd.board_model[val] = '\0'; |
| 8596 | |
| 8597 | np->vpd.mac_num = |
| 8598 | nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL; |
| 8599 | niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n", |
| 8600 | np->vpd.mac_num); |
| 8601 | |
| 8602 | return 0; |
| 8603 | } |
| 8604 | |
| 8605 | static int __devinit niu_get_and_validate_port(struct niu *np) |
| 8606 | { |
| 8607 | struct niu_parent *parent = np->parent; |
| 8608 | |
| 8609 | if (np->port <= 1) |
| 8610 | np->flags |= NIU_FLAGS_XMAC; |
| 8611 | |
| 8612 | if (!parent->num_ports) { |
| 8613 | if (parent->plat_type == PLAT_TYPE_NIU) { |
| 8614 | parent->num_ports = 2; |
| 8615 | } else { |
| 8616 | parent->num_ports = niu_pci_vpd_get_nports(np); |
| 8617 | if (!parent->num_ports) { |
| 8618 | /* Fall back to SPROM as last resort. |
| 8619 | * This will fail on most cards. |
| 8620 | */ |
| 8621 | parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) & |
| 8622 | ESPC_NUM_PORTS_MACS_VAL; |
| 8623 | |
| 8624 | /* All of the current probing methods fail on |
| 8625 | * Maramba on-board parts. |
| 8626 | */ |
| 8627 | if (!parent->num_ports) |
| 8628 | parent->num_ports = 4; |
| 8629 | } |
| 8630 | } |
| 8631 | } |
| 8632 | |
| 8633 | niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n", |
| 8634 | np->port, parent->num_ports); |
| 8635 | if (np->port >= parent->num_ports) |
| 8636 | return -ENODEV; |
| 8637 | |
| 8638 | return 0; |
| 8639 | } |
| 8640 | |
| 8641 | static int __devinit phy_record(struct niu_parent *parent, |
| 8642 | struct phy_probe_info *p, |
| 8643 | int dev_id_1, int dev_id_2, u8 phy_port, |
| 8644 | int type) |
| 8645 | { |
| 8646 | u32 id = (dev_id_1 << 16) | dev_id_2; |
| 8647 | u8 idx; |
| 8648 | |
| 8649 | if (dev_id_1 < 0 || dev_id_2 < 0) |
| 8650 | return 0; |
| 8651 | if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) { |
| 8652 | if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) && |
| 8653 | ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) && |
| 8654 | ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706)) |
| 8655 | return 0; |
| 8656 | } else { |
| 8657 | if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R) |
| 8658 | return 0; |
| 8659 | } |
| 8660 | |
| 8661 | pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n", |
| 8662 | parent->index, id, |
| 8663 | (type == PHY_TYPE_PMA_PMD ? |
| 8664 | "PMA/PMD" : |
| 8665 | (type == PHY_TYPE_PCS ? |
| 8666 | "PCS" : "MII")), |
| 8667 | phy_port); |
| 8668 | |
| 8669 | if (p->cur[type] >= NIU_MAX_PORTS) { |
| 8670 | printk(KERN_ERR PFX "Too many PHY ports.\n"); |
| 8671 | return -EINVAL; |
| 8672 | } |
| 8673 | idx = p->cur[type]; |
| 8674 | p->phy_id[type][idx] = id; |
| 8675 | p->phy_port[type][idx] = phy_port; |
| 8676 | p->cur[type] = idx + 1; |
| 8677 | return 0; |
| 8678 | } |
| 8679 | |
| 8680 | static int __devinit port_has_10g(struct phy_probe_info *p, int port) |
| 8681 | { |
| 8682 | int i; |
| 8683 | |
| 8684 | for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) { |
| 8685 | if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port) |
| 8686 | return 1; |
| 8687 | } |
| 8688 | for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) { |
| 8689 | if (p->phy_port[PHY_TYPE_PCS][i] == port) |
| 8690 | return 1; |
| 8691 | } |
| 8692 | |
| 8693 | return 0; |
| 8694 | } |
| 8695 | |
| 8696 | static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest) |
| 8697 | { |
| 8698 | int port, cnt; |
| 8699 | |
| 8700 | cnt = 0; |
| 8701 | *lowest = 32; |
| 8702 | for (port = 8; port < 32; port++) { |
| 8703 | if (port_has_10g(p, port)) { |
| 8704 | if (!cnt) |
| 8705 | *lowest = port; |
| 8706 | cnt++; |
| 8707 | } |
| 8708 | } |
| 8709 | |
| 8710 | return cnt; |
| 8711 | } |
| 8712 | |
| 8713 | static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest) |
| 8714 | { |
| 8715 | *lowest = 32; |
| 8716 | if (p->cur[PHY_TYPE_MII]) |
| 8717 | *lowest = p->phy_port[PHY_TYPE_MII][0]; |
| 8718 | |
| 8719 | return p->cur[PHY_TYPE_MII]; |
| 8720 | } |
| 8721 | |
| 8722 | static void __devinit niu_n2_divide_channels(struct niu_parent *parent) |
| 8723 | { |
| 8724 | int num_ports = parent->num_ports; |
| 8725 | int i; |
| 8726 | |
| 8727 | for (i = 0; i < num_ports; i++) { |
| 8728 | parent->rxchan_per_port[i] = (16 / num_ports); |
| 8729 | parent->txchan_per_port[i] = (16 / num_ports); |
| 8730 | |
| 8731 | pr_info(PFX "niu%d: Port %u [%u RX chans] " |
| 8732 | "[%u TX chans]\n", |
| 8733 | parent->index, i, |
| 8734 | parent->rxchan_per_port[i], |
| 8735 | parent->txchan_per_port[i]); |
| 8736 | } |
| 8737 | } |
| 8738 | |
| 8739 | static void __devinit niu_divide_channels(struct niu_parent *parent, |
| 8740 | int num_10g, int num_1g) |
| 8741 | { |
| 8742 | int num_ports = parent->num_ports; |
| 8743 | int rx_chans_per_10g, rx_chans_per_1g; |
| 8744 | int tx_chans_per_10g, tx_chans_per_1g; |
| 8745 | int i, tot_rx, tot_tx; |
| 8746 | |
| 8747 | if (!num_10g || !num_1g) { |
| 8748 | rx_chans_per_10g = rx_chans_per_1g = |
| 8749 | (NIU_NUM_RXCHAN / num_ports); |
| 8750 | tx_chans_per_10g = tx_chans_per_1g = |
| 8751 | (NIU_NUM_TXCHAN / num_ports); |
| 8752 | } else { |
| 8753 | rx_chans_per_1g = NIU_NUM_RXCHAN / 8; |
| 8754 | rx_chans_per_10g = (NIU_NUM_RXCHAN - |
| 8755 | (rx_chans_per_1g * num_1g)) / |
| 8756 | num_10g; |
| 8757 | |
| 8758 | tx_chans_per_1g = NIU_NUM_TXCHAN / 6; |
| 8759 | tx_chans_per_10g = (NIU_NUM_TXCHAN - |
| 8760 | (tx_chans_per_1g * num_1g)) / |
| 8761 | num_10g; |
| 8762 | } |
| 8763 | |
| 8764 | tot_rx = tot_tx = 0; |
| 8765 | for (i = 0; i < num_ports; i++) { |
| 8766 | int type = phy_decode(parent->port_phy, i); |
| 8767 | |
| 8768 | if (type == PORT_TYPE_10G) { |
| 8769 | parent->rxchan_per_port[i] = rx_chans_per_10g; |
| 8770 | parent->txchan_per_port[i] = tx_chans_per_10g; |
| 8771 | } else { |
| 8772 | parent->rxchan_per_port[i] = rx_chans_per_1g; |
| 8773 | parent->txchan_per_port[i] = tx_chans_per_1g; |
| 8774 | } |
| 8775 | pr_info(PFX "niu%d: Port %u [%u RX chans] " |
| 8776 | "[%u TX chans]\n", |
| 8777 | parent->index, i, |
| 8778 | parent->rxchan_per_port[i], |
| 8779 | parent->txchan_per_port[i]); |
| 8780 | tot_rx += parent->rxchan_per_port[i]; |
| 8781 | tot_tx += parent->txchan_per_port[i]; |
| 8782 | } |
| 8783 | |
| 8784 | if (tot_rx > NIU_NUM_RXCHAN) { |
| 8785 | printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), " |
| 8786 | "resetting to one per port.\n", |
| 8787 | parent->index, tot_rx); |
| 8788 | for (i = 0; i < num_ports; i++) |
| 8789 | parent->rxchan_per_port[i] = 1; |
| 8790 | } |
| 8791 | if (tot_tx > NIU_NUM_TXCHAN) { |
| 8792 | printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), " |
| 8793 | "resetting to one per port.\n", |
| 8794 | parent->index, tot_tx); |
| 8795 | for (i = 0; i < num_ports; i++) |
| 8796 | parent->txchan_per_port[i] = 1; |
| 8797 | } |
| 8798 | if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) { |
| 8799 | printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, " |
| 8800 | "RX[%d] TX[%d]\n", |
| 8801 | parent->index, tot_rx, tot_tx); |
| 8802 | } |
| 8803 | } |
| 8804 | |
| 8805 | static void __devinit niu_divide_rdc_groups(struct niu_parent *parent, |
| 8806 | int num_10g, int num_1g) |
| 8807 | { |
| 8808 | int i, num_ports = parent->num_ports; |
| 8809 | int rdc_group, rdc_groups_per_port; |
| 8810 | int rdc_channel_base; |
| 8811 | |
| 8812 | rdc_group = 0; |
| 8813 | rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports; |
| 8814 | |
| 8815 | rdc_channel_base = 0; |
| 8816 | |
| 8817 | for (i = 0; i < num_ports; i++) { |
| 8818 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i]; |
| 8819 | int grp, num_channels = parent->rxchan_per_port[i]; |
| 8820 | int this_channel_offset; |
| 8821 | |
| 8822 | tp->first_table_num = rdc_group; |
| 8823 | tp->num_tables = rdc_groups_per_port; |
| 8824 | this_channel_offset = 0; |
| 8825 | for (grp = 0; grp < tp->num_tables; grp++) { |
| 8826 | struct rdc_table *rt = &tp->tables[grp]; |
| 8827 | int slot; |
| 8828 | |
| 8829 | pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ", |
| 8830 | parent->index, i, tp->first_table_num + grp); |
| 8831 | for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) { |
| 8832 | rt->rxdma_channel[slot] = |
| 8833 | rdc_channel_base + this_channel_offset; |
| 8834 | |
| 8835 | printk("%d ", rt->rxdma_channel[slot]); |
| 8836 | |
| 8837 | if (++this_channel_offset == num_channels) |
| 8838 | this_channel_offset = 0; |
| 8839 | } |
| 8840 | printk("]\n"); |
| 8841 | } |
| 8842 | |
| 8843 | parent->rdc_default[i] = rdc_channel_base; |
| 8844 | |
| 8845 | rdc_channel_base += num_channels; |
| 8846 | rdc_group += rdc_groups_per_port; |
| 8847 | } |
| 8848 | } |
| 8849 | |
| 8850 | static int __devinit fill_phy_probe_info(struct niu *np, |
| 8851 | struct niu_parent *parent, |
| 8852 | struct phy_probe_info *info) |
| 8853 | { |
| 8854 | unsigned long flags; |
| 8855 | int port, err; |
| 8856 | |
| 8857 | memset(info, 0, sizeof(*info)); |
| 8858 | |
| 8859 | /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */ |
| 8860 | niu_lock_parent(np, flags); |
| 8861 | err = 0; |
| 8862 | for (port = 8; port < 32; port++) { |
| 8863 | int dev_id_1, dev_id_2; |
| 8864 | |
| 8865 | dev_id_1 = mdio_read(np, port, |
| 8866 | NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1); |
| 8867 | dev_id_2 = mdio_read(np, port, |
| 8868 | NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2); |
| 8869 | err = phy_record(parent, info, dev_id_1, dev_id_2, port, |
| 8870 | PHY_TYPE_PMA_PMD); |
| 8871 | if (err) |
| 8872 | break; |
| 8873 | dev_id_1 = mdio_read(np, port, |
| 8874 | NIU_PCS_DEV_ADDR, MII_PHYSID1); |
| 8875 | dev_id_2 = mdio_read(np, port, |
| 8876 | NIU_PCS_DEV_ADDR, MII_PHYSID2); |
| 8877 | err = phy_record(parent, info, dev_id_1, dev_id_2, port, |
| 8878 | PHY_TYPE_PCS); |
| 8879 | if (err) |
| 8880 | break; |
| 8881 | dev_id_1 = mii_read(np, port, MII_PHYSID1); |
| 8882 | dev_id_2 = mii_read(np, port, MII_PHYSID2); |
| 8883 | err = phy_record(parent, info, dev_id_1, dev_id_2, port, |
| 8884 | PHY_TYPE_MII); |
| 8885 | if (err) |
| 8886 | break; |
| 8887 | } |
| 8888 | niu_unlock_parent(np, flags); |
| 8889 | |
| 8890 | return err; |
| 8891 | } |
| 8892 | |
| 8893 | static int __devinit walk_phys(struct niu *np, struct niu_parent *parent) |
| 8894 | { |
| 8895 | struct phy_probe_info *info = &parent->phy_probe_info; |
| 8896 | int lowest_10g, lowest_1g; |
| 8897 | int num_10g, num_1g; |
| 8898 | u32 val; |
| 8899 | int err; |
| 8900 | |
| 8901 | num_10g = num_1g = 0; |
| 8902 | |
| 8903 | if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || |
| 8904 | !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { |
| 8905 | num_10g = 0; |
| 8906 | num_1g = 2; |
| 8907 | parent->plat_type = PLAT_TYPE_ATCA_CP3220; |
| 8908 | parent->num_ports = 4; |
| 8909 | val = (phy_encode(PORT_TYPE_1G, 0) | |
| 8910 | phy_encode(PORT_TYPE_1G, 1) | |
| 8911 | phy_encode(PORT_TYPE_1G, 2) | |
| 8912 | phy_encode(PORT_TYPE_1G, 3)); |
| 8913 | } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { |
| 8914 | num_10g = 2; |
| 8915 | num_1g = 0; |
| 8916 | parent->num_ports = 2; |
| 8917 | val = (phy_encode(PORT_TYPE_10G, 0) | |
| 8918 | phy_encode(PORT_TYPE_10G, 1)); |
| 8919 | } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) && |
| 8920 | (parent->plat_type == PLAT_TYPE_NIU)) { |
| 8921 | /* this is the Monza case */ |
| 8922 | if (np->flags & NIU_FLAGS_10G) { |
| 8923 | val = (phy_encode(PORT_TYPE_10G, 0) | |
| 8924 | phy_encode(PORT_TYPE_10G, 1)); |
| 8925 | } else { |
| 8926 | val = (phy_encode(PORT_TYPE_1G, 0) | |
| 8927 | phy_encode(PORT_TYPE_1G, 1)); |
| 8928 | } |
| 8929 | } else { |
| 8930 | err = fill_phy_probe_info(np, parent, info); |
| 8931 | if (err) |
| 8932 | return err; |
| 8933 | |
| 8934 | num_10g = count_10g_ports(info, &lowest_10g); |
| 8935 | num_1g = count_1g_ports(info, &lowest_1g); |
| 8936 | |
| 8937 | switch ((num_10g << 4) | num_1g) { |
| 8938 | case 0x24: |
| 8939 | if (lowest_1g == 10) |
| 8940 | parent->plat_type = PLAT_TYPE_VF_P0; |
| 8941 | else if (lowest_1g == 26) |
| 8942 | parent->plat_type = PLAT_TYPE_VF_P1; |
| 8943 | else |
| 8944 | goto unknown_vg_1g_port; |
| 8945 | |
| 8946 | /* fallthru */ |
| 8947 | case 0x22: |
| 8948 | val = (phy_encode(PORT_TYPE_10G, 0) | |
| 8949 | phy_encode(PORT_TYPE_10G, 1) | |
| 8950 | phy_encode(PORT_TYPE_1G, 2) | |
| 8951 | phy_encode(PORT_TYPE_1G, 3)); |
| 8952 | break; |
| 8953 | |
| 8954 | case 0x20: |
| 8955 | val = (phy_encode(PORT_TYPE_10G, 0) | |
| 8956 | phy_encode(PORT_TYPE_10G, 1)); |
| 8957 | break; |
| 8958 | |
| 8959 | case 0x10: |
| 8960 | val = phy_encode(PORT_TYPE_10G, np->port); |
| 8961 | break; |
| 8962 | |
| 8963 | case 0x14: |
| 8964 | if (lowest_1g == 10) |
| 8965 | parent->plat_type = PLAT_TYPE_VF_P0; |
| 8966 | else if (lowest_1g == 26) |
| 8967 | parent->plat_type = PLAT_TYPE_VF_P1; |
| 8968 | else |
| 8969 | goto unknown_vg_1g_port; |
| 8970 | |
| 8971 | /* fallthru */ |
| 8972 | case 0x13: |
| 8973 | if ((lowest_10g & 0x7) == 0) |
| 8974 | val = (phy_encode(PORT_TYPE_10G, 0) | |
| 8975 | phy_encode(PORT_TYPE_1G, 1) | |
| 8976 | phy_encode(PORT_TYPE_1G, 2) | |
| 8977 | phy_encode(PORT_TYPE_1G, 3)); |
| 8978 | else |
| 8979 | val = (phy_encode(PORT_TYPE_1G, 0) | |
| 8980 | phy_encode(PORT_TYPE_10G, 1) | |
| 8981 | phy_encode(PORT_TYPE_1G, 2) | |
| 8982 | phy_encode(PORT_TYPE_1G, 3)); |
| 8983 | break; |
| 8984 | |
| 8985 | case 0x04: |
| 8986 | if (lowest_1g == 10) |
| 8987 | parent->plat_type = PLAT_TYPE_VF_P0; |
| 8988 | else if (lowest_1g == 26) |
| 8989 | parent->plat_type = PLAT_TYPE_VF_P1; |
| 8990 | else |
| 8991 | goto unknown_vg_1g_port; |
| 8992 | |
| 8993 | val = (phy_encode(PORT_TYPE_1G, 0) | |
| 8994 | phy_encode(PORT_TYPE_1G, 1) | |
| 8995 | phy_encode(PORT_TYPE_1G, 2) | |
| 8996 | phy_encode(PORT_TYPE_1G, 3)); |
| 8997 | break; |
| 8998 | |
| 8999 | default: |
| 9000 | printk(KERN_ERR PFX "Unsupported port config " |
| 9001 | "10G[%d] 1G[%d]\n", |
| 9002 | num_10g, num_1g); |
| 9003 | return -EINVAL; |
| 9004 | } |
| 9005 | } |
| 9006 | |
| 9007 | parent->port_phy = val; |
| 9008 | |
| 9009 | if (parent->plat_type == PLAT_TYPE_NIU) |
| 9010 | niu_n2_divide_channels(parent); |
| 9011 | else |
| 9012 | niu_divide_channels(parent, num_10g, num_1g); |
| 9013 | |
| 9014 | niu_divide_rdc_groups(parent, num_10g, num_1g); |
| 9015 | |
| 9016 | return 0; |
| 9017 | |
| 9018 | unknown_vg_1g_port: |
| 9019 | printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n", |
| 9020 | lowest_1g); |
| 9021 | return -EINVAL; |
| 9022 | } |
| 9023 | |
| 9024 | static int __devinit niu_probe_ports(struct niu *np) |
| 9025 | { |
| 9026 | struct niu_parent *parent = np->parent; |
| 9027 | int err, i; |
| 9028 | |
| 9029 | niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n", |
| 9030 | parent->port_phy); |
| 9031 | |
| 9032 | if (parent->port_phy == PORT_PHY_UNKNOWN) { |
| 9033 | err = walk_phys(np, parent); |
| 9034 | if (err) |
| 9035 | return err; |
| 9036 | |
| 9037 | niu_set_ldg_timer_res(np, 2); |
| 9038 | for (i = 0; i <= LDN_MAX; i++) |
| 9039 | niu_ldn_irq_enable(np, i, 0); |
| 9040 | } |
| 9041 | |
| 9042 | if (parent->port_phy == PORT_PHY_INVALID) |
| 9043 | return -EINVAL; |
| 9044 | |
| 9045 | return 0; |
| 9046 | } |
| 9047 | |
| 9048 | static int __devinit niu_classifier_swstate_init(struct niu *np) |
| 9049 | { |
| 9050 | struct niu_classifier *cp = &np->clas; |
| 9051 | |
| 9052 | niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n", |
| 9053 | np->parent->tcam_num_entries); |
| 9054 | |
| 9055 | cp->tcam_top = (u16) np->port; |
| 9056 | cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports; |
| 9057 | cp->h1_init = 0xffffffff; |
| 9058 | cp->h2_init = 0xffff; |
| 9059 | |
| 9060 | return fflp_early_init(np); |
| 9061 | } |
| 9062 | |
| 9063 | static void __devinit niu_link_config_init(struct niu *np) |
| 9064 | { |
| 9065 | struct niu_link_config *lp = &np->link_config; |
| 9066 | |
| 9067 | lp->advertising = (ADVERTISED_10baseT_Half | |
| 9068 | ADVERTISED_10baseT_Full | |
| 9069 | ADVERTISED_100baseT_Half | |
| 9070 | ADVERTISED_100baseT_Full | |
| 9071 | ADVERTISED_1000baseT_Half | |
| 9072 | ADVERTISED_1000baseT_Full | |
| 9073 | ADVERTISED_10000baseT_Full | |
| 9074 | ADVERTISED_Autoneg); |
| 9075 | lp->speed = lp->active_speed = SPEED_INVALID; |
| 9076 | lp->duplex = DUPLEX_FULL; |
| 9077 | lp->active_duplex = DUPLEX_INVALID; |
| 9078 | lp->autoneg = 1; |
| 9079 | #if 0 |
| 9080 | lp->loopback_mode = LOOPBACK_MAC; |
| 9081 | lp->active_speed = SPEED_10000; |
| 9082 | lp->active_duplex = DUPLEX_FULL; |
| 9083 | #else |
| 9084 | lp->loopback_mode = LOOPBACK_DISABLED; |
| 9085 | #endif |
| 9086 | } |
| 9087 | |
| 9088 | static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np) |
| 9089 | { |
| 9090 | switch (np->port) { |
| 9091 | case 0: |
| 9092 | np->mac_regs = np->regs + XMAC_PORT0_OFF; |
| 9093 | np->ipp_off = 0x00000; |
| 9094 | np->pcs_off = 0x04000; |
| 9095 | np->xpcs_off = 0x02000; |
| 9096 | break; |
| 9097 | |
| 9098 | case 1: |
| 9099 | np->mac_regs = np->regs + XMAC_PORT1_OFF; |
| 9100 | np->ipp_off = 0x08000; |
| 9101 | np->pcs_off = 0x0a000; |
| 9102 | np->xpcs_off = 0x08000; |
| 9103 | break; |
| 9104 | |
| 9105 | case 2: |
| 9106 | np->mac_regs = np->regs + BMAC_PORT2_OFF; |
| 9107 | np->ipp_off = 0x04000; |
| 9108 | np->pcs_off = 0x0e000; |
| 9109 | np->xpcs_off = ~0UL; |
| 9110 | break; |
| 9111 | |
| 9112 | case 3: |
| 9113 | np->mac_regs = np->regs + BMAC_PORT3_OFF; |
| 9114 | np->ipp_off = 0x0c000; |
| 9115 | np->pcs_off = 0x12000; |
| 9116 | np->xpcs_off = ~0UL; |
| 9117 | break; |
| 9118 | |
| 9119 | default: |
| 9120 | dev_err(np->device, PFX "Port %u is invalid, cannot " |
| 9121 | "compute MAC block offset.\n", np->port); |
| 9122 | return -EINVAL; |
| 9123 | } |
| 9124 | |
| 9125 | return 0; |
| 9126 | } |
| 9127 | |
| 9128 | static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map) |
| 9129 | { |
| 9130 | struct msix_entry msi_vec[NIU_NUM_LDG]; |
| 9131 | struct niu_parent *parent = np->parent; |
| 9132 | struct pci_dev *pdev = np->pdev; |
| 9133 | int i, num_irqs, err; |
| 9134 | u8 first_ldg; |
| 9135 | |
| 9136 | first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port; |
| 9137 | for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++) |
| 9138 | ldg_num_map[i] = first_ldg + i; |
| 9139 | |
| 9140 | num_irqs = (parent->rxchan_per_port[np->port] + |
| 9141 | parent->txchan_per_port[np->port] + |
| 9142 | (np->port == 0 ? 3 : 1)); |
| 9143 | BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports)); |
| 9144 | |
| 9145 | retry: |
| 9146 | for (i = 0; i < num_irqs; i++) { |
| 9147 | msi_vec[i].vector = 0; |
| 9148 | msi_vec[i].entry = i; |
| 9149 | } |
| 9150 | |
| 9151 | err = pci_enable_msix(pdev, msi_vec, num_irqs); |
| 9152 | if (err < 0) { |
| 9153 | np->flags &= ~NIU_FLAGS_MSIX; |
| 9154 | return; |
| 9155 | } |
| 9156 | if (err > 0) { |
| 9157 | num_irqs = err; |
| 9158 | goto retry; |
| 9159 | } |
| 9160 | |
| 9161 | np->flags |= NIU_FLAGS_MSIX; |
| 9162 | for (i = 0; i < num_irqs; i++) |
| 9163 | np->ldg[i].irq = msi_vec[i].vector; |
| 9164 | np->num_ldg = num_irqs; |
| 9165 | } |
| 9166 | |
| 9167 | static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map) |
| 9168 | { |
| 9169 | #ifdef CONFIG_SPARC64 |
| 9170 | struct of_device *op = np->op; |
| 9171 | const u32 *int_prop; |
| 9172 | int i; |
| 9173 | |
| 9174 | int_prop = of_get_property(op->node, "interrupts", NULL); |
| 9175 | if (!int_prop) |
| 9176 | return -ENODEV; |
| 9177 | |
| 9178 | for (i = 0; i < op->num_irqs; i++) { |
| 9179 | ldg_num_map[i] = int_prop[i]; |
| 9180 | np->ldg[i].irq = op->irqs[i]; |
| 9181 | } |
| 9182 | |
| 9183 | np->num_ldg = op->num_irqs; |
| 9184 | |
| 9185 | return 0; |
| 9186 | #else |
| 9187 | return -EINVAL; |
| 9188 | #endif |
| 9189 | } |
| 9190 | |
| 9191 | static int __devinit niu_ldg_init(struct niu *np) |
| 9192 | { |
| 9193 | struct niu_parent *parent = np->parent; |
| 9194 | u8 ldg_num_map[NIU_NUM_LDG]; |
| 9195 | int first_chan, num_chan; |
| 9196 | int i, err, ldg_rotor; |
| 9197 | u8 port; |
| 9198 | |
| 9199 | np->num_ldg = 1; |
| 9200 | np->ldg[0].irq = np->dev->irq; |
| 9201 | if (parent->plat_type == PLAT_TYPE_NIU) { |
| 9202 | err = niu_n2_irq_init(np, ldg_num_map); |
| 9203 | if (err) |
| 9204 | return err; |
| 9205 | } else |
| 9206 | niu_try_msix(np, ldg_num_map); |
| 9207 | |
| 9208 | port = np->port; |
| 9209 | for (i = 0; i < np->num_ldg; i++) { |
| 9210 | struct niu_ldg *lp = &np->ldg[i]; |
| 9211 | |
| 9212 | netif_napi_add(np->dev, &lp->napi, niu_poll, 64); |
| 9213 | |
| 9214 | lp->np = np; |
| 9215 | lp->ldg_num = ldg_num_map[i]; |
| 9216 | lp->timer = 2; /* XXX */ |
| 9217 | |
| 9218 | /* On N2 NIU the firmware has setup the SID mappings so they go |
| 9219 | * to the correct values that will route the LDG to the proper |
| 9220 | * interrupt in the NCU interrupt table. |
| 9221 | */ |
| 9222 | if (np->parent->plat_type != PLAT_TYPE_NIU) { |
| 9223 | err = niu_set_ldg_sid(np, lp->ldg_num, port, i); |
| 9224 | if (err) |
| 9225 | return err; |
| 9226 | } |
| 9227 | } |
| 9228 | |
| 9229 | /* We adopt the LDG assignment ordering used by the N2 NIU |
| 9230 | * 'interrupt' properties because that simplifies a lot of |
| 9231 | * things. This ordering is: |
| 9232 | * |
| 9233 | * MAC |
| 9234 | * MIF (if port zero) |
| 9235 | * SYSERR (if port zero) |
| 9236 | * RX channels |
| 9237 | * TX channels |
| 9238 | */ |
| 9239 | |
| 9240 | ldg_rotor = 0; |
| 9241 | |
| 9242 | err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor], |
| 9243 | LDN_MAC(port)); |
| 9244 | if (err) |
| 9245 | return err; |
| 9246 | |
| 9247 | ldg_rotor++; |
| 9248 | if (ldg_rotor == np->num_ldg) |
| 9249 | ldg_rotor = 0; |
| 9250 | |
| 9251 | if (port == 0) { |
| 9252 | err = niu_ldg_assign_ldn(np, parent, |
| 9253 | ldg_num_map[ldg_rotor], |
| 9254 | LDN_MIF); |
| 9255 | if (err) |
| 9256 | return err; |
| 9257 | |
| 9258 | ldg_rotor++; |
| 9259 | if (ldg_rotor == np->num_ldg) |
| 9260 | ldg_rotor = 0; |
| 9261 | |
| 9262 | err = niu_ldg_assign_ldn(np, parent, |
| 9263 | ldg_num_map[ldg_rotor], |
| 9264 | LDN_DEVICE_ERROR); |
| 9265 | if (err) |
| 9266 | return err; |
| 9267 | |
| 9268 | ldg_rotor++; |
| 9269 | if (ldg_rotor == np->num_ldg) |
| 9270 | ldg_rotor = 0; |
| 9271 | |
| 9272 | } |
| 9273 | |
| 9274 | first_chan = 0; |
| 9275 | for (i = 0; i < port; i++) |
| 9276 | first_chan += parent->rxchan_per_port[port]; |
| 9277 | num_chan = parent->rxchan_per_port[port]; |
| 9278 | |
| 9279 | for (i = first_chan; i < (first_chan + num_chan); i++) { |
| 9280 | err = niu_ldg_assign_ldn(np, parent, |
| 9281 | ldg_num_map[ldg_rotor], |
| 9282 | LDN_RXDMA(i)); |
| 9283 | if (err) |
| 9284 | return err; |
| 9285 | ldg_rotor++; |
| 9286 | if (ldg_rotor == np->num_ldg) |
| 9287 | ldg_rotor = 0; |
| 9288 | } |
| 9289 | |
| 9290 | first_chan = 0; |
| 9291 | for (i = 0; i < port; i++) |
| 9292 | first_chan += parent->txchan_per_port[port]; |
| 9293 | num_chan = parent->txchan_per_port[port]; |
| 9294 | for (i = first_chan; i < (first_chan + num_chan); i++) { |
| 9295 | err = niu_ldg_assign_ldn(np, parent, |
| 9296 | ldg_num_map[ldg_rotor], |
| 9297 | LDN_TXDMA(i)); |
| 9298 | if (err) |
| 9299 | return err; |
| 9300 | ldg_rotor++; |
| 9301 | if (ldg_rotor == np->num_ldg) |
| 9302 | ldg_rotor = 0; |
| 9303 | } |
| 9304 | |
| 9305 | return 0; |
| 9306 | } |
| 9307 | |
| 9308 | static void __devexit niu_ldg_free(struct niu *np) |
| 9309 | { |
| 9310 | if (np->flags & NIU_FLAGS_MSIX) |
| 9311 | pci_disable_msix(np->pdev); |
| 9312 | } |
| 9313 | |
| 9314 | static int __devinit niu_get_of_props(struct niu *np) |
| 9315 | { |
| 9316 | #ifdef CONFIG_SPARC64 |
| 9317 | struct net_device *dev = np->dev; |
| 9318 | struct device_node *dp; |
| 9319 | const char *phy_type; |
| 9320 | const u8 *mac_addr; |
| 9321 | const char *model; |
| 9322 | int prop_len; |
| 9323 | |
| 9324 | if (np->parent->plat_type == PLAT_TYPE_NIU) |
| 9325 | dp = np->op->node; |
| 9326 | else |
| 9327 | dp = pci_device_to_OF_node(np->pdev); |
| 9328 | |
| 9329 | phy_type = of_get_property(dp, "phy-type", &prop_len); |
| 9330 | if (!phy_type) { |
| 9331 | dev_err(np->device, PFX "%s: OF node lacks " |
| 9332 | "phy-type property\n", |
| 9333 | dp->full_name); |
| 9334 | return -EINVAL; |
| 9335 | } |
| 9336 | |
| 9337 | if (!strcmp(phy_type, "none")) |
| 9338 | return -ENODEV; |
| 9339 | |
| 9340 | strcpy(np->vpd.phy_type, phy_type); |
| 9341 | |
| 9342 | if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { |
| 9343 | dev_err(np->device, PFX "%s: Illegal phy string [%s].\n", |
| 9344 | dp->full_name, np->vpd.phy_type); |
| 9345 | return -EINVAL; |
| 9346 | } |
| 9347 | |
| 9348 | mac_addr = of_get_property(dp, "local-mac-address", &prop_len); |
| 9349 | if (!mac_addr) { |
| 9350 | dev_err(np->device, PFX "%s: OF node lacks " |
| 9351 | "local-mac-address property\n", |
| 9352 | dp->full_name); |
| 9353 | return -EINVAL; |
| 9354 | } |
| 9355 | if (prop_len != dev->addr_len) { |
| 9356 | dev_err(np->device, PFX "%s: OF MAC address prop len (%d) " |
| 9357 | "is wrong.\n", |
| 9358 | dp->full_name, prop_len); |
| 9359 | } |
| 9360 | memcpy(dev->perm_addr, mac_addr, dev->addr_len); |
| 9361 | if (!is_valid_ether_addr(&dev->perm_addr[0])) { |
| 9362 | int i; |
| 9363 | |
| 9364 | dev_err(np->device, PFX "%s: OF MAC address is invalid\n", |
| 9365 | dp->full_name); |
| 9366 | dev_err(np->device, PFX "%s: [ \n", |
| 9367 | dp->full_name); |
| 9368 | for (i = 0; i < 6; i++) |
| 9369 | printk("%02x ", dev->perm_addr[i]); |
| 9370 | printk("]\n"); |
| 9371 | return -EINVAL; |
| 9372 | } |
| 9373 | |
| 9374 | memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); |
| 9375 | |
| 9376 | model = of_get_property(dp, "model", &prop_len); |
| 9377 | |
| 9378 | if (model) |
| 9379 | strcpy(np->vpd.model, model); |
| 9380 | |
| 9381 | if (of_find_property(dp, "hot-swappable-phy", &prop_len)) { |
| 9382 | np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | |
| 9383 | NIU_FLAGS_HOTPLUG_PHY); |
| 9384 | } |
| 9385 | |
| 9386 | return 0; |
| 9387 | #else |
| 9388 | return -EINVAL; |
| 9389 | #endif |
| 9390 | } |
| 9391 | |
| 9392 | static int __devinit niu_get_invariants(struct niu *np) |
| 9393 | { |
| 9394 | int err, have_props; |
| 9395 | u32 offset; |
| 9396 | |
| 9397 | err = niu_get_of_props(np); |
| 9398 | if (err == -ENODEV) |
| 9399 | return err; |
| 9400 | |
| 9401 | have_props = !err; |
| 9402 | |
| 9403 | err = niu_init_mac_ipp_pcs_base(np); |
| 9404 | if (err) |
| 9405 | return err; |
| 9406 | |
| 9407 | if (have_props) { |
| 9408 | err = niu_get_and_validate_port(np); |
| 9409 | if (err) |
| 9410 | return err; |
| 9411 | |
| 9412 | } else { |
| 9413 | if (np->parent->plat_type == PLAT_TYPE_NIU) |
| 9414 | return -EINVAL; |
| 9415 | |
| 9416 | nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE); |
| 9417 | offset = niu_pci_vpd_offset(np); |
| 9418 | niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n", |
| 9419 | offset); |
| 9420 | if (offset) |
| 9421 | niu_pci_vpd_fetch(np, offset); |
| 9422 | nw64(ESPC_PIO_EN, 0); |
| 9423 | |
| 9424 | if (np->flags & NIU_FLAGS_VPD_VALID) { |
| 9425 | niu_pci_vpd_validate(np); |
| 9426 | err = niu_get_and_validate_port(np); |
| 9427 | if (err) |
| 9428 | return err; |
| 9429 | } |
| 9430 | |
| 9431 | if (!(np->flags & NIU_FLAGS_VPD_VALID)) { |
| 9432 | err = niu_get_and_validate_port(np); |
| 9433 | if (err) |
| 9434 | return err; |
| 9435 | err = niu_pci_probe_sprom(np); |
| 9436 | if (err) |
| 9437 | return err; |
| 9438 | } |
| 9439 | } |
| 9440 | |
| 9441 | err = niu_probe_ports(np); |
| 9442 | if (err) |
| 9443 | return err; |
| 9444 | |
| 9445 | niu_ldg_init(np); |
| 9446 | |
| 9447 | niu_classifier_swstate_init(np); |
| 9448 | niu_link_config_init(np); |
| 9449 | |
| 9450 | err = niu_determine_phy_disposition(np); |
| 9451 | if (!err) |
| 9452 | err = niu_init_link(np); |
| 9453 | |
| 9454 | return err; |
| 9455 | } |
| 9456 | |
| 9457 | static LIST_HEAD(niu_parent_list); |
| 9458 | static DEFINE_MUTEX(niu_parent_lock); |
| 9459 | static int niu_parent_index; |
| 9460 | |
| 9461 | static ssize_t show_port_phy(struct device *dev, |
| 9462 | struct device_attribute *attr, char *buf) |
| 9463 | { |
| 9464 | struct platform_device *plat_dev = to_platform_device(dev); |
| 9465 | struct niu_parent *p = plat_dev->dev.platform_data; |
| 9466 | u32 port_phy = p->port_phy; |
| 9467 | char *orig_buf = buf; |
| 9468 | int i; |
| 9469 | |
| 9470 | if (port_phy == PORT_PHY_UNKNOWN || |
| 9471 | port_phy == PORT_PHY_INVALID) |
| 9472 | return 0; |
| 9473 | |
| 9474 | for (i = 0; i < p->num_ports; i++) { |
| 9475 | const char *type_str; |
| 9476 | int type; |
| 9477 | |
| 9478 | type = phy_decode(port_phy, i); |
| 9479 | if (type == PORT_TYPE_10G) |
| 9480 | type_str = "10G"; |
| 9481 | else |
| 9482 | type_str = "1G"; |
| 9483 | buf += sprintf(buf, |
| 9484 | (i == 0) ? "%s" : " %s", |
| 9485 | type_str); |
| 9486 | } |
| 9487 | buf += sprintf(buf, "\n"); |
| 9488 | return buf - orig_buf; |
| 9489 | } |
| 9490 | |
| 9491 | static ssize_t show_plat_type(struct device *dev, |
| 9492 | struct device_attribute *attr, char *buf) |
| 9493 | { |
| 9494 | struct platform_device *plat_dev = to_platform_device(dev); |
| 9495 | struct niu_parent *p = plat_dev->dev.platform_data; |
| 9496 | const char *type_str; |
| 9497 | |
| 9498 | switch (p->plat_type) { |
| 9499 | case PLAT_TYPE_ATLAS: |
| 9500 | type_str = "atlas"; |
| 9501 | break; |
| 9502 | case PLAT_TYPE_NIU: |
| 9503 | type_str = "niu"; |
| 9504 | break; |
| 9505 | case PLAT_TYPE_VF_P0: |
| 9506 | type_str = "vf_p0"; |
| 9507 | break; |
| 9508 | case PLAT_TYPE_VF_P1: |
| 9509 | type_str = "vf_p1"; |
| 9510 | break; |
| 9511 | default: |
| 9512 | type_str = "unknown"; |
| 9513 | break; |
| 9514 | } |
| 9515 | |
| 9516 | return sprintf(buf, "%s\n", type_str); |
| 9517 | } |
| 9518 | |
| 9519 | static ssize_t __show_chan_per_port(struct device *dev, |
| 9520 | struct device_attribute *attr, char *buf, |
| 9521 | int rx) |
| 9522 | { |
| 9523 | struct platform_device *plat_dev = to_platform_device(dev); |
| 9524 | struct niu_parent *p = plat_dev->dev.platform_data; |
| 9525 | char *orig_buf = buf; |
| 9526 | u8 *arr; |
| 9527 | int i; |
| 9528 | |
| 9529 | arr = (rx ? p->rxchan_per_port : p->txchan_per_port); |
| 9530 | |
| 9531 | for (i = 0; i < p->num_ports; i++) { |
| 9532 | buf += sprintf(buf, |
| 9533 | (i == 0) ? "%d" : " %d", |
| 9534 | arr[i]); |
| 9535 | } |
| 9536 | buf += sprintf(buf, "\n"); |
| 9537 | |
| 9538 | return buf - orig_buf; |
| 9539 | } |
| 9540 | |
| 9541 | static ssize_t show_rxchan_per_port(struct device *dev, |
| 9542 | struct device_attribute *attr, char *buf) |
| 9543 | { |
| 9544 | return __show_chan_per_port(dev, attr, buf, 1); |
| 9545 | } |
| 9546 | |
| 9547 | static ssize_t show_txchan_per_port(struct device *dev, |
| 9548 | struct device_attribute *attr, char *buf) |
| 9549 | { |
| 9550 | return __show_chan_per_port(dev, attr, buf, 1); |
| 9551 | } |
| 9552 | |
| 9553 | static ssize_t show_num_ports(struct device *dev, |
| 9554 | struct device_attribute *attr, char *buf) |
| 9555 | { |
| 9556 | struct platform_device *plat_dev = to_platform_device(dev); |
| 9557 | struct niu_parent *p = plat_dev->dev.platform_data; |
| 9558 | |
| 9559 | return sprintf(buf, "%d\n", p->num_ports); |
| 9560 | } |
| 9561 | |
| 9562 | static struct device_attribute niu_parent_attributes[] = { |
| 9563 | __ATTR(port_phy, S_IRUGO, show_port_phy, NULL), |
| 9564 | __ATTR(plat_type, S_IRUGO, show_plat_type, NULL), |
| 9565 | __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL), |
| 9566 | __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL), |
| 9567 | __ATTR(num_ports, S_IRUGO, show_num_ports, NULL), |
| 9568 | {} |
| 9569 | }; |
| 9570 | |
| 9571 | static struct niu_parent * __devinit niu_new_parent(struct niu *np, |
| 9572 | union niu_parent_id *id, |
| 9573 | u8 ptype) |
| 9574 | { |
| 9575 | struct platform_device *plat_dev; |
| 9576 | struct niu_parent *p; |
| 9577 | int i; |
| 9578 | |
| 9579 | niudbg(PROBE, "niu_new_parent: Creating new parent.\n"); |
| 9580 | |
| 9581 | plat_dev = platform_device_register_simple("niu", niu_parent_index, |
| 9582 | NULL, 0); |
| 9583 | if (IS_ERR(plat_dev)) |
| 9584 | return NULL; |
| 9585 | |
| 9586 | for (i = 0; attr_name(niu_parent_attributes[i]); i++) { |
| 9587 | int err = device_create_file(&plat_dev->dev, |
| 9588 | &niu_parent_attributes[i]); |
| 9589 | if (err) |
| 9590 | goto fail_unregister; |
| 9591 | } |
| 9592 | |
| 9593 | p = kzalloc(sizeof(*p), GFP_KERNEL); |
| 9594 | if (!p) |
| 9595 | goto fail_unregister; |
| 9596 | |
| 9597 | p->index = niu_parent_index++; |
| 9598 | |
| 9599 | plat_dev->dev.platform_data = p; |
| 9600 | p->plat_dev = plat_dev; |
| 9601 | |
| 9602 | memcpy(&p->id, id, sizeof(*id)); |
| 9603 | p->plat_type = ptype; |
| 9604 | INIT_LIST_HEAD(&p->list); |
| 9605 | atomic_set(&p->refcnt, 0); |
| 9606 | list_add(&p->list, &niu_parent_list); |
| 9607 | spin_lock_init(&p->lock); |
| 9608 | |
| 9609 | p->rxdma_clock_divider = 7500; |
| 9610 | |
| 9611 | p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES; |
| 9612 | if (p->plat_type == PLAT_TYPE_NIU) |
| 9613 | p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES; |
| 9614 | |
| 9615 | for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { |
| 9616 | int index = i - CLASS_CODE_USER_PROG1; |
| 9617 | |
| 9618 | p->tcam_key[index] = TCAM_KEY_TSEL; |
| 9619 | p->flow_key[index] = (FLOW_KEY_IPSA | |
| 9620 | FLOW_KEY_IPDA | |
| 9621 | FLOW_KEY_PROTO | |
| 9622 | (FLOW_KEY_L4_BYTE12 << |
| 9623 | FLOW_KEY_L4_0_SHIFT) | |
| 9624 | (FLOW_KEY_L4_BYTE12 << |
| 9625 | FLOW_KEY_L4_1_SHIFT)); |
| 9626 | } |
| 9627 | |
| 9628 | for (i = 0; i < LDN_MAX + 1; i++) |
| 9629 | p->ldg_map[i] = LDG_INVALID; |
| 9630 | |
| 9631 | return p; |
| 9632 | |
| 9633 | fail_unregister: |
| 9634 | platform_device_unregister(plat_dev); |
| 9635 | return NULL; |
| 9636 | } |
| 9637 | |
| 9638 | static struct niu_parent * __devinit niu_get_parent(struct niu *np, |
| 9639 | union niu_parent_id *id, |
| 9640 | u8 ptype) |
| 9641 | { |
| 9642 | struct niu_parent *p, *tmp; |
| 9643 | int port = np->port; |
| 9644 | |
| 9645 | niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n", |
| 9646 | ptype, port); |
| 9647 | |
| 9648 | mutex_lock(&niu_parent_lock); |
| 9649 | p = NULL; |
| 9650 | list_for_each_entry(tmp, &niu_parent_list, list) { |
| 9651 | if (!memcmp(id, &tmp->id, sizeof(*id))) { |
| 9652 | p = tmp; |
| 9653 | break; |
| 9654 | } |
| 9655 | } |
| 9656 | if (!p) |
| 9657 | p = niu_new_parent(np, id, ptype); |
| 9658 | |
| 9659 | if (p) { |
| 9660 | char port_name[6]; |
| 9661 | int err; |
| 9662 | |
| 9663 | sprintf(port_name, "port%d", port); |
| 9664 | err = sysfs_create_link(&p->plat_dev->dev.kobj, |
| 9665 | &np->device->kobj, |
| 9666 | port_name); |
| 9667 | if (!err) { |
| 9668 | p->ports[port] = np; |
| 9669 | atomic_inc(&p->refcnt); |
| 9670 | } |
| 9671 | } |
| 9672 | mutex_unlock(&niu_parent_lock); |
| 9673 | |
| 9674 | return p; |
| 9675 | } |
| 9676 | |
| 9677 | static void niu_put_parent(struct niu *np) |
| 9678 | { |
| 9679 | struct niu_parent *p = np->parent; |
| 9680 | u8 port = np->port; |
| 9681 | char port_name[6]; |
| 9682 | |
| 9683 | BUG_ON(!p || p->ports[port] != np); |
| 9684 | |
| 9685 | niudbg(PROBE, "niu_put_parent: port[%u]\n", port); |
| 9686 | |
| 9687 | sprintf(port_name, "port%d", port); |
| 9688 | |
| 9689 | mutex_lock(&niu_parent_lock); |
| 9690 | |
| 9691 | sysfs_remove_link(&p->plat_dev->dev.kobj, port_name); |
| 9692 | |
| 9693 | p->ports[port] = NULL; |
| 9694 | np->parent = NULL; |
| 9695 | |
| 9696 | if (atomic_dec_and_test(&p->refcnt)) { |
| 9697 | list_del(&p->list); |
| 9698 | platform_device_unregister(p->plat_dev); |
| 9699 | } |
| 9700 | |
| 9701 | mutex_unlock(&niu_parent_lock); |
| 9702 | } |
| 9703 | |
| 9704 | static void *niu_pci_alloc_coherent(struct device *dev, size_t size, |
| 9705 | u64 *handle, gfp_t flag) |
| 9706 | { |
| 9707 | dma_addr_t dh; |
| 9708 | void *ret; |
| 9709 | |
| 9710 | ret = dma_alloc_coherent(dev, size, &dh, flag); |
| 9711 | if (ret) |
| 9712 | *handle = dh; |
| 9713 | return ret; |
| 9714 | } |
| 9715 | |
| 9716 | static void niu_pci_free_coherent(struct device *dev, size_t size, |
| 9717 | void *cpu_addr, u64 handle) |
| 9718 | { |
| 9719 | dma_free_coherent(dev, size, cpu_addr, handle); |
| 9720 | } |
| 9721 | |
| 9722 | static u64 niu_pci_map_page(struct device *dev, struct page *page, |
| 9723 | unsigned long offset, size_t size, |
| 9724 | enum dma_data_direction direction) |
| 9725 | { |
| 9726 | return dma_map_page(dev, page, offset, size, direction); |
| 9727 | } |
| 9728 | |
| 9729 | static void niu_pci_unmap_page(struct device *dev, u64 dma_address, |
| 9730 | size_t size, enum dma_data_direction direction) |
| 9731 | { |
| 9732 | dma_unmap_page(dev, dma_address, size, direction); |
| 9733 | } |
| 9734 | |
| 9735 | static u64 niu_pci_map_single(struct device *dev, void *cpu_addr, |
| 9736 | size_t size, |
| 9737 | enum dma_data_direction direction) |
| 9738 | { |
| 9739 | return dma_map_single(dev, cpu_addr, size, direction); |
| 9740 | } |
| 9741 | |
| 9742 | static void niu_pci_unmap_single(struct device *dev, u64 dma_address, |
| 9743 | size_t size, |
| 9744 | enum dma_data_direction direction) |
| 9745 | { |
| 9746 | dma_unmap_single(dev, dma_address, size, direction); |
| 9747 | } |
| 9748 | |
| 9749 | static const struct niu_ops niu_pci_ops = { |
| 9750 | .alloc_coherent = niu_pci_alloc_coherent, |
| 9751 | .free_coherent = niu_pci_free_coherent, |
| 9752 | .map_page = niu_pci_map_page, |
| 9753 | .unmap_page = niu_pci_unmap_page, |
| 9754 | .map_single = niu_pci_map_single, |
| 9755 | .unmap_single = niu_pci_unmap_single, |
| 9756 | }; |
| 9757 | |
| 9758 | static void __devinit niu_driver_version(void) |
| 9759 | { |
| 9760 | static int niu_version_printed; |
| 9761 | |
| 9762 | if (niu_version_printed++ == 0) |
| 9763 | pr_info("%s", version); |
| 9764 | } |
| 9765 | |
| 9766 | static struct net_device * __devinit niu_alloc_and_init( |
| 9767 | struct device *gen_dev, struct pci_dev *pdev, |
| 9768 | struct of_device *op, const struct niu_ops *ops, |
| 9769 | u8 port) |
| 9770 | { |
| 9771 | struct net_device *dev; |
| 9772 | struct niu *np; |
| 9773 | |
| 9774 | dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN); |
| 9775 | if (!dev) { |
| 9776 | dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n"); |
| 9777 | return NULL; |
| 9778 | } |
| 9779 | |
| 9780 | SET_NETDEV_DEV(dev, gen_dev); |
| 9781 | |
| 9782 | np = netdev_priv(dev); |
| 9783 | np->dev = dev; |
| 9784 | np->pdev = pdev; |
| 9785 | np->op = op; |
| 9786 | np->device = gen_dev; |
| 9787 | np->ops = ops; |
| 9788 | |
| 9789 | np->msg_enable = niu_debug; |
| 9790 | |
| 9791 | spin_lock_init(&np->lock); |
| 9792 | INIT_WORK(&np->reset_task, niu_reset_task); |
| 9793 | |
| 9794 | np->port = port; |
| 9795 | |
| 9796 | return dev; |
| 9797 | } |
| 9798 | |
| 9799 | static const struct net_device_ops niu_netdev_ops = { |
| 9800 | .ndo_open = niu_open, |
| 9801 | .ndo_stop = niu_close, |
| 9802 | .ndo_start_xmit = niu_start_xmit, |
| 9803 | .ndo_get_stats = niu_get_stats, |
| 9804 | .ndo_set_multicast_list = niu_set_rx_mode, |
| 9805 | .ndo_validate_addr = eth_validate_addr, |
| 9806 | .ndo_set_mac_address = niu_set_mac_addr, |
| 9807 | .ndo_do_ioctl = niu_ioctl, |
| 9808 | .ndo_tx_timeout = niu_tx_timeout, |
| 9809 | .ndo_change_mtu = niu_change_mtu, |
| 9810 | }; |
| 9811 | |
| 9812 | static void __devinit niu_assign_netdev_ops(struct net_device *dev) |
| 9813 | { |
| 9814 | dev->netdev_ops = &niu_netdev_ops; |
| 9815 | dev->ethtool_ops = &niu_ethtool_ops; |
| 9816 | dev->watchdog_timeo = NIU_TX_TIMEOUT; |
| 9817 | } |
| 9818 | |
| 9819 | static void __devinit niu_device_announce(struct niu *np) |
| 9820 | { |
| 9821 | struct net_device *dev = np->dev; |
| 9822 | |
| 9823 | pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr); |
| 9824 | |
| 9825 | if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) { |
| 9826 | pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", |
| 9827 | dev->name, |
| 9828 | (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), |
| 9829 | (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), |
| 9830 | (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"), |
| 9831 | (np->mac_xcvr == MAC_XCVR_MII ? "MII" : |
| 9832 | (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), |
| 9833 | np->vpd.phy_type); |
| 9834 | } else { |
| 9835 | pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", |
| 9836 | dev->name, |
| 9837 | (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), |
| 9838 | (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), |
| 9839 | (np->flags & NIU_FLAGS_FIBER ? "FIBER" : |
| 9840 | (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" : |
| 9841 | "COPPER")), |
| 9842 | (np->mac_xcvr == MAC_XCVR_MII ? "MII" : |
| 9843 | (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), |
| 9844 | np->vpd.phy_type); |
| 9845 | } |
| 9846 | } |
| 9847 | |
| 9848 | static int __devinit niu_pci_init_one(struct pci_dev *pdev, |
| 9849 | const struct pci_device_id *ent) |
| 9850 | { |
| 9851 | union niu_parent_id parent_id; |
| 9852 | struct net_device *dev; |
| 9853 | struct niu *np; |
| 9854 | int err, pos; |
| 9855 | u64 dma_mask; |
| 9856 | u16 val16; |
| 9857 | |
| 9858 | niu_driver_version(); |
| 9859 | |
| 9860 | err = pci_enable_device(pdev); |
| 9861 | if (err) { |
| 9862 | dev_err(&pdev->dev, PFX "Cannot enable PCI device, " |
| 9863 | "aborting.\n"); |
| 9864 | return err; |
| 9865 | } |
| 9866 | |
| 9867 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || |
| 9868 | !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
| 9869 | dev_err(&pdev->dev, PFX "Cannot find proper PCI device " |
| 9870 | "base addresses, aborting.\n"); |
| 9871 | err = -ENODEV; |
| 9872 | goto err_out_disable_pdev; |
| 9873 | } |
| 9874 | |
| 9875 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
| 9876 | if (err) { |
| 9877 | dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, " |
| 9878 | "aborting.\n"); |
| 9879 | goto err_out_disable_pdev; |
| 9880 | } |
| 9881 | |
| 9882 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
| 9883 | if (pos <= 0) { |
| 9884 | dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, " |
| 9885 | "aborting.\n"); |
| 9886 | goto err_out_free_res; |
| 9887 | } |
| 9888 | |
| 9889 | dev = niu_alloc_and_init(&pdev->dev, pdev, NULL, |
| 9890 | &niu_pci_ops, PCI_FUNC(pdev->devfn)); |
| 9891 | if (!dev) { |
| 9892 | err = -ENOMEM; |
| 9893 | goto err_out_free_res; |
| 9894 | } |
| 9895 | np = netdev_priv(dev); |
| 9896 | |
| 9897 | memset(&parent_id, 0, sizeof(parent_id)); |
| 9898 | parent_id.pci.domain = pci_domain_nr(pdev->bus); |
| 9899 | parent_id.pci.bus = pdev->bus->number; |
| 9900 | parent_id.pci.device = PCI_SLOT(pdev->devfn); |
| 9901 | |
| 9902 | np->parent = niu_get_parent(np, &parent_id, |
| 9903 | PLAT_TYPE_ATLAS); |
| 9904 | if (!np->parent) { |
| 9905 | err = -ENOMEM; |
| 9906 | goto err_out_free_dev; |
| 9907 | } |
| 9908 | |
| 9909 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16); |
| 9910 | val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; |
| 9911 | val16 |= (PCI_EXP_DEVCTL_CERE | |
| 9912 | PCI_EXP_DEVCTL_NFERE | |
| 9913 | PCI_EXP_DEVCTL_FERE | |
| 9914 | PCI_EXP_DEVCTL_URRE | |
| 9915 | PCI_EXP_DEVCTL_RELAX_EN); |
| 9916 | pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16); |
| 9917 | |
| 9918 | dma_mask = DMA_44BIT_MASK; |
| 9919 | err = pci_set_dma_mask(pdev, dma_mask); |
| 9920 | if (!err) { |
| 9921 | dev->features |= NETIF_F_HIGHDMA; |
| 9922 | err = pci_set_consistent_dma_mask(pdev, dma_mask); |
| 9923 | if (err) { |
| 9924 | dev_err(&pdev->dev, PFX "Unable to obtain 44 bit " |
| 9925 | "DMA for consistent allocations, " |
| 9926 | "aborting.\n"); |
| 9927 | goto err_out_release_parent; |
| 9928 | } |
| 9929 | } |
| 9930 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
| 9931 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
| 9932 | if (err) { |
| 9933 | dev_err(&pdev->dev, PFX "No usable DMA configuration, " |
| 9934 | "aborting.\n"); |
| 9935 | goto err_out_release_parent; |
| 9936 | } |
| 9937 | } |
| 9938 | |
| 9939 | dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM); |
| 9940 | |
| 9941 | np->regs = pci_ioremap_bar(pdev, 0); |
| 9942 | if (!np->regs) { |
| 9943 | dev_err(&pdev->dev, PFX "Cannot map device registers, " |
| 9944 | "aborting.\n"); |
| 9945 | err = -ENOMEM; |
| 9946 | goto err_out_release_parent; |
| 9947 | } |
| 9948 | |
| 9949 | pci_set_master(pdev); |
| 9950 | pci_save_state(pdev); |
| 9951 | |
| 9952 | dev->irq = pdev->irq; |
| 9953 | |
| 9954 | niu_assign_netdev_ops(dev); |
| 9955 | |
| 9956 | err = niu_get_invariants(np); |
| 9957 | if (err) { |
| 9958 | if (err != -ENODEV) |
| 9959 | dev_err(&pdev->dev, PFX "Problem fetching invariants " |
| 9960 | "of chip, aborting.\n"); |
| 9961 | goto err_out_iounmap; |
| 9962 | } |
| 9963 | |
| 9964 | err = register_netdev(dev); |
| 9965 | if (err) { |
| 9966 | dev_err(&pdev->dev, PFX "Cannot register net device, " |
| 9967 | "aborting.\n"); |
| 9968 | goto err_out_iounmap; |
| 9969 | } |
| 9970 | |
| 9971 | pci_set_drvdata(pdev, dev); |
| 9972 | |
| 9973 | niu_device_announce(np); |
| 9974 | |
| 9975 | return 0; |
| 9976 | |
| 9977 | err_out_iounmap: |
| 9978 | if (np->regs) { |
| 9979 | iounmap(np->regs); |
| 9980 | np->regs = NULL; |
| 9981 | } |
| 9982 | |
| 9983 | err_out_release_parent: |
| 9984 | niu_put_parent(np); |
| 9985 | |
| 9986 | err_out_free_dev: |
| 9987 | free_netdev(dev); |
| 9988 | |
| 9989 | err_out_free_res: |
| 9990 | pci_release_regions(pdev); |
| 9991 | |
| 9992 | err_out_disable_pdev: |
| 9993 | pci_disable_device(pdev); |
| 9994 | pci_set_drvdata(pdev, NULL); |
| 9995 | |
| 9996 | return err; |
| 9997 | } |
| 9998 | |
| 9999 | static void __devexit niu_pci_remove_one(struct pci_dev *pdev) |
| 10000 | { |
| 10001 | struct net_device *dev = pci_get_drvdata(pdev); |
| 10002 | |
| 10003 | if (dev) { |
| 10004 | struct niu *np = netdev_priv(dev); |
| 10005 | |
| 10006 | unregister_netdev(dev); |
| 10007 | if (np->regs) { |
| 10008 | iounmap(np->regs); |
| 10009 | np->regs = NULL; |
| 10010 | } |
| 10011 | |
| 10012 | niu_ldg_free(np); |
| 10013 | |
| 10014 | niu_put_parent(np); |
| 10015 | |
| 10016 | free_netdev(dev); |
| 10017 | pci_release_regions(pdev); |
| 10018 | pci_disable_device(pdev); |
| 10019 | pci_set_drvdata(pdev, NULL); |
| 10020 | } |
| 10021 | } |
| 10022 | |
| 10023 | static int niu_suspend(struct pci_dev *pdev, pm_message_t state) |
| 10024 | { |
| 10025 | struct net_device *dev = pci_get_drvdata(pdev); |
| 10026 | struct niu *np = netdev_priv(dev); |
| 10027 | unsigned long flags; |
| 10028 | |
| 10029 | if (!netif_running(dev)) |
| 10030 | return 0; |
| 10031 | |
| 10032 | flush_scheduled_work(); |
| 10033 | niu_netif_stop(np); |
| 10034 | |
| 10035 | del_timer_sync(&np->timer); |
| 10036 | |
| 10037 | spin_lock_irqsave(&np->lock, flags); |
| 10038 | niu_enable_interrupts(np, 0); |
| 10039 | spin_unlock_irqrestore(&np->lock, flags); |
| 10040 | |
| 10041 | netif_device_detach(dev); |
| 10042 | |
| 10043 | spin_lock_irqsave(&np->lock, flags); |
| 10044 | niu_stop_hw(np); |
| 10045 | spin_unlock_irqrestore(&np->lock, flags); |
| 10046 | |
| 10047 | pci_save_state(pdev); |
| 10048 | |
| 10049 | return 0; |
| 10050 | } |
| 10051 | |
| 10052 | static int niu_resume(struct pci_dev *pdev) |
| 10053 | { |
| 10054 | struct net_device *dev = pci_get_drvdata(pdev); |
| 10055 | struct niu *np = netdev_priv(dev); |
| 10056 | unsigned long flags; |
| 10057 | int err; |
| 10058 | |
| 10059 | if (!netif_running(dev)) |
| 10060 | return 0; |
| 10061 | |
| 10062 | pci_restore_state(pdev); |
| 10063 | |
| 10064 | netif_device_attach(dev); |
| 10065 | |
| 10066 | spin_lock_irqsave(&np->lock, flags); |
| 10067 | |
| 10068 | err = niu_init_hw(np); |
| 10069 | if (!err) { |
| 10070 | np->timer.expires = jiffies + HZ; |
| 10071 | add_timer(&np->timer); |
| 10072 | niu_netif_start(np); |
| 10073 | } |
| 10074 | |
| 10075 | spin_unlock_irqrestore(&np->lock, flags); |
| 10076 | |
| 10077 | return err; |
| 10078 | } |
| 10079 | |
| 10080 | static struct pci_driver niu_pci_driver = { |
| 10081 | .name = DRV_MODULE_NAME, |
| 10082 | .id_table = niu_pci_tbl, |
| 10083 | .probe = niu_pci_init_one, |
| 10084 | .remove = __devexit_p(niu_pci_remove_one), |
| 10085 | .suspend = niu_suspend, |
| 10086 | .resume = niu_resume, |
| 10087 | }; |
| 10088 | |
| 10089 | #ifdef CONFIG_SPARC64 |
| 10090 | static void *niu_phys_alloc_coherent(struct device *dev, size_t size, |
| 10091 | u64 *dma_addr, gfp_t flag) |
| 10092 | { |
| 10093 | unsigned long order = get_order(size); |
| 10094 | unsigned long page = __get_free_pages(flag, order); |
| 10095 | |
| 10096 | if (page == 0UL) |
| 10097 | return NULL; |
| 10098 | memset((char *)page, 0, PAGE_SIZE << order); |
| 10099 | *dma_addr = __pa(page); |
| 10100 | |
| 10101 | return (void *) page; |
| 10102 | } |
| 10103 | |
| 10104 | static void niu_phys_free_coherent(struct device *dev, size_t size, |
| 10105 | void *cpu_addr, u64 handle) |
| 10106 | { |
| 10107 | unsigned long order = get_order(size); |
| 10108 | |
| 10109 | free_pages((unsigned long) cpu_addr, order); |
| 10110 | } |
| 10111 | |
| 10112 | static u64 niu_phys_map_page(struct device *dev, struct page *page, |
| 10113 | unsigned long offset, size_t size, |
| 10114 | enum dma_data_direction direction) |
| 10115 | { |
| 10116 | return page_to_phys(page) + offset; |
| 10117 | } |
| 10118 | |
| 10119 | static void niu_phys_unmap_page(struct device *dev, u64 dma_address, |
| 10120 | size_t size, enum dma_data_direction direction) |
| 10121 | { |
| 10122 | /* Nothing to do. */ |
| 10123 | } |
| 10124 | |
| 10125 | static u64 niu_phys_map_single(struct device *dev, void *cpu_addr, |
| 10126 | size_t size, |
| 10127 | enum dma_data_direction direction) |
| 10128 | { |
| 10129 | return __pa(cpu_addr); |
| 10130 | } |
| 10131 | |
| 10132 | static void niu_phys_unmap_single(struct device *dev, u64 dma_address, |
| 10133 | size_t size, |
| 10134 | enum dma_data_direction direction) |
| 10135 | { |
| 10136 | /* Nothing to do. */ |
| 10137 | } |
| 10138 | |
| 10139 | static const struct niu_ops niu_phys_ops = { |
| 10140 | .alloc_coherent = niu_phys_alloc_coherent, |
| 10141 | .free_coherent = niu_phys_free_coherent, |
| 10142 | .map_page = niu_phys_map_page, |
| 10143 | .unmap_page = niu_phys_unmap_page, |
| 10144 | .map_single = niu_phys_map_single, |
| 10145 | .unmap_single = niu_phys_unmap_single, |
| 10146 | }; |
| 10147 | |
| 10148 | static int __devinit niu_of_probe(struct of_device *op, |
| 10149 | const struct of_device_id *match) |
| 10150 | { |
| 10151 | union niu_parent_id parent_id; |
| 10152 | struct net_device *dev; |
| 10153 | struct niu *np; |
| 10154 | const u32 *reg; |
| 10155 | int err; |
| 10156 | |
| 10157 | niu_driver_version(); |
| 10158 | |
| 10159 | reg = of_get_property(op->node, "reg", NULL); |
| 10160 | if (!reg) { |
| 10161 | dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n", |
| 10162 | op->node->full_name); |
| 10163 | return -ENODEV; |
| 10164 | } |
| 10165 | |
| 10166 | dev = niu_alloc_and_init(&op->dev, NULL, op, |
| 10167 | &niu_phys_ops, reg[0] & 0x1); |
| 10168 | if (!dev) { |
| 10169 | err = -ENOMEM; |
| 10170 | goto err_out; |
| 10171 | } |
| 10172 | np = netdev_priv(dev); |
| 10173 | |
| 10174 | memset(&parent_id, 0, sizeof(parent_id)); |
| 10175 | parent_id.of = of_get_parent(op->node); |
| 10176 | |
| 10177 | np->parent = niu_get_parent(np, &parent_id, |
| 10178 | PLAT_TYPE_NIU); |
| 10179 | if (!np->parent) { |
| 10180 | err = -ENOMEM; |
| 10181 | goto err_out_free_dev; |
| 10182 | } |
| 10183 | |
| 10184 | dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM); |
| 10185 | |
| 10186 | np->regs = of_ioremap(&op->resource[1], 0, |
| 10187 | resource_size(&op->resource[1]), |
| 10188 | "niu regs"); |
| 10189 | if (!np->regs) { |
| 10190 | dev_err(&op->dev, PFX "Cannot map device registers, " |
| 10191 | "aborting.\n"); |
| 10192 | err = -ENOMEM; |
| 10193 | goto err_out_release_parent; |
| 10194 | } |
| 10195 | |
| 10196 | np->vir_regs_1 = of_ioremap(&op->resource[2], 0, |
| 10197 | resource_size(&op->resource[2]), |
| 10198 | "niu vregs-1"); |
| 10199 | if (!np->vir_regs_1) { |
| 10200 | dev_err(&op->dev, PFX "Cannot map device vir registers 1, " |
| 10201 | "aborting.\n"); |
| 10202 | err = -ENOMEM; |
| 10203 | goto err_out_iounmap; |
| 10204 | } |
| 10205 | |
| 10206 | np->vir_regs_2 = of_ioremap(&op->resource[3], 0, |
| 10207 | resource_size(&op->resource[3]), |
| 10208 | "niu vregs-2"); |
| 10209 | if (!np->vir_regs_2) { |
| 10210 | dev_err(&op->dev, PFX "Cannot map device vir registers 2, " |
| 10211 | "aborting.\n"); |
| 10212 | err = -ENOMEM; |
| 10213 | goto err_out_iounmap; |
| 10214 | } |
| 10215 | |
| 10216 | niu_assign_netdev_ops(dev); |
| 10217 | |
| 10218 | err = niu_get_invariants(np); |
| 10219 | if (err) { |
| 10220 | if (err != -ENODEV) |
| 10221 | dev_err(&op->dev, PFX "Problem fetching invariants " |
| 10222 | "of chip, aborting.\n"); |
| 10223 | goto err_out_iounmap; |
| 10224 | } |
| 10225 | |
| 10226 | err = register_netdev(dev); |
| 10227 | if (err) { |
| 10228 | dev_err(&op->dev, PFX "Cannot register net device, " |
| 10229 | "aborting.\n"); |
| 10230 | goto err_out_iounmap; |
| 10231 | } |
| 10232 | |
| 10233 | dev_set_drvdata(&op->dev, dev); |
| 10234 | |
| 10235 | niu_device_announce(np); |
| 10236 | |
| 10237 | return 0; |
| 10238 | |
| 10239 | err_out_iounmap: |
| 10240 | if (np->vir_regs_1) { |
| 10241 | of_iounmap(&op->resource[2], np->vir_regs_1, |
| 10242 | resource_size(&op->resource[2])); |
| 10243 | np->vir_regs_1 = NULL; |
| 10244 | } |
| 10245 | |
| 10246 | if (np->vir_regs_2) { |
| 10247 | of_iounmap(&op->resource[3], np->vir_regs_2, |
| 10248 | resource_size(&op->resource[3])); |
| 10249 | np->vir_regs_2 = NULL; |
| 10250 | } |
| 10251 | |
| 10252 | if (np->regs) { |
| 10253 | of_iounmap(&op->resource[1], np->regs, |
| 10254 | resource_size(&op->resource[1])); |
| 10255 | np->regs = NULL; |
| 10256 | } |
| 10257 | |
| 10258 | err_out_release_parent: |
| 10259 | niu_put_parent(np); |
| 10260 | |
| 10261 | err_out_free_dev: |
| 10262 | free_netdev(dev); |
| 10263 | |
| 10264 | err_out: |
| 10265 | return err; |
| 10266 | } |
| 10267 | |
| 10268 | static int __devexit niu_of_remove(struct of_device *op) |
| 10269 | { |
| 10270 | struct net_device *dev = dev_get_drvdata(&op->dev); |
| 10271 | |
| 10272 | if (dev) { |
| 10273 | struct niu *np = netdev_priv(dev); |
| 10274 | |
| 10275 | unregister_netdev(dev); |
| 10276 | |
| 10277 | if (np->vir_regs_1) { |
| 10278 | of_iounmap(&op->resource[2], np->vir_regs_1, |
| 10279 | resource_size(&op->resource[2])); |
| 10280 | np->vir_regs_1 = NULL; |
| 10281 | } |
| 10282 | |
| 10283 | if (np->vir_regs_2) { |
| 10284 | of_iounmap(&op->resource[3], np->vir_regs_2, |
| 10285 | resource_size(&op->resource[3])); |
| 10286 | np->vir_regs_2 = NULL; |
| 10287 | } |
| 10288 | |
| 10289 | if (np->regs) { |
| 10290 | of_iounmap(&op->resource[1], np->regs, |
| 10291 | resource_size(&op->resource[1])); |
| 10292 | np->regs = NULL; |
| 10293 | } |
| 10294 | |
| 10295 | niu_ldg_free(np); |
| 10296 | |
| 10297 | niu_put_parent(np); |
| 10298 | |
| 10299 | free_netdev(dev); |
| 10300 | dev_set_drvdata(&op->dev, NULL); |
| 10301 | } |
| 10302 | return 0; |
| 10303 | } |
| 10304 | |
| 10305 | static const struct of_device_id niu_match[] = { |
| 10306 | { |
| 10307 | .name = "network", |
| 10308 | .compatible = "SUNW,niusl", |
| 10309 | }, |
| 10310 | {}, |
| 10311 | }; |
| 10312 | MODULE_DEVICE_TABLE(of, niu_match); |
| 10313 | |
| 10314 | static struct of_platform_driver niu_of_driver = { |
| 10315 | .name = "niu", |
| 10316 | .match_table = niu_match, |
| 10317 | .probe = niu_of_probe, |
| 10318 | .remove = __devexit_p(niu_of_remove), |
| 10319 | }; |
| 10320 | |
| 10321 | #endif /* CONFIG_SPARC64 */ |
| 10322 | |
| 10323 | static int __init niu_init(void) |
| 10324 | { |
| 10325 | int err = 0; |
| 10326 | |
| 10327 | BUILD_BUG_ON(PAGE_SIZE < 4 * 1024); |
| 10328 | |
| 10329 | niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT); |
| 10330 | |
| 10331 | #ifdef CONFIG_SPARC64 |
| 10332 | err = of_register_driver(&niu_of_driver, &of_bus_type); |
| 10333 | #endif |
| 10334 | |
| 10335 | if (!err) { |
| 10336 | err = pci_register_driver(&niu_pci_driver); |
| 10337 | #ifdef CONFIG_SPARC64 |
| 10338 | if (err) |
| 10339 | of_unregister_driver(&niu_of_driver); |
| 10340 | #endif |
| 10341 | } |
| 10342 | |
| 10343 | return err; |
| 10344 | } |
| 10345 | |
| 10346 | static void __exit niu_exit(void) |
| 10347 | { |
| 10348 | pci_unregister_driver(&niu_pci_driver); |
| 10349 | #ifdef CONFIG_SPARC64 |
| 10350 | of_unregister_driver(&niu_of_driver); |
| 10351 | #endif |
| 10352 | } |
| 10353 | |
| 10354 | module_init(niu_init); |
| 10355 | module_exit(niu_exit); |