| 1 | /* |
| 2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. |
| 3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) |
| 4 | * |
| 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
| 6 | * pages and then divide them into 2K frame buffers. This way I know I |
| 7 | * have buffers large enough to hold one frame within one buffer descriptor. |
| 8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which |
| 9 | * will be much more memory efficient and will easily handle lots of |
| 10 | * small packets. |
| 11 | * |
| 12 | * Much better multiple PHY support by Magnus Damm. |
| 13 | * Copyright (c) 2000 Ericsson Radio Systems AB. |
| 14 | * |
| 15 | * Support for FEC controller of ColdFire processors. |
| 16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) |
| 17 | * |
| 18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) |
| 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
| 20 | */ |
| 21 | |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/kernel.h> |
| 24 | #include <linux/string.h> |
| 25 | #include <linux/ptrace.h> |
| 26 | #include <linux/errno.h> |
| 27 | #include <linux/ioport.h> |
| 28 | #include <linux/slab.h> |
| 29 | #include <linux/interrupt.h> |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/init.h> |
| 32 | #include <linux/delay.h> |
| 33 | #include <linux/netdevice.h> |
| 34 | #include <linux/etherdevice.h> |
| 35 | #include <linux/skbuff.h> |
| 36 | #include <linux/spinlock.h> |
| 37 | #include <linux/workqueue.h> |
| 38 | #include <linux/bitops.h> |
| 39 | #include <linux/io.h> |
| 40 | #include <linux/irq.h> |
| 41 | #include <linux/clk.h> |
| 42 | #include <linux/platform_device.h> |
| 43 | |
| 44 | #include <asm/cacheflush.h> |
| 45 | |
| 46 | #ifndef CONFIG_ARCH_MXC |
| 47 | #include <asm/coldfire.h> |
| 48 | #include <asm/mcfsim.h> |
| 49 | #endif |
| 50 | |
| 51 | #include "fec.h" |
| 52 | |
| 53 | #ifdef CONFIG_ARCH_MXC |
| 54 | #include <mach/hardware.h> |
| 55 | #define FEC_ALIGNMENT 0xf |
| 56 | #else |
| 57 | #define FEC_ALIGNMENT 0x3 |
| 58 | #endif |
| 59 | |
| 60 | /* |
| 61 | * Define the fixed address of the FEC hardware. |
| 62 | */ |
| 63 | #if defined(CONFIG_M5272) |
| 64 | #define HAVE_mii_link_interrupt |
| 65 | |
| 66 | static unsigned char fec_mac_default[] = { |
| 67 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 68 | }; |
| 69 | |
| 70 | /* |
| 71 | * Some hardware gets it MAC address out of local flash memory. |
| 72 | * if this is non-zero then assume it is the address to get MAC from. |
| 73 | */ |
| 74 | #if defined(CONFIG_NETtel) |
| 75 | #define FEC_FLASHMAC 0xf0006006 |
| 76 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) |
| 77 | #define FEC_FLASHMAC 0xf0006000 |
| 78 | #elif defined(CONFIG_CANCam) |
| 79 | #define FEC_FLASHMAC 0xf0020000 |
| 80 | #elif defined (CONFIG_M5272C3) |
| 81 | #define FEC_FLASHMAC (0xffe04000 + 4) |
| 82 | #elif defined(CONFIG_MOD5272) |
| 83 | #define FEC_FLASHMAC 0xffc0406b |
| 84 | #else |
| 85 | #define FEC_FLASHMAC 0 |
| 86 | #endif |
| 87 | #endif /* CONFIG_M5272 */ |
| 88 | |
| 89 | /* Forward declarations of some structures to support different PHYs */ |
| 90 | |
| 91 | typedef struct { |
| 92 | uint mii_data; |
| 93 | void (*funct)(uint mii_reg, struct net_device *dev); |
| 94 | } phy_cmd_t; |
| 95 | |
| 96 | typedef struct { |
| 97 | uint id; |
| 98 | char *name; |
| 99 | |
| 100 | const phy_cmd_t *config; |
| 101 | const phy_cmd_t *startup; |
| 102 | const phy_cmd_t *ack_int; |
| 103 | const phy_cmd_t *shutdown; |
| 104 | } phy_info_t; |
| 105 | |
| 106 | /* The number of Tx and Rx buffers. These are allocated from the page |
| 107 | * pool. The code may assume these are power of two, so it it best |
| 108 | * to keep them that size. |
| 109 | * We don't need to allocate pages for the transmitter. We just use |
| 110 | * the skbuffer directly. |
| 111 | */ |
| 112 | #define FEC_ENET_RX_PAGES 8 |
| 113 | #define FEC_ENET_RX_FRSIZE 2048 |
| 114 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) |
| 115 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) |
| 116 | #define FEC_ENET_TX_FRSIZE 2048 |
| 117 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) |
| 118 | #define TX_RING_SIZE 16 /* Must be power of two */ |
| 119 | #define TX_RING_MOD_MASK 15 /* for this to work */ |
| 120 | |
| 121 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
| 122 | #error "FEC: descriptor ring size constants too large" |
| 123 | #endif |
| 124 | |
| 125 | /* Interrupt events/masks. */ |
| 126 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
| 127 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ |
| 128 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ |
| 129 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ |
| 130 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ |
| 131 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ |
| 132 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ |
| 133 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ |
| 134 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ |
| 135 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ |
| 136 | |
| 137 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
| 138 | */ |
| 139 | #define PKT_MAXBUF_SIZE 1518 |
| 140 | #define PKT_MINBUF_SIZE 64 |
| 141 | #define PKT_MAXBLR_SIZE 1520 |
| 142 | |
| 143 | |
| 144 | /* |
| 145 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
| 146 | * size bits. Other FEC hardware does not, so we need to take that into |
| 147 | * account when setting it. |
| 148 | */ |
| 149 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
| 150 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) |
| 151 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
| 152 | #else |
| 153 | #define OPT_FRAME_SIZE 0 |
| 154 | #endif |
| 155 | |
| 156 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and |
| 157 | * tx_bd_base always point to the base of the buffer descriptors. The |
| 158 | * cur_rx and cur_tx point to the currently available buffer. |
| 159 | * The dirty_tx tracks the current buffer that is being sent by the |
| 160 | * controller. The cur_tx and dirty_tx are equal under both completely |
| 161 | * empty and completely full conditions. The empty/ready indicator in |
| 162 | * the buffer descriptor determines the actual condition. |
| 163 | */ |
| 164 | struct fec_enet_private { |
| 165 | /* Hardware registers of the FEC device */ |
| 166 | void __iomem *hwp; |
| 167 | |
| 168 | struct net_device *netdev; |
| 169 | |
| 170 | struct clk *clk; |
| 171 | |
| 172 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
| 173 | unsigned char *tx_bounce[TX_RING_SIZE]; |
| 174 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; |
| 175 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
| 176 | ushort skb_cur; |
| 177 | ushort skb_dirty; |
| 178 | |
| 179 | /* CPM dual port RAM relative addresses */ |
| 180 | dma_addr_t bd_dma; |
| 181 | /* Address of Rx and Tx buffers */ |
| 182 | struct bufdesc *rx_bd_base; |
| 183 | struct bufdesc *tx_bd_base; |
| 184 | /* The next free ring entry */ |
| 185 | struct bufdesc *cur_rx, *cur_tx; |
| 186 | /* The ring entries to be free()ed */ |
| 187 | struct bufdesc *dirty_tx; |
| 188 | |
| 189 | uint tx_full; |
| 190 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
| 191 | spinlock_t hw_lock; |
| 192 | /* hold while accessing the mii_list_t() elements */ |
| 193 | spinlock_t mii_lock; |
| 194 | |
| 195 | uint phy_id; |
| 196 | uint phy_id_done; |
| 197 | uint phy_status; |
| 198 | uint phy_speed; |
| 199 | phy_info_t const *phy; |
| 200 | struct work_struct phy_task; |
| 201 | |
| 202 | uint sequence_done; |
| 203 | uint mii_phy_task_queued; |
| 204 | |
| 205 | uint phy_addr; |
| 206 | |
| 207 | int index; |
| 208 | int opened; |
| 209 | int link; |
| 210 | int old_link; |
| 211 | int full_duplex; |
| 212 | }; |
| 213 | |
| 214 | static void fec_enet_mii(struct net_device *dev); |
| 215 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
| 216 | static void fec_enet_tx(struct net_device *dev); |
| 217 | static void fec_enet_rx(struct net_device *dev); |
| 218 | static int fec_enet_close(struct net_device *dev); |
| 219 | static void fec_restart(struct net_device *dev, int duplex); |
| 220 | static void fec_stop(struct net_device *dev); |
| 221 | |
| 222 | |
| 223 | /* MII processing. We keep this as simple as possible. Requests are |
| 224 | * placed on the list (if there is room). When the request is finished |
| 225 | * by the MII, an optional function may be called. |
| 226 | */ |
| 227 | typedef struct mii_list { |
| 228 | uint mii_regval; |
| 229 | void (*mii_func)(uint val, struct net_device *dev); |
| 230 | struct mii_list *mii_next; |
| 231 | } mii_list_t; |
| 232 | |
| 233 | #define NMII 20 |
| 234 | static mii_list_t mii_cmds[NMII]; |
| 235 | static mii_list_t *mii_free; |
| 236 | static mii_list_t *mii_head; |
| 237 | static mii_list_t *mii_tail; |
| 238 | |
| 239 | static int mii_queue(struct net_device *dev, int request, |
| 240 | void (*func)(uint, struct net_device *)); |
| 241 | |
| 242 | /* Make MII read/write commands for the FEC */ |
| 243 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) |
| 244 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ |
| 245 | (VAL & 0xffff)) |
| 246 | #define mk_mii_end 0 |
| 247 | |
| 248 | /* Transmitter timeout */ |
| 249 | #define TX_TIMEOUT (2 * HZ) |
| 250 | |
| 251 | /* Register definitions for the PHY */ |
| 252 | |
| 253 | #define MII_REG_CR 0 /* Control Register */ |
| 254 | #define MII_REG_SR 1 /* Status Register */ |
| 255 | #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ |
| 256 | #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ |
| 257 | #define MII_REG_ANAR 4 /* A-N Advertisement Register */ |
| 258 | #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ |
| 259 | #define MII_REG_ANER 6 /* A-N Expansion Register */ |
| 260 | #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ |
| 261 | #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ |
| 262 | |
| 263 | /* values for phy_status */ |
| 264 | |
| 265 | #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ |
| 266 | #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ |
| 267 | #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ |
| 268 | #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ |
| 269 | #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ |
| 270 | #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ |
| 271 | #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ |
| 272 | |
| 273 | #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ |
| 274 | #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ |
| 275 | #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ |
| 276 | #define PHY_STAT_SPMASK 0xf000 /* mask for speed */ |
| 277 | #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ |
| 278 | #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ |
| 279 | #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ |
| 280 | #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ |
| 281 | |
| 282 | |
| 283 | static int |
| 284 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 285 | { |
| 286 | struct fec_enet_private *fep = netdev_priv(dev); |
| 287 | struct bufdesc *bdp; |
| 288 | void *bufaddr; |
| 289 | unsigned short status; |
| 290 | unsigned long flags; |
| 291 | |
| 292 | if (!fep->link) { |
| 293 | /* Link is down or autonegotiation is in progress. */ |
| 294 | return NETDEV_TX_BUSY; |
| 295 | } |
| 296 | |
| 297 | spin_lock_irqsave(&fep->hw_lock, flags); |
| 298 | /* Fill in a Tx ring entry */ |
| 299 | bdp = fep->cur_tx; |
| 300 | |
| 301 | status = bdp->cbd_sc; |
| 302 | |
| 303 | if (status & BD_ENET_TX_READY) { |
| 304 | /* Ooops. All transmit buffers are full. Bail out. |
| 305 | * This should not happen, since dev->tbusy should be set. |
| 306 | */ |
| 307 | printk("%s: tx queue full!.\n", dev->name); |
| 308 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
| 309 | return NETDEV_TX_BUSY; |
| 310 | } |
| 311 | |
| 312 | /* Clear all of the status flags */ |
| 313 | status &= ~BD_ENET_TX_STATS; |
| 314 | |
| 315 | /* Set buffer length and buffer pointer */ |
| 316 | bufaddr = skb->data; |
| 317 | bdp->cbd_datlen = skb->len; |
| 318 | |
| 319 | /* |
| 320 | * On some FEC implementations data must be aligned on |
| 321 | * 4-byte boundaries. Use bounce buffers to copy data |
| 322 | * and get it aligned. Ugh. |
| 323 | */ |
| 324 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
| 325 | unsigned int index; |
| 326 | index = bdp - fep->tx_bd_base; |
| 327 | memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len); |
| 328 | bufaddr = fep->tx_bounce[index]; |
| 329 | } |
| 330 | |
| 331 | /* Save skb pointer */ |
| 332 | fep->tx_skbuff[fep->skb_cur] = skb; |
| 333 | |
| 334 | dev->stats.tx_bytes += skb->len; |
| 335 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
| 336 | |
| 337 | /* Push the data cache so the CPM does not get stale memory |
| 338 | * data. |
| 339 | */ |
| 340 | bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr, |
| 341 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
| 342 | |
| 343 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
| 344 | * it's the last BD of the frame, and to put the CRC on the end. |
| 345 | */ |
| 346 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
| 347 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
| 348 | bdp->cbd_sc = status; |
| 349 | |
| 350 | dev->trans_start = jiffies; |
| 351 | |
| 352 | /* Trigger transmission start */ |
| 353 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
| 354 | |
| 355 | /* If this was the last BD in the ring, start at the beginning again. */ |
| 356 | if (status & BD_ENET_TX_WRAP) |
| 357 | bdp = fep->tx_bd_base; |
| 358 | else |
| 359 | bdp++; |
| 360 | |
| 361 | if (bdp == fep->dirty_tx) { |
| 362 | fep->tx_full = 1; |
| 363 | netif_stop_queue(dev); |
| 364 | } |
| 365 | |
| 366 | fep->cur_tx = bdp; |
| 367 | |
| 368 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
| 369 | |
| 370 | return NETDEV_TX_OK; |
| 371 | } |
| 372 | |
| 373 | static void |
| 374 | fec_timeout(struct net_device *dev) |
| 375 | { |
| 376 | struct fec_enet_private *fep = netdev_priv(dev); |
| 377 | |
| 378 | dev->stats.tx_errors++; |
| 379 | |
| 380 | fec_restart(dev, fep->full_duplex); |
| 381 | netif_wake_queue(dev); |
| 382 | } |
| 383 | |
| 384 | static irqreturn_t |
| 385 | fec_enet_interrupt(int irq, void * dev_id) |
| 386 | { |
| 387 | struct net_device *dev = dev_id; |
| 388 | struct fec_enet_private *fep = netdev_priv(dev); |
| 389 | uint int_events; |
| 390 | irqreturn_t ret = IRQ_NONE; |
| 391 | |
| 392 | do { |
| 393 | int_events = readl(fep->hwp + FEC_IEVENT); |
| 394 | writel(int_events, fep->hwp + FEC_IEVENT); |
| 395 | |
| 396 | if (int_events & FEC_ENET_RXF) { |
| 397 | ret = IRQ_HANDLED; |
| 398 | fec_enet_rx(dev); |
| 399 | } |
| 400 | |
| 401 | /* Transmit OK, or non-fatal error. Update the buffer |
| 402 | * descriptors. FEC handles all errors, we just discover |
| 403 | * them as part of the transmit process. |
| 404 | */ |
| 405 | if (int_events & FEC_ENET_TXF) { |
| 406 | ret = IRQ_HANDLED; |
| 407 | fec_enet_tx(dev); |
| 408 | } |
| 409 | |
| 410 | if (int_events & FEC_ENET_MII) { |
| 411 | ret = IRQ_HANDLED; |
| 412 | fec_enet_mii(dev); |
| 413 | } |
| 414 | |
| 415 | } while (int_events); |
| 416 | |
| 417 | return ret; |
| 418 | } |
| 419 | |
| 420 | |
| 421 | static void |
| 422 | fec_enet_tx(struct net_device *dev) |
| 423 | { |
| 424 | struct fec_enet_private *fep; |
| 425 | struct bufdesc *bdp; |
| 426 | unsigned short status; |
| 427 | struct sk_buff *skb; |
| 428 | |
| 429 | fep = netdev_priv(dev); |
| 430 | spin_lock(&fep->hw_lock); |
| 431 | bdp = fep->dirty_tx; |
| 432 | |
| 433 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
| 434 | if (bdp == fep->cur_tx && fep->tx_full == 0) |
| 435 | break; |
| 436 | |
| 437 | dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
| 438 | bdp->cbd_bufaddr = 0; |
| 439 | |
| 440 | skb = fep->tx_skbuff[fep->skb_dirty]; |
| 441 | /* Check for errors. */ |
| 442 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
| 443 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
| 444 | BD_ENET_TX_CSL)) { |
| 445 | dev->stats.tx_errors++; |
| 446 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
| 447 | dev->stats.tx_heartbeat_errors++; |
| 448 | if (status & BD_ENET_TX_LC) /* Late collision */ |
| 449 | dev->stats.tx_window_errors++; |
| 450 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
| 451 | dev->stats.tx_aborted_errors++; |
| 452 | if (status & BD_ENET_TX_UN) /* Underrun */ |
| 453 | dev->stats.tx_fifo_errors++; |
| 454 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
| 455 | dev->stats.tx_carrier_errors++; |
| 456 | } else { |
| 457 | dev->stats.tx_packets++; |
| 458 | } |
| 459 | |
| 460 | if (status & BD_ENET_TX_READY) |
| 461 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
| 462 | |
| 463 | /* Deferred means some collisions occurred during transmit, |
| 464 | * but we eventually sent the packet OK. |
| 465 | */ |
| 466 | if (status & BD_ENET_TX_DEF) |
| 467 | dev->stats.collisions++; |
| 468 | |
| 469 | /* Free the sk buffer associated with this last transmit */ |
| 470 | dev_kfree_skb_any(skb); |
| 471 | fep->tx_skbuff[fep->skb_dirty] = NULL; |
| 472 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; |
| 473 | |
| 474 | /* Update pointer to next buffer descriptor to be transmitted */ |
| 475 | if (status & BD_ENET_TX_WRAP) |
| 476 | bdp = fep->tx_bd_base; |
| 477 | else |
| 478 | bdp++; |
| 479 | |
| 480 | /* Since we have freed up a buffer, the ring is no longer full |
| 481 | */ |
| 482 | if (fep->tx_full) { |
| 483 | fep->tx_full = 0; |
| 484 | if (netif_queue_stopped(dev)) |
| 485 | netif_wake_queue(dev); |
| 486 | } |
| 487 | } |
| 488 | fep->dirty_tx = bdp; |
| 489 | spin_unlock(&fep->hw_lock); |
| 490 | } |
| 491 | |
| 492 | |
| 493 | /* During a receive, the cur_rx points to the current incoming buffer. |
| 494 | * When we update through the ring, if the next incoming buffer has |
| 495 | * not been given to the system, we just set the empty indicator, |
| 496 | * effectively tossing the packet. |
| 497 | */ |
| 498 | static void |
| 499 | fec_enet_rx(struct net_device *dev) |
| 500 | { |
| 501 | struct fec_enet_private *fep = netdev_priv(dev); |
| 502 | struct bufdesc *bdp; |
| 503 | unsigned short status; |
| 504 | struct sk_buff *skb; |
| 505 | ushort pkt_len; |
| 506 | __u8 *data; |
| 507 | |
| 508 | #ifdef CONFIG_M532x |
| 509 | flush_cache_all(); |
| 510 | #endif |
| 511 | |
| 512 | spin_lock(&fep->hw_lock); |
| 513 | |
| 514 | /* First, grab all of the stats for the incoming packet. |
| 515 | * These get messed up if we get called due to a busy condition. |
| 516 | */ |
| 517 | bdp = fep->cur_rx; |
| 518 | |
| 519 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
| 520 | |
| 521 | /* Since we have allocated space to hold a complete frame, |
| 522 | * the last indicator should be set. |
| 523 | */ |
| 524 | if ((status & BD_ENET_RX_LAST) == 0) |
| 525 | printk("FEC ENET: rcv is not +last\n"); |
| 526 | |
| 527 | if (!fep->opened) |
| 528 | goto rx_processing_done; |
| 529 | |
| 530 | /* Check for errors. */ |
| 531 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | |
| 532 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
| 533 | dev->stats.rx_errors++; |
| 534 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
| 535 | /* Frame too long or too short. */ |
| 536 | dev->stats.rx_length_errors++; |
| 537 | } |
| 538 | if (status & BD_ENET_RX_NO) /* Frame alignment */ |
| 539 | dev->stats.rx_frame_errors++; |
| 540 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
| 541 | dev->stats.rx_crc_errors++; |
| 542 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
| 543 | dev->stats.rx_fifo_errors++; |
| 544 | } |
| 545 | |
| 546 | /* Report late collisions as a frame error. |
| 547 | * On this error, the BD is closed, but we don't know what we |
| 548 | * have in the buffer. So, just drop this frame on the floor. |
| 549 | */ |
| 550 | if (status & BD_ENET_RX_CL) { |
| 551 | dev->stats.rx_errors++; |
| 552 | dev->stats.rx_frame_errors++; |
| 553 | goto rx_processing_done; |
| 554 | } |
| 555 | |
| 556 | /* Process the incoming frame. */ |
| 557 | dev->stats.rx_packets++; |
| 558 | pkt_len = bdp->cbd_datlen; |
| 559 | dev->stats.rx_bytes += pkt_len; |
| 560 | data = (__u8*)__va(bdp->cbd_bufaddr); |
| 561 | |
| 562 | dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, |
| 563 | DMA_FROM_DEVICE); |
| 564 | |
| 565 | /* This does 16 byte alignment, exactly what we need. |
| 566 | * The packet length includes FCS, but we don't want to |
| 567 | * include that when passing upstream as it messes up |
| 568 | * bridging applications. |
| 569 | */ |
| 570 | skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN); |
| 571 | |
| 572 | if (unlikely(!skb)) { |
| 573 | printk("%s: Memory squeeze, dropping packet.\n", |
| 574 | dev->name); |
| 575 | dev->stats.rx_dropped++; |
| 576 | } else { |
| 577 | skb_reserve(skb, NET_IP_ALIGN); |
| 578 | skb_put(skb, pkt_len - 4); /* Make room */ |
| 579 | skb_copy_to_linear_data(skb, data, pkt_len - 4); |
| 580 | skb->protocol = eth_type_trans(skb, dev); |
| 581 | netif_rx(skb); |
| 582 | } |
| 583 | |
| 584 | bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, |
| 585 | DMA_FROM_DEVICE); |
| 586 | rx_processing_done: |
| 587 | /* Clear the status flags for this buffer */ |
| 588 | status &= ~BD_ENET_RX_STATS; |
| 589 | |
| 590 | /* Mark the buffer empty */ |
| 591 | status |= BD_ENET_RX_EMPTY; |
| 592 | bdp->cbd_sc = status; |
| 593 | |
| 594 | /* Update BD pointer to next entry */ |
| 595 | if (status & BD_ENET_RX_WRAP) |
| 596 | bdp = fep->rx_bd_base; |
| 597 | else |
| 598 | bdp++; |
| 599 | /* Doing this here will keep the FEC running while we process |
| 600 | * incoming frames. On a heavily loaded network, we should be |
| 601 | * able to keep up at the expense of system resources. |
| 602 | */ |
| 603 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
| 604 | } |
| 605 | fep->cur_rx = bdp; |
| 606 | |
| 607 | spin_unlock(&fep->hw_lock); |
| 608 | } |
| 609 | |
| 610 | /* called from interrupt context */ |
| 611 | static void |
| 612 | fec_enet_mii(struct net_device *dev) |
| 613 | { |
| 614 | struct fec_enet_private *fep; |
| 615 | mii_list_t *mip; |
| 616 | |
| 617 | fep = netdev_priv(dev); |
| 618 | spin_lock(&fep->mii_lock); |
| 619 | |
| 620 | if ((mip = mii_head) == NULL) { |
| 621 | printk("MII and no head!\n"); |
| 622 | goto unlock; |
| 623 | } |
| 624 | |
| 625 | if (mip->mii_func != NULL) |
| 626 | (*(mip->mii_func))(readl(fep->hwp + FEC_MII_DATA), dev); |
| 627 | |
| 628 | mii_head = mip->mii_next; |
| 629 | mip->mii_next = mii_free; |
| 630 | mii_free = mip; |
| 631 | |
| 632 | if ((mip = mii_head) != NULL) |
| 633 | writel(mip->mii_regval, fep->hwp + FEC_MII_DATA); |
| 634 | |
| 635 | unlock: |
| 636 | spin_unlock(&fep->mii_lock); |
| 637 | } |
| 638 | |
| 639 | static int |
| 640 | mii_queue_unlocked(struct net_device *dev, int regval, |
| 641 | void (*func)(uint, struct net_device *)) |
| 642 | { |
| 643 | struct fec_enet_private *fep; |
| 644 | mii_list_t *mip; |
| 645 | int retval; |
| 646 | |
| 647 | /* Add PHY address to register command */ |
| 648 | fep = netdev_priv(dev); |
| 649 | |
| 650 | regval |= fep->phy_addr << 23; |
| 651 | retval = 0; |
| 652 | |
| 653 | if ((mip = mii_free) != NULL) { |
| 654 | mii_free = mip->mii_next; |
| 655 | mip->mii_regval = regval; |
| 656 | mip->mii_func = func; |
| 657 | mip->mii_next = NULL; |
| 658 | if (mii_head) { |
| 659 | mii_tail->mii_next = mip; |
| 660 | mii_tail = mip; |
| 661 | } else { |
| 662 | mii_head = mii_tail = mip; |
| 663 | writel(regval, fep->hwp + FEC_MII_DATA); |
| 664 | } |
| 665 | } else { |
| 666 | retval = 1; |
| 667 | } |
| 668 | |
| 669 | return retval; |
| 670 | } |
| 671 | |
| 672 | static int |
| 673 | mii_queue(struct net_device *dev, int regval, |
| 674 | void (*func)(uint, struct net_device *)) |
| 675 | { |
| 676 | struct fec_enet_private *fep; |
| 677 | unsigned long flags; |
| 678 | int retval; |
| 679 | fep = netdev_priv(dev); |
| 680 | spin_lock_irqsave(&fep->mii_lock, flags); |
| 681 | retval = mii_queue_unlocked(dev, regval, func); |
| 682 | spin_unlock_irqrestore(&fep->mii_lock, flags); |
| 683 | return retval; |
| 684 | } |
| 685 | |
| 686 | static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) |
| 687 | { |
| 688 | if(!c) |
| 689 | return; |
| 690 | |
| 691 | for (; c->mii_data != mk_mii_end; c++) |
| 692 | mii_queue(dev, c->mii_data, c->funct); |
| 693 | } |
| 694 | |
| 695 | static void mii_parse_sr(uint mii_reg, struct net_device *dev) |
| 696 | { |
| 697 | struct fec_enet_private *fep = netdev_priv(dev); |
| 698 | volatile uint *s = &(fep->phy_status); |
| 699 | uint status; |
| 700 | |
| 701 | status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); |
| 702 | |
| 703 | if (mii_reg & 0x0004) |
| 704 | status |= PHY_STAT_LINK; |
| 705 | if (mii_reg & 0x0010) |
| 706 | status |= PHY_STAT_FAULT; |
| 707 | if (mii_reg & 0x0020) |
| 708 | status |= PHY_STAT_ANC; |
| 709 | *s = status; |
| 710 | } |
| 711 | |
| 712 | static void mii_parse_cr(uint mii_reg, struct net_device *dev) |
| 713 | { |
| 714 | struct fec_enet_private *fep = netdev_priv(dev); |
| 715 | volatile uint *s = &(fep->phy_status); |
| 716 | uint status; |
| 717 | |
| 718 | status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP); |
| 719 | |
| 720 | if (mii_reg & 0x1000) |
| 721 | status |= PHY_CONF_ANE; |
| 722 | if (mii_reg & 0x4000) |
| 723 | status |= PHY_CONF_LOOP; |
| 724 | *s = status; |
| 725 | } |
| 726 | |
| 727 | static void mii_parse_anar(uint mii_reg, struct net_device *dev) |
| 728 | { |
| 729 | struct fec_enet_private *fep = netdev_priv(dev); |
| 730 | volatile uint *s = &(fep->phy_status); |
| 731 | uint status; |
| 732 | |
| 733 | status = *s & ~(PHY_CONF_SPMASK); |
| 734 | |
| 735 | if (mii_reg & 0x0020) |
| 736 | status |= PHY_CONF_10HDX; |
| 737 | if (mii_reg & 0x0040) |
| 738 | status |= PHY_CONF_10FDX; |
| 739 | if (mii_reg & 0x0080) |
| 740 | status |= PHY_CONF_100HDX; |
| 741 | if (mii_reg & 0x00100) |
| 742 | status |= PHY_CONF_100FDX; |
| 743 | *s = status; |
| 744 | } |
| 745 | |
| 746 | /* ------------------------------------------------------------------------- */ |
| 747 | /* The Level one LXT970 is used by many boards */ |
| 748 | |
| 749 | #define MII_LXT970_MIRROR 16 /* Mirror register */ |
| 750 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ |
| 751 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ |
| 752 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ |
| 753 | #define MII_LXT970_CSR 20 /* Chip Status Register */ |
| 754 | |
| 755 | static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) |
| 756 | { |
| 757 | struct fec_enet_private *fep = netdev_priv(dev); |
| 758 | volatile uint *s = &(fep->phy_status); |
| 759 | uint status; |
| 760 | |
| 761 | status = *s & ~(PHY_STAT_SPMASK); |
| 762 | if (mii_reg & 0x0800) { |
| 763 | if (mii_reg & 0x1000) |
| 764 | status |= PHY_STAT_100FDX; |
| 765 | else |
| 766 | status |= PHY_STAT_100HDX; |
| 767 | } else { |
| 768 | if (mii_reg & 0x1000) |
| 769 | status |= PHY_STAT_10FDX; |
| 770 | else |
| 771 | status |= PHY_STAT_10HDX; |
| 772 | } |
| 773 | *s = status; |
| 774 | } |
| 775 | |
| 776 | static phy_cmd_t const phy_cmd_lxt970_config[] = { |
| 777 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 778 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 779 | { mk_mii_end, } |
| 780 | }; |
| 781 | static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */ |
| 782 | { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, |
| 783 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 784 | { mk_mii_end, } |
| 785 | }; |
| 786 | static phy_cmd_t const phy_cmd_lxt970_ack_int[] = { |
| 787 | /* read SR and ISR to acknowledge */ |
| 788 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 789 | { mk_mii_read(MII_LXT970_ISR), NULL }, |
| 790 | |
| 791 | /* find out the current status */ |
| 792 | { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, |
| 793 | { mk_mii_end, } |
| 794 | }; |
| 795 | static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */ |
| 796 | { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, |
| 797 | { mk_mii_end, } |
| 798 | }; |
| 799 | static phy_info_t const phy_info_lxt970 = { |
| 800 | .id = 0x07810000, |
| 801 | .name = "LXT970", |
| 802 | .config = phy_cmd_lxt970_config, |
| 803 | .startup = phy_cmd_lxt970_startup, |
| 804 | .ack_int = phy_cmd_lxt970_ack_int, |
| 805 | .shutdown = phy_cmd_lxt970_shutdown |
| 806 | }; |
| 807 | |
| 808 | /* ------------------------------------------------------------------------- */ |
| 809 | /* The Level one LXT971 is used on some of my custom boards */ |
| 810 | |
| 811 | /* register definitions for the 971 */ |
| 812 | |
| 813 | #define MII_LXT971_PCR 16 /* Port Control Register */ |
| 814 | #define MII_LXT971_SR2 17 /* Status Register 2 */ |
| 815 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ |
| 816 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ |
| 817 | #define MII_LXT971_LCR 20 /* LED Control Register */ |
| 818 | #define MII_LXT971_TCR 30 /* Transmit Control Register */ |
| 819 | |
| 820 | /* |
| 821 | * I had some nice ideas of running the MDIO faster... |
| 822 | * The 971 should support 8MHz and I tried it, but things acted really |
| 823 | * weird, so 2.5 MHz ought to be enough for anyone... |
| 824 | */ |
| 825 | |
| 826 | static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) |
| 827 | { |
| 828 | struct fec_enet_private *fep = netdev_priv(dev); |
| 829 | volatile uint *s = &(fep->phy_status); |
| 830 | uint status; |
| 831 | |
| 832 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
| 833 | |
| 834 | if (mii_reg & 0x0400) { |
| 835 | fep->link = 1; |
| 836 | status |= PHY_STAT_LINK; |
| 837 | } else { |
| 838 | fep->link = 0; |
| 839 | } |
| 840 | if (mii_reg & 0x0080) |
| 841 | status |= PHY_STAT_ANC; |
| 842 | if (mii_reg & 0x4000) { |
| 843 | if (mii_reg & 0x0200) |
| 844 | status |= PHY_STAT_100FDX; |
| 845 | else |
| 846 | status |= PHY_STAT_100HDX; |
| 847 | } else { |
| 848 | if (mii_reg & 0x0200) |
| 849 | status |= PHY_STAT_10FDX; |
| 850 | else |
| 851 | status |= PHY_STAT_10HDX; |
| 852 | } |
| 853 | if (mii_reg & 0x0008) |
| 854 | status |= PHY_STAT_FAULT; |
| 855 | |
| 856 | *s = status; |
| 857 | } |
| 858 | |
| 859 | static phy_cmd_t const phy_cmd_lxt971_config[] = { |
| 860 | /* limit to 10MBit because my prototype board |
| 861 | * doesn't work with 100. */ |
| 862 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 863 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 864 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, |
| 865 | { mk_mii_end, } |
| 866 | }; |
| 867 | static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */ |
| 868 | { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, |
| 869 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 870 | { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */ |
| 871 | /* Somehow does the 971 tell me that the link is down |
| 872 | * the first read after power-up. |
| 873 | * read here to get a valid value in ack_int */ |
| 874 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 875 | { mk_mii_end, } |
| 876 | }; |
| 877 | static phy_cmd_t const phy_cmd_lxt971_ack_int[] = { |
| 878 | /* acknowledge the int before reading status ! */ |
| 879 | { mk_mii_read(MII_LXT971_ISR), NULL }, |
| 880 | /* find out the current status */ |
| 881 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 882 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, |
| 883 | { mk_mii_end, } |
| 884 | }; |
| 885 | static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */ |
| 886 | { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, |
| 887 | { mk_mii_end, } |
| 888 | }; |
| 889 | static phy_info_t const phy_info_lxt971 = { |
| 890 | .id = 0x0001378e, |
| 891 | .name = "LXT971", |
| 892 | .config = phy_cmd_lxt971_config, |
| 893 | .startup = phy_cmd_lxt971_startup, |
| 894 | .ack_int = phy_cmd_lxt971_ack_int, |
| 895 | .shutdown = phy_cmd_lxt971_shutdown |
| 896 | }; |
| 897 | |
| 898 | /* ------------------------------------------------------------------------- */ |
| 899 | /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ |
| 900 | |
| 901 | /* register definitions */ |
| 902 | |
| 903 | #define MII_QS6612_MCR 17 /* Mode Control Register */ |
| 904 | #define MII_QS6612_FTR 27 /* Factory Test Register */ |
| 905 | #define MII_QS6612_MCO 28 /* Misc. Control Register */ |
| 906 | #define MII_QS6612_ISR 29 /* Interrupt Source Register */ |
| 907 | #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ |
| 908 | #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ |
| 909 | |
| 910 | static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) |
| 911 | { |
| 912 | struct fec_enet_private *fep = netdev_priv(dev); |
| 913 | volatile uint *s = &(fep->phy_status); |
| 914 | uint status; |
| 915 | |
| 916 | status = *s & ~(PHY_STAT_SPMASK); |
| 917 | |
| 918 | switch((mii_reg >> 2) & 7) { |
| 919 | case 1: status |= PHY_STAT_10HDX; break; |
| 920 | case 2: status |= PHY_STAT_100HDX; break; |
| 921 | case 5: status |= PHY_STAT_10FDX; break; |
| 922 | case 6: status |= PHY_STAT_100FDX; break; |
| 923 | } |
| 924 | |
| 925 | *s = status; |
| 926 | } |
| 927 | |
| 928 | static phy_cmd_t const phy_cmd_qs6612_config[] = { |
| 929 | /* The PHY powers up isolated on the RPX, |
| 930 | * so send a command to allow operation. |
| 931 | */ |
| 932 | { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, |
| 933 | |
| 934 | /* parse cr and anar to get some info */ |
| 935 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 936 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 937 | { mk_mii_end, } |
| 938 | }; |
| 939 | static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */ |
| 940 | { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, |
| 941 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 942 | { mk_mii_end, } |
| 943 | }; |
| 944 | static phy_cmd_t const phy_cmd_qs6612_ack_int[] = { |
| 945 | /* we need to read ISR, SR and ANER to acknowledge */ |
| 946 | { mk_mii_read(MII_QS6612_ISR), NULL }, |
| 947 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 948 | { mk_mii_read(MII_REG_ANER), NULL }, |
| 949 | |
| 950 | /* read pcr to get info */ |
| 951 | { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, |
| 952 | { mk_mii_end, } |
| 953 | }; |
| 954 | static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */ |
| 955 | { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, |
| 956 | { mk_mii_end, } |
| 957 | }; |
| 958 | static phy_info_t const phy_info_qs6612 = { |
| 959 | .id = 0x00181440, |
| 960 | .name = "QS6612", |
| 961 | .config = phy_cmd_qs6612_config, |
| 962 | .startup = phy_cmd_qs6612_startup, |
| 963 | .ack_int = phy_cmd_qs6612_ack_int, |
| 964 | .shutdown = phy_cmd_qs6612_shutdown |
| 965 | }; |
| 966 | |
| 967 | /* ------------------------------------------------------------------------- */ |
| 968 | /* AMD AM79C874 phy */ |
| 969 | |
| 970 | /* register definitions for the 874 */ |
| 971 | |
| 972 | #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */ |
| 973 | #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */ |
| 974 | #define MII_AM79C874_DR 18 /* Diagnostic Register */ |
| 975 | #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */ |
| 976 | #define MII_AM79C874_MCR 21 /* ModeControl Register */ |
| 977 | #define MII_AM79C874_DC 23 /* Disconnect Counter */ |
| 978 | #define MII_AM79C874_REC 24 /* Recieve Error Counter */ |
| 979 | |
| 980 | static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev) |
| 981 | { |
| 982 | struct fec_enet_private *fep = netdev_priv(dev); |
| 983 | volatile uint *s = &(fep->phy_status); |
| 984 | uint status; |
| 985 | |
| 986 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC); |
| 987 | |
| 988 | if (mii_reg & 0x0080) |
| 989 | status |= PHY_STAT_ANC; |
| 990 | if (mii_reg & 0x0400) |
| 991 | status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX); |
| 992 | else |
| 993 | status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX); |
| 994 | |
| 995 | *s = status; |
| 996 | } |
| 997 | |
| 998 | static phy_cmd_t const phy_cmd_am79c874_config[] = { |
| 999 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 1000 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 1001 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, |
| 1002 | { mk_mii_end, } |
| 1003 | }; |
| 1004 | static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */ |
| 1005 | { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, |
| 1006 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 1007 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1008 | { mk_mii_end, } |
| 1009 | }; |
| 1010 | static phy_cmd_t const phy_cmd_am79c874_ack_int[] = { |
| 1011 | /* find out the current status */ |
| 1012 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1013 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, |
| 1014 | /* we only need to read ISR to acknowledge */ |
| 1015 | { mk_mii_read(MII_AM79C874_ICSR), NULL }, |
| 1016 | { mk_mii_end, } |
| 1017 | }; |
| 1018 | static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */ |
| 1019 | { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, |
| 1020 | { mk_mii_end, } |
| 1021 | }; |
| 1022 | static phy_info_t const phy_info_am79c874 = { |
| 1023 | .id = 0x00022561, |
| 1024 | .name = "AM79C874", |
| 1025 | .config = phy_cmd_am79c874_config, |
| 1026 | .startup = phy_cmd_am79c874_startup, |
| 1027 | .ack_int = phy_cmd_am79c874_ack_int, |
| 1028 | .shutdown = phy_cmd_am79c874_shutdown |
| 1029 | }; |
| 1030 | |
| 1031 | |
| 1032 | /* ------------------------------------------------------------------------- */ |
| 1033 | /* Kendin KS8721BL phy */ |
| 1034 | |
| 1035 | /* register definitions for the 8721 */ |
| 1036 | |
| 1037 | #define MII_KS8721BL_RXERCR 21 |
| 1038 | #define MII_KS8721BL_ICSR 27 |
| 1039 | #define MII_KS8721BL_PHYCR 31 |
| 1040 | |
| 1041 | static phy_cmd_t const phy_cmd_ks8721bl_config[] = { |
| 1042 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 1043 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 1044 | { mk_mii_end, } |
| 1045 | }; |
| 1046 | static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */ |
| 1047 | { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL }, |
| 1048 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 1049 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1050 | { mk_mii_end, } |
| 1051 | }; |
| 1052 | static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = { |
| 1053 | /* find out the current status */ |
| 1054 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1055 | /* we only need to read ISR to acknowledge */ |
| 1056 | { mk_mii_read(MII_KS8721BL_ICSR), NULL }, |
| 1057 | { mk_mii_end, } |
| 1058 | }; |
| 1059 | static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */ |
| 1060 | { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL }, |
| 1061 | { mk_mii_end, } |
| 1062 | }; |
| 1063 | static phy_info_t const phy_info_ks8721bl = { |
| 1064 | .id = 0x00022161, |
| 1065 | .name = "KS8721BL", |
| 1066 | .config = phy_cmd_ks8721bl_config, |
| 1067 | .startup = phy_cmd_ks8721bl_startup, |
| 1068 | .ack_int = phy_cmd_ks8721bl_ack_int, |
| 1069 | .shutdown = phy_cmd_ks8721bl_shutdown |
| 1070 | }; |
| 1071 | |
| 1072 | /* ------------------------------------------------------------------------- */ |
| 1073 | /* register definitions for the DP83848 */ |
| 1074 | |
| 1075 | #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */ |
| 1076 | |
| 1077 | static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev) |
| 1078 | { |
| 1079 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1080 | volatile uint *s = &(fep->phy_status); |
| 1081 | |
| 1082 | *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
| 1083 | |
| 1084 | /* Link up */ |
| 1085 | if (mii_reg & 0x0001) { |
| 1086 | fep->link = 1; |
| 1087 | *s |= PHY_STAT_LINK; |
| 1088 | } else |
| 1089 | fep->link = 0; |
| 1090 | /* Status of link */ |
| 1091 | if (mii_reg & 0x0010) /* Autonegotioation complete */ |
| 1092 | *s |= PHY_STAT_ANC; |
| 1093 | if (mii_reg & 0x0002) { /* 10MBps? */ |
| 1094 | if (mii_reg & 0x0004) /* Full Duplex? */ |
| 1095 | *s |= PHY_STAT_10FDX; |
| 1096 | else |
| 1097 | *s |= PHY_STAT_10HDX; |
| 1098 | } else { /* 100 Mbps? */ |
| 1099 | if (mii_reg & 0x0004) /* Full Duplex? */ |
| 1100 | *s |= PHY_STAT_100FDX; |
| 1101 | else |
| 1102 | *s |= PHY_STAT_100HDX; |
| 1103 | } |
| 1104 | if (mii_reg & 0x0008) |
| 1105 | *s |= PHY_STAT_FAULT; |
| 1106 | } |
| 1107 | |
| 1108 | static phy_info_t phy_info_dp83848= { |
| 1109 | 0x020005c9, |
| 1110 | "DP83848", |
| 1111 | |
| 1112 | (const phy_cmd_t []) { /* config */ |
| 1113 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 1114 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 1115 | { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 }, |
| 1116 | { mk_mii_end, } |
| 1117 | }, |
| 1118 | (const phy_cmd_t []) { /* startup - enable interrupts */ |
| 1119 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 1120 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1121 | { mk_mii_end, } |
| 1122 | }, |
| 1123 | (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */ |
| 1124 | { mk_mii_end, } |
| 1125 | }, |
| 1126 | (const phy_cmd_t []) { /* shutdown */ |
| 1127 | { mk_mii_end, } |
| 1128 | }, |
| 1129 | }; |
| 1130 | |
| 1131 | /* ------------------------------------------------------------------------- */ |
| 1132 | |
| 1133 | static phy_info_t const * const phy_info[] = { |
| 1134 | &phy_info_lxt970, |
| 1135 | &phy_info_lxt971, |
| 1136 | &phy_info_qs6612, |
| 1137 | &phy_info_am79c874, |
| 1138 | &phy_info_ks8721bl, |
| 1139 | &phy_info_dp83848, |
| 1140 | NULL |
| 1141 | }; |
| 1142 | |
| 1143 | /* ------------------------------------------------------------------------- */ |
| 1144 | #ifdef HAVE_mii_link_interrupt |
| 1145 | static irqreturn_t |
| 1146 | mii_link_interrupt(int irq, void * dev_id); |
| 1147 | |
| 1148 | /* |
| 1149 | * This is specific to the MII interrupt setup of the M5272EVB. |
| 1150 | */ |
| 1151 | static void __inline__ fec_request_mii_intr(struct net_device *dev) |
| 1152 | { |
| 1153 | if (request_irq(66, mii_link_interrupt, IRQF_DISABLED, "fec(MII)", dev) != 0) |
| 1154 | printk("FEC: Could not allocate fec(MII) IRQ(66)!\n"); |
| 1155 | } |
| 1156 | |
| 1157 | static void __inline__ fec_disable_phy_intr(void) |
| 1158 | { |
| 1159 | volatile unsigned long *icrp; |
| 1160 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); |
| 1161 | *icrp = 0x08000000; |
| 1162 | } |
| 1163 | |
| 1164 | static void __inline__ fec_phy_ack_intr(void) |
| 1165 | { |
| 1166 | volatile unsigned long *icrp; |
| 1167 | /* Acknowledge the interrupt */ |
| 1168 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); |
| 1169 | *icrp = 0x0d000000; |
| 1170 | } |
| 1171 | #endif |
| 1172 | |
| 1173 | #ifdef CONFIG_M5272 |
| 1174 | static void __inline__ fec_get_mac(struct net_device *dev) |
| 1175 | { |
| 1176 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1177 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
| 1178 | |
| 1179 | if (FEC_FLASHMAC) { |
| 1180 | /* |
| 1181 | * Get MAC address from FLASH. |
| 1182 | * If it is all 1's or 0's, use the default. |
| 1183 | */ |
| 1184 | iap = (unsigned char *)FEC_FLASHMAC; |
| 1185 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
| 1186 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) |
| 1187 | iap = fec_mac_default; |
| 1188 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && |
| 1189 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) |
| 1190 | iap = fec_mac_default; |
| 1191 | } else { |
| 1192 | *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW); |
| 1193 | *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16); |
| 1194 | iap = &tmpaddr[0]; |
| 1195 | } |
| 1196 | |
| 1197 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
| 1198 | |
| 1199 | /* Adjust MAC if using default MAC address */ |
| 1200 | if (iap == fec_mac_default) |
| 1201 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; |
| 1202 | } |
| 1203 | #endif |
| 1204 | |
| 1205 | /* ------------------------------------------------------------------------- */ |
| 1206 | |
| 1207 | static void mii_display_status(struct net_device *dev) |
| 1208 | { |
| 1209 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1210 | volatile uint *s = &(fep->phy_status); |
| 1211 | |
| 1212 | if (!fep->link && !fep->old_link) { |
| 1213 | /* Link is still down - don't print anything */ |
| 1214 | return; |
| 1215 | } |
| 1216 | |
| 1217 | printk("%s: status: ", dev->name); |
| 1218 | |
| 1219 | if (!fep->link) { |
| 1220 | printk("link down"); |
| 1221 | } else { |
| 1222 | printk("link up"); |
| 1223 | |
| 1224 | switch(*s & PHY_STAT_SPMASK) { |
| 1225 | case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break; |
| 1226 | case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break; |
| 1227 | case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break; |
| 1228 | case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break; |
| 1229 | default: |
| 1230 | printk(", Unknown speed/duplex"); |
| 1231 | } |
| 1232 | |
| 1233 | if (*s & PHY_STAT_ANC) |
| 1234 | printk(", auto-negotiation complete"); |
| 1235 | } |
| 1236 | |
| 1237 | if (*s & PHY_STAT_FAULT) |
| 1238 | printk(", remote fault"); |
| 1239 | |
| 1240 | printk(".\n"); |
| 1241 | } |
| 1242 | |
| 1243 | static void mii_display_config(struct work_struct *work) |
| 1244 | { |
| 1245 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
| 1246 | struct net_device *dev = fep->netdev; |
| 1247 | uint status = fep->phy_status; |
| 1248 | |
| 1249 | /* |
| 1250 | ** When we get here, phy_task is already removed from |
| 1251 | ** the workqueue. It is thus safe to allow to reuse it. |
| 1252 | */ |
| 1253 | fep->mii_phy_task_queued = 0; |
| 1254 | printk("%s: config: auto-negotiation ", dev->name); |
| 1255 | |
| 1256 | if (status & PHY_CONF_ANE) |
| 1257 | printk("on"); |
| 1258 | else |
| 1259 | printk("off"); |
| 1260 | |
| 1261 | if (status & PHY_CONF_100FDX) |
| 1262 | printk(", 100FDX"); |
| 1263 | if (status & PHY_CONF_100HDX) |
| 1264 | printk(", 100HDX"); |
| 1265 | if (status & PHY_CONF_10FDX) |
| 1266 | printk(", 10FDX"); |
| 1267 | if (status & PHY_CONF_10HDX) |
| 1268 | printk(", 10HDX"); |
| 1269 | if (!(status & PHY_CONF_SPMASK)) |
| 1270 | printk(", No speed/duplex selected?"); |
| 1271 | |
| 1272 | if (status & PHY_CONF_LOOP) |
| 1273 | printk(", loopback enabled"); |
| 1274 | |
| 1275 | printk(".\n"); |
| 1276 | |
| 1277 | fep->sequence_done = 1; |
| 1278 | } |
| 1279 | |
| 1280 | static void mii_relink(struct work_struct *work) |
| 1281 | { |
| 1282 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
| 1283 | struct net_device *dev = fep->netdev; |
| 1284 | int duplex; |
| 1285 | |
| 1286 | /* |
| 1287 | ** When we get here, phy_task is already removed from |
| 1288 | ** the workqueue. It is thus safe to allow to reuse it. |
| 1289 | */ |
| 1290 | fep->mii_phy_task_queued = 0; |
| 1291 | fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; |
| 1292 | mii_display_status(dev); |
| 1293 | fep->old_link = fep->link; |
| 1294 | |
| 1295 | if (fep->link) { |
| 1296 | duplex = 0; |
| 1297 | if (fep->phy_status |
| 1298 | & (PHY_STAT_100FDX | PHY_STAT_10FDX)) |
| 1299 | duplex = 1; |
| 1300 | fec_restart(dev, duplex); |
| 1301 | } else |
| 1302 | fec_stop(dev); |
| 1303 | } |
| 1304 | |
| 1305 | /* mii_queue_relink is called in interrupt context from mii_link_interrupt */ |
| 1306 | static void mii_queue_relink(uint mii_reg, struct net_device *dev) |
| 1307 | { |
| 1308 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1309 | |
| 1310 | /* |
| 1311 | * We cannot queue phy_task twice in the workqueue. It |
| 1312 | * would cause an endless loop in the workqueue. |
| 1313 | * Fortunately, if the last mii_relink entry has not yet been |
| 1314 | * executed now, it will do the job for the current interrupt, |
| 1315 | * which is just what we want. |
| 1316 | */ |
| 1317 | if (fep->mii_phy_task_queued) |
| 1318 | return; |
| 1319 | |
| 1320 | fep->mii_phy_task_queued = 1; |
| 1321 | INIT_WORK(&fep->phy_task, mii_relink); |
| 1322 | schedule_work(&fep->phy_task); |
| 1323 | } |
| 1324 | |
| 1325 | /* mii_queue_config is called in interrupt context from fec_enet_mii */ |
| 1326 | static void mii_queue_config(uint mii_reg, struct net_device *dev) |
| 1327 | { |
| 1328 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1329 | |
| 1330 | if (fep->mii_phy_task_queued) |
| 1331 | return; |
| 1332 | |
| 1333 | fep->mii_phy_task_queued = 1; |
| 1334 | INIT_WORK(&fep->phy_task, mii_display_config); |
| 1335 | schedule_work(&fep->phy_task); |
| 1336 | } |
| 1337 | |
| 1338 | phy_cmd_t const phy_cmd_relink[] = { |
| 1339 | { mk_mii_read(MII_REG_CR), mii_queue_relink }, |
| 1340 | { mk_mii_end, } |
| 1341 | }; |
| 1342 | phy_cmd_t const phy_cmd_config[] = { |
| 1343 | { mk_mii_read(MII_REG_CR), mii_queue_config }, |
| 1344 | { mk_mii_end, } |
| 1345 | }; |
| 1346 | |
| 1347 | /* Read remainder of PHY ID. */ |
| 1348 | static void |
| 1349 | mii_discover_phy3(uint mii_reg, struct net_device *dev) |
| 1350 | { |
| 1351 | struct fec_enet_private *fep; |
| 1352 | int i; |
| 1353 | |
| 1354 | fep = netdev_priv(dev); |
| 1355 | fep->phy_id |= (mii_reg & 0xffff); |
| 1356 | printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id); |
| 1357 | |
| 1358 | for(i = 0; phy_info[i]; i++) { |
| 1359 | if(phy_info[i]->id == (fep->phy_id >> 4)) |
| 1360 | break; |
| 1361 | } |
| 1362 | |
| 1363 | if (phy_info[i]) |
| 1364 | printk(" -- %s\n", phy_info[i]->name); |
| 1365 | else |
| 1366 | printk(" -- unknown PHY!\n"); |
| 1367 | |
| 1368 | fep->phy = phy_info[i]; |
| 1369 | fep->phy_id_done = 1; |
| 1370 | } |
| 1371 | |
| 1372 | /* Scan all of the MII PHY addresses looking for someone to respond |
| 1373 | * with a valid ID. This usually happens quickly. |
| 1374 | */ |
| 1375 | static void |
| 1376 | mii_discover_phy(uint mii_reg, struct net_device *dev) |
| 1377 | { |
| 1378 | struct fec_enet_private *fep; |
| 1379 | uint phytype; |
| 1380 | |
| 1381 | fep = netdev_priv(dev); |
| 1382 | |
| 1383 | if (fep->phy_addr < 32) { |
| 1384 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { |
| 1385 | |
| 1386 | /* Got first part of ID, now get remainder */ |
| 1387 | fep->phy_id = phytype << 16; |
| 1388 | mii_queue_unlocked(dev, mk_mii_read(MII_REG_PHYIR2), |
| 1389 | mii_discover_phy3); |
| 1390 | } else { |
| 1391 | fep->phy_addr++; |
| 1392 | mii_queue_unlocked(dev, mk_mii_read(MII_REG_PHYIR1), |
| 1393 | mii_discover_phy); |
| 1394 | } |
| 1395 | } else { |
| 1396 | printk("FEC: No PHY device found.\n"); |
| 1397 | /* Disable external MII interface */ |
| 1398 | writel(0, fep->hwp + FEC_MII_SPEED); |
| 1399 | fep->phy_speed = 0; |
| 1400 | #ifdef HAVE_mii_link_interrupt |
| 1401 | fec_disable_phy_intr(); |
| 1402 | #endif |
| 1403 | } |
| 1404 | } |
| 1405 | |
| 1406 | /* This interrupt occurs when the PHY detects a link change */ |
| 1407 | #ifdef HAVE_mii_link_interrupt |
| 1408 | static irqreturn_t |
| 1409 | mii_link_interrupt(int irq, void * dev_id) |
| 1410 | { |
| 1411 | struct net_device *dev = dev_id; |
| 1412 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1413 | |
| 1414 | fec_phy_ack_intr(); |
| 1415 | |
| 1416 | mii_do_cmd(dev, fep->phy->ack_int); |
| 1417 | mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ |
| 1418 | |
| 1419 | return IRQ_HANDLED; |
| 1420 | } |
| 1421 | #endif |
| 1422 | |
| 1423 | static void fec_enet_free_buffers(struct net_device *dev) |
| 1424 | { |
| 1425 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1426 | int i; |
| 1427 | struct sk_buff *skb; |
| 1428 | struct bufdesc *bdp; |
| 1429 | |
| 1430 | bdp = fep->rx_bd_base; |
| 1431 | for (i = 0; i < RX_RING_SIZE; i++) { |
| 1432 | skb = fep->rx_skbuff[i]; |
| 1433 | |
| 1434 | if (bdp->cbd_bufaddr) |
| 1435 | dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, |
| 1436 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
| 1437 | if (skb) |
| 1438 | dev_kfree_skb(skb); |
| 1439 | bdp++; |
| 1440 | } |
| 1441 | |
| 1442 | bdp = fep->tx_bd_base; |
| 1443 | for (i = 0; i < TX_RING_SIZE; i++) |
| 1444 | kfree(fep->tx_bounce[i]); |
| 1445 | } |
| 1446 | |
| 1447 | static int fec_enet_alloc_buffers(struct net_device *dev) |
| 1448 | { |
| 1449 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1450 | int i; |
| 1451 | struct sk_buff *skb; |
| 1452 | struct bufdesc *bdp; |
| 1453 | |
| 1454 | bdp = fep->rx_bd_base; |
| 1455 | for (i = 0; i < RX_RING_SIZE; i++) { |
| 1456 | skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE); |
| 1457 | if (!skb) { |
| 1458 | fec_enet_free_buffers(dev); |
| 1459 | return -ENOMEM; |
| 1460 | } |
| 1461 | fep->rx_skbuff[i] = skb; |
| 1462 | |
| 1463 | bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data, |
| 1464 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
| 1465 | bdp->cbd_sc = BD_ENET_RX_EMPTY; |
| 1466 | bdp++; |
| 1467 | } |
| 1468 | |
| 1469 | /* Set the last buffer to wrap. */ |
| 1470 | bdp--; |
| 1471 | bdp->cbd_sc |= BD_SC_WRAP; |
| 1472 | |
| 1473 | bdp = fep->tx_bd_base; |
| 1474 | for (i = 0; i < TX_RING_SIZE; i++) { |
| 1475 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); |
| 1476 | |
| 1477 | bdp->cbd_sc = 0; |
| 1478 | bdp->cbd_bufaddr = 0; |
| 1479 | bdp++; |
| 1480 | } |
| 1481 | |
| 1482 | /* Set the last buffer to wrap. */ |
| 1483 | bdp--; |
| 1484 | bdp->cbd_sc |= BD_SC_WRAP; |
| 1485 | |
| 1486 | return 0; |
| 1487 | } |
| 1488 | |
| 1489 | static int |
| 1490 | fec_enet_open(struct net_device *dev) |
| 1491 | { |
| 1492 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1493 | int ret; |
| 1494 | |
| 1495 | /* I should reset the ring buffers here, but I don't yet know |
| 1496 | * a simple way to do that. |
| 1497 | */ |
| 1498 | |
| 1499 | ret = fec_enet_alloc_buffers(dev); |
| 1500 | if (ret) |
| 1501 | return ret; |
| 1502 | |
| 1503 | fep->sequence_done = 0; |
| 1504 | fep->link = 0; |
| 1505 | |
| 1506 | fec_restart(dev, 1); |
| 1507 | |
| 1508 | if (fep->phy) { |
| 1509 | mii_do_cmd(dev, fep->phy->ack_int); |
| 1510 | mii_do_cmd(dev, fep->phy->config); |
| 1511 | mii_do_cmd(dev, phy_cmd_config); /* display configuration */ |
| 1512 | |
| 1513 | /* Poll until the PHY tells us its configuration |
| 1514 | * (not link state). |
| 1515 | * Request is initiated by mii_do_cmd above, but answer |
| 1516 | * comes by interrupt. |
| 1517 | * This should take about 25 usec per register at 2.5 MHz, |
| 1518 | * and we read approximately 5 registers. |
| 1519 | */ |
| 1520 | while(!fep->sequence_done) |
| 1521 | schedule(); |
| 1522 | |
| 1523 | mii_do_cmd(dev, fep->phy->startup); |
| 1524 | } |
| 1525 | |
| 1526 | /* Set the initial link state to true. A lot of hardware |
| 1527 | * based on this device does not implement a PHY interrupt, |
| 1528 | * so we are never notified of link change. |
| 1529 | */ |
| 1530 | fep->link = 1; |
| 1531 | |
| 1532 | netif_start_queue(dev); |
| 1533 | fep->opened = 1; |
| 1534 | return 0; |
| 1535 | } |
| 1536 | |
| 1537 | static int |
| 1538 | fec_enet_close(struct net_device *dev) |
| 1539 | { |
| 1540 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1541 | |
| 1542 | /* Don't know what to do yet. */ |
| 1543 | fep->opened = 0; |
| 1544 | netif_stop_queue(dev); |
| 1545 | fec_stop(dev); |
| 1546 | |
| 1547 | fec_enet_free_buffers(dev); |
| 1548 | |
| 1549 | return 0; |
| 1550 | } |
| 1551 | |
| 1552 | /* Set or clear the multicast filter for this adaptor. |
| 1553 | * Skeleton taken from sunlance driver. |
| 1554 | * The CPM Ethernet implementation allows Multicast as well as individual |
| 1555 | * MAC address filtering. Some of the drivers check to make sure it is |
| 1556 | * a group multicast address, and discard those that are not. I guess I |
| 1557 | * will do the same for now, but just remove the test if you want |
| 1558 | * individual filtering as well (do the upper net layers want or support |
| 1559 | * this kind of feature?). |
| 1560 | */ |
| 1561 | |
| 1562 | #define HASH_BITS 6 /* #bits in hash */ |
| 1563 | #define CRC32_POLY 0xEDB88320 |
| 1564 | |
| 1565 | static void set_multicast_list(struct net_device *dev) |
| 1566 | { |
| 1567 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1568 | struct dev_mc_list *dmi; |
| 1569 | unsigned int i, j, bit, data, crc, tmp; |
| 1570 | unsigned char hash; |
| 1571 | |
| 1572 | if (dev->flags & IFF_PROMISC) { |
| 1573 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
| 1574 | tmp |= 0x8; |
| 1575 | writel(tmp, fep->hwp + FEC_R_CNTRL); |
| 1576 | return; |
| 1577 | } |
| 1578 | |
| 1579 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
| 1580 | tmp &= ~0x8; |
| 1581 | writel(tmp, fep->hwp + FEC_R_CNTRL); |
| 1582 | |
| 1583 | if (dev->flags & IFF_ALLMULTI) { |
| 1584 | /* Catch all multicast addresses, so set the |
| 1585 | * filter to all 1's |
| 1586 | */ |
| 1587 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
| 1588 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); |
| 1589 | |
| 1590 | return; |
| 1591 | } |
| 1592 | |
| 1593 | /* Clear filter and add the addresses in hash register |
| 1594 | */ |
| 1595 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
| 1596 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); |
| 1597 | |
| 1598 | dmi = dev->mc_list; |
| 1599 | |
| 1600 | for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) { |
| 1601 | /* Only support group multicast for now */ |
| 1602 | if (!(dmi->dmi_addr[0] & 1)) |
| 1603 | continue; |
| 1604 | |
| 1605 | /* calculate crc32 value of mac address */ |
| 1606 | crc = 0xffffffff; |
| 1607 | |
| 1608 | for (i = 0; i < dmi->dmi_addrlen; i++) { |
| 1609 | data = dmi->dmi_addr[i]; |
| 1610 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
| 1611 | crc = (crc >> 1) ^ |
| 1612 | (((crc ^ data) & 1) ? CRC32_POLY : 0); |
| 1613 | } |
| 1614 | } |
| 1615 | |
| 1616 | /* only upper 6 bits (HASH_BITS) are used |
| 1617 | * which point to specific bit in he hash registers |
| 1618 | */ |
| 1619 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; |
| 1620 | |
| 1621 | if (hash > 31) { |
| 1622 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
| 1623 | tmp |= 1 << (hash - 32); |
| 1624 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
| 1625 | } else { |
| 1626 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); |
| 1627 | tmp |= 1 << hash; |
| 1628 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); |
| 1629 | } |
| 1630 | } |
| 1631 | } |
| 1632 | |
| 1633 | /* Set a MAC change in hardware. */ |
| 1634 | static int |
| 1635 | fec_set_mac_address(struct net_device *dev, void *p) |
| 1636 | { |
| 1637 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1638 | struct sockaddr *addr = p; |
| 1639 | |
| 1640 | if (!is_valid_ether_addr(addr->sa_data)) |
| 1641 | return -EADDRNOTAVAIL; |
| 1642 | |
| 1643 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
| 1644 | |
| 1645 | writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
| 1646 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), |
| 1647 | fep->hwp + FEC_ADDR_LOW); |
| 1648 | writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), |
| 1649 | fep + FEC_ADDR_HIGH); |
| 1650 | return 0; |
| 1651 | } |
| 1652 | |
| 1653 | static const struct net_device_ops fec_netdev_ops = { |
| 1654 | .ndo_open = fec_enet_open, |
| 1655 | .ndo_stop = fec_enet_close, |
| 1656 | .ndo_start_xmit = fec_enet_start_xmit, |
| 1657 | .ndo_set_multicast_list = set_multicast_list, |
| 1658 | .ndo_change_mtu = eth_change_mtu, |
| 1659 | .ndo_validate_addr = eth_validate_addr, |
| 1660 | .ndo_tx_timeout = fec_timeout, |
| 1661 | .ndo_set_mac_address = fec_set_mac_address, |
| 1662 | }; |
| 1663 | |
| 1664 | /* |
| 1665 | * XXX: We need to clean up on failure exits here. |
| 1666 | * |
| 1667 | * index is only used in legacy code |
| 1668 | */ |
| 1669 | int __init fec_enet_init(struct net_device *dev, int index) |
| 1670 | { |
| 1671 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1672 | struct bufdesc *cbd_base; |
| 1673 | int i; |
| 1674 | |
| 1675 | /* Allocate memory for buffer descriptors. */ |
| 1676 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, |
| 1677 | GFP_KERNEL); |
| 1678 | if (!cbd_base) { |
| 1679 | printk("FEC: allocate descriptor memory failed?\n"); |
| 1680 | return -ENOMEM; |
| 1681 | } |
| 1682 | |
| 1683 | spin_lock_init(&fep->hw_lock); |
| 1684 | spin_lock_init(&fep->mii_lock); |
| 1685 | |
| 1686 | fep->index = index; |
| 1687 | fep->hwp = (void __iomem *)dev->base_addr; |
| 1688 | fep->netdev = dev; |
| 1689 | |
| 1690 | /* Set the Ethernet address */ |
| 1691 | #ifdef CONFIG_M5272 |
| 1692 | fec_get_mac(dev); |
| 1693 | #else |
| 1694 | { |
| 1695 | unsigned long l; |
| 1696 | l = readl(fep->hwp + FEC_ADDR_LOW); |
| 1697 | dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24); |
| 1698 | dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16); |
| 1699 | dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8); |
| 1700 | dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0); |
| 1701 | l = readl(fep->hwp + FEC_ADDR_HIGH); |
| 1702 | dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24); |
| 1703 | dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16); |
| 1704 | } |
| 1705 | #endif |
| 1706 | |
| 1707 | /* Set receive and transmit descriptor base. */ |
| 1708 | fep->rx_bd_base = cbd_base; |
| 1709 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; |
| 1710 | |
| 1711 | #ifdef HAVE_mii_link_interrupt |
| 1712 | fec_request_mii_intr(dev); |
| 1713 | #endif |
| 1714 | /* The FEC Ethernet specific entries in the device structure */ |
| 1715 | dev->watchdog_timeo = TX_TIMEOUT; |
| 1716 | dev->netdev_ops = &fec_netdev_ops; |
| 1717 | |
| 1718 | for (i=0; i<NMII-1; i++) |
| 1719 | mii_cmds[i].mii_next = &mii_cmds[i+1]; |
| 1720 | mii_free = mii_cmds; |
| 1721 | |
| 1722 | /* Set MII speed to 2.5 MHz */ |
| 1723 | fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999) |
| 1724 | / 2500000) / 2) & 0x3F) << 1; |
| 1725 | fec_restart(dev, 0); |
| 1726 | |
| 1727 | /* Queue up command to detect the PHY and initialize the |
| 1728 | * remainder of the interface. |
| 1729 | */ |
| 1730 | fep->phy_id_done = 0; |
| 1731 | fep->phy_addr = 0; |
| 1732 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); |
| 1733 | |
| 1734 | return 0; |
| 1735 | } |
| 1736 | |
| 1737 | /* This function is called to start or restart the FEC during a link |
| 1738 | * change. This only happens when switching between half and full |
| 1739 | * duplex. |
| 1740 | */ |
| 1741 | static void |
| 1742 | fec_restart(struct net_device *dev, int duplex) |
| 1743 | { |
| 1744 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1745 | struct bufdesc *bdp; |
| 1746 | int i; |
| 1747 | |
| 1748 | /* Whack a reset. We should wait for this. */ |
| 1749 | writel(1, fep->hwp + FEC_ECNTRL); |
| 1750 | udelay(10); |
| 1751 | |
| 1752 | /* Clear any outstanding interrupt. */ |
| 1753 | writel(0xffc00000, fep->hwp + FEC_IEVENT); |
| 1754 | |
| 1755 | /* Reset all multicast. */ |
| 1756 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
| 1757 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); |
| 1758 | #ifndef CONFIG_M5272 |
| 1759 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); |
| 1760 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); |
| 1761 | #endif |
| 1762 | |
| 1763 | /* Set maximum receive buffer size. */ |
| 1764 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); |
| 1765 | |
| 1766 | /* Set receive and transmit descriptor base. */ |
| 1767 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); |
| 1768 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, |
| 1769 | fep->hwp + FEC_X_DES_START); |
| 1770 | |
| 1771 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; |
| 1772 | fep->cur_rx = fep->rx_bd_base; |
| 1773 | |
| 1774 | /* Reset SKB transmit buffers. */ |
| 1775 | fep->skb_cur = fep->skb_dirty = 0; |
| 1776 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
| 1777 | if (fep->tx_skbuff[i]) { |
| 1778 | dev_kfree_skb_any(fep->tx_skbuff[i]); |
| 1779 | fep->tx_skbuff[i] = NULL; |
| 1780 | } |
| 1781 | } |
| 1782 | |
| 1783 | /* Initialize the receive buffer descriptors. */ |
| 1784 | bdp = fep->rx_bd_base; |
| 1785 | for (i = 0; i < RX_RING_SIZE; i++) { |
| 1786 | |
| 1787 | /* Initialize the BD for every fragment in the page. */ |
| 1788 | bdp->cbd_sc = BD_ENET_RX_EMPTY; |
| 1789 | bdp++; |
| 1790 | } |
| 1791 | |
| 1792 | /* Set the last buffer to wrap */ |
| 1793 | bdp--; |
| 1794 | bdp->cbd_sc |= BD_SC_WRAP; |
| 1795 | |
| 1796 | /* ...and the same for transmit */ |
| 1797 | bdp = fep->tx_bd_base; |
| 1798 | for (i = 0; i < TX_RING_SIZE; i++) { |
| 1799 | |
| 1800 | /* Initialize the BD for every fragment in the page. */ |
| 1801 | bdp->cbd_sc = 0; |
| 1802 | bdp->cbd_bufaddr = 0; |
| 1803 | bdp++; |
| 1804 | } |
| 1805 | |
| 1806 | /* Set the last buffer to wrap */ |
| 1807 | bdp--; |
| 1808 | bdp->cbd_sc |= BD_SC_WRAP; |
| 1809 | |
| 1810 | /* Enable MII mode */ |
| 1811 | if (duplex) { |
| 1812 | /* MII enable / FD enable */ |
| 1813 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); |
| 1814 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
| 1815 | } else { |
| 1816 | /* MII enable / No Rcv on Xmit */ |
| 1817 | writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); |
| 1818 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
| 1819 | } |
| 1820 | fep->full_duplex = duplex; |
| 1821 | |
| 1822 | /* Set MII speed */ |
| 1823 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
| 1824 | |
| 1825 | /* And last, enable the transmit and receive processing */ |
| 1826 | writel(2, fep->hwp + FEC_ECNTRL); |
| 1827 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
| 1828 | |
| 1829 | /* Enable interrupts we wish to service */ |
| 1830 | writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, |
| 1831 | fep->hwp + FEC_IMASK); |
| 1832 | } |
| 1833 | |
| 1834 | static void |
| 1835 | fec_stop(struct net_device *dev) |
| 1836 | { |
| 1837 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1838 | |
| 1839 | /* We cannot expect a graceful transmit stop without link !!! */ |
| 1840 | if (fep->link) { |
| 1841 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ |
| 1842 | udelay(10); |
| 1843 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) |
| 1844 | printk("fec_stop : Graceful transmit stop did not complete !\n"); |
| 1845 | } |
| 1846 | |
| 1847 | /* Whack a reset. We should wait for this. */ |
| 1848 | writel(1, fep->hwp + FEC_ECNTRL); |
| 1849 | udelay(10); |
| 1850 | |
| 1851 | /* Clear outstanding MII command interrupts. */ |
| 1852 | writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); |
| 1853 | |
| 1854 | writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); |
| 1855 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
| 1856 | } |
| 1857 | |
| 1858 | static int __devinit |
| 1859 | fec_probe(struct platform_device *pdev) |
| 1860 | { |
| 1861 | struct fec_enet_private *fep; |
| 1862 | struct net_device *ndev; |
| 1863 | int i, irq, ret = 0; |
| 1864 | struct resource *r; |
| 1865 | |
| 1866 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1867 | if (!r) |
| 1868 | return -ENXIO; |
| 1869 | |
| 1870 | r = request_mem_region(r->start, resource_size(r), pdev->name); |
| 1871 | if (!r) |
| 1872 | return -EBUSY; |
| 1873 | |
| 1874 | /* Init network device */ |
| 1875 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); |
| 1876 | if (!ndev) |
| 1877 | return -ENOMEM; |
| 1878 | |
| 1879 | SET_NETDEV_DEV(ndev, &pdev->dev); |
| 1880 | |
| 1881 | /* setup board info structure */ |
| 1882 | fep = netdev_priv(ndev); |
| 1883 | memset(fep, 0, sizeof(*fep)); |
| 1884 | |
| 1885 | ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r)); |
| 1886 | |
| 1887 | if (!ndev->base_addr) { |
| 1888 | ret = -ENOMEM; |
| 1889 | goto failed_ioremap; |
| 1890 | } |
| 1891 | |
| 1892 | platform_set_drvdata(pdev, ndev); |
| 1893 | |
| 1894 | /* This device has up to three irqs on some platforms */ |
| 1895 | for (i = 0; i < 3; i++) { |
| 1896 | irq = platform_get_irq(pdev, i); |
| 1897 | if (i && irq < 0) |
| 1898 | break; |
| 1899 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); |
| 1900 | if (ret) { |
| 1901 | while (i >= 0) { |
| 1902 | irq = platform_get_irq(pdev, i); |
| 1903 | free_irq(irq, ndev); |
| 1904 | i--; |
| 1905 | } |
| 1906 | goto failed_irq; |
| 1907 | } |
| 1908 | } |
| 1909 | |
| 1910 | fep->clk = clk_get(&pdev->dev, "fec_clk"); |
| 1911 | if (IS_ERR(fep->clk)) { |
| 1912 | ret = PTR_ERR(fep->clk); |
| 1913 | goto failed_clk; |
| 1914 | } |
| 1915 | clk_enable(fep->clk); |
| 1916 | |
| 1917 | ret = fec_enet_init(ndev, 0); |
| 1918 | if (ret) |
| 1919 | goto failed_init; |
| 1920 | |
| 1921 | ret = register_netdev(ndev); |
| 1922 | if (ret) |
| 1923 | goto failed_register; |
| 1924 | |
| 1925 | return 0; |
| 1926 | |
| 1927 | failed_register: |
| 1928 | failed_init: |
| 1929 | clk_disable(fep->clk); |
| 1930 | clk_put(fep->clk); |
| 1931 | failed_clk: |
| 1932 | for (i = 0; i < 3; i++) { |
| 1933 | irq = platform_get_irq(pdev, i); |
| 1934 | if (irq > 0) |
| 1935 | free_irq(irq, ndev); |
| 1936 | } |
| 1937 | failed_irq: |
| 1938 | iounmap((void __iomem *)ndev->base_addr); |
| 1939 | failed_ioremap: |
| 1940 | free_netdev(ndev); |
| 1941 | |
| 1942 | return ret; |
| 1943 | } |
| 1944 | |
| 1945 | static int __devexit |
| 1946 | fec_drv_remove(struct platform_device *pdev) |
| 1947 | { |
| 1948 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 1949 | struct fec_enet_private *fep = netdev_priv(ndev); |
| 1950 | |
| 1951 | platform_set_drvdata(pdev, NULL); |
| 1952 | |
| 1953 | fec_stop(ndev); |
| 1954 | clk_disable(fep->clk); |
| 1955 | clk_put(fep->clk); |
| 1956 | iounmap((void __iomem *)ndev->base_addr); |
| 1957 | unregister_netdev(ndev); |
| 1958 | free_netdev(ndev); |
| 1959 | return 0; |
| 1960 | } |
| 1961 | |
| 1962 | static int |
| 1963 | fec_suspend(struct platform_device *dev, pm_message_t state) |
| 1964 | { |
| 1965 | struct net_device *ndev = platform_get_drvdata(dev); |
| 1966 | struct fec_enet_private *fep; |
| 1967 | |
| 1968 | if (ndev) { |
| 1969 | fep = netdev_priv(ndev); |
| 1970 | if (netif_running(ndev)) { |
| 1971 | netif_device_detach(ndev); |
| 1972 | fec_stop(ndev); |
| 1973 | } |
| 1974 | } |
| 1975 | return 0; |
| 1976 | } |
| 1977 | |
| 1978 | static int |
| 1979 | fec_resume(struct platform_device *dev) |
| 1980 | { |
| 1981 | struct net_device *ndev = platform_get_drvdata(dev); |
| 1982 | |
| 1983 | if (ndev) { |
| 1984 | if (netif_running(ndev)) { |
| 1985 | fec_enet_init(ndev, 0); |
| 1986 | netif_device_attach(ndev); |
| 1987 | } |
| 1988 | } |
| 1989 | return 0; |
| 1990 | } |
| 1991 | |
| 1992 | static struct platform_driver fec_driver = { |
| 1993 | .driver = { |
| 1994 | .name = "fec", |
| 1995 | .owner = THIS_MODULE, |
| 1996 | }, |
| 1997 | .probe = fec_probe, |
| 1998 | .remove = __devexit_p(fec_drv_remove), |
| 1999 | .suspend = fec_suspend, |
| 2000 | .resume = fec_resume, |
| 2001 | }; |
| 2002 | |
| 2003 | static int __init |
| 2004 | fec_enet_module_init(void) |
| 2005 | { |
| 2006 | printk(KERN_INFO "FEC Ethernet Driver\n"); |
| 2007 | |
| 2008 | return platform_driver_register(&fec_driver); |
| 2009 | } |
| 2010 | |
| 2011 | static void __exit |
| 2012 | fec_enet_cleanup(void) |
| 2013 | { |
| 2014 | platform_driver_unregister(&fec_driver); |
| 2015 | } |
| 2016 | |
| 2017 | module_exit(fec_enet_cleanup); |
| 2018 | module_init(fec_enet_module_init); |
| 2019 | |
| 2020 | MODULE_LICENSE("GPL"); |