| 1 | /* |
| 2 | * linux/drivers/net/ethoc.c |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 Avionic Design Development GmbH |
| 5 | * Copyright (C) 2008-2009 Avionic Design GmbH |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * Written by Thierry Reding <thierry.reding@avionic-design.de> |
| 12 | */ |
| 13 | |
| 14 | #include <linux/etherdevice.h> |
| 15 | #include <linux/crc32.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/mii.h> |
| 18 | #include <linux/phy.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <net/ethoc.h> |
| 21 | |
| 22 | /* register offsets */ |
| 23 | #define MODER 0x00 |
| 24 | #define INT_SOURCE 0x04 |
| 25 | #define INT_MASK 0x08 |
| 26 | #define IPGT 0x0c |
| 27 | #define IPGR1 0x10 |
| 28 | #define IPGR2 0x14 |
| 29 | #define PACKETLEN 0x18 |
| 30 | #define COLLCONF 0x1c |
| 31 | #define TX_BD_NUM 0x20 |
| 32 | #define CTRLMODER 0x24 |
| 33 | #define MIIMODER 0x28 |
| 34 | #define MIICOMMAND 0x2c |
| 35 | #define MIIADDRESS 0x30 |
| 36 | #define MIITX_DATA 0x34 |
| 37 | #define MIIRX_DATA 0x38 |
| 38 | #define MIISTATUS 0x3c |
| 39 | #define MAC_ADDR0 0x40 |
| 40 | #define MAC_ADDR1 0x44 |
| 41 | #define ETH_HASH0 0x48 |
| 42 | #define ETH_HASH1 0x4c |
| 43 | #define ETH_TXCTRL 0x50 |
| 44 | |
| 45 | /* mode register */ |
| 46 | #define MODER_RXEN (1 << 0) /* receive enable */ |
| 47 | #define MODER_TXEN (1 << 1) /* transmit enable */ |
| 48 | #define MODER_NOPRE (1 << 2) /* no preamble */ |
| 49 | #define MODER_BRO (1 << 3) /* broadcast address */ |
| 50 | #define MODER_IAM (1 << 4) /* individual address mode */ |
| 51 | #define MODER_PRO (1 << 5) /* promiscuous mode */ |
| 52 | #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ |
| 53 | #define MODER_LOOP (1 << 7) /* loopback */ |
| 54 | #define MODER_NBO (1 << 8) /* no back-off */ |
| 55 | #define MODER_EDE (1 << 9) /* excess defer enable */ |
| 56 | #define MODER_FULLD (1 << 10) /* full duplex */ |
| 57 | #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ |
| 58 | #define MODER_DCRC (1 << 12) /* delayed CRC enable */ |
| 59 | #define MODER_CRC (1 << 13) /* CRC enable */ |
| 60 | #define MODER_HUGE (1 << 14) /* huge packets enable */ |
| 61 | #define MODER_PAD (1 << 15) /* padding enabled */ |
| 62 | #define MODER_RSM (1 << 16) /* receive small packets */ |
| 63 | |
| 64 | /* interrupt source and mask registers */ |
| 65 | #define INT_MASK_TXF (1 << 0) /* transmit frame */ |
| 66 | #define INT_MASK_TXE (1 << 1) /* transmit error */ |
| 67 | #define INT_MASK_RXF (1 << 2) /* receive frame */ |
| 68 | #define INT_MASK_RXE (1 << 3) /* receive error */ |
| 69 | #define INT_MASK_BUSY (1 << 4) |
| 70 | #define INT_MASK_TXC (1 << 5) /* transmit control frame */ |
| 71 | #define INT_MASK_RXC (1 << 6) /* receive control frame */ |
| 72 | |
| 73 | #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) |
| 74 | #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) |
| 75 | |
| 76 | #define INT_MASK_ALL ( \ |
| 77 | INT_MASK_TXF | INT_MASK_TXE | \ |
| 78 | INT_MASK_RXF | INT_MASK_RXE | \ |
| 79 | INT_MASK_TXC | INT_MASK_RXC | \ |
| 80 | INT_MASK_BUSY \ |
| 81 | ) |
| 82 | |
| 83 | /* packet length register */ |
| 84 | #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) |
| 85 | #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) |
| 86 | #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ |
| 87 | PACKETLEN_MAX(max)) |
| 88 | |
| 89 | /* transmit buffer number register */ |
| 90 | #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) |
| 91 | |
| 92 | /* control module mode register */ |
| 93 | #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ |
| 94 | #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ |
| 95 | #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ |
| 96 | |
| 97 | /* MII mode register */ |
| 98 | #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ |
| 99 | #define MIIMODER_NOPRE (1 << 8) /* no preamble */ |
| 100 | |
| 101 | /* MII command register */ |
| 102 | #define MIICOMMAND_SCAN (1 << 0) /* scan status */ |
| 103 | #define MIICOMMAND_READ (1 << 1) /* read status */ |
| 104 | #define MIICOMMAND_WRITE (1 << 2) /* write control data */ |
| 105 | |
| 106 | /* MII address register */ |
| 107 | #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) |
| 108 | #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) |
| 109 | #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ |
| 110 | MIIADDRESS_RGAD(reg)) |
| 111 | |
| 112 | /* MII transmit data register */ |
| 113 | #define MIITX_DATA_VAL(x) ((x) & 0xffff) |
| 114 | |
| 115 | /* MII receive data register */ |
| 116 | #define MIIRX_DATA_VAL(x) ((x) & 0xffff) |
| 117 | |
| 118 | /* MII status register */ |
| 119 | #define MIISTATUS_LINKFAIL (1 << 0) |
| 120 | #define MIISTATUS_BUSY (1 << 1) |
| 121 | #define MIISTATUS_INVALID (1 << 2) |
| 122 | |
| 123 | /* TX buffer descriptor */ |
| 124 | #define TX_BD_CS (1 << 0) /* carrier sense lost */ |
| 125 | #define TX_BD_DF (1 << 1) /* defer indication */ |
| 126 | #define TX_BD_LC (1 << 2) /* late collision */ |
| 127 | #define TX_BD_RL (1 << 3) /* retransmission limit */ |
| 128 | #define TX_BD_RETRY_MASK (0x00f0) |
| 129 | #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) |
| 130 | #define TX_BD_UR (1 << 8) /* transmitter underrun */ |
| 131 | #define TX_BD_CRC (1 << 11) /* TX CRC enable */ |
| 132 | #define TX_BD_PAD (1 << 12) /* pad enable for short packets */ |
| 133 | #define TX_BD_WRAP (1 << 13) |
| 134 | #define TX_BD_IRQ (1 << 14) /* interrupt request enable */ |
| 135 | #define TX_BD_READY (1 << 15) /* TX buffer ready */ |
| 136 | #define TX_BD_LEN(x) (((x) & 0xffff) << 16) |
| 137 | #define TX_BD_LEN_MASK (0xffff << 16) |
| 138 | |
| 139 | #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ |
| 140 | TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) |
| 141 | |
| 142 | /* RX buffer descriptor */ |
| 143 | #define RX_BD_LC (1 << 0) /* late collision */ |
| 144 | #define RX_BD_CRC (1 << 1) /* RX CRC error */ |
| 145 | #define RX_BD_SF (1 << 2) /* short frame */ |
| 146 | #define RX_BD_TL (1 << 3) /* too long */ |
| 147 | #define RX_BD_DN (1 << 4) /* dribble nibble */ |
| 148 | #define RX_BD_IS (1 << 5) /* invalid symbol */ |
| 149 | #define RX_BD_OR (1 << 6) /* receiver overrun */ |
| 150 | #define RX_BD_MISS (1 << 7) |
| 151 | #define RX_BD_CF (1 << 8) /* control frame */ |
| 152 | #define RX_BD_WRAP (1 << 13) |
| 153 | #define RX_BD_IRQ (1 << 14) /* interrupt request enable */ |
| 154 | #define RX_BD_EMPTY (1 << 15) |
| 155 | #define RX_BD_LEN(x) (((x) & 0xffff) << 16) |
| 156 | |
| 157 | #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ |
| 158 | RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) |
| 159 | |
| 160 | #define ETHOC_BUFSIZ 1536 |
| 161 | #define ETHOC_ZLEN 64 |
| 162 | #define ETHOC_BD_BASE 0x400 |
| 163 | #define ETHOC_TIMEOUT (HZ / 2) |
| 164 | #define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) |
| 165 | |
| 166 | /** |
| 167 | * struct ethoc - driver-private device structure |
| 168 | * @iobase: pointer to I/O memory region |
| 169 | * @membase: pointer to buffer memory region |
| 170 | * @num_tx: number of send buffers |
| 171 | * @cur_tx: last send buffer written |
| 172 | * @dty_tx: last buffer actually sent |
| 173 | * @num_rx: number of receive buffers |
| 174 | * @cur_rx: current receive buffer |
| 175 | * @netdev: pointer to network device structure |
| 176 | * @napi: NAPI structure |
| 177 | * @stats: network device statistics |
| 178 | * @msg_enable: device state flags |
| 179 | * @rx_lock: receive lock |
| 180 | * @lock: device lock |
| 181 | * @phy: attached PHY |
| 182 | * @mdio: MDIO bus for PHY access |
| 183 | * @phy_id: address of attached PHY |
| 184 | */ |
| 185 | struct ethoc { |
| 186 | void __iomem *iobase; |
| 187 | void __iomem *membase; |
| 188 | |
| 189 | unsigned int num_tx; |
| 190 | unsigned int cur_tx; |
| 191 | unsigned int dty_tx; |
| 192 | |
| 193 | unsigned int num_rx; |
| 194 | unsigned int cur_rx; |
| 195 | |
| 196 | struct net_device *netdev; |
| 197 | struct napi_struct napi; |
| 198 | struct net_device_stats stats; |
| 199 | u32 msg_enable; |
| 200 | |
| 201 | spinlock_t rx_lock; |
| 202 | spinlock_t lock; |
| 203 | |
| 204 | struct phy_device *phy; |
| 205 | struct mii_bus *mdio; |
| 206 | s8 phy_id; |
| 207 | }; |
| 208 | |
| 209 | /** |
| 210 | * struct ethoc_bd - buffer descriptor |
| 211 | * @stat: buffer statistics |
| 212 | * @addr: physical memory address |
| 213 | */ |
| 214 | struct ethoc_bd { |
| 215 | u32 stat; |
| 216 | u32 addr; |
| 217 | }; |
| 218 | |
| 219 | static u32 ethoc_read(struct ethoc *dev, loff_t offset) |
| 220 | { |
| 221 | return ioread32(dev->iobase + offset); |
| 222 | } |
| 223 | |
| 224 | static void ethoc_write(struct ethoc *dev, loff_t offset, u32 data) |
| 225 | { |
| 226 | iowrite32(data, dev->iobase + offset); |
| 227 | } |
| 228 | |
| 229 | static void ethoc_read_bd(struct ethoc *dev, int index, struct ethoc_bd *bd) |
| 230 | { |
| 231 | loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); |
| 232 | bd->stat = ethoc_read(dev, offset + 0); |
| 233 | bd->addr = ethoc_read(dev, offset + 4); |
| 234 | } |
| 235 | |
| 236 | static void ethoc_write_bd(struct ethoc *dev, int index, |
| 237 | const struct ethoc_bd *bd) |
| 238 | { |
| 239 | loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); |
| 240 | ethoc_write(dev, offset + 0, bd->stat); |
| 241 | ethoc_write(dev, offset + 4, bd->addr); |
| 242 | } |
| 243 | |
| 244 | static void ethoc_enable_irq(struct ethoc *dev, u32 mask) |
| 245 | { |
| 246 | u32 imask = ethoc_read(dev, INT_MASK); |
| 247 | imask |= mask; |
| 248 | ethoc_write(dev, INT_MASK, imask); |
| 249 | } |
| 250 | |
| 251 | static void ethoc_disable_irq(struct ethoc *dev, u32 mask) |
| 252 | { |
| 253 | u32 imask = ethoc_read(dev, INT_MASK); |
| 254 | imask &= ~mask; |
| 255 | ethoc_write(dev, INT_MASK, imask); |
| 256 | } |
| 257 | |
| 258 | static void ethoc_ack_irq(struct ethoc *dev, u32 mask) |
| 259 | { |
| 260 | ethoc_write(dev, INT_SOURCE, mask); |
| 261 | } |
| 262 | |
| 263 | static void ethoc_enable_rx_and_tx(struct ethoc *dev) |
| 264 | { |
| 265 | u32 mode = ethoc_read(dev, MODER); |
| 266 | mode |= MODER_RXEN | MODER_TXEN; |
| 267 | ethoc_write(dev, MODER, mode); |
| 268 | } |
| 269 | |
| 270 | static void ethoc_disable_rx_and_tx(struct ethoc *dev) |
| 271 | { |
| 272 | u32 mode = ethoc_read(dev, MODER); |
| 273 | mode &= ~(MODER_RXEN | MODER_TXEN); |
| 274 | ethoc_write(dev, MODER, mode); |
| 275 | } |
| 276 | |
| 277 | static int ethoc_init_ring(struct ethoc *dev) |
| 278 | { |
| 279 | struct ethoc_bd bd; |
| 280 | int i; |
| 281 | |
| 282 | dev->cur_tx = 0; |
| 283 | dev->dty_tx = 0; |
| 284 | dev->cur_rx = 0; |
| 285 | |
| 286 | /* setup transmission buffers */ |
| 287 | bd.addr = 0; |
| 288 | bd.stat = TX_BD_IRQ | TX_BD_CRC; |
| 289 | |
| 290 | for (i = 0; i < dev->num_tx; i++) { |
| 291 | if (i == dev->num_tx - 1) |
| 292 | bd.stat |= TX_BD_WRAP; |
| 293 | |
| 294 | ethoc_write_bd(dev, i, &bd); |
| 295 | bd.addr += ETHOC_BUFSIZ; |
| 296 | } |
| 297 | |
| 298 | bd.addr = dev->num_tx * ETHOC_BUFSIZ; |
| 299 | bd.stat = RX_BD_EMPTY | RX_BD_IRQ; |
| 300 | |
| 301 | for (i = 0; i < dev->num_rx; i++) { |
| 302 | if (i == dev->num_rx - 1) |
| 303 | bd.stat |= RX_BD_WRAP; |
| 304 | |
| 305 | ethoc_write_bd(dev, dev->num_tx + i, &bd); |
| 306 | bd.addr += ETHOC_BUFSIZ; |
| 307 | } |
| 308 | |
| 309 | return 0; |
| 310 | } |
| 311 | |
| 312 | static int ethoc_reset(struct ethoc *dev) |
| 313 | { |
| 314 | u32 mode; |
| 315 | |
| 316 | /* TODO: reset controller? */ |
| 317 | |
| 318 | ethoc_disable_rx_and_tx(dev); |
| 319 | |
| 320 | /* TODO: setup registers */ |
| 321 | |
| 322 | /* enable FCS generation and automatic padding */ |
| 323 | mode = ethoc_read(dev, MODER); |
| 324 | mode |= MODER_CRC | MODER_PAD; |
| 325 | ethoc_write(dev, MODER, mode); |
| 326 | |
| 327 | /* set full-duplex mode */ |
| 328 | mode = ethoc_read(dev, MODER); |
| 329 | mode |= MODER_FULLD; |
| 330 | ethoc_write(dev, MODER, mode); |
| 331 | ethoc_write(dev, IPGT, 0x15); |
| 332 | |
| 333 | ethoc_ack_irq(dev, INT_MASK_ALL); |
| 334 | ethoc_enable_irq(dev, INT_MASK_ALL); |
| 335 | ethoc_enable_rx_and_tx(dev); |
| 336 | return 0; |
| 337 | } |
| 338 | |
| 339 | static unsigned int ethoc_update_rx_stats(struct ethoc *dev, |
| 340 | struct ethoc_bd *bd) |
| 341 | { |
| 342 | struct net_device *netdev = dev->netdev; |
| 343 | unsigned int ret = 0; |
| 344 | |
| 345 | if (bd->stat & RX_BD_TL) { |
| 346 | dev_err(&netdev->dev, "RX: frame too long\n"); |
| 347 | dev->stats.rx_length_errors++; |
| 348 | ret++; |
| 349 | } |
| 350 | |
| 351 | if (bd->stat & RX_BD_SF) { |
| 352 | dev_err(&netdev->dev, "RX: frame too short\n"); |
| 353 | dev->stats.rx_length_errors++; |
| 354 | ret++; |
| 355 | } |
| 356 | |
| 357 | if (bd->stat & RX_BD_DN) { |
| 358 | dev_err(&netdev->dev, "RX: dribble nibble\n"); |
| 359 | dev->stats.rx_frame_errors++; |
| 360 | } |
| 361 | |
| 362 | if (bd->stat & RX_BD_CRC) { |
| 363 | dev_err(&netdev->dev, "RX: wrong CRC\n"); |
| 364 | dev->stats.rx_crc_errors++; |
| 365 | ret++; |
| 366 | } |
| 367 | |
| 368 | if (bd->stat & RX_BD_OR) { |
| 369 | dev_err(&netdev->dev, "RX: overrun\n"); |
| 370 | dev->stats.rx_over_errors++; |
| 371 | ret++; |
| 372 | } |
| 373 | |
| 374 | if (bd->stat & RX_BD_MISS) |
| 375 | dev->stats.rx_missed_errors++; |
| 376 | |
| 377 | if (bd->stat & RX_BD_LC) { |
| 378 | dev_err(&netdev->dev, "RX: late collision\n"); |
| 379 | dev->stats.collisions++; |
| 380 | ret++; |
| 381 | } |
| 382 | |
| 383 | return ret; |
| 384 | } |
| 385 | |
| 386 | static int ethoc_rx(struct net_device *dev, int limit) |
| 387 | { |
| 388 | struct ethoc *priv = netdev_priv(dev); |
| 389 | int count; |
| 390 | |
| 391 | for (count = 0; count < limit; ++count) { |
| 392 | unsigned int entry; |
| 393 | struct ethoc_bd bd; |
| 394 | |
| 395 | entry = priv->num_tx + (priv->cur_rx % priv->num_rx); |
| 396 | ethoc_read_bd(priv, entry, &bd); |
| 397 | if (bd.stat & RX_BD_EMPTY) |
| 398 | break; |
| 399 | |
| 400 | if (ethoc_update_rx_stats(priv, &bd) == 0) { |
| 401 | int size = bd.stat >> 16; |
| 402 | struct sk_buff *skb = netdev_alloc_skb(dev, size); |
| 403 | if (likely(skb)) { |
| 404 | void *src = priv->membase + bd.addr; |
| 405 | memcpy_fromio(skb_put(skb, size), src, size); |
| 406 | skb->protocol = eth_type_trans(skb, dev); |
| 407 | priv->stats.rx_packets++; |
| 408 | priv->stats.rx_bytes += size; |
| 409 | netif_receive_skb(skb); |
| 410 | } else { |
| 411 | if (net_ratelimit()) |
| 412 | dev_warn(&dev->dev, "low on memory - " |
| 413 | "packet dropped\n"); |
| 414 | |
| 415 | priv->stats.rx_dropped++; |
| 416 | break; |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | /* clear the buffer descriptor so it can be reused */ |
| 421 | bd.stat &= ~RX_BD_STATS; |
| 422 | bd.stat |= RX_BD_EMPTY; |
| 423 | ethoc_write_bd(priv, entry, &bd); |
| 424 | priv->cur_rx++; |
| 425 | } |
| 426 | |
| 427 | return count; |
| 428 | } |
| 429 | |
| 430 | static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd) |
| 431 | { |
| 432 | struct net_device *netdev = dev->netdev; |
| 433 | |
| 434 | if (bd->stat & TX_BD_LC) { |
| 435 | dev_err(&netdev->dev, "TX: late collision\n"); |
| 436 | dev->stats.tx_window_errors++; |
| 437 | } |
| 438 | |
| 439 | if (bd->stat & TX_BD_RL) { |
| 440 | dev_err(&netdev->dev, "TX: retransmit limit\n"); |
| 441 | dev->stats.tx_aborted_errors++; |
| 442 | } |
| 443 | |
| 444 | if (bd->stat & TX_BD_UR) { |
| 445 | dev_err(&netdev->dev, "TX: underrun\n"); |
| 446 | dev->stats.tx_fifo_errors++; |
| 447 | } |
| 448 | |
| 449 | if (bd->stat & TX_BD_CS) { |
| 450 | dev_err(&netdev->dev, "TX: carrier sense lost\n"); |
| 451 | dev->stats.tx_carrier_errors++; |
| 452 | } |
| 453 | |
| 454 | if (bd->stat & TX_BD_STATS) |
| 455 | dev->stats.tx_errors++; |
| 456 | |
| 457 | dev->stats.collisions += (bd->stat >> 4) & 0xf; |
| 458 | dev->stats.tx_bytes += bd->stat >> 16; |
| 459 | dev->stats.tx_packets++; |
| 460 | return 0; |
| 461 | } |
| 462 | |
| 463 | static void ethoc_tx(struct net_device *dev) |
| 464 | { |
| 465 | struct ethoc *priv = netdev_priv(dev); |
| 466 | |
| 467 | spin_lock(&priv->lock); |
| 468 | |
| 469 | while (priv->dty_tx != priv->cur_tx) { |
| 470 | unsigned int entry = priv->dty_tx % priv->num_tx; |
| 471 | struct ethoc_bd bd; |
| 472 | |
| 473 | ethoc_read_bd(priv, entry, &bd); |
| 474 | if (bd.stat & TX_BD_READY) |
| 475 | break; |
| 476 | |
| 477 | entry = (++priv->dty_tx) % priv->num_tx; |
| 478 | (void)ethoc_update_tx_stats(priv, &bd); |
| 479 | } |
| 480 | |
| 481 | if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2)) |
| 482 | netif_wake_queue(dev); |
| 483 | |
| 484 | ethoc_ack_irq(priv, INT_MASK_TX); |
| 485 | spin_unlock(&priv->lock); |
| 486 | } |
| 487 | |
| 488 | static irqreturn_t ethoc_interrupt(int irq, void *dev_id) |
| 489 | { |
| 490 | struct net_device *dev = (struct net_device *)dev_id; |
| 491 | struct ethoc *priv = netdev_priv(dev); |
| 492 | u32 pending; |
| 493 | |
| 494 | ethoc_disable_irq(priv, INT_MASK_ALL); |
| 495 | pending = ethoc_read(priv, INT_SOURCE); |
| 496 | if (unlikely(pending == 0)) { |
| 497 | ethoc_enable_irq(priv, INT_MASK_ALL); |
| 498 | return IRQ_NONE; |
| 499 | } |
| 500 | |
| 501 | ethoc_ack_irq(priv, INT_MASK_ALL); |
| 502 | |
| 503 | if (pending & INT_MASK_BUSY) { |
| 504 | dev_err(&dev->dev, "packet dropped\n"); |
| 505 | priv->stats.rx_dropped++; |
| 506 | } |
| 507 | |
| 508 | if (pending & INT_MASK_RX) { |
| 509 | if (napi_schedule_prep(&priv->napi)) |
| 510 | __napi_schedule(&priv->napi); |
| 511 | } else { |
| 512 | ethoc_enable_irq(priv, INT_MASK_RX); |
| 513 | } |
| 514 | |
| 515 | if (pending & INT_MASK_TX) |
| 516 | ethoc_tx(dev); |
| 517 | |
| 518 | ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX); |
| 519 | return IRQ_HANDLED; |
| 520 | } |
| 521 | |
| 522 | static int ethoc_get_mac_address(struct net_device *dev, void *addr) |
| 523 | { |
| 524 | struct ethoc *priv = netdev_priv(dev); |
| 525 | u8 *mac = (u8 *)addr; |
| 526 | u32 reg; |
| 527 | |
| 528 | reg = ethoc_read(priv, MAC_ADDR0); |
| 529 | mac[2] = (reg >> 24) & 0xff; |
| 530 | mac[3] = (reg >> 16) & 0xff; |
| 531 | mac[4] = (reg >> 8) & 0xff; |
| 532 | mac[5] = (reg >> 0) & 0xff; |
| 533 | |
| 534 | reg = ethoc_read(priv, MAC_ADDR1); |
| 535 | mac[0] = (reg >> 8) & 0xff; |
| 536 | mac[1] = (reg >> 0) & 0xff; |
| 537 | |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | static int ethoc_poll(struct napi_struct *napi, int budget) |
| 542 | { |
| 543 | struct ethoc *priv = container_of(napi, struct ethoc, napi); |
| 544 | int work_done = 0; |
| 545 | |
| 546 | work_done = ethoc_rx(priv->netdev, budget); |
| 547 | if (work_done < budget) { |
| 548 | ethoc_enable_irq(priv, INT_MASK_RX); |
| 549 | napi_complete(napi); |
| 550 | } |
| 551 | |
| 552 | return work_done; |
| 553 | } |
| 554 | |
| 555 | static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg) |
| 556 | { |
| 557 | unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT; |
| 558 | struct ethoc *priv = bus->priv; |
| 559 | |
| 560 | ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); |
| 561 | ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ); |
| 562 | |
| 563 | while (time_before(jiffies, timeout)) { |
| 564 | u32 status = ethoc_read(priv, MIISTATUS); |
| 565 | if (!(status & MIISTATUS_BUSY)) { |
| 566 | u32 data = ethoc_read(priv, MIIRX_DATA); |
| 567 | /* reset MII command register */ |
| 568 | ethoc_write(priv, MIICOMMAND, 0); |
| 569 | return data; |
| 570 | } |
| 571 | |
| 572 | schedule(); |
| 573 | } |
| 574 | |
| 575 | return -EBUSY; |
| 576 | } |
| 577 | |
| 578 | static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
| 579 | { |
| 580 | unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT; |
| 581 | struct ethoc *priv = bus->priv; |
| 582 | |
| 583 | ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); |
| 584 | ethoc_write(priv, MIITX_DATA, val); |
| 585 | ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE); |
| 586 | |
| 587 | while (time_before(jiffies, timeout)) { |
| 588 | u32 stat = ethoc_read(priv, MIISTATUS); |
| 589 | if (!(stat & MIISTATUS_BUSY)) |
| 590 | return 0; |
| 591 | |
| 592 | schedule(); |
| 593 | } |
| 594 | |
| 595 | return -EBUSY; |
| 596 | } |
| 597 | |
| 598 | static int ethoc_mdio_reset(struct mii_bus *bus) |
| 599 | { |
| 600 | return 0; |
| 601 | } |
| 602 | |
| 603 | static void ethoc_mdio_poll(struct net_device *dev) |
| 604 | { |
| 605 | } |
| 606 | |
| 607 | static int ethoc_mdio_probe(struct net_device *dev) |
| 608 | { |
| 609 | struct ethoc *priv = netdev_priv(dev); |
| 610 | struct phy_device *phy; |
| 611 | int i; |
| 612 | |
| 613 | for (i = 0; i < PHY_MAX_ADDR; i++) { |
| 614 | phy = priv->mdio->phy_map[i]; |
| 615 | if (phy) { |
| 616 | if (priv->phy_id != -1) { |
| 617 | /* attach to specified PHY */ |
| 618 | if (priv->phy_id == phy->addr) |
| 619 | break; |
| 620 | } else { |
| 621 | /* autoselect PHY if none was specified */ |
| 622 | if (phy->addr != 0) |
| 623 | break; |
| 624 | } |
| 625 | } |
| 626 | } |
| 627 | |
| 628 | if (!phy) { |
| 629 | dev_err(&dev->dev, "no PHY found\n"); |
| 630 | return -ENXIO; |
| 631 | } |
| 632 | |
| 633 | phy = phy_connect(dev, dev_name(&phy->dev), ðoc_mdio_poll, 0, |
| 634 | PHY_INTERFACE_MODE_GMII); |
| 635 | if (IS_ERR(phy)) { |
| 636 | dev_err(&dev->dev, "could not attach to PHY\n"); |
| 637 | return PTR_ERR(phy); |
| 638 | } |
| 639 | |
| 640 | priv->phy = phy; |
| 641 | return 0; |
| 642 | } |
| 643 | |
| 644 | static int ethoc_open(struct net_device *dev) |
| 645 | { |
| 646 | struct ethoc *priv = netdev_priv(dev); |
| 647 | unsigned int min_tx = 2; |
| 648 | unsigned int num_bd; |
| 649 | int ret; |
| 650 | |
| 651 | ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED, |
| 652 | dev->name, dev); |
| 653 | if (ret) |
| 654 | return ret; |
| 655 | |
| 656 | /* calculate the number of TX/RX buffers */ |
| 657 | num_bd = (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ; |
| 658 | priv->num_tx = min(min_tx, num_bd / 4); |
| 659 | priv->num_rx = num_bd - priv->num_tx; |
| 660 | ethoc_write(priv, TX_BD_NUM, priv->num_tx); |
| 661 | |
| 662 | ethoc_init_ring(priv); |
| 663 | ethoc_reset(priv); |
| 664 | |
| 665 | if (netif_queue_stopped(dev)) { |
| 666 | dev_dbg(&dev->dev, " resuming queue\n"); |
| 667 | netif_wake_queue(dev); |
| 668 | } else { |
| 669 | dev_dbg(&dev->dev, " starting queue\n"); |
| 670 | netif_start_queue(dev); |
| 671 | } |
| 672 | |
| 673 | phy_start(priv->phy); |
| 674 | napi_enable(&priv->napi); |
| 675 | |
| 676 | if (netif_msg_ifup(priv)) { |
| 677 | dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n", |
| 678 | dev->base_addr, dev->mem_start, dev->mem_end); |
| 679 | } |
| 680 | |
| 681 | return 0; |
| 682 | } |
| 683 | |
| 684 | static int ethoc_stop(struct net_device *dev) |
| 685 | { |
| 686 | struct ethoc *priv = netdev_priv(dev); |
| 687 | |
| 688 | napi_disable(&priv->napi); |
| 689 | |
| 690 | if (priv->phy) |
| 691 | phy_stop(priv->phy); |
| 692 | |
| 693 | ethoc_disable_rx_and_tx(priv); |
| 694 | free_irq(dev->irq, dev); |
| 695 | |
| 696 | if (!netif_queue_stopped(dev)) |
| 697 | netif_stop_queue(dev); |
| 698 | |
| 699 | return 0; |
| 700 | } |
| 701 | |
| 702 | static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 703 | { |
| 704 | struct ethoc *priv = netdev_priv(dev); |
| 705 | struct mii_ioctl_data *mdio = if_mii(ifr); |
| 706 | struct phy_device *phy = NULL; |
| 707 | |
| 708 | if (!netif_running(dev)) |
| 709 | return -EINVAL; |
| 710 | |
| 711 | if (cmd != SIOCGMIIPHY) { |
| 712 | if (mdio->phy_id >= PHY_MAX_ADDR) |
| 713 | return -ERANGE; |
| 714 | |
| 715 | phy = priv->mdio->phy_map[mdio->phy_id]; |
| 716 | if (!phy) |
| 717 | return -ENODEV; |
| 718 | } else { |
| 719 | phy = priv->phy; |
| 720 | } |
| 721 | |
| 722 | return phy_mii_ioctl(phy, mdio, cmd); |
| 723 | } |
| 724 | |
| 725 | static int ethoc_config(struct net_device *dev, struct ifmap *map) |
| 726 | { |
| 727 | return -ENOSYS; |
| 728 | } |
| 729 | |
| 730 | static int ethoc_set_mac_address(struct net_device *dev, void *addr) |
| 731 | { |
| 732 | struct ethoc *priv = netdev_priv(dev); |
| 733 | u8 *mac = (u8 *)addr; |
| 734 | |
| 735 | ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | |
| 736 | (mac[4] << 8) | (mac[5] << 0)); |
| 737 | ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); |
| 738 | |
| 739 | return 0; |
| 740 | } |
| 741 | |
| 742 | static void ethoc_set_multicast_list(struct net_device *dev) |
| 743 | { |
| 744 | struct ethoc *priv = netdev_priv(dev); |
| 745 | u32 mode = ethoc_read(priv, MODER); |
| 746 | struct dev_mc_list *mc = NULL; |
| 747 | u32 hash[2] = { 0, 0 }; |
| 748 | |
| 749 | /* set loopback mode if requested */ |
| 750 | if (dev->flags & IFF_LOOPBACK) |
| 751 | mode |= MODER_LOOP; |
| 752 | else |
| 753 | mode &= ~MODER_LOOP; |
| 754 | |
| 755 | /* receive broadcast frames if requested */ |
| 756 | if (dev->flags & IFF_BROADCAST) |
| 757 | mode &= ~MODER_BRO; |
| 758 | else |
| 759 | mode |= MODER_BRO; |
| 760 | |
| 761 | /* enable promiscuous mode if requested */ |
| 762 | if (dev->flags & IFF_PROMISC) |
| 763 | mode |= MODER_PRO; |
| 764 | else |
| 765 | mode &= ~MODER_PRO; |
| 766 | |
| 767 | ethoc_write(priv, MODER, mode); |
| 768 | |
| 769 | /* receive multicast frames */ |
| 770 | if (dev->flags & IFF_ALLMULTI) { |
| 771 | hash[0] = 0xffffffff; |
| 772 | hash[1] = 0xffffffff; |
| 773 | } else { |
| 774 | for (mc = dev->mc_list; mc; mc = mc->next) { |
| 775 | u32 crc = ether_crc(mc->dmi_addrlen, mc->dmi_addr); |
| 776 | int bit = (crc >> 26) & 0x3f; |
| 777 | hash[bit >> 5] |= 1 << (bit & 0x1f); |
| 778 | } |
| 779 | } |
| 780 | |
| 781 | ethoc_write(priv, ETH_HASH0, hash[0]); |
| 782 | ethoc_write(priv, ETH_HASH1, hash[1]); |
| 783 | } |
| 784 | |
| 785 | static int ethoc_change_mtu(struct net_device *dev, int new_mtu) |
| 786 | { |
| 787 | return -ENOSYS; |
| 788 | } |
| 789 | |
| 790 | static void ethoc_tx_timeout(struct net_device *dev) |
| 791 | { |
| 792 | struct ethoc *priv = netdev_priv(dev); |
| 793 | u32 pending = ethoc_read(priv, INT_SOURCE); |
| 794 | if (likely(pending)) |
| 795 | ethoc_interrupt(dev->irq, dev); |
| 796 | } |
| 797 | |
| 798 | static struct net_device_stats *ethoc_stats(struct net_device *dev) |
| 799 | { |
| 800 | struct ethoc *priv = netdev_priv(dev); |
| 801 | return &priv->stats; |
| 802 | } |
| 803 | |
| 804 | static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 805 | { |
| 806 | struct ethoc *priv = netdev_priv(dev); |
| 807 | struct ethoc_bd bd; |
| 808 | unsigned int entry; |
| 809 | void *dest; |
| 810 | |
| 811 | if (unlikely(skb->len > ETHOC_BUFSIZ)) { |
| 812 | priv->stats.tx_errors++; |
| 813 | goto out; |
| 814 | } |
| 815 | |
| 816 | entry = priv->cur_tx % priv->num_tx; |
| 817 | spin_lock_irq(&priv->lock); |
| 818 | priv->cur_tx++; |
| 819 | |
| 820 | ethoc_read_bd(priv, entry, &bd); |
| 821 | if (unlikely(skb->len < ETHOC_ZLEN)) |
| 822 | bd.stat |= TX_BD_PAD; |
| 823 | else |
| 824 | bd.stat &= ~TX_BD_PAD; |
| 825 | |
| 826 | dest = priv->membase + bd.addr; |
| 827 | memcpy_toio(dest, skb->data, skb->len); |
| 828 | |
| 829 | bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); |
| 830 | bd.stat |= TX_BD_LEN(skb->len); |
| 831 | ethoc_write_bd(priv, entry, &bd); |
| 832 | |
| 833 | bd.stat |= TX_BD_READY; |
| 834 | ethoc_write_bd(priv, entry, &bd); |
| 835 | |
| 836 | if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) { |
| 837 | dev_dbg(&dev->dev, "stopping queue\n"); |
| 838 | netif_stop_queue(dev); |
| 839 | } |
| 840 | |
| 841 | dev->trans_start = jiffies; |
| 842 | spin_unlock_irq(&priv->lock); |
| 843 | out: |
| 844 | dev_kfree_skb(skb); |
| 845 | return NETDEV_TX_OK; |
| 846 | } |
| 847 | |
| 848 | static const struct net_device_ops ethoc_netdev_ops = { |
| 849 | .ndo_open = ethoc_open, |
| 850 | .ndo_stop = ethoc_stop, |
| 851 | .ndo_do_ioctl = ethoc_ioctl, |
| 852 | .ndo_set_config = ethoc_config, |
| 853 | .ndo_set_mac_address = ethoc_set_mac_address, |
| 854 | .ndo_set_multicast_list = ethoc_set_multicast_list, |
| 855 | .ndo_change_mtu = ethoc_change_mtu, |
| 856 | .ndo_tx_timeout = ethoc_tx_timeout, |
| 857 | .ndo_get_stats = ethoc_stats, |
| 858 | .ndo_start_xmit = ethoc_start_xmit, |
| 859 | }; |
| 860 | |
| 861 | /** |
| 862 | * ethoc_probe() - initialize OpenCores ethernet MAC |
| 863 | * pdev: platform device |
| 864 | */ |
| 865 | static int ethoc_probe(struct platform_device *pdev) |
| 866 | { |
| 867 | struct net_device *netdev = NULL; |
| 868 | struct resource *res = NULL; |
| 869 | struct resource *mmio = NULL; |
| 870 | struct resource *mem = NULL; |
| 871 | struct ethoc *priv = NULL; |
| 872 | unsigned int phy; |
| 873 | int ret = 0; |
| 874 | |
| 875 | /* allocate networking device */ |
| 876 | netdev = alloc_etherdev(sizeof(struct ethoc)); |
| 877 | if (!netdev) { |
| 878 | dev_err(&pdev->dev, "cannot allocate network device\n"); |
| 879 | ret = -ENOMEM; |
| 880 | goto out; |
| 881 | } |
| 882 | |
| 883 | SET_NETDEV_DEV(netdev, &pdev->dev); |
| 884 | platform_set_drvdata(pdev, netdev); |
| 885 | |
| 886 | /* obtain I/O memory space */ |
| 887 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 888 | if (!res) { |
| 889 | dev_err(&pdev->dev, "cannot obtain I/O memory space\n"); |
| 890 | ret = -ENXIO; |
| 891 | goto free; |
| 892 | } |
| 893 | |
| 894 | mmio = devm_request_mem_region(&pdev->dev, res->start, |
| 895 | res->end - res->start + 1, res->name); |
| 896 | if (!mmio) { |
| 897 | dev_err(&pdev->dev, "cannot request I/O memory space\n"); |
| 898 | ret = -ENXIO; |
| 899 | goto free; |
| 900 | } |
| 901 | |
| 902 | netdev->base_addr = mmio->start; |
| 903 | |
| 904 | /* obtain buffer memory space */ |
| 905 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 906 | if (!res) { |
| 907 | dev_err(&pdev->dev, "cannot obtain memory space\n"); |
| 908 | ret = -ENXIO; |
| 909 | goto free; |
| 910 | } |
| 911 | |
| 912 | mem = devm_request_mem_region(&pdev->dev, res->start, |
| 913 | res->end - res->start + 1, res->name); |
| 914 | if (!mem) { |
| 915 | dev_err(&pdev->dev, "cannot request memory space\n"); |
| 916 | ret = -ENXIO; |
| 917 | goto free; |
| 918 | } |
| 919 | |
| 920 | netdev->mem_start = mem->start; |
| 921 | netdev->mem_end = mem->end; |
| 922 | |
| 923 | /* obtain device IRQ number */ |
| 924 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 925 | if (!res) { |
| 926 | dev_err(&pdev->dev, "cannot obtain IRQ\n"); |
| 927 | ret = -ENXIO; |
| 928 | goto free; |
| 929 | } |
| 930 | |
| 931 | netdev->irq = res->start; |
| 932 | |
| 933 | /* setup driver-private data */ |
| 934 | priv = netdev_priv(netdev); |
| 935 | priv->netdev = netdev; |
| 936 | |
| 937 | priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr, |
| 938 | mmio->end - mmio->start + 1); |
| 939 | if (!priv->iobase) { |
| 940 | dev_err(&pdev->dev, "cannot remap I/O memory space\n"); |
| 941 | ret = -ENXIO; |
| 942 | goto error; |
| 943 | } |
| 944 | |
| 945 | priv->membase = devm_ioremap_nocache(&pdev->dev, netdev->mem_start, |
| 946 | mem->end - mem->start + 1); |
| 947 | if (!priv->membase) { |
| 948 | dev_err(&pdev->dev, "cannot remap memory space\n"); |
| 949 | ret = -ENXIO; |
| 950 | goto error; |
| 951 | } |
| 952 | |
| 953 | /* Allow the platform setup code to pass in a MAC address. */ |
| 954 | if (pdev->dev.platform_data) { |
| 955 | struct ethoc_platform_data *pdata = |
| 956 | (struct ethoc_platform_data *)pdev->dev.platform_data; |
| 957 | memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN); |
| 958 | priv->phy_id = pdata->phy_id; |
| 959 | } |
| 960 | |
| 961 | /* Check that the given MAC address is valid. If it isn't, read the |
| 962 | * current MAC from the controller. */ |
| 963 | if (!is_valid_ether_addr(netdev->dev_addr)) |
| 964 | ethoc_get_mac_address(netdev, netdev->dev_addr); |
| 965 | |
| 966 | /* Check the MAC again for validity, if it still isn't choose and |
| 967 | * program a random one. */ |
| 968 | if (!is_valid_ether_addr(netdev->dev_addr)) |
| 969 | random_ether_addr(netdev->dev_addr); |
| 970 | |
| 971 | ethoc_set_mac_address(netdev, netdev->dev_addr); |
| 972 | |
| 973 | /* register MII bus */ |
| 974 | priv->mdio = mdiobus_alloc(); |
| 975 | if (!priv->mdio) { |
| 976 | ret = -ENOMEM; |
| 977 | goto free; |
| 978 | } |
| 979 | |
| 980 | priv->mdio->name = "ethoc-mdio"; |
| 981 | snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d", |
| 982 | priv->mdio->name, pdev->id); |
| 983 | priv->mdio->read = ethoc_mdio_read; |
| 984 | priv->mdio->write = ethoc_mdio_write; |
| 985 | priv->mdio->reset = ethoc_mdio_reset; |
| 986 | priv->mdio->priv = priv; |
| 987 | |
| 988 | priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); |
| 989 | if (!priv->mdio->irq) { |
| 990 | ret = -ENOMEM; |
| 991 | goto free_mdio; |
| 992 | } |
| 993 | |
| 994 | for (phy = 0; phy < PHY_MAX_ADDR; phy++) |
| 995 | priv->mdio->irq[phy] = PHY_POLL; |
| 996 | |
| 997 | ret = mdiobus_register(priv->mdio); |
| 998 | if (ret) { |
| 999 | dev_err(&netdev->dev, "failed to register MDIO bus\n"); |
| 1000 | goto free_mdio; |
| 1001 | } |
| 1002 | |
| 1003 | ret = ethoc_mdio_probe(netdev); |
| 1004 | if (ret) { |
| 1005 | dev_err(&netdev->dev, "failed to probe MDIO bus\n"); |
| 1006 | goto error; |
| 1007 | } |
| 1008 | |
| 1009 | ether_setup(netdev); |
| 1010 | |
| 1011 | /* setup the net_device structure */ |
| 1012 | netdev->netdev_ops = ðoc_netdev_ops; |
| 1013 | netdev->watchdog_timeo = ETHOC_TIMEOUT; |
| 1014 | netdev->features |= 0; |
| 1015 | |
| 1016 | /* setup NAPI */ |
| 1017 | memset(&priv->napi, 0, sizeof(priv->napi)); |
| 1018 | netif_napi_add(netdev, &priv->napi, ethoc_poll, 64); |
| 1019 | |
| 1020 | spin_lock_init(&priv->rx_lock); |
| 1021 | spin_lock_init(&priv->lock); |
| 1022 | |
| 1023 | ret = register_netdev(netdev); |
| 1024 | if (ret < 0) { |
| 1025 | dev_err(&netdev->dev, "failed to register interface\n"); |
| 1026 | goto error; |
| 1027 | } |
| 1028 | |
| 1029 | goto out; |
| 1030 | |
| 1031 | error: |
| 1032 | mdiobus_unregister(priv->mdio); |
| 1033 | free_mdio: |
| 1034 | kfree(priv->mdio->irq); |
| 1035 | mdiobus_free(priv->mdio); |
| 1036 | free: |
| 1037 | free_netdev(netdev); |
| 1038 | out: |
| 1039 | return ret; |
| 1040 | } |
| 1041 | |
| 1042 | /** |
| 1043 | * ethoc_remove() - shutdown OpenCores ethernet MAC |
| 1044 | * @pdev: platform device |
| 1045 | */ |
| 1046 | static int ethoc_remove(struct platform_device *pdev) |
| 1047 | { |
| 1048 | struct net_device *netdev = platform_get_drvdata(pdev); |
| 1049 | struct ethoc *priv = netdev_priv(netdev); |
| 1050 | |
| 1051 | platform_set_drvdata(pdev, NULL); |
| 1052 | |
| 1053 | if (netdev) { |
| 1054 | phy_disconnect(priv->phy); |
| 1055 | priv->phy = NULL; |
| 1056 | |
| 1057 | if (priv->mdio) { |
| 1058 | mdiobus_unregister(priv->mdio); |
| 1059 | kfree(priv->mdio->irq); |
| 1060 | mdiobus_free(priv->mdio); |
| 1061 | } |
| 1062 | |
| 1063 | unregister_netdev(netdev); |
| 1064 | free_netdev(netdev); |
| 1065 | } |
| 1066 | |
| 1067 | return 0; |
| 1068 | } |
| 1069 | |
| 1070 | #ifdef CONFIG_PM |
| 1071 | static int ethoc_suspend(struct platform_device *pdev, pm_message_t state) |
| 1072 | { |
| 1073 | return -ENOSYS; |
| 1074 | } |
| 1075 | |
| 1076 | static int ethoc_resume(struct platform_device *pdev) |
| 1077 | { |
| 1078 | return -ENOSYS; |
| 1079 | } |
| 1080 | #else |
| 1081 | # define ethoc_suspend NULL |
| 1082 | # define ethoc_resume NULL |
| 1083 | #endif |
| 1084 | |
| 1085 | static struct platform_driver ethoc_driver = { |
| 1086 | .probe = ethoc_probe, |
| 1087 | .remove = ethoc_remove, |
| 1088 | .suspend = ethoc_suspend, |
| 1089 | .resume = ethoc_resume, |
| 1090 | .driver = { |
| 1091 | .name = "ethoc", |
| 1092 | }, |
| 1093 | }; |
| 1094 | |
| 1095 | static int __init ethoc_init(void) |
| 1096 | { |
| 1097 | return platform_driver_register(ðoc_driver); |
| 1098 | } |
| 1099 | |
| 1100 | static void __exit ethoc_exit(void) |
| 1101 | { |
| 1102 | platform_driver_unregister(ðoc_driver); |
| 1103 | } |
| 1104 | |
| 1105 | module_init(ethoc_init); |
| 1106 | module_exit(ethoc_exit); |
| 1107 | |
| 1108 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); |
| 1109 | MODULE_DESCRIPTION("OpenCores Ethernet MAC driver"); |
| 1110 | MODULE_LICENSE("GPL v2"); |
| 1111 | |