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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / ti / cpsw.c
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1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
27#include <linux/net_tstamp.h>
28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
31#include <linux/pm_runtime.h>
32#include <linux/of.h>
33#include <linux/of_net.h>
34#include <linux/of_device.h>
35#include <linux/if_vlan.h>
36
37#include <linux/platform_data/cpsw.h>
38
39#include "cpsw_ale.h"
40#include "cpts.h"
41#include "davinci_cpdma.h"
42
43#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
44 NETIF_MSG_DRV | NETIF_MSG_LINK | \
45 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
46 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
47 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
49 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
50 NETIF_MSG_RX_STATUS)
51
52#define cpsw_info(priv, type, format, ...) \
53do { \
54 if (netif_msg_##type(priv) && net_ratelimit()) \
55 dev_info(priv->dev, format, ## __VA_ARGS__); \
56} while (0)
57
58#define cpsw_err(priv, type, format, ...) \
59do { \
60 if (netif_msg_##type(priv) && net_ratelimit()) \
61 dev_err(priv->dev, format, ## __VA_ARGS__); \
62} while (0)
63
64#define cpsw_dbg(priv, type, format, ...) \
65do { \
66 if (netif_msg_##type(priv) && net_ratelimit()) \
67 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
68} while (0)
69
70#define cpsw_notice(priv, type, format, ...) \
71do { \
72 if (netif_msg_##type(priv) && net_ratelimit()) \
73 dev_notice(priv->dev, format, ## __VA_ARGS__); \
74} while (0)
75
76#define ALE_ALL_PORTS 0x7
77
78#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
79#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
80#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
81
82#define CPSW_VERSION_1 0x19010a
83#define CPSW_VERSION_2 0x19010c
84
85#define HOST_PORT_NUM 0
86#define SLIVER_SIZE 0x40
87
88#define CPSW1_HOST_PORT_OFFSET 0x028
89#define CPSW1_SLAVE_OFFSET 0x050
90#define CPSW1_SLAVE_SIZE 0x040
91#define CPSW1_CPDMA_OFFSET 0x100
92#define CPSW1_STATERAM_OFFSET 0x200
93#define CPSW1_CPTS_OFFSET 0x500
94#define CPSW1_ALE_OFFSET 0x600
95#define CPSW1_SLIVER_OFFSET 0x700
96
97#define CPSW2_HOST_PORT_OFFSET 0x108
98#define CPSW2_SLAVE_OFFSET 0x200
99#define CPSW2_SLAVE_SIZE 0x100
100#define CPSW2_CPDMA_OFFSET 0x800
101#define CPSW2_STATERAM_OFFSET 0xa00
102#define CPSW2_CPTS_OFFSET 0xc00
103#define CPSW2_ALE_OFFSET 0xd00
104#define CPSW2_SLIVER_OFFSET 0xd80
105#define CPSW2_BD_OFFSET 0x2000
106
107#define CPDMA_RXTHRESH 0x0c0
108#define CPDMA_RXFREE 0x0e0
109#define CPDMA_TXHDP 0x00
110#define CPDMA_RXHDP 0x20
111#define CPDMA_TXCP 0x40
112#define CPDMA_RXCP 0x60
113
114#define CPSW_POLL_WEIGHT 64
115#define CPSW_MIN_PACKET_SIZE 60
116#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
117
118#define RX_PRIORITY_MAPPING 0x76543210
119#define TX_PRIORITY_MAPPING 0x33221100
120#define CPDMA_TX_PRIORITY_MAP 0x76543210
121
122#define CPSW_VLAN_AWARE BIT(1)
123#define CPSW_ALE_VLAN_AWARE 1
124
125#define CPSW_FIFO_NORMAL_MODE (0 << 15)
126#define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
127#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
128
129#define CPSW_INTPACEEN (0x3f << 16)
130#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
131#define CPSW_CMINTMAX_CNT 63
132#define CPSW_CMINTMIN_CNT 2
133#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
134#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
135
136#define cpsw_enable_irq(priv) \
137 do { \
138 u32 i; \
139 for (i = 0; i < priv->num_irqs; i++) \
140 enable_irq(priv->irqs_table[i]); \
141 } while (0);
142#define cpsw_disable_irq(priv) \
143 do { \
144 u32 i; \
145 for (i = 0; i < priv->num_irqs; i++) \
146 disable_irq_nosync(priv->irqs_table[i]); \
147 } while (0);
148
149#define cpsw_slave_index(priv) \
150 ((priv->data.dual_emac) ? priv->emac_port : \
151 priv->data.active_slave)
152
153static int debug_level;
154module_param(debug_level, int, 0);
155MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
156
157static int ale_ageout = 10;
158module_param(ale_ageout, int, 0);
159MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
160
161static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
162module_param(rx_packet_max, int, 0);
163MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
164
165struct cpsw_wr_regs {
166 u32 id_ver;
167 u32 soft_reset;
168 u32 control;
169 u32 int_control;
170 u32 rx_thresh_en;
171 u32 rx_en;
172 u32 tx_en;
173 u32 misc_en;
174 u32 mem_allign1[8];
175 u32 rx_thresh_stat;
176 u32 rx_stat;
177 u32 tx_stat;
178 u32 misc_stat;
179 u32 mem_allign2[8];
180 u32 rx_imax;
181 u32 tx_imax;
182
183};
184
185struct cpsw_ss_regs {
186 u32 id_ver;
187 u32 control;
188 u32 soft_reset;
189 u32 stat_port_en;
190 u32 ptype;
191 u32 soft_idle;
192 u32 thru_rate;
193 u32 gap_thresh;
194 u32 tx_start_wds;
195 u32 flow_control;
196 u32 vlan_ltype;
197 u32 ts_ltype;
198 u32 dlr_ltype;
199};
200
201/* CPSW_PORT_V1 */
202#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
203#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
204#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
205#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
206#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
207#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
208#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
209#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
210
211/* CPSW_PORT_V2 */
212#define CPSW2_CONTROL 0x00 /* Control Register */
213#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
214#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
215#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
216#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
217#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
218#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
219
220/* CPSW_PORT_V1 and V2 */
221#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
222#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
223#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
224
225/* CPSW_PORT_V2 only */
226#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
227#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
228#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
229#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
230#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
231#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
232#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
233#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
234
235/* Bit definitions for the CPSW2_CONTROL register */
236#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
237#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
238#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
239#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
240#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
241#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
242#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
243#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
244#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
245#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
246#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
247#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
248#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
249#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
250#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
251#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
252
253#define CTRL_TS_BITS \
254 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
255 TS_ANNEX_D_EN | TS_LTYPE1_EN)
256
257#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
258#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
259#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
260
261/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
262#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
263#define TS_SEQ_ID_OFFSET_MASK (0x3f)
264#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
265#define TS_MSG_TYPE_EN_MASK (0xffff)
266
267/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
268#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
269
270/* Bit definitions for the CPSW1_TS_CTL register */
271#define CPSW_V1_TS_RX_EN BIT(0)
272#define CPSW_V1_TS_TX_EN BIT(4)
273#define CPSW_V1_MSG_TYPE_OFS 16
274
275/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
276#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
277
278struct cpsw_host_regs {
279 u32 max_blks;
280 u32 blk_cnt;
281 u32 tx_in_ctl;
282 u32 port_vlan;
283 u32 tx_pri_map;
284 u32 cpdma_tx_pri_map;
285 u32 cpdma_rx_chan_map;
286};
287
288struct cpsw_sliver_regs {
289 u32 id_ver;
290 u32 mac_control;
291 u32 mac_status;
292 u32 soft_reset;
293 u32 rx_maxlen;
294 u32 __reserved_0;
295 u32 rx_pause;
296 u32 tx_pause;
297 u32 __reserved_1;
298 u32 rx_pri_map;
299};
300
301struct cpsw_slave {
302 void __iomem *regs;
303 struct cpsw_sliver_regs __iomem *sliver;
304 int slave_num;
305 u32 mac_control;
306 struct cpsw_slave_data *data;
307 struct phy_device *phy;
308 struct net_device *ndev;
309 u32 port_vlan;
310 u32 open_stat;
311};
312
313static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
314{
315 return __raw_readl(slave->regs + offset);
316}
317
318static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
319{
320 __raw_writel(val, slave->regs + offset);
321}
322
323struct cpsw_priv {
324 spinlock_t lock;
325 struct platform_device *pdev;
326 struct net_device *ndev;
327 struct resource *cpsw_res;
328 struct resource *cpsw_wr_res;
329 struct napi_struct napi;
330 struct device *dev;
331 struct cpsw_platform_data data;
332 struct cpsw_ss_regs __iomem *regs;
333 struct cpsw_wr_regs __iomem *wr_regs;
334 struct cpsw_host_regs __iomem *host_port_regs;
335 u32 msg_enable;
336 u32 version;
337 u32 coal_intvl;
338 u32 bus_freq_mhz;
339 struct net_device_stats stats;
340 int rx_packet_max;
341 int host_port;
342 struct clk *clk;
343 u8 mac_addr[ETH_ALEN];
344 struct cpsw_slave *slaves;
345 struct cpdma_ctlr *dma;
346 struct cpdma_chan *txch, *rxch;
347 struct cpsw_ale *ale;
348 /* snapshot of IRQ numbers */
349 u32 irqs_table[4];
350 u32 num_irqs;
351 bool irq_enabled;
352 struct cpts *cpts;
353 u32 emac_port;
354};
355
356#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
357#define for_each_slave(priv, func, arg...) \
358 do { \
359 struct cpsw_slave *slave; \
360 int n; \
361 if (priv->data.dual_emac) \
362 (func)((priv)->slaves + priv->emac_port, ##arg);\
363 else \
364 for (n = (priv)->data.slaves, \
365 slave = (priv)->slaves; \
366 n; n--) \
367 (func)(slave++, ##arg); \
368 } while (0)
369#define cpsw_get_slave_ndev(priv, __slave_no__) \
370 (priv->slaves[__slave_no__].ndev)
371#define cpsw_get_slave_priv(priv, __slave_no__) \
372 ((priv->slaves[__slave_no__].ndev) ? \
373 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
374
375#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
376 do { \
377 if (!priv->data.dual_emac) \
378 break; \
379 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
380 ndev = cpsw_get_slave_ndev(priv, 0); \
381 priv = netdev_priv(ndev); \
382 skb->dev = ndev; \
383 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
384 ndev = cpsw_get_slave_ndev(priv, 1); \
385 priv = netdev_priv(ndev); \
386 skb->dev = ndev; \
387 } \
388 } while (0)
389#define cpsw_add_mcast(priv, addr) \
390 do { \
391 if (priv->data.dual_emac) { \
392 struct cpsw_slave *slave = priv->slaves + \
393 priv->emac_port; \
394 int slave_port = cpsw_get_slave_port(priv, \
395 slave->slave_num); \
396 cpsw_ale_add_mcast(priv->ale, addr, \
397 1 << slave_port | 1 << priv->host_port, \
398 ALE_VLAN, slave->port_vlan, 0); \
399 } else { \
400 cpsw_ale_add_mcast(priv->ale, addr, \
401 ALE_ALL_PORTS << priv->host_port, \
402 0, 0, 0); \
403 } \
404 } while (0)
405
406static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
407{
408 if (priv->host_port == 0)
409 return slave_num + 1;
410 else
411 return slave_num;
412}
413
414static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
415{
416 struct cpsw_priv *priv = netdev_priv(ndev);
417
418 if (ndev->flags & IFF_PROMISC) {
419 /* Enable promiscuous mode */
420 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
421 return;
422 }
423
424 /* Clear all mcast from ALE */
425 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
426
427 if (!netdev_mc_empty(ndev)) {
428 struct netdev_hw_addr *ha;
429
430 /* program multicast address list into ALE register */
431 netdev_for_each_mc_addr(ha, ndev) {
432 cpsw_add_mcast(priv, (u8 *)ha->addr);
433 }
434 }
435}
436
437static void cpsw_intr_enable(struct cpsw_priv *priv)
438{
439 __raw_writel(0xFF, &priv->wr_regs->tx_en);
440 __raw_writel(0xFF, &priv->wr_regs->rx_en);
441
442 cpdma_ctlr_int_ctrl(priv->dma, true);
443 return;
444}
445
446static void cpsw_intr_disable(struct cpsw_priv *priv)
447{
448 __raw_writel(0, &priv->wr_regs->tx_en);
449 __raw_writel(0, &priv->wr_regs->rx_en);
450
451 cpdma_ctlr_int_ctrl(priv->dma, false);
452 return;
453}
454
455void cpsw_tx_handler(void *token, int len, int status)
456{
457 struct sk_buff *skb = token;
458 struct net_device *ndev = skb->dev;
459 struct cpsw_priv *priv = netdev_priv(ndev);
460
461 /* Check whether the queue is stopped due to stalled tx dma, if the
462 * queue is stopped then start the queue as we have free desc for tx
463 */
464 if (unlikely(netif_queue_stopped(ndev)))
465 netif_wake_queue(ndev);
466 cpts_tx_timestamp(priv->cpts, skb);
467 priv->stats.tx_packets++;
468 priv->stats.tx_bytes += len;
469 dev_kfree_skb_any(skb);
470}
471
472void cpsw_rx_handler(void *token, int len, int status)
473{
474 struct sk_buff *skb = token;
475 struct sk_buff *new_skb;
476 struct net_device *ndev = skb->dev;
477 struct cpsw_priv *priv = netdev_priv(ndev);
478 int ret = 0;
479
480 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
481
482 if (unlikely(status < 0)) {
483 /* the interface is going down, skbs are purged */
484 dev_kfree_skb_any(skb);
485 return;
486 }
487
488 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
489 if (new_skb) {
490 skb_put(skb, len);
491 cpts_rx_timestamp(priv->cpts, skb);
492 skb->protocol = eth_type_trans(skb, ndev);
493 netif_receive_skb(skb);
494 priv->stats.rx_bytes += len;
495 priv->stats.rx_packets++;
496 } else {
497 priv->stats.rx_dropped++;
498 new_skb = skb;
499 }
500
501 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
502 skb_tailroom(new_skb), 0);
503 if (WARN_ON(ret < 0))
504 dev_kfree_skb_any(new_skb);
505}
506
507static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
508{
509 struct cpsw_priv *priv = dev_id;
510 u32 rx, tx, rx_thresh;
511
512 rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat);
513 rx = __raw_readl(&priv->wr_regs->rx_stat);
514 tx = __raw_readl(&priv->wr_regs->tx_stat);
515 if (!rx_thresh && !rx && !tx)
516 return IRQ_NONE;
517
518 cpsw_intr_disable(priv);
519 if (priv->irq_enabled == true) {
520 cpsw_disable_irq(priv);
521 priv->irq_enabled = false;
522 }
523
524 if (netif_running(priv->ndev)) {
525 napi_schedule(&priv->napi);
526 return IRQ_HANDLED;
527 }
528
529 priv = cpsw_get_slave_priv(priv, 1);
530 if (!priv)
531 return IRQ_NONE;
532
533 if (netif_running(priv->ndev)) {
534 napi_schedule(&priv->napi);
535 return IRQ_HANDLED;
536 }
537 return IRQ_NONE;
538}
539
540static int cpsw_poll(struct napi_struct *napi, int budget)
541{
542 struct cpsw_priv *priv = napi_to_priv(napi);
543 int num_tx, num_rx;
544
545 num_tx = cpdma_chan_process(priv->txch, 128);
546 if (num_tx)
547 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
548
549 num_rx = cpdma_chan_process(priv->rxch, budget);
550 if (num_rx < budget) {
551 struct cpsw_priv *prim_cpsw;
552
553 napi_complete(napi);
554 cpsw_intr_enable(priv);
555 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
556 prim_cpsw = cpsw_get_slave_priv(priv, 0);
557 if (prim_cpsw->irq_enabled == false) {
558 prim_cpsw->irq_enabled = true;
559 cpsw_enable_irq(priv);
560 }
561 }
562
563 if (num_rx || num_tx)
564 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
565 num_rx, num_tx);
566
567 return num_rx;
568}
569
570static inline void soft_reset(const char *module, void __iomem *reg)
571{
572 unsigned long timeout = jiffies + HZ;
573
574 __raw_writel(1, reg);
575 do {
576 cpu_relax();
577 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
578
579 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
580}
581
582#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
583 ((mac)[2] << 16) | ((mac)[3] << 24))
584#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
585
586static void cpsw_set_slave_mac(struct cpsw_slave *slave,
587 struct cpsw_priv *priv)
588{
589 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
590 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
591}
592
593static void _cpsw_adjust_link(struct cpsw_slave *slave,
594 struct cpsw_priv *priv, bool *link)
595{
596 struct phy_device *phy = slave->phy;
597 u32 mac_control = 0;
598 u32 slave_port;
599
600 if (!phy)
601 return;
602
603 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
604
605 if (phy->link) {
606 mac_control = priv->data.mac_control;
607
608 /* enable forwarding */
609 cpsw_ale_control_set(priv->ale, slave_port,
610 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
611
612 if (phy->speed == 1000)
613 mac_control |= BIT(7); /* GIGABITEN */
614 if (phy->duplex)
615 mac_control |= BIT(0); /* FULLDUPLEXEN */
616
617 /* set speed_in input in case RMII mode is used in 100Mbps */
618 if (phy->speed == 100)
619 mac_control |= BIT(15);
620
621 *link = true;
622 } else {
623 mac_control = 0;
624 /* disable forwarding */
625 cpsw_ale_control_set(priv->ale, slave_port,
626 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
627 }
628
629 if (mac_control != slave->mac_control) {
630 phy_print_status(phy);
631 __raw_writel(mac_control, &slave->sliver->mac_control);
632 }
633
634 slave->mac_control = mac_control;
635}
636
637static void cpsw_adjust_link(struct net_device *ndev)
638{
639 struct cpsw_priv *priv = netdev_priv(ndev);
640 bool link = false;
641
642 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
643
644 if (link) {
645 netif_carrier_on(ndev);
646 if (netif_running(ndev))
647 netif_wake_queue(ndev);
648 } else {
649 netif_carrier_off(ndev);
650 netif_stop_queue(ndev);
651 }
652}
653
654static int cpsw_get_coalesce(struct net_device *ndev,
655 struct ethtool_coalesce *coal)
656{
657 struct cpsw_priv *priv = netdev_priv(ndev);
658
659 coal->rx_coalesce_usecs = priv->coal_intvl;
660 return 0;
661}
662
663static int cpsw_set_coalesce(struct net_device *ndev,
664 struct ethtool_coalesce *coal)
665{
666 struct cpsw_priv *priv = netdev_priv(ndev);
667 u32 int_ctrl;
668 u32 num_interrupts = 0;
669 u32 prescale = 0;
670 u32 addnl_dvdr = 1;
671 u32 coal_intvl = 0;
672
673 if (!coal->rx_coalesce_usecs)
674 return -EINVAL;
675
676 coal_intvl = coal->rx_coalesce_usecs;
677
678 int_ctrl = readl(&priv->wr_regs->int_control);
679 prescale = priv->bus_freq_mhz * 4;
680
681 if (coal_intvl < CPSW_CMINTMIN_INTVL)
682 coal_intvl = CPSW_CMINTMIN_INTVL;
683
684 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
685 /* Interrupt pacer works with 4us Pulse, we can
686 * throttle further by dilating the 4us pulse.
687 */
688 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
689
690 if (addnl_dvdr > 1) {
691 prescale *= addnl_dvdr;
692 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
693 coal_intvl = (CPSW_CMINTMAX_INTVL
694 * addnl_dvdr);
695 } else {
696 addnl_dvdr = 1;
697 coal_intvl = CPSW_CMINTMAX_INTVL;
698 }
699 }
700
701 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
702 writel(num_interrupts, &priv->wr_regs->rx_imax);
703 writel(num_interrupts, &priv->wr_regs->tx_imax);
704
705 int_ctrl |= CPSW_INTPACEEN;
706 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
707 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
708 writel(int_ctrl, &priv->wr_regs->int_control);
709
710 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
711 if (priv->data.dual_emac) {
712 int i;
713
714 for (i = 0; i < priv->data.slaves; i++) {
715 priv = netdev_priv(priv->slaves[i].ndev);
716 priv->coal_intvl = coal_intvl;
717 }
718 } else {
719 priv->coal_intvl = coal_intvl;
720 }
721
722 return 0;
723}
724
725static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
726{
727 static char *leader = "........................................";
728
729 if (!val)
730 return 0;
731 else
732 return snprintf(buf, maxlen, "%s %s %10d\n", name,
733 leader + strlen(name), val);
734}
735
736static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
737{
738 u32 i;
739 u32 usage_count = 0;
740
741 if (!priv->data.dual_emac)
742 return 0;
743
744 for (i = 0; i < priv->data.slaves; i++)
745 if (priv->slaves[i].open_stat)
746 usage_count++;
747
748 return usage_count;
749}
750
751static inline int cpsw_tx_packet_submit(struct net_device *ndev,
752 struct cpsw_priv *priv, struct sk_buff *skb)
753{
754 if (!priv->data.dual_emac)
755 return cpdma_chan_submit(priv->txch, skb, skb->data,
756 skb->len, 0);
757
758 if (ndev == cpsw_get_slave_ndev(priv, 0))
759 return cpdma_chan_submit(priv->txch, skb, skb->data,
760 skb->len, 1);
761 else
762 return cpdma_chan_submit(priv->txch, skb, skb->data,
763 skb->len, 2);
764}
765
766static inline void cpsw_add_dual_emac_def_ale_entries(
767 struct cpsw_priv *priv, struct cpsw_slave *slave,
768 u32 slave_port)
769{
770 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
771
772 if (priv->version == CPSW_VERSION_1)
773 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
774 else
775 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
776 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
777 port_mask, port_mask, 0);
778 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
779 port_mask, ALE_VLAN, slave->port_vlan, 0);
780 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
781 priv->host_port, ALE_VLAN, slave->port_vlan);
782}
783
784static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
785{
786 char name[32];
787 u32 slave_port;
788
789 sprintf(name, "slave-%d", slave->slave_num);
790
791 soft_reset(name, &slave->sliver->soft_reset);
792
793 /* setup priority mapping */
794 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
795
796 switch (priv->version) {
797 case CPSW_VERSION_1:
798 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
799 break;
800 case CPSW_VERSION_2:
801 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
802 break;
803 }
804
805 /* setup max packet size, and mac address */
806 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
807 cpsw_set_slave_mac(slave, priv);
808
809 slave->mac_control = 0; /* no link yet */
810
811 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
812
813 if (priv->data.dual_emac)
814 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
815 else
816 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
817 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
818
819 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
820 &cpsw_adjust_link, slave->data->phy_if);
821 if (IS_ERR(slave->phy)) {
822 dev_err(priv->dev, "phy %s not found on slave %d\n",
823 slave->data->phy_id, slave->slave_num);
824 slave->phy = NULL;
825 } else {
826 dev_info(priv->dev, "phy found : id is : 0x%x\n",
827 slave->phy->phy_id);
828 phy_start(slave->phy);
829 }
830}
831
832static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
833{
834 const int vlan = priv->data.default_vlan;
835 const int port = priv->host_port;
836 u32 reg;
837 int i;
838
839 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
840 CPSW2_PORT_VLAN;
841
842 writel(vlan, &priv->host_port_regs->port_vlan);
843
844 for (i = 0; i < priv->data.slaves; i++)
845 slave_write(priv->slaves + i, vlan, reg);
846
847 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
848 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
849 (ALE_PORT_1 | ALE_PORT_2) << port);
850}
851
852static void cpsw_init_host_port(struct cpsw_priv *priv)
853{
854 u32 control_reg;
855 u32 fifo_mode;
856
857 /* soft reset the controller and initialize ale */
858 soft_reset("cpsw", &priv->regs->soft_reset);
859 cpsw_ale_start(priv->ale);
860
861 /* switch to vlan unaware mode */
862 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
863 CPSW_ALE_VLAN_AWARE);
864 control_reg = readl(&priv->regs->control);
865 control_reg |= CPSW_VLAN_AWARE;
866 writel(control_reg, &priv->regs->control);
867 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
868 CPSW_FIFO_NORMAL_MODE;
869 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
870
871 /* setup host port priority mapping */
872 __raw_writel(CPDMA_TX_PRIORITY_MAP,
873 &priv->host_port_regs->cpdma_tx_pri_map);
874 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
875
876 cpsw_ale_control_set(priv->ale, priv->host_port,
877 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
878
879 if (!priv->data.dual_emac) {
880 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
881 0, 0);
882 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
883 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
884 }
885}
886
887static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
888{
889 if (!slave->phy)
890 return;
891 phy_stop(slave->phy);
892 phy_disconnect(slave->phy);
893 slave->phy = NULL;
894}
895
896static int cpsw_ndo_open(struct net_device *ndev)
897{
898 struct cpsw_priv *priv = netdev_priv(ndev);
899 struct cpsw_priv *prim_cpsw;
900 int i, ret;
901 u32 reg;
902
903 if (!cpsw_common_res_usage_state(priv))
904 cpsw_intr_disable(priv);
905 netif_carrier_off(ndev);
906
907 pm_runtime_get_sync(&priv->pdev->dev);
908
909 reg = priv->version;
910
911 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
912 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
913 CPSW_RTL_VERSION(reg));
914
915 /* initialize host and slave ports */
916 if (!cpsw_common_res_usage_state(priv))
917 cpsw_init_host_port(priv);
918 for_each_slave(priv, cpsw_slave_open, priv);
919
920 /* Add default VLAN */
921 if (!priv->data.dual_emac)
922 cpsw_add_default_vlan(priv);
923
924 if (!cpsw_common_res_usage_state(priv)) {
925 /* setup tx dma to fixed prio and zero offset */
926 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
927 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
928
929 /* disable priority elevation */
930 __raw_writel(0, &priv->regs->ptype);
931
932 /* enable statistics collection only on all ports */
933 __raw_writel(0x7, &priv->regs->stat_port_en);
934
935 if (WARN_ON(!priv->data.rx_descs))
936 priv->data.rx_descs = 128;
937
938 for (i = 0; i < priv->data.rx_descs; i++) {
939 struct sk_buff *skb;
940
941 ret = -ENOMEM;
942 skb = __netdev_alloc_skb_ip_align(priv->ndev,
943 priv->rx_packet_max, GFP_KERNEL);
944 if (!skb)
945 goto err_cleanup;
946 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
947 skb_tailroom(skb), 0);
948 if (ret < 0) {
949 kfree_skb(skb);
950 goto err_cleanup;
951 }
952 }
953 /* continue even if we didn't manage to submit all
954 * receive descs
955 */
956 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
957 }
958
959 /* Enable Interrupt pacing if configured */
960 if (priv->coal_intvl != 0) {
961 struct ethtool_coalesce coal;
962
963 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
964 cpsw_set_coalesce(ndev, &coal);
965 }
966
967 prim_cpsw = cpsw_get_slave_priv(priv, 0);
968 if (prim_cpsw->irq_enabled == false) {
969 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
970 prim_cpsw->irq_enabled = true;
971 cpsw_enable_irq(prim_cpsw);
972 }
973 }
974
975 cpdma_ctlr_start(priv->dma);
976 cpsw_intr_enable(priv);
977 napi_enable(&priv->napi);
978 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
979 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
980
981 if (priv->data.dual_emac)
982 priv->slaves[priv->emac_port].open_stat = true;
983 return 0;
984
985err_cleanup:
986 cpdma_ctlr_stop(priv->dma);
987 for_each_slave(priv, cpsw_slave_stop, priv);
988 pm_runtime_put_sync(&priv->pdev->dev);
989 netif_carrier_off(priv->ndev);
990 return ret;
991}
992
993static int cpsw_ndo_stop(struct net_device *ndev)
994{
995 struct cpsw_priv *priv = netdev_priv(ndev);
996
997 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
998 netif_stop_queue(priv->ndev);
999 napi_disable(&priv->napi);
1000 netif_carrier_off(priv->ndev);
1001
1002 if (cpsw_common_res_usage_state(priv) <= 1) {
1003 cpsw_intr_disable(priv);
1004 cpdma_ctlr_int_ctrl(priv->dma, false);
1005 cpdma_ctlr_stop(priv->dma);
1006 cpsw_ale_stop(priv->ale);
1007 }
1008 for_each_slave(priv, cpsw_slave_stop, priv);
1009 pm_runtime_put_sync(&priv->pdev->dev);
1010 if (priv->data.dual_emac)
1011 priv->slaves[priv->emac_port].open_stat = false;
1012 return 0;
1013}
1014
1015static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1016 struct net_device *ndev)
1017{
1018 struct cpsw_priv *priv = netdev_priv(ndev);
1019 int ret;
1020
1021 ndev->trans_start = jiffies;
1022
1023 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1024 cpsw_err(priv, tx_err, "packet pad failed\n");
1025 priv->stats.tx_dropped++;
1026 return NETDEV_TX_OK;
1027 }
1028
1029 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1030 priv->cpts->tx_enable)
1031 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1032
1033 skb_tx_timestamp(skb);
1034
1035 ret = cpsw_tx_packet_submit(ndev, priv, skb);
1036 if (unlikely(ret != 0)) {
1037 cpsw_err(priv, tx_err, "desc submit failed\n");
1038 goto fail;
1039 }
1040
1041 /* If there is no more tx desc left free then we need to
1042 * tell the kernel to stop sending us tx frames.
1043 */
1044 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1045 netif_stop_queue(ndev);
1046
1047 return NETDEV_TX_OK;
1048fail:
1049 priv->stats.tx_dropped++;
1050 netif_stop_queue(ndev);
1051 return NETDEV_TX_BUSY;
1052}
1053
1054static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
1055{
1056 /*
1057 * The switch cannot operate in promiscuous mode without substantial
1058 * headache. For promiscuous mode to work, we would need to put the
1059 * ALE in bypass mode and route all traffic to the host port.
1060 * Subsequently, the host will need to operate as a "bridge", learn,
1061 * and flood as needed. For now, we simply complain here and
1062 * do nothing about it :-)
1063 */
1064 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
1065 dev_err(&ndev->dev, "promiscuity ignored!\n");
1066
1067 /*
1068 * The switch cannot filter multicast traffic unless it is configured
1069 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
1070 * whole bunch of additional logic that this driver does not implement
1071 * at present.
1072 */
1073 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
1074 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
1075}
1076
1077#ifdef CONFIG_TI_CPTS
1078
1079static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1080{
1081 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1082 u32 ts_en, seq_id;
1083
1084 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1085 slave_write(slave, 0, CPSW1_TS_CTL);
1086 return;
1087 }
1088
1089 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1090 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1091
1092 if (priv->cpts->tx_enable)
1093 ts_en |= CPSW_V1_TS_TX_EN;
1094
1095 if (priv->cpts->rx_enable)
1096 ts_en |= CPSW_V1_TS_RX_EN;
1097
1098 slave_write(slave, ts_en, CPSW1_TS_CTL);
1099 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1100}
1101
1102static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1103{
1104 struct cpsw_slave *slave;
1105 u32 ctrl, mtype;
1106
1107 if (priv->data.dual_emac)
1108 slave = &priv->slaves[priv->emac_port];
1109 else
1110 slave = &priv->slaves[priv->data.active_slave];
1111
1112 ctrl = slave_read(slave, CPSW2_CONTROL);
1113 ctrl &= ~CTRL_ALL_TS_MASK;
1114
1115 if (priv->cpts->tx_enable)
1116 ctrl |= CTRL_TX_TS_BITS;
1117
1118 if (priv->cpts->rx_enable)
1119 ctrl |= CTRL_RX_TS_BITS;
1120
1121 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1122
1123 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1124 slave_write(slave, ctrl, CPSW2_CONTROL);
1125 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1126}
1127
1128static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
1129{
1130 struct cpsw_priv *priv = netdev_priv(dev);
1131 struct cpts *cpts = priv->cpts;
1132 struct hwtstamp_config cfg;
1133
1134 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1135 return -EFAULT;
1136
1137 /* reserved for future extensions */
1138 if (cfg.flags)
1139 return -EINVAL;
1140
1141 switch (cfg.tx_type) {
1142 case HWTSTAMP_TX_OFF:
1143 cpts->tx_enable = 0;
1144 break;
1145 case HWTSTAMP_TX_ON:
1146 cpts->tx_enable = 1;
1147 break;
1148 default:
1149 return -ERANGE;
1150 }
1151
1152 switch (cfg.rx_filter) {
1153 case HWTSTAMP_FILTER_NONE:
1154 cpts->rx_enable = 0;
1155 break;
1156 case HWTSTAMP_FILTER_ALL:
1157 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1158 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1159 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1160 return -ERANGE;
1161 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1162 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1163 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1164 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1165 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1166 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1167 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1168 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1169 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1170 cpts->rx_enable = 1;
1171 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1172 break;
1173 default:
1174 return -ERANGE;
1175 }
1176
1177 switch (priv->version) {
1178 case CPSW_VERSION_1:
1179 cpsw_hwtstamp_v1(priv);
1180 break;
1181 case CPSW_VERSION_2:
1182 cpsw_hwtstamp_v2(priv);
1183 break;
1184 default:
1185 return -ENOTSUPP;
1186 }
1187
1188 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1189}
1190
1191#endif /*CONFIG_TI_CPTS*/
1192
1193static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1194{
1195 struct cpsw_priv *priv = netdev_priv(dev);
1196 struct mii_ioctl_data *data = if_mii(req);
1197 int slave_no = cpsw_slave_index(priv);
1198
1199 if (!netif_running(dev))
1200 return -EINVAL;
1201
1202 switch (cmd) {
1203#ifdef CONFIG_TI_CPTS
1204 case SIOCSHWTSTAMP:
1205 return cpsw_hwtstamp_ioctl(dev, req);
1206#endif
1207 case SIOCGMIIPHY:
1208 data->phy_id = priv->slaves[slave_no].phy->addr;
1209 break;
1210 default:
1211 return -ENOTSUPP;
1212 }
1213
1214 return 0;
1215}
1216
1217static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1218{
1219 struct cpsw_priv *priv = netdev_priv(ndev);
1220
1221 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1222 priv->stats.tx_errors++;
1223 cpsw_intr_disable(priv);
1224 cpdma_ctlr_int_ctrl(priv->dma, false);
1225 cpdma_chan_stop(priv->txch);
1226 cpdma_chan_start(priv->txch);
1227 cpdma_ctlr_int_ctrl(priv->dma, true);
1228 cpsw_intr_enable(priv);
1229 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1230 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1231
1232}
1233
1234static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1235{
1236 struct cpsw_priv *priv = netdev_priv(ndev);
1237 return &priv->stats;
1238}
1239
1240#ifdef CONFIG_NET_POLL_CONTROLLER
1241static void cpsw_ndo_poll_controller(struct net_device *ndev)
1242{
1243 struct cpsw_priv *priv = netdev_priv(ndev);
1244
1245 cpsw_intr_disable(priv);
1246 cpdma_ctlr_int_ctrl(priv->dma, false);
1247 cpsw_interrupt(ndev->irq, priv);
1248 cpdma_ctlr_int_ctrl(priv->dma, true);
1249 cpsw_intr_enable(priv);
1250 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1251 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1252
1253}
1254#endif
1255
1256static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1257 unsigned short vid)
1258{
1259 int ret;
1260
1261 ret = cpsw_ale_add_vlan(priv->ale, vid,
1262 ALE_ALL_PORTS << priv->host_port,
1263 0, ALE_ALL_PORTS << priv->host_port,
1264 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1265 if (ret != 0)
1266 return ret;
1267
1268 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1269 priv->host_port, ALE_VLAN, vid);
1270 if (ret != 0)
1271 goto clean_vid;
1272
1273 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1274 ALE_ALL_PORTS << priv->host_port,
1275 ALE_VLAN, vid, 0);
1276 if (ret != 0)
1277 goto clean_vlan_ucast;
1278 return 0;
1279
1280clean_vlan_ucast:
1281 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1282 priv->host_port, ALE_VLAN, vid);
1283clean_vid:
1284 cpsw_ale_del_vlan(priv->ale, vid, 0);
1285 return ret;
1286}
1287
1288static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1289 __be16 proto, u16 vid)
1290{
1291 struct cpsw_priv *priv = netdev_priv(ndev);
1292
1293 if (vid == priv->data.default_vlan)
1294 return 0;
1295
1296 if (priv->data.dual_emac) {
1297 /* In dual EMAC, reserved VLAN id should not be used for
1298 * creating VLAN interfaces as this can break the dual
1299 * EMAC port separation
1300 */
1301 int i;
1302
1303 for (i = 0; i < priv->data.slaves; i++) {
1304 if (vid == priv->slaves[i].port_vlan)
1305 return -EINVAL;
1306 }
1307 }
1308
1309 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1310 return cpsw_add_vlan_ale_entry(priv, vid);
1311}
1312
1313static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1314 __be16 proto, u16 vid)
1315{
1316 struct cpsw_priv *priv = netdev_priv(ndev);
1317 int ret;
1318
1319 if (vid == priv->data.default_vlan)
1320 return 0;
1321
1322 if (priv->data.dual_emac) {
1323 int i;
1324
1325 for (i = 0; i < priv->data.slaves; i++) {
1326 if (vid == priv->slaves[i].port_vlan)
1327 return -EINVAL;
1328 }
1329 }
1330
1331 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1332 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1333 if (ret != 0)
1334 return ret;
1335
1336 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1337 priv->host_port, ALE_VLAN, vid);
1338 if (ret != 0)
1339 return ret;
1340
1341 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1342 0, ALE_VLAN, vid);
1343}
1344
1345static const struct net_device_ops cpsw_netdev_ops = {
1346 .ndo_open = cpsw_ndo_open,
1347 .ndo_stop = cpsw_ndo_stop,
1348 .ndo_start_xmit = cpsw_ndo_start_xmit,
1349 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
1350 .ndo_do_ioctl = cpsw_ndo_ioctl,
1351 .ndo_validate_addr = eth_validate_addr,
1352 .ndo_change_mtu = eth_change_mtu,
1353 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1354 .ndo_get_stats = cpsw_ndo_get_stats,
1355 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1356#ifdef CONFIG_NET_POLL_CONTROLLER
1357 .ndo_poll_controller = cpsw_ndo_poll_controller,
1358#endif
1359 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1360 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1361};
1362
1363static void cpsw_get_drvinfo(struct net_device *ndev,
1364 struct ethtool_drvinfo *info)
1365{
1366 struct cpsw_priv *priv = netdev_priv(ndev);
1367
1368 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1369 strlcpy(info->version, "1.0", sizeof(info->version));
1370 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1371}
1372
1373static u32 cpsw_get_msglevel(struct net_device *ndev)
1374{
1375 struct cpsw_priv *priv = netdev_priv(ndev);
1376 return priv->msg_enable;
1377}
1378
1379static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1380{
1381 struct cpsw_priv *priv = netdev_priv(ndev);
1382 priv->msg_enable = value;
1383}
1384
1385static int cpsw_get_ts_info(struct net_device *ndev,
1386 struct ethtool_ts_info *info)
1387{
1388#ifdef CONFIG_TI_CPTS
1389 struct cpsw_priv *priv = netdev_priv(ndev);
1390
1391 info->so_timestamping =
1392 SOF_TIMESTAMPING_TX_HARDWARE |
1393 SOF_TIMESTAMPING_TX_SOFTWARE |
1394 SOF_TIMESTAMPING_RX_HARDWARE |
1395 SOF_TIMESTAMPING_RX_SOFTWARE |
1396 SOF_TIMESTAMPING_SOFTWARE |
1397 SOF_TIMESTAMPING_RAW_HARDWARE;
1398 info->phc_index = priv->cpts->phc_index;
1399 info->tx_types =
1400 (1 << HWTSTAMP_TX_OFF) |
1401 (1 << HWTSTAMP_TX_ON);
1402 info->rx_filters =
1403 (1 << HWTSTAMP_FILTER_NONE) |
1404 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1405#else
1406 info->so_timestamping =
1407 SOF_TIMESTAMPING_TX_SOFTWARE |
1408 SOF_TIMESTAMPING_RX_SOFTWARE |
1409 SOF_TIMESTAMPING_SOFTWARE;
1410 info->phc_index = -1;
1411 info->tx_types = 0;
1412 info->rx_filters = 0;
1413#endif
1414 return 0;
1415}
1416
1417static int cpsw_get_settings(struct net_device *ndev,
1418 struct ethtool_cmd *ecmd)
1419{
1420 struct cpsw_priv *priv = netdev_priv(ndev);
1421 int slave_no = cpsw_slave_index(priv);
1422
1423 if (priv->slaves[slave_no].phy)
1424 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1425 else
1426 return -EOPNOTSUPP;
1427}
1428
1429static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1430{
1431 struct cpsw_priv *priv = netdev_priv(ndev);
1432 int slave_no = cpsw_slave_index(priv);
1433
1434 if (priv->slaves[slave_no].phy)
1435 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1436 else
1437 return -EOPNOTSUPP;
1438}
1439
1440static const struct ethtool_ops cpsw_ethtool_ops = {
1441 .get_drvinfo = cpsw_get_drvinfo,
1442 .get_msglevel = cpsw_get_msglevel,
1443 .set_msglevel = cpsw_set_msglevel,
1444 .get_link = ethtool_op_get_link,
1445 .get_ts_info = cpsw_get_ts_info,
1446 .get_settings = cpsw_get_settings,
1447 .set_settings = cpsw_set_settings,
1448 .get_coalesce = cpsw_get_coalesce,
1449 .set_coalesce = cpsw_set_coalesce,
1450};
1451
1452static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1453 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1454{
1455 void __iomem *regs = priv->regs;
1456 int slave_num = slave->slave_num;
1457 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1458
1459 slave->data = data;
1460 slave->regs = regs + slave_reg_ofs;
1461 slave->sliver = regs + sliver_reg_ofs;
1462 slave->port_vlan = data->dual_emac_res_vlan;
1463}
1464
1465static int cpsw_probe_dt(struct cpsw_platform_data *data,
1466 struct platform_device *pdev)
1467{
1468 struct device_node *node = pdev->dev.of_node;
1469 struct device_node *slave_node;
1470 int i = 0, ret;
1471 u32 prop;
1472
1473 if (!node)
1474 return -EINVAL;
1475
1476 if (of_property_read_u32(node, "slaves", &prop)) {
1477 pr_err("Missing slaves property in the DT.\n");
1478 return -EINVAL;
1479 }
1480 data->slaves = prop;
1481
1482 if (of_property_read_u32(node, "active_slave", &prop)) {
1483 pr_err("Missing active_slave property in the DT.\n");
1484 ret = -EINVAL;
1485 goto error_ret;
1486 }
1487 data->active_slave = prop;
1488
1489 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1490 pr_err("Missing cpts_clock_mult property in the DT.\n");
1491 ret = -EINVAL;
1492 goto error_ret;
1493 }
1494 data->cpts_clock_mult = prop;
1495
1496 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1497 pr_err("Missing cpts_clock_shift property in the DT.\n");
1498 ret = -EINVAL;
1499 goto error_ret;
1500 }
1501 data->cpts_clock_shift = prop;
1502
1503 data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
1504 GFP_KERNEL);
1505 if (!data->slave_data)
1506 return -EINVAL;
1507
1508 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1509 pr_err("Missing cpdma_channels property in the DT.\n");
1510 ret = -EINVAL;
1511 goto error_ret;
1512 }
1513 data->channels = prop;
1514
1515 if (of_property_read_u32(node, "ale_entries", &prop)) {
1516 pr_err("Missing ale_entries property in the DT.\n");
1517 ret = -EINVAL;
1518 goto error_ret;
1519 }
1520 data->ale_entries = prop;
1521
1522 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1523 pr_err("Missing bd_ram_size property in the DT.\n");
1524 ret = -EINVAL;
1525 goto error_ret;
1526 }
1527 data->bd_ram_size = prop;
1528
1529 if (of_property_read_u32(node, "rx_descs", &prop)) {
1530 pr_err("Missing rx_descs property in the DT.\n");
1531 ret = -EINVAL;
1532 goto error_ret;
1533 }
1534 data->rx_descs = prop;
1535
1536 if (of_property_read_u32(node, "mac_control", &prop)) {
1537 pr_err("Missing mac_control property in the DT.\n");
1538 ret = -EINVAL;
1539 goto error_ret;
1540 }
1541 data->mac_control = prop;
1542
1543 if (!of_property_read_u32(node, "dual_emac", &prop))
1544 data->dual_emac = prop;
1545
1546 /*
1547 * Populate all the child nodes here...
1548 */
1549 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1550 /* We do not want to force this, as in some cases may not have child */
1551 if (ret)
1552 pr_warn("Doesn't have any child node\n");
1553
1554 for_each_node_by_name(slave_node, "slave") {
1555 struct cpsw_slave_data *slave_data = data->slave_data + i;
1556 const void *mac_addr = NULL;
1557 u32 phyid;
1558 int lenp;
1559 const __be32 *parp;
1560 struct device_node *mdio_node;
1561 struct platform_device *mdio;
1562
1563 parp = of_get_property(slave_node, "phy_id", &lenp);
1564 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1565 pr_err("Missing slave[%d] phy_id property\n", i);
1566 ret = -EINVAL;
1567 goto error_ret;
1568 }
1569 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1570 phyid = be32_to_cpup(parp+1);
1571 mdio = of_find_device_by_node(mdio_node);
1572 if (!mdio) {
1573 pr_err("Missing mdio platform device\n");
1574 return -EINVAL;
1575 }
1576 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1577 PHY_ID_FMT, mdio->name, phyid);
1578
1579 mac_addr = of_get_mac_address(slave_node);
1580 if (mac_addr)
1581 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1582
1583 if (data->dual_emac) {
1584 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1585 &prop)) {
1586 pr_err("Missing dual_emac_res_vlan in DT.\n");
1587 slave_data->dual_emac_res_vlan = i+1;
1588 pr_err("Using %d as Reserved VLAN for %d slave\n",
1589 slave_data->dual_emac_res_vlan, i);
1590 } else {
1591 slave_data->dual_emac_res_vlan = prop;
1592 }
1593 }
1594
1595 i++;
1596 }
1597
1598 return 0;
1599
1600error_ret:
1601 kfree(data->slave_data);
1602 return ret;
1603}
1604
1605static int cpsw_probe_dual_emac(struct platform_device *pdev,
1606 struct cpsw_priv *priv)
1607{
1608 struct cpsw_platform_data *data = &priv->data;
1609 struct net_device *ndev;
1610 struct cpsw_priv *priv_sl2;
1611 int ret = 0, i;
1612
1613 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1614 if (!ndev) {
1615 pr_err("cpsw: error allocating net_device\n");
1616 return -ENOMEM;
1617 }
1618
1619 priv_sl2 = netdev_priv(ndev);
1620 spin_lock_init(&priv_sl2->lock);
1621 priv_sl2->data = *data;
1622 priv_sl2->pdev = pdev;
1623 priv_sl2->ndev = ndev;
1624 priv_sl2->dev = &ndev->dev;
1625 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1626 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1627
1628 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1629 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1630 ETH_ALEN);
1631 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1632 } else {
1633 random_ether_addr(priv_sl2->mac_addr);
1634 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1635 }
1636 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1637
1638 priv_sl2->slaves = priv->slaves;
1639 priv_sl2->clk = priv->clk;
1640
1641 priv_sl2->coal_intvl = 0;
1642 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1643
1644 priv_sl2->cpsw_res = priv->cpsw_res;
1645 priv_sl2->regs = priv->regs;
1646 priv_sl2->host_port = priv->host_port;
1647 priv_sl2->host_port_regs = priv->host_port_regs;
1648 priv_sl2->wr_regs = priv->wr_regs;
1649 priv_sl2->dma = priv->dma;
1650 priv_sl2->txch = priv->txch;
1651 priv_sl2->rxch = priv->rxch;
1652 priv_sl2->ale = priv->ale;
1653 priv_sl2->emac_port = 1;
1654 priv->slaves[1].ndev = ndev;
1655 priv_sl2->cpts = priv->cpts;
1656 priv_sl2->version = priv->version;
1657
1658 for (i = 0; i < priv->num_irqs; i++) {
1659 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1660 priv_sl2->num_irqs = priv->num_irqs;
1661 }
1662 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1663
1664 ndev->netdev_ops = &cpsw_netdev_ops;
1665 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1666 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1667
1668 /* register the network device */
1669 SET_NETDEV_DEV(ndev, &pdev->dev);
1670 ret = register_netdev(ndev);
1671 if (ret) {
1672 pr_err("cpsw: error registering net device\n");
1673 free_netdev(ndev);
1674 ret = -ENODEV;
1675 }
1676
1677 return ret;
1678}
1679
1680static int cpsw_probe(struct platform_device *pdev)
1681{
1682 struct cpsw_platform_data *data;
1683 struct net_device *ndev;
1684 struct cpsw_priv *priv;
1685 struct cpdma_params dma_params;
1686 struct cpsw_ale_params ale_params;
1687 void __iomem *ss_regs, *wr_regs;
1688 struct resource *res;
1689 u32 slave_offset, sliver_offset, slave_size;
1690 int ret = 0, i, k = 0;
1691
1692 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1693 if (!ndev) {
1694 pr_err("error allocating net_device\n");
1695 return -ENOMEM;
1696 }
1697
1698 platform_set_drvdata(pdev, ndev);
1699 priv = netdev_priv(ndev);
1700 spin_lock_init(&priv->lock);
1701 priv->pdev = pdev;
1702 priv->ndev = ndev;
1703 priv->dev = &ndev->dev;
1704 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1705 priv->rx_packet_max = max(rx_packet_max, 128);
1706 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
1707 priv->irq_enabled = true;
1708 if (!priv->cpts) {
1709 pr_err("error allocating cpts\n");
1710 goto clean_ndev_ret;
1711 }
1712
1713 /*
1714 * This may be required here for child devices.
1715 */
1716 pm_runtime_enable(&pdev->dev);
1717
1718 if (cpsw_probe_dt(&priv->data, pdev)) {
1719 pr_err("cpsw: platform data missing\n");
1720 ret = -ENODEV;
1721 goto clean_ndev_ret;
1722 }
1723 data = &priv->data;
1724
1725 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1726 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1727 pr_info("Detected MACID = %pM", priv->mac_addr);
1728 } else {
1729 eth_random_addr(priv->mac_addr);
1730 pr_info("Random MACID = %pM", priv->mac_addr);
1731 }
1732
1733 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1734
1735 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1736 GFP_KERNEL);
1737 if (!priv->slaves) {
1738 ret = -EBUSY;
1739 goto clean_ndev_ret;
1740 }
1741 for (i = 0; i < data->slaves; i++)
1742 priv->slaves[i].slave_num = i;
1743
1744 priv->slaves[0].ndev = ndev;
1745 priv->emac_port = 0;
1746
1747 priv->clk = clk_get(&pdev->dev, "fck");
1748 if (IS_ERR(priv->clk)) {
1749 dev_err(&pdev->dev, "fck is not found\n");
1750 ret = -ENODEV;
1751 goto clean_slave_ret;
1752 }
1753 priv->coal_intvl = 0;
1754 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
1755
1756 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1757 if (!priv->cpsw_res) {
1758 dev_err(priv->dev, "error getting i/o resource\n");
1759 ret = -ENOENT;
1760 goto clean_clk_ret;
1761 }
1762 if (!request_mem_region(priv->cpsw_res->start,
1763 resource_size(priv->cpsw_res), ndev->name)) {
1764 dev_err(priv->dev, "failed request i/o region\n");
1765 ret = -ENXIO;
1766 goto clean_clk_ret;
1767 }
1768 ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
1769 if (!ss_regs) {
1770 dev_err(priv->dev, "unable to map i/o region\n");
1771 goto clean_cpsw_iores_ret;
1772 }
1773 priv->regs = ss_regs;
1774 priv->version = __raw_readl(&priv->regs->id_ver);
1775 priv->host_port = HOST_PORT_NUM;
1776
1777 priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1778 if (!priv->cpsw_wr_res) {
1779 dev_err(priv->dev, "error getting i/o resource\n");
1780 ret = -ENOENT;
1781 goto clean_iomap_ret;
1782 }
1783 if (!request_mem_region(priv->cpsw_wr_res->start,
1784 resource_size(priv->cpsw_wr_res), ndev->name)) {
1785 dev_err(priv->dev, "failed request i/o region\n");
1786 ret = -ENXIO;
1787 goto clean_iomap_ret;
1788 }
1789 wr_regs = ioremap(priv->cpsw_wr_res->start,
1790 resource_size(priv->cpsw_wr_res));
1791 if (!wr_regs) {
1792 dev_err(priv->dev, "unable to map i/o region\n");
1793 goto clean_cpsw_wr_iores_ret;
1794 }
1795 priv->wr_regs = wr_regs;
1796
1797 memset(&dma_params, 0, sizeof(dma_params));
1798 memset(&ale_params, 0, sizeof(ale_params));
1799
1800 switch (priv->version) {
1801 case CPSW_VERSION_1:
1802 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
1803 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
1804 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
1805 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
1806 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
1807 slave_offset = CPSW1_SLAVE_OFFSET;
1808 slave_size = CPSW1_SLAVE_SIZE;
1809 sliver_offset = CPSW1_SLIVER_OFFSET;
1810 dma_params.desc_mem_phys = 0;
1811 break;
1812 case CPSW_VERSION_2:
1813 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
1814 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
1815 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
1816 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
1817 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
1818 slave_offset = CPSW2_SLAVE_OFFSET;
1819 slave_size = CPSW2_SLAVE_SIZE;
1820 sliver_offset = CPSW2_SLIVER_OFFSET;
1821 dma_params.desc_mem_phys =
1822 (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
1823 break;
1824 default:
1825 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
1826 ret = -ENODEV;
1827 goto clean_cpsw_wr_iores_ret;
1828 }
1829 for (i = 0; i < priv->data.slaves; i++) {
1830 struct cpsw_slave *slave = &priv->slaves[i];
1831 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
1832 slave_offset += slave_size;
1833 sliver_offset += SLIVER_SIZE;
1834 }
1835
1836 dma_params.dev = &pdev->dev;
1837 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
1838 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
1839 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
1840 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
1841 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
1842
1843 dma_params.num_chan = data->channels;
1844 dma_params.has_soft_reset = true;
1845 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
1846 dma_params.desc_mem_size = data->bd_ram_size;
1847 dma_params.desc_align = 16;
1848 dma_params.has_ext_regs = true;
1849 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
1850
1851 priv->dma = cpdma_ctlr_create(&dma_params);
1852 if (!priv->dma) {
1853 dev_err(priv->dev, "error initializing dma\n");
1854 ret = -ENOMEM;
1855 goto clean_wr_iomap_ret;
1856 }
1857
1858 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
1859 cpsw_tx_handler);
1860 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
1861 cpsw_rx_handler);
1862
1863 if (WARN_ON(!priv->txch || !priv->rxch)) {
1864 dev_err(priv->dev, "error initializing dma channels\n");
1865 ret = -ENOMEM;
1866 goto clean_dma_ret;
1867 }
1868
1869 ale_params.dev = &ndev->dev;
1870 ale_params.ale_ageout = ale_ageout;
1871 ale_params.ale_entries = data->ale_entries;
1872 ale_params.ale_ports = data->slaves;
1873
1874 priv->ale = cpsw_ale_create(&ale_params);
1875 if (!priv->ale) {
1876 dev_err(priv->dev, "error initializing ale engine\n");
1877 ret = -ENODEV;
1878 goto clean_dma_ret;
1879 }
1880
1881 ndev->irq = platform_get_irq(pdev, 0);
1882 if (ndev->irq < 0) {
1883 dev_err(priv->dev, "error getting irq resource\n");
1884 ret = -ENOENT;
1885 goto clean_ale_ret;
1886 }
1887
1888 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1889 for (i = res->start; i <= res->end; i++) {
1890 if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
1891 dev_name(&pdev->dev), priv)) {
1892 dev_err(priv->dev, "error attaching irq\n");
1893 goto clean_ale_ret;
1894 }
1895 priv->irqs_table[k] = i;
1896 priv->num_irqs = k + 1;
1897 }
1898 k++;
1899 }
1900
1901 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1902
1903 ndev->netdev_ops = &cpsw_netdev_ops;
1904 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1905 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1906
1907 /* register the network device */
1908 SET_NETDEV_DEV(ndev, &pdev->dev);
1909 ret = register_netdev(ndev);
1910 if (ret) {
1911 dev_err(priv->dev, "error registering net device\n");
1912 ret = -ENODEV;
1913 goto clean_irq_ret;
1914 }
1915
1916 if (cpts_register(&pdev->dev, priv->cpts,
1917 data->cpts_clock_mult, data->cpts_clock_shift))
1918 dev_err(priv->dev, "error registering cpts device\n");
1919
1920 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
1921 priv->cpsw_res->start, ndev->irq);
1922
1923 if (priv->data.dual_emac) {
1924 ret = cpsw_probe_dual_emac(pdev, priv);
1925 if (ret) {
1926 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
1927 goto clean_irq_ret;
1928 }
1929 }
1930
1931 return 0;
1932
1933clean_irq_ret:
1934 for (i = 0; i < priv->num_irqs; i++)
1935 free_irq(priv->irqs_table[i], priv);
1936clean_ale_ret:
1937 cpsw_ale_destroy(priv->ale);
1938clean_dma_ret:
1939 cpdma_chan_destroy(priv->txch);
1940 cpdma_chan_destroy(priv->rxch);
1941 cpdma_ctlr_destroy(priv->dma);
1942clean_wr_iomap_ret:
1943 iounmap(priv->wr_regs);
1944clean_cpsw_wr_iores_ret:
1945 release_mem_region(priv->cpsw_wr_res->start,
1946 resource_size(priv->cpsw_wr_res));
1947clean_iomap_ret:
1948 iounmap(priv->regs);
1949clean_cpsw_iores_ret:
1950 release_mem_region(priv->cpsw_res->start,
1951 resource_size(priv->cpsw_res));
1952clean_clk_ret:
1953 clk_put(priv->clk);
1954clean_slave_ret:
1955 pm_runtime_disable(&pdev->dev);
1956 kfree(priv->slaves);
1957clean_ndev_ret:
1958 kfree(priv->data.slave_data);
1959 free_netdev(priv->ndev);
1960 return ret;
1961}
1962
1963static int cpsw_remove(struct platform_device *pdev)
1964{
1965 struct net_device *ndev = platform_get_drvdata(pdev);
1966 struct cpsw_priv *priv = netdev_priv(ndev);
1967 int i;
1968
1969 platform_set_drvdata(pdev, NULL);
1970 if (priv->data.dual_emac)
1971 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
1972 unregister_netdev(ndev);
1973
1974 cpts_unregister(priv->cpts);
1975 for (i = 0; i < priv->num_irqs; i++)
1976 free_irq(priv->irqs_table[i], priv);
1977
1978 cpsw_ale_destroy(priv->ale);
1979 cpdma_chan_destroy(priv->txch);
1980 cpdma_chan_destroy(priv->rxch);
1981 cpdma_ctlr_destroy(priv->dma);
1982 iounmap(priv->regs);
1983 release_mem_region(priv->cpsw_res->start,
1984 resource_size(priv->cpsw_res));
1985 iounmap(priv->wr_regs);
1986 release_mem_region(priv->cpsw_wr_res->start,
1987 resource_size(priv->cpsw_wr_res));
1988 pm_runtime_disable(&pdev->dev);
1989 clk_put(priv->clk);
1990 kfree(priv->slaves);
1991 kfree(priv->data.slave_data);
1992 if (priv->data.dual_emac)
1993 free_netdev(cpsw_get_slave_ndev(priv, 1));
1994 free_netdev(ndev);
1995 return 0;
1996}
1997
1998static int cpsw_suspend(struct device *dev)
1999{
2000 struct platform_device *pdev = to_platform_device(dev);
2001 struct net_device *ndev = platform_get_drvdata(pdev);
2002 struct cpsw_priv *priv = netdev_priv(ndev);
2003
2004 if (netif_running(ndev))
2005 cpsw_ndo_stop(ndev);
2006 soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset);
2007 soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset);
2008 pm_runtime_put_sync(&pdev->dev);
2009
2010 return 0;
2011}
2012
2013static int cpsw_resume(struct device *dev)
2014{
2015 struct platform_device *pdev = to_platform_device(dev);
2016 struct net_device *ndev = platform_get_drvdata(pdev);
2017
2018 pm_runtime_get_sync(&pdev->dev);
2019 if (netif_running(ndev))
2020 cpsw_ndo_open(ndev);
2021 return 0;
2022}
2023
2024static const struct dev_pm_ops cpsw_pm_ops = {
2025 .suspend = cpsw_suspend,
2026 .resume = cpsw_resume,
2027};
2028
2029static const struct of_device_id cpsw_of_mtable[] = {
2030 { .compatible = "ti,cpsw", },
2031 { /* sentinel */ },
2032};
2033MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2034
2035static struct platform_driver cpsw_driver = {
2036 .driver = {
2037 .name = "cpsw",
2038 .owner = THIS_MODULE,
2039 .pm = &cpsw_pm_ops,
2040 .of_match_table = of_match_ptr(cpsw_of_mtable),
2041 },
2042 .probe = cpsw_probe,
2043 .remove = cpsw_remove,
2044};
2045
2046static int __init cpsw_init(void)
2047{
2048 return platform_driver_register(&cpsw_driver);
2049}
2050late_initcall(cpsw_init);
2051
2052static void __exit cpsw_exit(void)
2053{
2054 platform_driver_unregister(&cpsw_driver);
2055}
2056module_exit(cpsw_exit);
2057
2058MODULE_LICENSE("GPL");
2059MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2060MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2061MODULE_DESCRIPTION("TI CPSW Ethernet driver");
kernel source for telekom puls (alcatel/mediatek)