projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / sb1250-mac.c
... / ...
CommitLineData
1/*
2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3 * Copyright (c) 2006, 2007 Maciej W. Rozycki
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 *
20 * This driver is designed for the Broadcom SiByte SOC built-in
21 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
22 *
23 * Updated to the driver model and the PHY abstraction layer
24 * by Maciej W. Rozycki.
25 */
26
27#include <linux/bug.h>
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/string.h>
31#include <linux/timer.h>
32#include <linux/errno.h>
33#include <linux/ioport.h>
34#include <linux/slab.h>
35#include <linux/interrupt.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/init.h>
40#include <linux/bitops.h>
41#include <linux/err.h>
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
45#include <linux/platform_device.h>
46#include <linux/prefetch.h>
47
48#include <asm/cache.h>
49#include <asm/io.h>
50#include <asm/processor.h> /* Processor type for cache alignment. */
51
52/* Operational parameters that usually are not changed. */
53
54#define CONFIG_SBMAC_COALESCE
55
56/* Time in jiffies before concluding the transmitter is hung. */
57#define TX_TIMEOUT (2*HZ)
58
59
60MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
61MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
62
63/* A few user-configurable values which may be modified when a driver
64 module is loaded. */
65
66/* 1 normal messages, 0 quiet .. 7 verbose. */
67static int debug = 1;
68module_param(debug, int, S_IRUGO);
69MODULE_PARM_DESC(debug, "Debug messages");
70
71#ifdef CONFIG_SBMAC_COALESCE
72static int int_pktcnt_tx = 255;
73module_param(int_pktcnt_tx, int, S_IRUGO);
74MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
75
76static int int_timeout_tx = 255;
77module_param(int_timeout_tx, int, S_IRUGO);
78MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
79
80static int int_pktcnt_rx = 64;
81module_param(int_pktcnt_rx, int, S_IRUGO);
82MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
83
84static int int_timeout_rx = 64;
85module_param(int_timeout_rx, int, S_IRUGO);
86MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
87#endif
88
89#include <asm/sibyte/board.h>
90#include <asm/sibyte/sb1250.h>
91#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
92#include <asm/sibyte/bcm1480_regs.h>
93#include <asm/sibyte/bcm1480_int.h>
94#define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
95#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
96#include <asm/sibyte/sb1250_regs.h>
97#include <asm/sibyte/sb1250_int.h>
98#else
99#error invalid SiByte MAC configuration
100#endif
101#include <asm/sibyte/sb1250_scd.h>
102#include <asm/sibyte/sb1250_mac.h>
103#include <asm/sibyte/sb1250_dma.h>
104
105#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
106#define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
107#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
108#define UNIT_INT(n) (K_INT_MAC_0 + (n))
109#else
110#error invalid SiByte MAC configuration
111#endif
112
113#ifdef K_INT_PHY
114#define SBMAC_PHY_INT K_INT_PHY
115#else
116#define SBMAC_PHY_INT PHY_POLL
117#endif
118
119/**********************************************************************
120 * Simple types
121 ********************************************************************* */
122
123enum sbmac_speed {
124 sbmac_speed_none = 0,
125 sbmac_speed_10 = SPEED_10,
126 sbmac_speed_100 = SPEED_100,
127 sbmac_speed_1000 = SPEED_1000,
128};
129
130enum sbmac_duplex {
131 sbmac_duplex_none = -1,
132 sbmac_duplex_half = DUPLEX_HALF,
133 sbmac_duplex_full = DUPLEX_FULL,
134};
135
136enum sbmac_fc {
137 sbmac_fc_none,
138 sbmac_fc_disabled,
139 sbmac_fc_frame,
140 sbmac_fc_collision,
141 sbmac_fc_carrier,
142};
143
144enum sbmac_state {
145 sbmac_state_uninit,
146 sbmac_state_off,
147 sbmac_state_on,
148 sbmac_state_broken,
149};
150
151
152/**********************************************************************
153 * Macros
154 ********************************************************************* */
155
156
157#define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
158 (d)->sbdma_dscrtable : (d)->f+1)
159
160
161#define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
162
163#define SBMAC_MAX_TXDESCR 256
164#define SBMAC_MAX_RXDESCR 256
165
166#define ENET_PACKET_SIZE 1518
167/*#define ENET_PACKET_SIZE 9216 */
168
169/**********************************************************************
170 * DMA Descriptor structure
171 ********************************************************************* */
172
173struct sbdmadscr {
174 uint64_t dscr_a;
175 uint64_t dscr_b;
176};
177
178/**********************************************************************
179 * DMA Controller structure
180 ********************************************************************* */
181
182struct sbmacdma {
183
184 /*
185 * This stuff is used to identify the channel and the registers
186 * associated with it.
187 */
188 struct sbmac_softc *sbdma_eth; /* back pointer to associated
189 MAC */
190 int sbdma_channel; /* channel number */
191 int sbdma_txdir; /* direction (1=transmit) */
192 int sbdma_maxdescr; /* total # of descriptors
193 in ring */
194#ifdef CONFIG_SBMAC_COALESCE
195 int sbdma_int_pktcnt;
196 /* # descriptors rx/tx
197 before interrupt */
198 int sbdma_int_timeout;
199 /* # usec rx/tx interrupt */
200#endif
201 void __iomem *sbdma_config0; /* DMA config register 0 */
202 void __iomem *sbdma_config1; /* DMA config register 1 */
203 void __iomem *sbdma_dscrbase;
204 /* descriptor base address */
205 void __iomem *sbdma_dscrcnt; /* descriptor count register */
206 void __iomem *sbdma_curdscr; /* current descriptor
207 address */
208 void __iomem *sbdma_oodpktlost;
209 /* pkt drop (rx only) */
210
211 /*
212 * This stuff is for maintenance of the ring
213 */
214 void *sbdma_dscrtable_unaligned;
215 struct sbdmadscr *sbdma_dscrtable;
216 /* base of descriptor table */
217 struct sbdmadscr *sbdma_dscrtable_end;
218 /* end of descriptor table */
219 struct sk_buff **sbdma_ctxtable;
220 /* context table, one
221 per descr */
222 dma_addr_t sbdma_dscrtable_phys;
223 /* and also the phys addr */
224 struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */
225 struct sbdmadscr *sbdma_remptr; /* next dscr for sw
226 to remove */
227};
228
229
230/**********************************************************************
231 * Ethernet softc structure
232 ********************************************************************* */
233
234struct sbmac_softc {
235
236 /*
237 * Linux-specific things
238 */
239 struct net_device *sbm_dev; /* pointer to linux device */
240 struct napi_struct napi;
241 struct phy_device *phy_dev; /* the associated PHY device */
242 struct mii_bus *mii_bus; /* the MII bus */
243 int phy_irq[PHY_MAX_ADDR];
244 spinlock_t sbm_lock; /* spin lock */
245 int sbm_devflags; /* current device flags */
246
247 /*
248 * Controller-specific things
249 */
250 void __iomem *sbm_base; /* MAC's base address */
251 enum sbmac_state sbm_state; /* current state */
252
253 void __iomem *sbm_macenable; /* MAC Enable Register */
254 void __iomem *sbm_maccfg; /* MAC Config Register */
255 void __iomem *sbm_fifocfg; /* FIFO Config Register */
256 void __iomem *sbm_framecfg; /* Frame Config Register */
257 void __iomem *sbm_rxfilter; /* Receive Filter Register */
258 void __iomem *sbm_isr; /* Interrupt Status Register */
259 void __iomem *sbm_imr; /* Interrupt Mask Register */
260 void __iomem *sbm_mdio; /* MDIO Register */
261
262 enum sbmac_speed sbm_speed; /* current speed */
263 enum sbmac_duplex sbm_duplex; /* current duplex */
264 enum sbmac_fc sbm_fc; /* cur. flow control setting */
265 int sbm_pause; /* current pause setting */
266 int sbm_link; /* current link state */
267
268 unsigned char sbm_hwaddr[ETH_ALEN];
269
270 struct sbmacdma sbm_txdma; /* only channel 0 for now */
271 struct sbmacdma sbm_rxdma;
272 int rx_hw_checksum;
273 int sbe_idx;
274};
275
276
277/**********************************************************************
278 * Externs
279 ********************************************************************* */
280
281/**********************************************************************
282 * Prototypes
283 ********************************************************************* */
284
285static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
286 int txrx, int maxdescr);
287static void sbdma_channel_start(struct sbmacdma *d, int rxtx);
288static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
289 struct sk_buff *m);
290static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m);
291static void sbdma_emptyring(struct sbmacdma *d);
292static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d);
293static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
294 int work_to_do, int poll);
295static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
296 int poll);
297static int sbmac_initctx(struct sbmac_softc *s);
298static void sbmac_channel_start(struct sbmac_softc *s);
299static void sbmac_channel_stop(struct sbmac_softc *s);
300static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *,
301 enum sbmac_state);
302static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff);
303static uint64_t sbmac_addr2reg(unsigned char *ptr);
304static irqreturn_t sbmac_intr(int irq, void *dev_instance);
305static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
306static void sbmac_setmulti(struct sbmac_softc *sc);
307static int sbmac_init(struct platform_device *pldev, long long base);
308static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
309static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
310 enum sbmac_fc fc);
311
312static int sbmac_open(struct net_device *dev);
313static void sbmac_tx_timeout (struct net_device *dev);
314static void sbmac_set_rx_mode(struct net_device *dev);
315static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
316static int sbmac_close(struct net_device *dev);
317static int sbmac_poll(struct napi_struct *napi, int budget);
318
319static void sbmac_mii_poll(struct net_device *dev);
320static int sbmac_mii_probe(struct net_device *dev);
321
322static void sbmac_mii_sync(void __iomem *sbm_mdio);
323static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
324 int bitcnt);
325static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx);
326static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
327 u16 val);
328
329
330/**********************************************************************
331 * Globals
332 ********************************************************************* */
333
334static char sbmac_string[] = "sb1250-mac";
335
336static char sbmac_mdio_string[] = "sb1250-mac-mdio";
337
338
339/**********************************************************************
340 * MDIO constants
341 ********************************************************************* */
342
343#define MII_COMMAND_START 0x01
344#define MII_COMMAND_READ 0x02
345#define MII_COMMAND_WRITE 0x01
346#define MII_COMMAND_ACK 0x02
347
348#define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
349
350#define ENABLE 1
351#define DISABLE 0
352
353/**********************************************************************
354 * SBMAC_MII_SYNC(sbm_mdio)
355 *
356 * Synchronize with the MII - send a pattern of bits to the MII
357 * that will guarantee that it is ready to accept a command.
358 *
359 * Input parameters:
360 * sbm_mdio - address of the MAC's MDIO register
361 *
362 * Return value:
363 * nothing
364 ********************************************************************* */
365
366static void sbmac_mii_sync(void __iomem *sbm_mdio)
367{
368 int cnt;
369 uint64_t bits;
370 int mac_mdio_genc;
371
372 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
373
374 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
375
376 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
377
378 for (cnt = 0; cnt < 32; cnt++) {
379 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
380 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
381 }
382}
383
384/**********************************************************************
385 * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)
386 *
387 * Send some bits to the MII. The bits to be sent are right-
388 * justified in the 'data' parameter.
389 *
390 * Input parameters:
391 * sbm_mdio - address of the MAC's MDIO register
392 * data - data to send
393 * bitcnt - number of bits to send
394 ********************************************************************* */
395
396static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
397 int bitcnt)
398{
399 int i;
400 uint64_t bits;
401 unsigned int curmask;
402 int mac_mdio_genc;
403
404 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
405
406 bits = M_MAC_MDIO_DIR_OUTPUT;
407 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
408
409 curmask = 1 << (bitcnt - 1);
410
411 for (i = 0; i < bitcnt; i++) {
412 if (data & curmask)
413 bits |= M_MAC_MDIO_OUT;
414 else bits &= ~M_MAC_MDIO_OUT;
415 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
416 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
417 __raw_writeq(bits | mac_mdio_genc, sbm_mdio);
418 curmask >>= 1;
419 }
420}
421
422
423
424/**********************************************************************
425 * SBMAC_MII_READ(bus, phyaddr, regidx)
426 * Read a PHY register.
427 *
428 * Input parameters:
429 * bus - MDIO bus handle
430 * phyaddr - PHY's address
431 * regnum - index of register to read
432 *
433 * Return value:
434 * value read, or 0xffff if an error occurred.
435 ********************************************************************* */
436
437static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
438{
439 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
440 void __iomem *sbm_mdio = sc->sbm_mdio;
441 int idx;
442 int error;
443 int regval;
444 int mac_mdio_genc;
445
446 /*
447 * Synchronize ourselves so that the PHY knows the next
448 * thing coming down is a command
449 */
450 sbmac_mii_sync(sbm_mdio);
451
452 /*
453 * Send the data to the PHY. The sequence is
454 * a "start" command (2 bits)
455 * a "read" command (2 bits)
456 * the PHY addr (5 bits)
457 * the register index (5 bits)
458 */
459 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
460 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2);
461 sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
462 sbmac_mii_senddata(sbm_mdio, regidx, 5);
463
464 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
465
466 /*
467 * Switch the port around without a clock transition.
468 */
469 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
470
471 /*
472 * Send out a clock pulse to signal we want the status
473 */
474 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
475 sbm_mdio);
476 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
477
478 /*
479 * If an error occurred, the PHY will signal '1' back
480 */
481 error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;
482
483 /*
484 * Issue an 'idle' clock pulse, but keep the direction
485 * the same.
486 */
487 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
488 sbm_mdio);
489 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
490
491 regval = 0;
492
493 for (idx = 0; idx < 16; idx++) {
494 regval <<= 1;
495
496 if (error == 0) {
497 if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)
498 regval |= 1;
499 }
500
501 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
502 sbm_mdio);
503 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);
504 }
505
506 /* Switch back to output */
507 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
508
509 if (error == 0)
510 return regval;
511 return 0xffff;
512}
513
514
515/**********************************************************************
516 * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
517 *
518 * Write a value to a PHY register.
519 *
520 * Input parameters:
521 * bus - MDIO bus handle
522 * phyaddr - PHY to use
523 * regidx - register within the PHY
524 * regval - data to write to register
525 *
526 * Return value:
527 * 0 for success
528 ********************************************************************* */
529
530static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
531 u16 regval)
532{
533 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
534 void __iomem *sbm_mdio = sc->sbm_mdio;
535 int mac_mdio_genc;
536
537 sbmac_mii_sync(sbm_mdio);
538
539 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
540 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2);
541 sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
542 sbmac_mii_senddata(sbm_mdio, regidx, 5);
543 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2);
544 sbmac_mii_senddata(sbm_mdio, regval, 16);
545
546 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
547
548 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
549
550 return 0;
551}
552
553
554
555/**********************************************************************
556 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
557 *
558 * Initialize a DMA channel context. Since there are potentially
559 * eight DMA channels per MAC, it's nice to do this in a standard
560 * way.
561 *
562 * Input parameters:
563 * d - struct sbmacdma (DMA channel context)
564 * s - struct sbmac_softc (pointer to a MAC)
565 * chan - channel number (0..1 right now)
566 * txrx - Identifies DMA_TX or DMA_RX for channel direction
567 * maxdescr - number of descriptors
568 *
569 * Return value:
570 * nothing
571 ********************************************************************* */
572
573static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
574 int txrx, int maxdescr)
575{
576#ifdef CONFIG_SBMAC_COALESCE
577 int int_pktcnt, int_timeout;
578#endif
579
580 /*
581 * Save away interesting stuff in the structure
582 */
583
584 d->sbdma_eth = s;
585 d->sbdma_channel = chan;
586 d->sbdma_txdir = txrx;
587
588#if 0
589 /* RMON clearing */
590 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
591#endif
592
593 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES);
594 __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS);
595 __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL);
596 __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL);
597 __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR);
598 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT);
599 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD);
600 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD);
601 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT);
602 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE);
603 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES);
604 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST);
605 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST);
606 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD);
607 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD);
608 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT);
609 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE);
610 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR);
611 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR);
612 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR);
613 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR);
614
615 /*
616 * initialize register pointers
617 */
618
619 d->sbdma_config0 =
620 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
621 d->sbdma_config1 =
622 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
623 d->sbdma_dscrbase =
624 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
625 d->sbdma_dscrcnt =
626 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
627 d->sbdma_curdscr =
628 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
629 if (d->sbdma_txdir)
630 d->sbdma_oodpktlost = NULL;
631 else
632 d->sbdma_oodpktlost =
633 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
634
635 /*
636 * Allocate memory for the ring
637 */
638
639 d->sbdma_maxdescr = maxdescr;
640
641 d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1,
642 sizeof(*d->sbdma_dscrtable),
643 GFP_KERNEL);
644
645 /*
646 * The descriptor table must be aligned to at least 16 bytes or the
647 * MAC will corrupt it.
648 */
649 d->sbdma_dscrtable = (struct sbdmadscr *)
650 ALIGN((unsigned long)d->sbdma_dscrtable_unaligned,
651 sizeof(*d->sbdma_dscrtable));
652
653 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
654
655 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
656
657 /*
658 * And context table
659 */
660
661 d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
662 sizeof(*d->sbdma_ctxtable), GFP_KERNEL);
663
664#ifdef CONFIG_SBMAC_COALESCE
665 /*
666 * Setup Rx/Tx DMA coalescing defaults
667 */
668
669 int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
670 if ( int_pktcnt ) {
671 d->sbdma_int_pktcnt = int_pktcnt;
672 } else {
673 d->sbdma_int_pktcnt = 1;
674 }
675
676 int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
677 if ( int_timeout ) {
678 d->sbdma_int_timeout = int_timeout;
679 } else {
680 d->sbdma_int_timeout = 0;
681 }
682#endif
683
684}
685
686/**********************************************************************
687 * SBDMA_CHANNEL_START(d)
688 *
689 * Initialize the hardware registers for a DMA channel.
690 *
691 * Input parameters:
692 * d - DMA channel to init (context must be previously init'd
693 * rxtx - DMA_RX or DMA_TX depending on what type of channel
694 *
695 * Return value:
696 * nothing
697 ********************************************************************* */
698
699static void sbdma_channel_start(struct sbmacdma *d, int rxtx)
700{
701 /*
702 * Turn on the DMA channel
703 */
704
705#ifdef CONFIG_SBMAC_COALESCE
706 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
707 0, d->sbdma_config1);
708 __raw_writeq(M_DMA_EOP_INT_EN |
709 V_DMA_RINGSZ(d->sbdma_maxdescr) |
710 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
711 0, d->sbdma_config0);
712#else
713 __raw_writeq(0, d->sbdma_config1);
714 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
715 0, d->sbdma_config0);
716#endif
717
718 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
719
720 /*
721 * Initialize ring pointers
722 */
723
724 d->sbdma_addptr = d->sbdma_dscrtable;
725 d->sbdma_remptr = d->sbdma_dscrtable;
726}
727
728/**********************************************************************
729 * SBDMA_CHANNEL_STOP(d)
730 *
731 * Initialize the hardware registers for a DMA channel.
732 *
733 * Input parameters:
734 * d - DMA channel to init (context must be previously init'd
735 *
736 * Return value:
737 * nothing
738 ********************************************************************* */
739
740static void sbdma_channel_stop(struct sbmacdma *d)
741{
742 /*
743 * Turn off the DMA channel
744 */
745
746 __raw_writeq(0, d->sbdma_config1);
747
748 __raw_writeq(0, d->sbdma_dscrbase);
749
750 __raw_writeq(0, d->sbdma_config0);
751
752 /*
753 * Zero ring pointers
754 */
755
756 d->sbdma_addptr = NULL;
757 d->sbdma_remptr = NULL;
758}
759
760static inline void sbdma_align_skb(struct sk_buff *skb,
761 unsigned int power2, unsigned int offset)
762{
763 unsigned char *addr = skb->data;
764 unsigned char *newaddr = PTR_ALIGN(addr, power2);
765
766 skb_reserve(skb, newaddr - addr + offset);
767}
768
769
770/**********************************************************************
771 * SBDMA_ADD_RCVBUFFER(d,sb)
772 *
773 * Add a buffer to the specified DMA channel. For receive channels,
774 * this queues a buffer for inbound packets.
775 *
776 * Input parameters:
777 * sc - softc structure
778 * d - DMA channel descriptor
779 * sb - sk_buff to add, or NULL if we should allocate one
780 *
781 * Return value:
782 * 0 if buffer could not be added (ring is full)
783 * 1 if buffer added successfully
784 ********************************************************************* */
785
786
787static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
788 struct sk_buff *sb)
789{
790 struct net_device *dev = sc->sbm_dev;
791 struct sbdmadscr *dsc;
792 struct sbdmadscr *nextdsc;
793 struct sk_buff *sb_new = NULL;
794 int pktsize = ENET_PACKET_SIZE;
795
796 /* get pointer to our current place in the ring */
797
798 dsc = d->sbdma_addptr;
799 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
800
801 /*
802 * figure out if the ring is full - if the next descriptor
803 * is the same as the one that we're going to remove from
804 * the ring, the ring is full
805 */
806
807 if (nextdsc == d->sbdma_remptr) {
808 return -ENOSPC;
809 }
810
811 /*
812 * Allocate a sk_buff if we don't already have one.
813 * If we do have an sk_buff, reset it so that it's empty.
814 *
815 * Note: sk_buffs don't seem to be guaranteed to have any sort
816 * of alignment when they are allocated. Therefore, allocate enough
817 * extra space to make sure that:
818 *
819 * 1. the data does not start in the middle of a cache line.
820 * 2. The data does not end in the middle of a cache line
821 * 3. The buffer can be aligned such that the IP addresses are
822 * naturally aligned.
823 *
824 * Remember, the SOCs MAC writes whole cache lines at a time,
825 * without reading the old contents first. So, if the sk_buff's
826 * data portion starts in the middle of a cache line, the SOC
827 * DMA will trash the beginning (and ending) portions.
828 */
829
830 if (sb == NULL) {
831 sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE +
832 SMP_CACHE_BYTES * 2 +
833 NET_IP_ALIGN);
834 if (sb_new == NULL)
835 return -ENOBUFS;
836
837 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN);
838 }
839 else {
840 sb_new = sb;
841 /*
842 * nothing special to reinit buffer, it's already aligned
843 * and sb->data already points to a good place.
844 */
845 }
846
847 /*
848 * fill in the descriptor
849 */
850
851#ifdef CONFIG_SBMAC_COALESCE
852 /*
853 * Do not interrupt per DMA transfer.
854 */
855 dsc->dscr_a = virt_to_phys(sb_new->data) |
856 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0;
857#else
858 dsc->dscr_a = virt_to_phys(sb_new->data) |
859 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) |
860 M_DMA_DSCRA_INTERRUPT;
861#endif
862
863 /* receiving: no options */
864 dsc->dscr_b = 0;
865
866 /*
867 * fill in the context
868 */
869
870 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
871
872 /*
873 * point at next packet
874 */
875
876 d->sbdma_addptr = nextdsc;
877
878 /*
879 * Give the buffer to the DMA engine.
880 */
881
882 __raw_writeq(1, d->sbdma_dscrcnt);
883
884 return 0; /* we did it */
885}
886
887/**********************************************************************
888 * SBDMA_ADD_TXBUFFER(d,sb)
889 *
890 * Add a transmit buffer to the specified DMA channel, causing a
891 * transmit to start.
892 *
893 * Input parameters:
894 * d - DMA channel descriptor
895 * sb - sk_buff to add
896 *
897 * Return value:
898 * 0 transmit queued successfully
899 * otherwise error code
900 ********************************************************************* */
901
902
903static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb)
904{
905 struct sbdmadscr *dsc;
906 struct sbdmadscr *nextdsc;
907 uint64_t phys;
908 uint64_t ncb;
909 int length;
910
911 /* get pointer to our current place in the ring */
912
913 dsc = d->sbdma_addptr;
914 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
915
916 /*
917 * figure out if the ring is full - if the next descriptor
918 * is the same as the one that we're going to remove from
919 * the ring, the ring is full
920 */
921
922 if (nextdsc == d->sbdma_remptr) {
923 return -ENOSPC;
924 }
925
926 /*
927 * Under Linux, it's not necessary to copy/coalesce buffers
928 * like it is on NetBSD. We think they're all contiguous,
929 * but that may not be true for GBE.
930 */
931
932 length = sb->len;
933
934 /*
935 * fill in the descriptor. Note that the number of cache
936 * blocks in the descriptor is the number of blocks
937 * *spanned*, so we need to add in the offset (if any)
938 * while doing the calculation.
939 */
940
941 phys = virt_to_phys(sb->data);
942 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
943
944 dsc->dscr_a = phys |
945 V_DMA_DSCRA_A_SIZE(ncb) |
946#ifndef CONFIG_SBMAC_COALESCE
947 M_DMA_DSCRA_INTERRUPT |
948#endif
949 M_DMA_ETHTX_SOP;
950
951 /* transmitting: set outbound options and length */
952
953 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
954 V_DMA_DSCRB_PKT_SIZE(length);
955
956 /*
957 * fill in the context
958 */
959
960 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
961
962 /*
963 * point at next packet
964 */
965
966 d->sbdma_addptr = nextdsc;
967
968 /*
969 * Give the buffer to the DMA engine.
970 */
971
972 __raw_writeq(1, d->sbdma_dscrcnt);
973
974 return 0; /* we did it */
975}
976
977
978
979
980/**********************************************************************
981 * SBDMA_EMPTYRING(d)
982 *
983 * Free all allocated sk_buffs on the specified DMA channel;
984 *
985 * Input parameters:
986 * d - DMA channel
987 *
988 * Return value:
989 * nothing
990 ********************************************************************* */
991
992static void sbdma_emptyring(struct sbmacdma *d)
993{
994 int idx;
995 struct sk_buff *sb;
996
997 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
998 sb = d->sbdma_ctxtable[idx];
999 if (sb) {
1000 dev_kfree_skb(sb);
1001 d->sbdma_ctxtable[idx] = NULL;
1002 }
1003 }
1004}
1005
1006
1007/**********************************************************************
1008 * SBDMA_FILLRING(d)
1009 *
1010 * Fill the specified DMA channel (must be receive channel)
1011 * with sk_buffs
1012 *
1013 * Input parameters:
1014 * sc - softc structure
1015 * d - DMA channel
1016 *
1017 * Return value:
1018 * nothing
1019 ********************************************************************* */
1020
1021static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d)
1022{
1023 int idx;
1024
1025 for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) {
1026 if (sbdma_add_rcvbuffer(sc, d, NULL) != 0)
1027 break;
1028 }
1029}
1030
1031#ifdef CONFIG_NET_POLL_CONTROLLER
1032static void sbmac_netpoll(struct net_device *netdev)
1033{
1034 struct sbmac_softc *sc = netdev_priv(netdev);
1035 int irq = sc->sbm_dev->irq;
1036
1037 __raw_writeq(0, sc->sbm_imr);
1038
1039 sbmac_intr(irq, netdev);
1040
1041#ifdef CONFIG_SBMAC_COALESCE
1042 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1043 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1044 sc->sbm_imr);
1045#else
1046 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1047 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1048#endif
1049}
1050#endif
1051
1052/**********************************************************************
1053 * SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1054 *
1055 * Process "completed" receive buffers on the specified DMA channel.
1056 *
1057 * Input parameters:
1058 * sc - softc structure
1059 * d - DMA channel context
1060 * work_to_do - no. of packets to process before enabling interrupt
1061 * again (for NAPI)
1062 * poll - 1: using polling (for NAPI)
1063 *
1064 * Return value:
1065 * nothing
1066 ********************************************************************* */
1067
1068static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1069 int work_to_do, int poll)
1070{
1071 struct net_device *dev = sc->sbm_dev;
1072 int curidx;
1073 int hwidx;
1074 struct sbdmadscr *dsc;
1075 struct sk_buff *sb;
1076 int len;
1077 int work_done = 0;
1078 int dropped = 0;
1079
1080 prefetch(d);
1081
1082again:
1083 /* Check if the HW dropped any frames */
1084 dev->stats.rx_fifo_errors
1085 += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1086 __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1087
1088 while (work_to_do-- > 0) {
1089 /*
1090 * figure out where we are (as an index) and where
1091 * the hardware is (also as an index)
1092 *
1093 * This could be done faster if (for example) the
1094 * descriptor table was page-aligned and contiguous in
1095 * both virtual and physical memory -- you could then
1096 * just compare the low-order bits of the virtual address
1097 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1098 */
1099
1100 dsc = d->sbdma_remptr;
1101 curidx = dsc - d->sbdma_dscrtable;
1102
1103 prefetch(dsc);
1104 prefetch(&d->sbdma_ctxtable[curidx]);
1105
1106 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1107 d->sbdma_dscrtable_phys) /
1108 sizeof(*d->sbdma_dscrtable);
1109
1110 /*
1111 * If they're the same, that means we've processed all
1112 * of the descriptors up to (but not including) the one that
1113 * the hardware is working on right now.
1114 */
1115
1116 if (curidx == hwidx)
1117 goto done;
1118
1119 /*
1120 * Otherwise, get the packet's sk_buff ptr back
1121 */
1122
1123 sb = d->sbdma_ctxtable[curidx];
1124 d->sbdma_ctxtable[curidx] = NULL;
1125
1126 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1127
1128 /*
1129 * Check packet status. If good, process it.
1130 * If not, silently drop it and put it back on the
1131 * receive ring.
1132 */
1133
1134 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1135
1136 /*
1137 * Add a new buffer to replace the old one. If we fail
1138 * to allocate a buffer, we're going to drop this
1139 * packet and put it right back on the receive ring.
1140 */
1141
1142 if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) ==
1143 -ENOBUFS)) {
1144 dev->stats.rx_dropped++;
1145 /* Re-add old buffer */
1146 sbdma_add_rcvbuffer(sc, d, sb);
1147 /* No point in continuing at the moment */
1148 printk(KERN_ERR "dropped packet (1)\n");
1149 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1150 goto done;
1151 } else {
1152 /*
1153 * Set length into the packet
1154 */
1155 skb_put(sb,len);
1156
1157 /*
1158 * Buffer has been replaced on the
1159 * receive ring. Pass the buffer to
1160 * the kernel
1161 */
1162 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1163 /* Check hw IPv4/TCP checksum if supported */
1164 if (sc->rx_hw_checksum == ENABLE) {
1165 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1166 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1167 sb->ip_summed = CHECKSUM_UNNECESSARY;
1168 /* don't need to set sb->csum */
1169 } else {
1170 skb_checksum_none_assert(sb);
1171 }
1172 }
1173 prefetch(sb->data);
1174 prefetch((const void *)(((char *)sb->data)+32));
1175 if (poll)
1176 dropped = netif_receive_skb(sb);
1177 else
1178 dropped = netif_rx(sb);
1179
1180 if (dropped == NET_RX_DROP) {
1181 dev->stats.rx_dropped++;
1182 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1183 goto done;
1184 }
1185 else {
1186 dev->stats.rx_bytes += len;
1187 dev->stats.rx_packets++;
1188 }
1189 }
1190 } else {
1191 /*
1192 * Packet was mangled somehow. Just drop it and
1193 * put it back on the receive ring.
1194 */
1195 dev->stats.rx_errors++;
1196 sbdma_add_rcvbuffer(sc, d, sb);
1197 }
1198
1199
1200 /*
1201 * .. and advance to the next buffer.
1202 */
1203
1204 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1205 work_done++;
1206 }
1207 if (!poll) {
1208 work_to_do = 32;
1209 goto again; /* collect fifo drop statistics again */
1210 }
1211done:
1212 return work_done;
1213}
1214
1215/**********************************************************************
1216 * SBDMA_TX_PROCESS(sc,d)
1217 *
1218 * Process "completed" transmit buffers on the specified DMA channel.
1219 * This is normally called within the interrupt service routine.
1220 * Note that this isn't really ideal for priority channels, since
1221 * it processes all of the packets on a given channel before
1222 * returning.
1223 *
1224 * Input parameters:
1225 * sc - softc structure
1226 * d - DMA channel context
1227 * poll - 1: using polling (for NAPI)
1228 *
1229 * Return value:
1230 * nothing
1231 ********************************************************************* */
1232
1233static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
1234 int poll)
1235{
1236 struct net_device *dev = sc->sbm_dev;
1237 int curidx;
1238 int hwidx;
1239 struct sbdmadscr *dsc;
1240 struct sk_buff *sb;
1241 unsigned long flags;
1242 int packets_handled = 0;
1243
1244 spin_lock_irqsave(&(sc->sbm_lock), flags);
1245
1246 if (d->sbdma_remptr == d->sbdma_addptr)
1247 goto end_unlock;
1248
1249 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1250 d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable);
1251
1252 for (;;) {
1253 /*
1254 * figure out where we are (as an index) and where
1255 * the hardware is (also as an index)
1256 *
1257 * This could be done faster if (for example) the
1258 * descriptor table was page-aligned and contiguous in
1259 * both virtual and physical memory -- you could then
1260 * just compare the low-order bits of the virtual address
1261 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1262 */
1263
1264 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1265
1266 /*
1267 * If they're the same, that means we've processed all
1268 * of the descriptors up to (but not including) the one that
1269 * the hardware is working on right now.
1270 */
1271
1272 if (curidx == hwidx)
1273 break;
1274
1275 /*
1276 * Otherwise, get the packet's sk_buff ptr back
1277 */
1278
1279 dsc = &(d->sbdma_dscrtable[curidx]);
1280 sb = d->sbdma_ctxtable[curidx];
1281 d->sbdma_ctxtable[curidx] = NULL;
1282
1283 /*
1284 * Stats
1285 */
1286
1287 dev->stats.tx_bytes += sb->len;
1288 dev->stats.tx_packets++;
1289
1290 /*
1291 * for transmits, we just free buffers.
1292 */
1293
1294 dev_kfree_skb_irq(sb);
1295
1296 /*
1297 * .. and advance to the next buffer.
1298 */
1299
1300 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1301
1302 packets_handled++;
1303
1304 }
1305
1306 /*
1307 * Decide if we should wake up the protocol or not.
1308 * Other drivers seem to do this when we reach a low
1309 * watermark on the transmit queue.
1310 */
1311
1312 if (packets_handled)
1313 netif_wake_queue(d->sbdma_eth->sbm_dev);
1314
1315end_unlock:
1316 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1317
1318}
1319
1320
1321
1322/**********************************************************************
1323 * SBMAC_INITCTX(s)
1324 *
1325 * Initialize an Ethernet context structure - this is called
1326 * once per MAC on the 1250. Memory is allocated here, so don't
1327 * call it again from inside the ioctl routines that bring the
1328 * interface up/down
1329 *
1330 * Input parameters:
1331 * s - sbmac context structure
1332 *
1333 * Return value:
1334 * 0
1335 ********************************************************************* */
1336
1337static int sbmac_initctx(struct sbmac_softc *s)
1338{
1339
1340 /*
1341 * figure out the addresses of some ports
1342 */
1343
1344 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1345 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1346 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1347 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1348 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1349 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1350 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1351 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1352
1353 /*
1354 * Initialize the DMA channels. Right now, only one per MAC is used
1355 * Note: Only do this _once_, as it allocates memory from the kernel!
1356 */
1357
1358 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1359 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1360
1361 /*
1362 * initial state is OFF
1363 */
1364
1365 s->sbm_state = sbmac_state_off;
1366
1367 return 0;
1368}
1369
1370
1371static void sbdma_uninitctx(struct sbmacdma *d)
1372{
1373 if (d->sbdma_dscrtable_unaligned) {
1374 kfree(d->sbdma_dscrtable_unaligned);
1375 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1376 }
1377
1378 if (d->sbdma_ctxtable) {
1379 kfree(d->sbdma_ctxtable);
1380 d->sbdma_ctxtable = NULL;
1381 }
1382}
1383
1384
1385static void sbmac_uninitctx(struct sbmac_softc *sc)
1386{
1387 sbdma_uninitctx(&(sc->sbm_txdma));
1388 sbdma_uninitctx(&(sc->sbm_rxdma));
1389}
1390
1391
1392/**********************************************************************
1393 * SBMAC_CHANNEL_START(s)
1394 *
1395 * Start packet processing on this MAC.
1396 *
1397 * Input parameters:
1398 * s - sbmac structure
1399 *
1400 * Return value:
1401 * nothing
1402 ********************************************************************* */
1403
1404static void sbmac_channel_start(struct sbmac_softc *s)
1405{
1406 uint64_t reg;
1407 void __iomem *port;
1408 uint64_t cfg,fifo,framecfg;
1409 int idx, th_value;
1410
1411 /*
1412 * Don't do this if running
1413 */
1414
1415 if (s->sbm_state == sbmac_state_on)
1416 return;
1417
1418 /*
1419 * Bring the controller out of reset, but leave it off.
1420 */
1421
1422 __raw_writeq(0, s->sbm_macenable);
1423
1424 /*
1425 * Ignore all received packets
1426 */
1427
1428 __raw_writeq(0, s->sbm_rxfilter);
1429
1430 /*
1431 * Calculate values for various control registers.
1432 */
1433
1434 cfg = M_MAC_RETRY_EN |
1435 M_MAC_TX_HOLD_SOP_EN |
1436 V_MAC_TX_PAUSE_CNT_16K |
1437 M_MAC_AP_STAT_EN |
1438 M_MAC_FAST_SYNC |
1439 M_MAC_SS_EN |
1440 0;
1441
1442 /*
1443 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1444 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1445 * Use a larger RD_THRSH for gigabit
1446 */
1447 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1448 th_value = 28;
1449 else
1450 th_value = 64;
1451
1452 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1453 ((s->sbm_speed == sbmac_speed_1000)
1454 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1455 V_MAC_TX_RL_THRSH(4) |
1456 V_MAC_RX_PL_THRSH(4) |
1457 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1458 V_MAC_RX_RL_THRSH(8) |
1459 0;
1460
1461 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1462 V_MAC_MAX_FRAMESZ_DEFAULT |
1463 V_MAC_BACKOFF_SEL(1);
1464
1465 /*
1466 * Clear out the hash address map
1467 */
1468
1469 port = s->sbm_base + R_MAC_HASH_BASE;
1470 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1471 __raw_writeq(0, port);
1472 port += sizeof(uint64_t);
1473 }
1474
1475 /*
1476 * Clear out the exact-match table
1477 */
1478
1479 port = s->sbm_base + R_MAC_ADDR_BASE;
1480 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1481 __raw_writeq(0, port);
1482 port += sizeof(uint64_t);
1483 }
1484
1485 /*
1486 * Clear out the DMA Channel mapping table registers
1487 */
1488
1489 port = s->sbm_base + R_MAC_CHUP0_BASE;
1490 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1491 __raw_writeq(0, port);
1492 port += sizeof(uint64_t);
1493 }
1494
1495
1496 port = s->sbm_base + R_MAC_CHLO0_BASE;
1497 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1498 __raw_writeq(0, port);
1499 port += sizeof(uint64_t);
1500 }
1501
1502 /*
1503 * Program the hardware address. It goes into the hardware-address
1504 * register as well as the first filter register.
1505 */
1506
1507 reg = sbmac_addr2reg(s->sbm_hwaddr);
1508
1509 port = s->sbm_base + R_MAC_ADDR_BASE;
1510 __raw_writeq(reg, port);
1511 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1512
1513#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1514 /*
1515 * Pass1 SOCs do not receive packets addressed to the
1516 * destination address in the R_MAC_ETHERNET_ADDR register.
1517 * Set the value to zero.
1518 */
1519 __raw_writeq(0, port);
1520#else
1521 __raw_writeq(reg, port);
1522#endif
1523
1524 /*
1525 * Set the receive filter for no packets, and write values
1526 * to the various config registers
1527 */
1528
1529 __raw_writeq(0, s->sbm_rxfilter);
1530 __raw_writeq(0, s->sbm_imr);
1531 __raw_writeq(framecfg, s->sbm_framecfg);
1532 __raw_writeq(fifo, s->sbm_fifocfg);
1533 __raw_writeq(cfg, s->sbm_maccfg);
1534
1535 /*
1536 * Initialize DMA channels (rings should be ok now)
1537 */
1538
1539 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1540 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1541
1542 /*
1543 * Configure the speed, duplex, and flow control
1544 */
1545
1546 sbmac_set_speed(s,s->sbm_speed);
1547 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1548
1549 /*
1550 * Fill the receive ring
1551 */
1552
1553 sbdma_fillring(s, &(s->sbm_rxdma));
1554
1555 /*
1556 * Turn on the rest of the bits in the enable register
1557 */
1558
1559#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1560 __raw_writeq(M_MAC_RXDMA_EN0 |
1561 M_MAC_TXDMA_EN0, s->sbm_macenable);
1562#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1563 __raw_writeq(M_MAC_RXDMA_EN0 |
1564 M_MAC_TXDMA_EN0 |
1565 M_MAC_RX_ENABLE |
1566 M_MAC_TX_ENABLE, s->sbm_macenable);
1567#else
1568#error invalid SiByte MAC configuration
1569#endif
1570
1571#ifdef CONFIG_SBMAC_COALESCE
1572 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1573 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1574#else
1575 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1576 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1577#endif
1578
1579 /*
1580 * Enable receiving unicasts and broadcasts
1581 */
1582
1583 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1584
1585 /*
1586 * we're running now.
1587 */
1588
1589 s->sbm_state = sbmac_state_on;
1590
1591 /*
1592 * Program multicast addresses
1593 */
1594
1595 sbmac_setmulti(s);
1596
1597 /*
1598 * If channel was in promiscuous mode before, turn that on
1599 */
1600
1601 if (s->sbm_devflags & IFF_PROMISC) {
1602 sbmac_promiscuous_mode(s,1);
1603 }
1604
1605}
1606
1607
1608/**********************************************************************
1609 * SBMAC_CHANNEL_STOP(s)
1610 *
1611 * Stop packet processing on this MAC.
1612 *
1613 * Input parameters:
1614 * s - sbmac structure
1615 *
1616 * Return value:
1617 * nothing
1618 ********************************************************************* */
1619
1620static void sbmac_channel_stop(struct sbmac_softc *s)
1621{
1622 /* don't do this if already stopped */
1623
1624 if (s->sbm_state == sbmac_state_off)
1625 return;
1626
1627 /* don't accept any packets, disable all interrupts */
1628
1629 __raw_writeq(0, s->sbm_rxfilter);
1630 __raw_writeq(0, s->sbm_imr);
1631
1632 /* Turn off ticker */
1633
1634 /* XXX */
1635
1636 /* turn off receiver and transmitter */
1637
1638 __raw_writeq(0, s->sbm_macenable);
1639
1640 /* We're stopped now. */
1641
1642 s->sbm_state = sbmac_state_off;
1643
1644 /*
1645 * Stop DMA channels (rings should be ok now)
1646 */
1647
1648 sbdma_channel_stop(&(s->sbm_rxdma));
1649 sbdma_channel_stop(&(s->sbm_txdma));
1650
1651 /* Empty the receive and transmit rings */
1652
1653 sbdma_emptyring(&(s->sbm_rxdma));
1654 sbdma_emptyring(&(s->sbm_txdma));
1655
1656}
1657
1658/**********************************************************************
1659 * SBMAC_SET_CHANNEL_STATE(state)
1660 *
1661 * Set the channel's state ON or OFF
1662 *
1663 * Input parameters:
1664 * state - new state
1665 *
1666 * Return value:
1667 * old state
1668 ********************************************************************* */
1669static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc,
1670 enum sbmac_state state)
1671{
1672 enum sbmac_state oldstate = sc->sbm_state;
1673
1674 /*
1675 * If same as previous state, return
1676 */
1677
1678 if (state == oldstate) {
1679 return oldstate;
1680 }
1681
1682 /*
1683 * If new state is ON, turn channel on
1684 */
1685
1686 if (state == sbmac_state_on) {
1687 sbmac_channel_start(sc);
1688 }
1689 else {
1690 sbmac_channel_stop(sc);
1691 }
1692
1693 /*
1694 * Return previous state
1695 */
1696
1697 return oldstate;
1698}
1699
1700
1701/**********************************************************************
1702 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1703 *
1704 * Turn on or off promiscuous mode
1705 *
1706 * Input parameters:
1707 * sc - softc
1708 * onoff - 1 to turn on, 0 to turn off
1709 *
1710 * Return value:
1711 * nothing
1712 ********************************************************************* */
1713
1714static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1715{
1716 uint64_t reg;
1717
1718 if (sc->sbm_state != sbmac_state_on)
1719 return;
1720
1721 if (onoff) {
1722 reg = __raw_readq(sc->sbm_rxfilter);
1723 reg |= M_MAC_ALLPKT_EN;
1724 __raw_writeq(reg, sc->sbm_rxfilter);
1725 }
1726 else {
1727 reg = __raw_readq(sc->sbm_rxfilter);
1728 reg &= ~M_MAC_ALLPKT_EN;
1729 __raw_writeq(reg, sc->sbm_rxfilter);
1730 }
1731}
1732
1733/**********************************************************************
1734 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1735 *
1736 * Set the iphdr offset as 15 assuming ethernet encapsulation
1737 *
1738 * Input parameters:
1739 * sc - softc
1740 *
1741 * Return value:
1742 * nothing
1743 ********************************************************************* */
1744
1745static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1746{
1747 uint64_t reg;
1748
1749 /* Hard code the off set to 15 for now */
1750 reg = __raw_readq(sc->sbm_rxfilter);
1751 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1752 __raw_writeq(reg, sc->sbm_rxfilter);
1753
1754 /* BCM1250 pass1 didn't have hardware checksum. Everything
1755 later does. */
1756 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1757 sc->rx_hw_checksum = DISABLE;
1758 } else {
1759 sc->rx_hw_checksum = ENABLE;
1760 }
1761}
1762
1763
1764/**********************************************************************
1765 * SBMAC_ADDR2REG(ptr)
1766 *
1767 * Convert six bytes into the 64-bit register value that
1768 * we typically write into the SBMAC's address/mcast registers
1769 *
1770 * Input parameters:
1771 * ptr - pointer to 6 bytes
1772 *
1773 * Return value:
1774 * register value
1775 ********************************************************************* */
1776
1777static uint64_t sbmac_addr2reg(unsigned char *ptr)
1778{
1779 uint64_t reg = 0;
1780
1781 ptr += 6;
1782
1783 reg |= (uint64_t) *(--ptr);
1784 reg <<= 8;
1785 reg |= (uint64_t) *(--ptr);
1786 reg <<= 8;
1787 reg |= (uint64_t) *(--ptr);
1788 reg <<= 8;
1789 reg |= (uint64_t) *(--ptr);
1790 reg <<= 8;
1791 reg |= (uint64_t) *(--ptr);
1792 reg <<= 8;
1793 reg |= (uint64_t) *(--ptr);
1794
1795 return reg;
1796}
1797
1798
1799/**********************************************************************
1800 * SBMAC_SET_SPEED(s,speed)
1801 *
1802 * Configure LAN speed for the specified MAC.
1803 * Warning: must be called when MAC is off!
1804 *
1805 * Input parameters:
1806 * s - sbmac structure
1807 * speed - speed to set MAC to (see enum sbmac_speed)
1808 *
1809 * Return value:
1810 * 1 if successful
1811 * 0 indicates invalid parameters
1812 ********************************************************************* */
1813
1814static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed)
1815{
1816 uint64_t cfg;
1817 uint64_t framecfg;
1818
1819 /*
1820 * Save new current values
1821 */
1822
1823 s->sbm_speed = speed;
1824
1825 if (s->sbm_state == sbmac_state_on)
1826 return 0; /* save for next restart */
1827
1828 /*
1829 * Read current register values
1830 */
1831
1832 cfg = __raw_readq(s->sbm_maccfg);
1833 framecfg = __raw_readq(s->sbm_framecfg);
1834
1835 /*
1836 * Mask out the stuff we want to change
1837 */
1838
1839 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1840 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1841 M_MAC_SLOT_SIZE);
1842
1843 /*
1844 * Now add in the new bits
1845 */
1846
1847 switch (speed) {
1848 case sbmac_speed_10:
1849 framecfg |= V_MAC_IFG_RX_10 |
1850 V_MAC_IFG_TX_10 |
1851 K_MAC_IFG_THRSH_10 |
1852 V_MAC_SLOT_SIZE_10;
1853 cfg |= V_MAC_SPEED_SEL_10MBPS;
1854 break;
1855
1856 case sbmac_speed_100:
1857 framecfg |= V_MAC_IFG_RX_100 |
1858 V_MAC_IFG_TX_100 |
1859 V_MAC_IFG_THRSH_100 |
1860 V_MAC_SLOT_SIZE_100;
1861 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1862 break;
1863
1864 case sbmac_speed_1000:
1865 framecfg |= V_MAC_IFG_RX_1000 |
1866 V_MAC_IFG_TX_1000 |
1867 V_MAC_IFG_THRSH_1000 |
1868 V_MAC_SLOT_SIZE_1000;
1869 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1870 break;
1871
1872 default:
1873 return 0;
1874 }
1875
1876 /*
1877 * Send the bits back to the hardware
1878 */
1879
1880 __raw_writeq(framecfg, s->sbm_framecfg);
1881 __raw_writeq(cfg, s->sbm_maccfg);
1882
1883 return 1;
1884}
1885
1886/**********************************************************************
1887 * SBMAC_SET_DUPLEX(s,duplex,fc)
1888 *
1889 * Set Ethernet duplex and flow control options for this MAC
1890 * Warning: must be called when MAC is off!
1891 *
1892 * Input parameters:
1893 * s - sbmac structure
1894 * duplex - duplex setting (see enum sbmac_duplex)
1895 * fc - flow control setting (see enum sbmac_fc)
1896 *
1897 * Return value:
1898 * 1 if ok
1899 * 0 if an invalid parameter combination was specified
1900 ********************************************************************* */
1901
1902static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
1903 enum sbmac_fc fc)
1904{
1905 uint64_t cfg;
1906
1907 /*
1908 * Save new current values
1909 */
1910
1911 s->sbm_duplex = duplex;
1912 s->sbm_fc = fc;
1913
1914 if (s->sbm_state == sbmac_state_on)
1915 return 0; /* save for next restart */
1916
1917 /*
1918 * Read current register values
1919 */
1920
1921 cfg = __raw_readq(s->sbm_maccfg);
1922
1923 /*
1924 * Mask off the stuff we're about to change
1925 */
1926
1927 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1928
1929
1930 switch (duplex) {
1931 case sbmac_duplex_half:
1932 switch (fc) {
1933 case sbmac_fc_disabled:
1934 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1935 break;
1936
1937 case sbmac_fc_collision:
1938 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1939 break;
1940
1941 case sbmac_fc_carrier:
1942 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
1943 break;
1944
1945 case sbmac_fc_frame: /* not valid in half duplex */
1946 default: /* invalid selection */
1947 return 0;
1948 }
1949 break;
1950
1951 case sbmac_duplex_full:
1952 switch (fc) {
1953 case sbmac_fc_disabled:
1954 cfg |= V_MAC_FC_CMD_DISABLED;
1955 break;
1956
1957 case sbmac_fc_frame:
1958 cfg |= V_MAC_FC_CMD_ENABLED;
1959 break;
1960
1961 case sbmac_fc_collision: /* not valid in full duplex */
1962 case sbmac_fc_carrier: /* not valid in full duplex */
1963 default:
1964 return 0;
1965 }
1966 break;
1967 default:
1968 return 0;
1969 }
1970
1971 /*
1972 * Send the bits back to the hardware
1973 */
1974
1975 __raw_writeq(cfg, s->sbm_maccfg);
1976
1977 return 1;
1978}
1979
1980
1981
1982
1983/**********************************************************************
1984 * SBMAC_INTR()
1985 *
1986 * Interrupt handler for MAC interrupts
1987 *
1988 * Input parameters:
1989 * MAC structure
1990 *
1991 * Return value:
1992 * nothing
1993 ********************************************************************* */
1994static irqreturn_t sbmac_intr(int irq,void *dev_instance)
1995{
1996 struct net_device *dev = (struct net_device *) dev_instance;
1997 struct sbmac_softc *sc = netdev_priv(dev);
1998 uint64_t isr;
1999 int handled = 0;
2000
2001 /*
2002 * Read the ISR (this clears the bits in the real
2003 * register, except for counter addr)
2004 */
2005
2006 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2007
2008 if (isr == 0)
2009 return IRQ_RETVAL(0);
2010 handled = 1;
2011
2012 /*
2013 * Transmits on channel 0
2014 */
2015
2016 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2017 sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2018
2019 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2020 if (napi_schedule_prep(&sc->napi)) {
2021 __raw_writeq(0, sc->sbm_imr);
2022 __napi_schedule(&sc->napi);
2023 /* Depend on the exit from poll to reenable intr */
2024 }
2025 else {
2026 /* may leave some packets behind */
2027 sbdma_rx_process(sc,&(sc->sbm_rxdma),
2028 SBMAC_MAX_RXDESCR * 2, 0);
2029 }
2030 }
2031 return IRQ_RETVAL(handled);
2032}
2033
2034/**********************************************************************
2035 * SBMAC_START_TX(skb,dev)
2036 *
2037 * Start output on the specified interface. Basically, we
2038 * queue as many buffers as we can until the ring fills up, or
2039 * we run off the end of the queue, whichever comes first.
2040 *
2041 * Input parameters:
2042 *
2043 *
2044 * Return value:
2045 * nothing
2046 ********************************************************************* */
2047static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2048{
2049 struct sbmac_softc *sc = netdev_priv(dev);
2050 unsigned long flags;
2051
2052 /* lock eth irq */
2053 spin_lock_irqsave(&sc->sbm_lock, flags);
2054
2055 /*
2056 * Put the buffer on the transmit ring. If we
2057 * don't have room, stop the queue.
2058 */
2059
2060 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2061 /* XXX save skb that we could not send */
2062 netif_stop_queue(dev);
2063 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2064
2065 return NETDEV_TX_BUSY;
2066 }
2067
2068 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2069
2070 return NETDEV_TX_OK;
2071}
2072
2073/**********************************************************************
2074 * SBMAC_SETMULTI(sc)
2075 *
2076 * Reprogram the multicast table into the hardware, given
2077 * the list of multicasts associated with the interface
2078 * structure.
2079 *
2080 * Input parameters:
2081 * sc - softc
2082 *
2083 * Return value:
2084 * nothing
2085 ********************************************************************* */
2086
2087static void sbmac_setmulti(struct sbmac_softc *sc)
2088{
2089 uint64_t reg;
2090 void __iomem *port;
2091 int idx;
2092 struct netdev_hw_addr *ha;
2093 struct net_device *dev = sc->sbm_dev;
2094
2095 /*
2096 * Clear out entire multicast table. We do this by nuking
2097 * the entire hash table and all the direct matches except
2098 * the first one, which is used for our station address
2099 */
2100
2101 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2102 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2103 __raw_writeq(0, port);
2104 }
2105
2106 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2107 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2108 __raw_writeq(0, port);
2109 }
2110
2111 /*
2112 * Clear the filter to say we don't want any multicasts.
2113 */
2114
2115 reg = __raw_readq(sc->sbm_rxfilter);
2116 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2117 __raw_writeq(reg, sc->sbm_rxfilter);
2118
2119 if (dev->flags & IFF_ALLMULTI) {
2120 /*
2121 * Enable ALL multicasts. Do this by inverting the
2122 * multicast enable bit.
2123 */
2124 reg = __raw_readq(sc->sbm_rxfilter);
2125 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2126 __raw_writeq(reg, sc->sbm_rxfilter);
2127 return;
2128 }
2129
2130
2131 /*
2132 * Progam new multicast entries. For now, only use the
2133 * perfect filter. In the future we'll need to use the
2134 * hash filter if the perfect filter overflows
2135 */
2136
2137 /* XXX only using perfect filter for now, need to use hash
2138 * XXX if the table overflows */
2139
2140 idx = 1; /* skip station address */
2141 netdev_for_each_mc_addr(ha, dev) {
2142 if (idx == MAC_ADDR_COUNT)
2143 break;
2144 reg = sbmac_addr2reg(ha->addr);
2145 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2146 __raw_writeq(reg, port);
2147 idx++;
2148 }
2149
2150 /*
2151 * Enable the "accept multicast bits" if we programmed at least one
2152 * multicast.
2153 */
2154
2155 if (idx > 1) {
2156 reg = __raw_readq(sc->sbm_rxfilter);
2157 reg |= M_MAC_MCAST_EN;
2158 __raw_writeq(reg, sc->sbm_rxfilter);
2159 }
2160}
2161
2162static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2163{
2164 if (new_mtu > ENET_PACKET_SIZE)
2165 return -EINVAL;
2166 _dev->mtu = new_mtu;
2167 pr_info("changing the mtu to %d\n", new_mtu);
2168 return 0;
2169}
2170
2171static const struct net_device_ops sbmac_netdev_ops = {
2172 .ndo_open = sbmac_open,
2173 .ndo_stop = sbmac_close,
2174 .ndo_start_xmit = sbmac_start_tx,
2175 .ndo_set_rx_mode = sbmac_set_rx_mode,
2176 .ndo_tx_timeout = sbmac_tx_timeout,
2177 .ndo_do_ioctl = sbmac_mii_ioctl,
2178 .ndo_change_mtu = sb1250_change_mtu,
2179 .ndo_validate_addr = eth_validate_addr,
2180 .ndo_set_mac_address = eth_mac_addr,
2181#ifdef CONFIG_NET_POLL_CONTROLLER
2182 .ndo_poll_controller = sbmac_netpoll,
2183#endif
2184};
2185
2186/**********************************************************************
2187 * SBMAC_INIT(dev)
2188 *
2189 * Attach routine - init hardware and hook ourselves into linux
2190 *
2191 * Input parameters:
2192 * dev - net_device structure
2193 *
2194 * Return value:
2195 * status
2196 ********************************************************************* */
2197
2198static int sbmac_init(struct platform_device *pldev, long long base)
2199{
2200 struct net_device *dev = dev_get_drvdata(&pldev->dev);
2201 int idx = pldev->id;
2202 struct sbmac_softc *sc = netdev_priv(dev);
2203 unsigned char *eaddr;
2204 uint64_t ea_reg;
2205 int i;
2206 int err;
2207
2208 sc->sbm_dev = dev;
2209 sc->sbe_idx = idx;
2210
2211 eaddr = sc->sbm_hwaddr;
2212
2213 /*
2214 * Read the ethernet address. The firmware left this programmed
2215 * for us in the ethernet address register for each mac.
2216 */
2217
2218 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2219 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2220 for (i = 0; i < 6; i++) {
2221 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2222 ea_reg >>= 8;
2223 }
2224
2225 for (i = 0; i < 6; i++) {
2226 dev->dev_addr[i] = eaddr[i];
2227 }
2228
2229 /*
2230 * Initialize context (get pointers to registers and stuff), then
2231 * allocate the memory for the descriptor tables.
2232 */
2233
2234 sbmac_initctx(sc);
2235
2236 /*
2237 * Set up Linux device callins
2238 */
2239
2240 spin_lock_init(&(sc->sbm_lock));
2241
2242 dev->netdev_ops = &sbmac_netdev_ops;
2243 dev->watchdog_timeo = TX_TIMEOUT;
2244
2245 netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2246
2247 dev->irq = UNIT_INT(idx);
2248
2249 /* This is needed for PASS2 for Rx H/W checksum feature */
2250 sbmac_set_iphdr_offset(sc);
2251
2252 sc->mii_bus = mdiobus_alloc();
2253 if (sc->mii_bus == NULL) {
2254 err = -ENOMEM;
2255 goto uninit_ctx;
2256 }
2257
2258 sc->mii_bus->name = sbmac_mdio_string;
2259 snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2260 pldev->name, idx);
2261 sc->mii_bus->priv = sc;
2262 sc->mii_bus->read = sbmac_mii_read;
2263 sc->mii_bus->write = sbmac_mii_write;
2264 sc->mii_bus->irq = sc->phy_irq;
2265 for (i = 0; i < PHY_MAX_ADDR; ++i)
2266 sc->mii_bus->irq[i] = SBMAC_PHY_INT;
2267
2268 sc->mii_bus->parent = &pldev->dev;
2269 /*
2270 * Probe PHY address
2271 */
2272 err = mdiobus_register(sc->mii_bus);
2273 if (err) {
2274 printk(KERN_ERR "%s: unable to register MDIO bus\n",
2275 dev->name);
2276 goto free_mdio;
2277 }
2278 dev_set_drvdata(&pldev->dev, sc->mii_bus);
2279
2280 err = register_netdev(dev);
2281 if (err) {
2282 printk(KERN_ERR "%s.%d: unable to register netdev\n",
2283 sbmac_string, idx);
2284 goto unreg_mdio;
2285 }
2286
2287 pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name);
2288
2289 if (sc->rx_hw_checksum == ENABLE)
2290 pr_info("%s: enabling TCP rcv checksum\n", dev->name);
2291
2292 /*
2293 * Display Ethernet address (this is called during the config
2294 * process so we need to finish off the config message that
2295 * was being displayed)
2296 */
2297 pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n",
2298 dev->name, base, eaddr);
2299
2300 return 0;
2301unreg_mdio:
2302 mdiobus_unregister(sc->mii_bus);
2303 dev_set_drvdata(&pldev->dev, NULL);
2304free_mdio:
2305 mdiobus_free(sc->mii_bus);
2306uninit_ctx:
2307 sbmac_uninitctx(sc);
2308 return err;
2309}
2310
2311
2312static int sbmac_open(struct net_device *dev)
2313{
2314 struct sbmac_softc *sc = netdev_priv(dev);
2315 int err;
2316
2317 if (debug > 1)
2318 pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2319
2320 /*
2321 * map/route interrupt (clear status first, in case something
2322 * weird is pending; we haven't initialized the mac registers
2323 * yet)
2324 */
2325
2326 __raw_readq(sc->sbm_isr);
2327 err = request_irq(dev->irq, sbmac_intr, IRQF_SHARED, dev->name, dev);
2328 if (err) {
2329 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name,
2330 dev->irq);
2331 goto out_err;
2332 }
2333
2334 sc->sbm_speed = sbmac_speed_none;
2335 sc->sbm_duplex = sbmac_duplex_none;
2336 sc->sbm_fc = sbmac_fc_none;
2337 sc->sbm_pause = -1;
2338 sc->sbm_link = 0;
2339
2340 /*
2341 * Attach to the PHY
2342 */
2343 err = sbmac_mii_probe(dev);
2344 if (err)
2345 goto out_unregister;
2346
2347 /*
2348 * Turn on the channel
2349 */
2350
2351 sbmac_set_channel_state(sc,sbmac_state_on);
2352
2353 netif_start_queue(dev);
2354
2355 sbmac_set_rx_mode(dev);
2356
2357 phy_start(sc->phy_dev);
2358
2359 napi_enable(&sc->napi);
2360
2361 return 0;
2362
2363out_unregister:
2364 free_irq(dev->irq, dev);
2365out_err:
2366 return err;
2367}
2368
2369static int sbmac_mii_probe(struct net_device *dev)
2370{
2371 struct sbmac_softc *sc = netdev_priv(dev);
2372 struct phy_device *phy_dev;
2373 int i;
2374
2375 for (i = 0; i < PHY_MAX_ADDR; i++) {
2376 phy_dev = sc->mii_bus->phy_map[i];
2377 if (phy_dev)
2378 break;
2379 }
2380 if (!phy_dev) {
2381 printk(KERN_ERR "%s: no PHY found\n", dev->name);
2382 return -ENXIO;
2383 }
2384
2385 phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), &sbmac_mii_poll,
2386 PHY_INTERFACE_MODE_GMII);
2387 if (IS_ERR(phy_dev)) {
2388 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
2389 return PTR_ERR(phy_dev);
2390 }
2391
2392 /* Remove any features not supported by the controller */
2393 phy_dev->supported &= SUPPORTED_10baseT_Half |
2394 SUPPORTED_10baseT_Full |
2395 SUPPORTED_100baseT_Half |
2396 SUPPORTED_100baseT_Full |
2397 SUPPORTED_1000baseT_Half |
2398 SUPPORTED_1000baseT_Full |
2399 SUPPORTED_Autoneg |
2400 SUPPORTED_MII |
2401 SUPPORTED_Pause |
2402 SUPPORTED_Asym_Pause;
2403 phy_dev->advertising = phy_dev->supported;
2404
2405 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2406 dev->name, phy_dev->drv->name,
2407 dev_name(&phy_dev->dev), phy_dev->irq);
2408
2409 sc->phy_dev = phy_dev;
2410
2411 return 0;
2412}
2413
2414
2415static void sbmac_mii_poll(struct net_device *dev)
2416{
2417 struct sbmac_softc *sc = netdev_priv(dev);
2418 struct phy_device *phy_dev = sc->phy_dev;
2419 unsigned long flags;
2420 enum sbmac_fc fc;
2421 int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg;
2422
2423 link_chg = (sc->sbm_link != phy_dev->link);
2424 speed_chg = (sc->sbm_speed != phy_dev->speed);
2425 duplex_chg = (sc->sbm_duplex != phy_dev->duplex);
2426 pause_chg = (sc->sbm_pause != phy_dev->pause);
2427
2428 if (!link_chg && !speed_chg && !duplex_chg && !pause_chg)
2429 return; /* Hmmm... */
2430
2431 if (!phy_dev->link) {
2432 if (link_chg) {
2433 sc->sbm_link = phy_dev->link;
2434 sc->sbm_speed = sbmac_speed_none;
2435 sc->sbm_duplex = sbmac_duplex_none;
2436 sc->sbm_fc = sbmac_fc_disabled;
2437 sc->sbm_pause = -1;
2438 pr_info("%s: link unavailable\n", dev->name);
2439 }
2440 return;
2441 }
2442
2443 if (phy_dev->duplex == DUPLEX_FULL) {
2444 if (phy_dev->pause)
2445 fc = sbmac_fc_frame;
2446 else
2447 fc = sbmac_fc_disabled;
2448 } else
2449 fc = sbmac_fc_collision;
2450 fc_chg = (sc->sbm_fc != fc);
2451
2452 pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed,
2453 phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H');
2454
2455 spin_lock_irqsave(&sc->sbm_lock, flags);
2456
2457 sc->sbm_speed = phy_dev->speed;
2458 sc->sbm_duplex = phy_dev->duplex;
2459 sc->sbm_fc = fc;
2460 sc->sbm_pause = phy_dev->pause;
2461 sc->sbm_link = phy_dev->link;
2462
2463 if ((speed_chg || duplex_chg || fc_chg) &&
2464 sc->sbm_state != sbmac_state_off) {
2465 /*
2466 * something changed, restart the channel
2467 */
2468 if (debug > 1)
2469 pr_debug("%s: restarting channel "
2470 "because PHY state changed\n", dev->name);
2471 sbmac_channel_stop(sc);
2472 sbmac_channel_start(sc);
2473 }
2474
2475 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2476}
2477
2478
2479static void sbmac_tx_timeout (struct net_device *dev)
2480{
2481 struct sbmac_softc *sc = netdev_priv(dev);
2482 unsigned long flags;
2483
2484 spin_lock_irqsave(&sc->sbm_lock, flags);
2485
2486
2487 dev->trans_start = jiffies; /* prevent tx timeout */
2488 dev->stats.tx_errors++;
2489
2490 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2491
2492 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2493}
2494
2495
2496
2497
2498static void sbmac_set_rx_mode(struct net_device *dev)
2499{
2500 unsigned long flags;
2501 struct sbmac_softc *sc = netdev_priv(dev);
2502
2503 spin_lock_irqsave(&sc->sbm_lock, flags);
2504 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2505 /*
2506 * Promiscuous changed.
2507 */
2508
2509 if (dev->flags & IFF_PROMISC) {
2510 sbmac_promiscuous_mode(sc,1);
2511 }
2512 else {
2513 sbmac_promiscuous_mode(sc,0);
2514 }
2515 }
2516 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2517
2518 /*
2519 * Program the multicasts. Do this every time.
2520 */
2521
2522 sbmac_setmulti(sc);
2523
2524}
2525
2526static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2527{
2528 struct sbmac_softc *sc = netdev_priv(dev);
2529
2530 if (!netif_running(dev) || !sc->phy_dev)
2531 return -EINVAL;
2532
2533 return phy_mii_ioctl(sc->phy_dev, rq, cmd);
2534}
2535
2536static int sbmac_close(struct net_device *dev)
2537{
2538 struct sbmac_softc *sc = netdev_priv(dev);
2539
2540 napi_disable(&sc->napi);
2541
2542 phy_stop(sc->phy_dev);
2543
2544 sbmac_set_channel_state(sc, sbmac_state_off);
2545
2546 netif_stop_queue(dev);
2547
2548 if (debug > 1)
2549 pr_debug("%s: Shutting down ethercard\n", dev->name);
2550
2551 phy_disconnect(sc->phy_dev);
2552 sc->phy_dev = NULL;
2553 free_irq(dev->irq, dev);
2554
2555 sbdma_emptyring(&(sc->sbm_txdma));
2556 sbdma_emptyring(&(sc->sbm_rxdma));
2557
2558 return 0;
2559}
2560
2561static int sbmac_poll(struct napi_struct *napi, int budget)
2562{
2563 struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2564 int work_done;
2565
2566 work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2567 sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2568
2569 if (work_done < budget) {
2570 napi_complete(napi);
2571
2572#ifdef CONFIG_SBMAC_COALESCE
2573 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2574 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2575 sc->sbm_imr);
2576#else
2577 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2578 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2579#endif
2580 }
2581
2582 return work_done;
2583}
2584
2585
2586static int sbmac_probe(struct platform_device *pldev)
2587{
2588 struct net_device *dev;
2589 struct sbmac_softc *sc;
2590 void __iomem *sbm_base;
2591 struct resource *res;
2592 u64 sbmac_orig_hwaddr;
2593 int err;
2594
2595 res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
2596 BUG_ON(!res);
2597 sbm_base = ioremap_nocache(res->start, resource_size(res));
2598 if (!sbm_base) {
2599 printk(KERN_ERR "%s: unable to map device registers\n",
2600 dev_name(&pldev->dev));
2601 err = -ENOMEM;
2602 goto out_out;
2603 }
2604
2605 /*
2606 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2607 * value for us by the firmware if we're going to use this MAC.
2608 * If we find a zero, skip this MAC.
2609 */
2610 sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2611 pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev),
2612 sbmac_orig_hwaddr ? "" : "not ", (long long)res->start);
2613 if (sbmac_orig_hwaddr == 0) {
2614 err = 0;
2615 goto out_unmap;
2616 }
2617
2618 /*
2619 * Okay, cool. Initialize this MAC.
2620 */
2621 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2622 if (!dev) {
2623 err = -ENOMEM;
2624 goto out_unmap;
2625 }
2626
2627 dev_set_drvdata(&pldev->dev, dev);
2628 SET_NETDEV_DEV(dev, &pldev->dev);
2629
2630 sc = netdev_priv(dev);
2631 sc->sbm_base = sbm_base;
2632
2633 err = sbmac_init(pldev, res->start);
2634 if (err)
2635 goto out_kfree;
2636
2637 return 0;
2638
2639out_kfree:
2640 free_netdev(dev);
2641 __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR);
2642
2643out_unmap:
2644 iounmap(sbm_base);
2645
2646out_out:
2647 return err;
2648}
2649
2650static int __exit sbmac_remove(struct platform_device *pldev)
2651{
2652 struct net_device *dev = dev_get_drvdata(&pldev->dev);
2653 struct sbmac_softc *sc = netdev_priv(dev);
2654
2655 unregister_netdev(dev);
2656 sbmac_uninitctx(sc);
2657 mdiobus_unregister(sc->mii_bus);
2658 mdiobus_free(sc->mii_bus);
2659 iounmap(sc->sbm_base);
2660 free_netdev(dev);
2661
2662 return 0;
2663}
2664
2665static struct platform_driver sbmac_driver = {
2666 .probe = sbmac_probe,
2667 .remove = __exit_p(sbmac_remove),
2668 .driver = {
2669 .name = sbmac_string,
2670 .owner = THIS_MODULE,
2671 },
2672};
2673
2674module_platform_driver(sbmac_driver);
kernel source for telekom puls (alcatel/mediatek)