| 1 | /* bnx2x_hsi.h: Broadcom Everest network driver. |
| 2 | * |
| 3 | * Copyright (c) 2007-2009 Broadcom Corporation |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation. |
| 8 | */ |
| 9 | |
| 10 | |
| 11 | #define PORT_0 0 |
| 12 | #define PORT_1 1 |
| 13 | #define PORT_MAX 2 |
| 14 | |
| 15 | /**************************************************************************** |
| 16 | * Shared HW configuration * |
| 17 | ****************************************************************************/ |
| 18 | struct shared_hw_cfg { /* NVRAM Offset */ |
| 19 | /* Up to 16 bytes of NULL-terminated string */ |
| 20 | u8 part_num[16]; /* 0x104 */ |
| 21 | |
| 22 | u32 config; /* 0x114 */ |
| 23 | #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 |
| 24 | #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 |
| 25 | #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 |
| 26 | #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 |
| 27 | #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 |
| 28 | |
| 29 | #define SHARED_HW_CFG_PORT_SWAP 0x00000004 |
| 30 | |
| 31 | #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 |
| 32 | |
| 33 | #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 |
| 34 | #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 |
| 35 | /* Whatever MFW found in NVM |
| 36 | (if multiple found, priority order is: NC-SI, UMP, IPMI) */ |
| 37 | #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 |
| 38 | #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 |
| 39 | #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 |
| 40 | #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 |
| 41 | /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI |
| 42 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ |
| 43 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 |
| 44 | /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI |
| 45 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ |
| 46 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 |
| 47 | /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP |
| 48 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ |
| 49 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 |
| 50 | |
| 51 | #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 |
| 52 | #define SHARED_HW_CFG_LED_MODE_SHIFT 16 |
| 53 | #define SHARED_HW_CFG_LED_MAC1 0x00000000 |
| 54 | #define SHARED_HW_CFG_LED_PHY1 0x00010000 |
| 55 | #define SHARED_HW_CFG_LED_PHY2 0x00020000 |
| 56 | #define SHARED_HW_CFG_LED_PHY3 0x00030000 |
| 57 | #define SHARED_HW_CFG_LED_MAC2 0x00040000 |
| 58 | #define SHARED_HW_CFG_LED_PHY4 0x00050000 |
| 59 | #define SHARED_HW_CFG_LED_PHY5 0x00060000 |
| 60 | #define SHARED_HW_CFG_LED_PHY6 0x00070000 |
| 61 | #define SHARED_HW_CFG_LED_MAC3 0x00080000 |
| 62 | #define SHARED_HW_CFG_LED_PHY7 0x00090000 |
| 63 | #define SHARED_HW_CFG_LED_PHY9 0x000a0000 |
| 64 | #define SHARED_HW_CFG_LED_PHY11 0x000b0000 |
| 65 | #define SHARED_HW_CFG_LED_MAC4 0x000c0000 |
| 66 | #define SHARED_HW_CFG_LED_PHY8 0x000d0000 |
| 67 | |
| 68 | #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 |
| 69 | #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 |
| 70 | #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 |
| 71 | #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 |
| 72 | #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 |
| 73 | #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 |
| 74 | #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 |
| 75 | #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 |
| 76 | |
| 77 | u32 config2; /* 0x118 */ |
| 78 | /* one time auto detect grace period (in sec) */ |
| 79 | #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff |
| 80 | #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 |
| 81 | |
| 82 | #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 |
| 83 | |
| 84 | /* The default value for the core clock is 250MHz and it is |
| 85 | achieved by setting the clock change to 4 */ |
| 86 | #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 |
| 87 | #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 |
| 88 | |
| 89 | #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 |
| 90 | #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 |
| 91 | |
| 92 | #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 |
| 93 | |
| 94 | /* The fan failure mechanism is usually related to the PHY type |
| 95 | since the power consumption of the board is determined by the PHY. |
| 96 | Currently, fan is required for most designs with SFX7101, BCM8727 |
| 97 | and BCM8481. If a fan is not required for a board which uses one |
| 98 | of those PHYs, this field should be set to "Disabled". If a fan is |
| 99 | required for a different PHY type, this option should be set to |
| 100 | "Enabled". |
| 101 | The fan failure indication is expected on |
| 102 | SPIO5 */ |
| 103 | #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 |
| 104 | #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 |
| 105 | #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 |
| 106 | #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 |
| 107 | #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 |
| 108 | |
| 109 | u32 power_dissipated; /* 0x11c */ |
| 110 | #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 |
| 111 | #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 |
| 112 | |
| 113 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 |
| 114 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 |
| 115 | #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 |
| 116 | #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 |
| 117 | #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 |
| 118 | #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 |
| 119 | |
| 120 | u32 ump_nc_si_config; /* 0x120 */ |
| 121 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 |
| 122 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 |
| 123 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 |
| 124 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 |
| 125 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 |
| 126 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 |
| 127 | |
| 128 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 |
| 129 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 |
| 130 | |
| 131 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 |
| 132 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 |
| 133 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 |
| 134 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 |
| 135 | |
| 136 | u32 board; /* 0x124 */ |
| 137 | #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 |
| 138 | #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 |
| 139 | |
| 140 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 |
| 141 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 |
| 142 | |
| 143 | #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 |
| 144 | #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 |
| 145 | |
| 146 | u32 reserved; /* 0x128 */ |
| 147 | |
| 148 | }; |
| 149 | |
| 150 | |
| 151 | /**************************************************************************** |
| 152 | * Port HW configuration * |
| 153 | ****************************************************************************/ |
| 154 | struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ |
| 155 | |
| 156 | u32 pci_id; |
| 157 | #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 |
| 158 | #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff |
| 159 | |
| 160 | u32 pci_sub_id; |
| 161 | #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 |
| 162 | #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff |
| 163 | |
| 164 | u32 power_dissipated; |
| 165 | #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 |
| 166 | #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 |
| 167 | #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 |
| 168 | #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 |
| 169 | #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 |
| 170 | #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 |
| 171 | #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff |
| 172 | #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 |
| 173 | |
| 174 | u32 power_consumed; |
| 175 | #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 |
| 176 | #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 |
| 177 | #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 |
| 178 | #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 |
| 179 | #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 |
| 180 | #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 |
| 181 | #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff |
| 182 | #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 |
| 183 | |
| 184 | u32 mac_upper; |
| 185 | #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff |
| 186 | #define PORT_HW_CFG_UPPERMAC_SHIFT 0 |
| 187 | u32 mac_lower; |
| 188 | |
| 189 | u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ |
| 190 | u32 iscsi_mac_lower; |
| 191 | |
| 192 | u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ |
| 193 | u32 rdma_mac_lower; |
| 194 | |
| 195 | u32 serdes_config; |
| 196 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF |
| 197 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 |
| 198 | |
| 199 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 |
| 200 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 |
| 201 | |
| 202 | |
| 203 | u32 Reserved0[16]; /* 0x158 */ |
| 204 | |
| 205 | /* for external PHY, or forced mode or during AN */ |
| 206 | u16 xgxs_config_rx[4]; /* 0x198 */ |
| 207 | |
| 208 | u16 xgxs_config_tx[4]; /* 0x1A0 */ |
| 209 | |
| 210 | u32 Reserved1[64]; /* 0x1A8 */ |
| 211 | |
| 212 | u32 lane_config; |
| 213 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff |
| 214 | #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 |
| 215 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff |
| 216 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 |
| 217 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 |
| 218 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 |
| 219 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 |
| 220 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 |
| 221 | /* AN and forced */ |
| 222 | #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b |
| 223 | /* forced only */ |
| 224 | #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 |
| 225 | /* forced only */ |
| 226 | #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 |
| 227 | /* forced only */ |
| 228 | #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 |
| 229 | |
| 230 | u32 external_phy_config; |
| 231 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 |
| 232 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 |
| 233 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 |
| 234 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 |
| 235 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 |
| 236 | |
| 237 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 |
| 238 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 |
| 239 | |
| 240 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 |
| 241 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 |
| 242 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 |
| 243 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 |
| 244 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 |
| 245 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 |
| 246 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 |
| 247 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 |
| 248 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 |
| 249 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 |
| 250 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 |
| 251 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 |
| 252 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 |
| 253 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 |
| 254 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 |
| 255 | |
| 256 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff |
| 257 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 |
| 258 | |
| 259 | u32 speed_capability_mask; |
| 260 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 |
| 261 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 |
| 262 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 |
| 263 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 |
| 264 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 |
| 265 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 |
| 266 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 |
| 267 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 |
| 268 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 |
| 269 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000 |
| 270 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000 |
| 271 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000 |
| 272 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000 |
| 273 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000 |
| 274 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 |
| 275 | |
| 276 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff |
| 277 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 |
| 278 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 |
| 279 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 |
| 280 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 |
| 281 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 |
| 282 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 |
| 283 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 |
| 284 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 |
| 285 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080 |
| 286 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100 |
| 287 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200 |
| 288 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400 |
| 289 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800 |
| 290 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 |
| 291 | |
| 292 | u32 reserved[2]; |
| 293 | |
| 294 | }; |
| 295 | |
| 296 | |
| 297 | /**************************************************************************** |
| 298 | * Shared Feature configuration * |
| 299 | ****************************************************************************/ |
| 300 | struct shared_feat_cfg { /* NVRAM Offset */ |
| 301 | |
| 302 | u32 config; /* 0x450 */ |
| 303 | #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 |
| 304 | |
| 305 | /* Use the values from options 47 and 48 instead of the HW default |
| 306 | values */ |
| 307 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000 |
| 308 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002 |
| 309 | |
| 310 | #define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100 |
| 311 | |
| 312 | }; |
| 313 | |
| 314 | |
| 315 | /**************************************************************************** |
| 316 | * Port Feature configuration * |
| 317 | ****************************************************************************/ |
| 318 | struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ |
| 319 | |
| 320 | u32 config; |
| 321 | #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f |
| 322 | #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 |
| 323 | #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 |
| 324 | #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 |
| 325 | #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 |
| 326 | #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 |
| 327 | #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 |
| 328 | #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 |
| 329 | #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 |
| 330 | #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 |
| 331 | #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 |
| 332 | #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 |
| 333 | #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a |
| 334 | #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b |
| 335 | #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c |
| 336 | #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d |
| 337 | #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e |
| 338 | #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f |
| 339 | #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 |
| 340 | #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 |
| 341 | #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 |
| 342 | #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 |
| 343 | #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 |
| 344 | #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 |
| 345 | #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 |
| 346 | #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 |
| 347 | #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 |
| 348 | #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 |
| 349 | #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 |
| 350 | #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 |
| 351 | #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 |
| 352 | #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 |
| 353 | #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 |
| 354 | #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 |
| 355 | #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 |
| 356 | #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 |
| 357 | #define PORT_FEATURE_EN_SIZE_MASK 0x07000000 |
| 358 | #define PORT_FEATURE_EN_SIZE_SHIFT 24 |
| 359 | #define PORT_FEATURE_WOL_ENABLED 0x01000000 |
| 360 | #define PORT_FEATURE_MBA_ENABLED 0x02000000 |
| 361 | #define PORT_FEATURE_MFW_ENABLED 0x04000000 |
| 362 | |
| 363 | /* Reserved bits: 28-29 */ |
| 364 | /* Check the optic vendor via i2c against a list of approved modules |
| 365 | in a separate nvram image */ |
| 366 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 |
| 367 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 |
| 368 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000 |
| 369 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000 |
| 370 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 |
| 371 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 |
| 372 | |
| 373 | |
| 374 | u32 wol_config; |
| 375 | /* Default is used when driver sets to "auto" mode */ |
| 376 | #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 |
| 377 | #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 |
| 378 | #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 |
| 379 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 |
| 380 | #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 |
| 381 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 |
| 382 | #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 |
| 383 | #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 |
| 384 | #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 |
| 385 | |
| 386 | u32 mba_config; |
| 387 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003 |
| 388 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 |
| 389 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 |
| 390 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 |
| 391 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 |
| 392 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 |
| 393 | #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 |
| 394 | #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 |
| 395 | #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 |
| 396 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 |
| 397 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 |
| 398 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 |
| 399 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 |
| 400 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 |
| 401 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 |
| 402 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 |
| 403 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 |
| 404 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 |
| 405 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 |
| 406 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 |
| 407 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 |
| 408 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 |
| 409 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 |
| 410 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 |
| 411 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 |
| 412 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 |
| 413 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 |
| 414 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 |
| 415 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 |
| 416 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 |
| 417 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 |
| 418 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 |
| 419 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 |
| 420 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 |
| 421 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 |
| 422 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 |
| 423 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 |
| 424 | #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 |
| 425 | #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 |
| 426 | #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 |
| 427 | #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 |
| 428 | #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 |
| 429 | #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 |
| 430 | #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 |
| 431 | #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 |
| 432 | #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 |
| 433 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 |
| 434 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000 |
| 435 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000 |
| 436 | #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000 |
| 437 | #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000 |
| 438 | #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000 |
| 439 | #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000 |
| 440 | #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000 |
| 441 | |
| 442 | u32 bmc_config; |
| 443 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 |
| 444 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 |
| 445 | |
| 446 | u32 mba_vlan_cfg; |
| 447 | #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff |
| 448 | #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 |
| 449 | #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 |
| 450 | |
| 451 | u32 resource_cfg; |
| 452 | #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 |
| 453 | #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 |
| 454 | #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 |
| 455 | #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 |
| 456 | #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 |
| 457 | |
| 458 | u32 smbus_config; |
| 459 | /* Obsolete */ |
| 460 | #define PORT_FEATURE_SMBUS_EN 0x00000001 |
| 461 | #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe |
| 462 | #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 |
| 463 | |
| 464 | u32 reserved1; |
| 465 | |
| 466 | u32 link_config; /* Used as HW defaults for the driver */ |
| 467 | #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 |
| 468 | #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 |
| 469 | /* (forced) low speed switch (< 10G) */ |
| 470 | #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 |
| 471 | /* (forced) high speed switch (>= 10G) */ |
| 472 | #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 |
| 473 | #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 |
| 474 | #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 |
| 475 | |
| 476 | #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 |
| 477 | #define PORT_FEATURE_LINK_SPEED_SHIFT 16 |
| 478 | #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 |
| 479 | #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 |
| 480 | #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 |
| 481 | #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 |
| 482 | #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 |
| 483 | #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 |
| 484 | #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 |
| 485 | #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 |
| 486 | #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000 |
| 487 | #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000 |
| 488 | #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000 |
| 489 | #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000 |
| 490 | #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000 |
| 491 | #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000 |
| 492 | #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000 |
| 493 | |
| 494 | #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 |
| 495 | #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 |
| 496 | #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 |
| 497 | #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 |
| 498 | #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 |
| 499 | #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 |
| 500 | #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 |
| 501 | |
| 502 | /* The default for MCP link configuration, |
| 503 | uses the same defines as link_config */ |
| 504 | u32 mfw_wol_link_cfg; |
| 505 | |
| 506 | u32 reserved[19]; |
| 507 | |
| 508 | }; |
| 509 | |
| 510 | |
| 511 | /**************************************************************************** |
| 512 | * Device Information * |
| 513 | ****************************************************************************/ |
| 514 | struct shm_dev_info { /* size */ |
| 515 | |
| 516 | u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ |
| 517 | |
| 518 | struct shared_hw_cfg shared_hw_config; /* 40 */ |
| 519 | |
| 520 | struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ |
| 521 | |
| 522 | struct shared_feat_cfg shared_feature_config; /* 4 */ |
| 523 | |
| 524 | struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ |
| 525 | |
| 526 | }; |
| 527 | |
| 528 | |
| 529 | #define FUNC_0 0 |
| 530 | #define FUNC_1 1 |
| 531 | #define FUNC_2 2 |
| 532 | #define FUNC_3 3 |
| 533 | #define FUNC_4 4 |
| 534 | #define FUNC_5 5 |
| 535 | #define FUNC_6 6 |
| 536 | #define FUNC_7 7 |
| 537 | #define E1_FUNC_MAX 2 |
| 538 | #define E1H_FUNC_MAX 8 |
| 539 | |
| 540 | #define VN_0 0 |
| 541 | #define VN_1 1 |
| 542 | #define VN_2 2 |
| 543 | #define VN_3 3 |
| 544 | #define E1VN_MAX 1 |
| 545 | #define E1HVN_MAX 4 |
| 546 | |
| 547 | |
| 548 | /* This value (in milliseconds) determines the frequency of the driver |
| 549 | * issuing the PULSE message code. The firmware monitors this periodic |
| 550 | * pulse to determine when to switch to an OS-absent mode. */ |
| 551 | #define DRV_PULSE_PERIOD_MS 250 |
| 552 | |
| 553 | /* This value (in milliseconds) determines how long the driver should |
| 554 | * wait for an acknowledgement from the firmware before timing out. Once |
| 555 | * the firmware has timed out, the driver will assume there is no firmware |
| 556 | * running and there won't be any firmware-driver synchronization during a |
| 557 | * driver reset. */ |
| 558 | #define FW_ACK_TIME_OUT_MS 5000 |
| 559 | |
| 560 | #define FW_ACK_POLL_TIME_MS 1 |
| 561 | |
| 562 | #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) |
| 563 | |
| 564 | /* LED Blink rate that will achieve ~15.9Hz */ |
| 565 | #define LED_BLINK_RATE_VAL 480 |
| 566 | |
| 567 | /**************************************************************************** |
| 568 | * Driver <-> FW Mailbox * |
| 569 | ****************************************************************************/ |
| 570 | struct drv_port_mb { |
| 571 | |
| 572 | u32 link_status; |
| 573 | /* Driver should update this field on any link change event */ |
| 574 | |
| 575 | #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 |
| 576 | #define LINK_STATUS_LINK_UP 0x00000001 |
| 577 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E |
| 578 | #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) |
| 579 | #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) |
| 580 | #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) |
| 581 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) |
| 582 | #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) |
| 583 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) |
| 584 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) |
| 585 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) |
| 586 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) |
| 587 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) |
| 588 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) |
| 589 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) |
| 590 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) |
| 591 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) |
| 592 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1) |
| 593 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1) |
| 594 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1) |
| 595 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1) |
| 596 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1) |
| 597 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1) |
| 598 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1) |
| 599 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1) |
| 600 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1) |
| 601 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1) |
| 602 | |
| 603 | #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 |
| 604 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 |
| 605 | |
| 606 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 |
| 607 | #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 |
| 608 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 |
| 609 | |
| 610 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 |
| 611 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 |
| 612 | #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 |
| 613 | #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 |
| 614 | #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 |
| 615 | #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 |
| 616 | #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 |
| 617 | |
| 618 | #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 |
| 619 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 |
| 620 | |
| 621 | #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 |
| 622 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 |
| 623 | |
| 624 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 |
| 625 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) |
| 626 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) |
| 627 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) |
| 628 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) |
| 629 | |
| 630 | #define LINK_STATUS_SERDES_LINK 0x00100000 |
| 631 | |
| 632 | #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 |
| 633 | #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 |
| 634 | #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 |
| 635 | #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000 |
| 636 | #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000 |
| 637 | #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000 |
| 638 | #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000 |
| 639 | #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000 |
| 640 | |
| 641 | u32 port_stx; |
| 642 | |
| 643 | u32 stat_nig_timer; |
| 644 | |
| 645 | /* MCP firmware does not use this field */ |
| 646 | u32 ext_phy_fw_version; |
| 647 | |
| 648 | }; |
| 649 | |
| 650 | |
| 651 | struct drv_func_mb { |
| 652 | |
| 653 | u32 drv_mb_header; |
| 654 | #define DRV_MSG_CODE_MASK 0xffff0000 |
| 655 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 |
| 656 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 |
| 657 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 |
| 658 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 |
| 659 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 |
| 660 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 |
| 661 | #define DRV_MSG_CODE_DCC_OK 0x30000000 |
| 662 | #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 |
| 663 | #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 |
| 664 | #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 |
| 665 | #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 |
| 666 | #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 |
| 667 | #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 |
| 668 | #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 |
| 669 | #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 |
| 670 | /* |
| 671 | * The optic module verification commands requris bootcode |
| 672 | * v5.0.6 or later |
| 673 | */ |
| 674 | #define DRV_MSG_CODE_VRFY_OPT_MDL 0xa0000000 |
| 675 | #define REQ_BC_VER_4_VRFY_OPT_MDL 0x00050006 |
| 676 | |
| 677 | #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 |
| 678 | #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 |
| 679 | #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 |
| 680 | #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 |
| 681 | |
| 682 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff |
| 683 | |
| 684 | u32 drv_mb_param; |
| 685 | |
| 686 | u32 fw_mb_header; |
| 687 | #define FW_MSG_CODE_MASK 0xffff0000 |
| 688 | #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 |
| 689 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 |
| 690 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 |
| 691 | #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 |
| 692 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 |
| 693 | #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 |
| 694 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 |
| 695 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 |
| 696 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 |
| 697 | #define FW_MSG_CODE_DCC_DONE 0x30100000 |
| 698 | #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 |
| 699 | #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 |
| 700 | #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 |
| 701 | #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 |
| 702 | #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 |
| 703 | #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 |
| 704 | #define FW_MSG_CODE_NO_KEY 0x80f00000 |
| 705 | #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 |
| 706 | #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 |
| 707 | #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 |
| 708 | #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 |
| 709 | #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 |
| 710 | #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 |
| 711 | #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 |
| 712 | #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 |
| 713 | #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 |
| 714 | |
| 715 | #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 |
| 716 | #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 |
| 717 | #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 |
| 718 | #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 |
| 719 | |
| 720 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff |
| 721 | |
| 722 | u32 fw_mb_param; |
| 723 | |
| 724 | u32 drv_pulse_mb; |
| 725 | #define DRV_PULSE_SEQ_MASK 0x00007fff |
| 726 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 |
| 727 | /* The system time is in the format of |
| 728 | * (year-2001)*12*32 + month*32 + day. */ |
| 729 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 |
| 730 | /* Indicate to the firmware not to go into the |
| 731 | * OS-absent when it is not getting driver pulse. |
| 732 | * This is used for debugging as well for PXE(MBA). */ |
| 733 | |
| 734 | u32 mcp_pulse_mb; |
| 735 | #define MCP_PULSE_SEQ_MASK 0x00007fff |
| 736 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 |
| 737 | /* Indicates to the driver not to assert due to lack |
| 738 | * of MCP response */ |
| 739 | #define MCP_EVENT_MASK 0xffff0000 |
| 740 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 |
| 741 | |
| 742 | u32 iscsi_boot_signature; |
| 743 | u32 iscsi_boot_block_offset; |
| 744 | |
| 745 | u32 drv_status; |
| 746 | #define DRV_STATUS_PMF 0x00000001 |
| 747 | |
| 748 | #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 |
| 749 | #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 |
| 750 | #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 |
| 751 | #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 |
| 752 | #define DRV_STATUS_DCC_RESERVED1 0x00000800 |
| 753 | #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 |
| 754 | #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 |
| 755 | |
| 756 | u32 virt_mac_upper; |
| 757 | #define VIRT_MAC_SIGN_MASK 0xffff0000 |
| 758 | #define VIRT_MAC_SIGNATURE 0x564d0000 |
| 759 | u32 virt_mac_lower; |
| 760 | |
| 761 | }; |
| 762 | |
| 763 | |
| 764 | /**************************************************************************** |
| 765 | * Management firmware state * |
| 766 | ****************************************************************************/ |
| 767 | /* Allocate 440 bytes for management firmware */ |
| 768 | #define MGMTFW_STATE_WORD_SIZE 110 |
| 769 | |
| 770 | struct mgmtfw_state { |
| 771 | u32 opaque[MGMTFW_STATE_WORD_SIZE]; |
| 772 | }; |
| 773 | |
| 774 | |
| 775 | /**************************************************************************** |
| 776 | * Multi-Function configuration * |
| 777 | ****************************************************************************/ |
| 778 | struct shared_mf_cfg { |
| 779 | |
| 780 | u32 clp_mb; |
| 781 | #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 |
| 782 | /* set by CLP */ |
| 783 | #define SHARED_MF_CLP_EXIT 0x00000001 |
| 784 | /* set by MCP */ |
| 785 | #define SHARED_MF_CLP_EXIT_DONE 0x00010000 |
| 786 | |
| 787 | }; |
| 788 | |
| 789 | struct port_mf_cfg { |
| 790 | |
| 791 | u32 dynamic_cfg; /* device control channel */ |
| 792 | #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff |
| 793 | #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 |
| 794 | #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK |
| 795 | |
| 796 | u32 reserved[3]; |
| 797 | |
| 798 | }; |
| 799 | |
| 800 | struct func_mf_cfg { |
| 801 | |
| 802 | u32 config; |
| 803 | /* E/R/I/D */ |
| 804 | /* function 0 of each port cannot be hidden */ |
| 805 | #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 |
| 806 | |
| 807 | #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007 |
| 808 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 |
| 809 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 |
| 810 | #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 |
| 811 | #define FUNC_MF_CFG_PROTOCOL_DEFAULT\ |
| 812 | FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA |
| 813 | |
| 814 | #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 |
| 815 | |
| 816 | /* PRI */ |
| 817 | /* 0 - low priority, 3 - high priority */ |
| 818 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 |
| 819 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 |
| 820 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 |
| 821 | |
| 822 | /* MINBW, MAXBW */ |
| 823 | /* value range - 0..100, increments in 100Mbps */ |
| 824 | #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 |
| 825 | #define FUNC_MF_CFG_MIN_BW_SHIFT 16 |
| 826 | #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 |
| 827 | #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 |
| 828 | #define FUNC_MF_CFG_MAX_BW_SHIFT 24 |
| 829 | #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 |
| 830 | |
| 831 | u32 mac_upper; /* MAC */ |
| 832 | #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff |
| 833 | #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 |
| 834 | #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK |
| 835 | u32 mac_lower; |
| 836 | #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff |
| 837 | |
| 838 | u32 e1hov_tag; /* VNI */ |
| 839 | #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff |
| 840 | #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 |
| 841 | #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK |
| 842 | |
| 843 | u32 reserved[2]; |
| 844 | |
| 845 | }; |
| 846 | |
| 847 | struct mf_cfg { |
| 848 | |
| 849 | struct shared_mf_cfg shared_mf_config; |
| 850 | struct port_mf_cfg port_mf_config[PORT_MAX]; |
| 851 | struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; |
| 852 | |
| 853 | }; |
| 854 | |
| 855 | |
| 856 | /**************************************************************************** |
| 857 | * Shared Memory Region * |
| 858 | ****************************************************************************/ |
| 859 | struct shmem_region { /* SharedMem Offset (size) */ |
| 860 | |
| 861 | u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ |
| 862 | #define SHR_MEM_FORMAT_REV_ID ('A'<<24) |
| 863 | #define SHR_MEM_FORMAT_REV_MASK 0xff000000 |
| 864 | /* validity bits */ |
| 865 | #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 |
| 866 | #define SHR_MEM_VALIDITY_MB 0x00200000 |
| 867 | #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 |
| 868 | #define SHR_MEM_VALIDITY_RESERVED 0x00000007 |
| 869 | /* One licensing bit should be set */ |
| 870 | #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 |
| 871 | #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 |
| 872 | #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 |
| 873 | #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 |
| 874 | /* Active MFW */ |
| 875 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 |
| 876 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 |
| 877 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 |
| 878 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 |
| 879 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 |
| 880 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 |
| 881 | |
| 882 | struct shm_dev_info dev_info; /* 0x8 (0x438) */ |
| 883 | |
| 884 | u8 reserved[52*PORT_MAX]; |
| 885 | |
| 886 | /* FW information (for internal FW use) */ |
| 887 | u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ |
| 888 | struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ |
| 889 | |
| 890 | struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ |
| 891 | struct drv_func_mb func_mb[E1H_FUNC_MAX]; |
| 892 | |
| 893 | struct mf_cfg mf_cfg; |
| 894 | |
| 895 | }; /* 0x6dc */ |
| 896 | |
| 897 | |
| 898 | struct shmem2_region { |
| 899 | |
| 900 | u32 size; |
| 901 | |
| 902 | u32 dcc_support; |
| 903 | #define SHMEM_DCC_SUPPORT_NONE 0x00000000 |
| 904 | #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 |
| 905 | #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 |
| 906 | #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 |
| 907 | #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 |
| 908 | #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 |
| 909 | #define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE |
| 910 | |
| 911 | }; |
| 912 | |
| 913 | |
| 914 | struct emac_stats { |
| 915 | u32 rx_stat_ifhcinoctets; |
| 916 | u32 rx_stat_ifhcinbadoctets; |
| 917 | u32 rx_stat_etherstatsfragments; |
| 918 | u32 rx_stat_ifhcinucastpkts; |
| 919 | u32 rx_stat_ifhcinmulticastpkts; |
| 920 | u32 rx_stat_ifhcinbroadcastpkts; |
| 921 | u32 rx_stat_dot3statsfcserrors; |
| 922 | u32 rx_stat_dot3statsalignmenterrors; |
| 923 | u32 rx_stat_dot3statscarriersenseerrors; |
| 924 | u32 rx_stat_xonpauseframesreceived; |
| 925 | u32 rx_stat_xoffpauseframesreceived; |
| 926 | u32 rx_stat_maccontrolframesreceived; |
| 927 | u32 rx_stat_xoffstateentered; |
| 928 | u32 rx_stat_dot3statsframestoolong; |
| 929 | u32 rx_stat_etherstatsjabbers; |
| 930 | u32 rx_stat_etherstatsundersizepkts; |
| 931 | u32 rx_stat_etherstatspkts64octets; |
| 932 | u32 rx_stat_etherstatspkts65octetsto127octets; |
| 933 | u32 rx_stat_etherstatspkts128octetsto255octets; |
| 934 | u32 rx_stat_etherstatspkts256octetsto511octets; |
| 935 | u32 rx_stat_etherstatspkts512octetsto1023octets; |
| 936 | u32 rx_stat_etherstatspkts1024octetsto1522octets; |
| 937 | u32 rx_stat_etherstatspktsover1522octets; |
| 938 | |
| 939 | u32 rx_stat_falsecarriererrors; |
| 940 | |
| 941 | u32 tx_stat_ifhcoutoctets; |
| 942 | u32 tx_stat_ifhcoutbadoctets; |
| 943 | u32 tx_stat_etherstatscollisions; |
| 944 | u32 tx_stat_outxonsent; |
| 945 | u32 tx_stat_outxoffsent; |
| 946 | u32 tx_stat_flowcontroldone; |
| 947 | u32 tx_stat_dot3statssinglecollisionframes; |
| 948 | u32 tx_stat_dot3statsmultiplecollisionframes; |
| 949 | u32 tx_stat_dot3statsdeferredtransmissions; |
| 950 | u32 tx_stat_dot3statsexcessivecollisions; |
| 951 | u32 tx_stat_dot3statslatecollisions; |
| 952 | u32 tx_stat_ifhcoutucastpkts; |
| 953 | u32 tx_stat_ifhcoutmulticastpkts; |
| 954 | u32 tx_stat_ifhcoutbroadcastpkts; |
| 955 | u32 tx_stat_etherstatspkts64octets; |
| 956 | u32 tx_stat_etherstatspkts65octetsto127octets; |
| 957 | u32 tx_stat_etherstatspkts128octetsto255octets; |
| 958 | u32 tx_stat_etherstatspkts256octetsto511octets; |
| 959 | u32 tx_stat_etherstatspkts512octetsto1023octets; |
| 960 | u32 tx_stat_etherstatspkts1024octetsto1522octets; |
| 961 | u32 tx_stat_etherstatspktsover1522octets; |
| 962 | u32 tx_stat_dot3statsinternalmactransmiterrors; |
| 963 | }; |
| 964 | |
| 965 | |
| 966 | struct bmac_stats { |
| 967 | u32 tx_stat_gtpkt_lo; |
| 968 | u32 tx_stat_gtpkt_hi; |
| 969 | u32 tx_stat_gtxpf_lo; |
| 970 | u32 tx_stat_gtxpf_hi; |
| 971 | u32 tx_stat_gtfcs_lo; |
| 972 | u32 tx_stat_gtfcs_hi; |
| 973 | u32 tx_stat_gtmca_lo; |
| 974 | u32 tx_stat_gtmca_hi; |
| 975 | u32 tx_stat_gtbca_lo; |
| 976 | u32 tx_stat_gtbca_hi; |
| 977 | u32 tx_stat_gtfrg_lo; |
| 978 | u32 tx_stat_gtfrg_hi; |
| 979 | u32 tx_stat_gtovr_lo; |
| 980 | u32 tx_stat_gtovr_hi; |
| 981 | u32 tx_stat_gt64_lo; |
| 982 | u32 tx_stat_gt64_hi; |
| 983 | u32 tx_stat_gt127_lo; |
| 984 | u32 tx_stat_gt127_hi; |
| 985 | u32 tx_stat_gt255_lo; |
| 986 | u32 tx_stat_gt255_hi; |
| 987 | u32 tx_stat_gt511_lo; |
| 988 | u32 tx_stat_gt511_hi; |
| 989 | u32 tx_stat_gt1023_lo; |
| 990 | u32 tx_stat_gt1023_hi; |
| 991 | u32 tx_stat_gt1518_lo; |
| 992 | u32 tx_stat_gt1518_hi; |
| 993 | u32 tx_stat_gt2047_lo; |
| 994 | u32 tx_stat_gt2047_hi; |
| 995 | u32 tx_stat_gt4095_lo; |
| 996 | u32 tx_stat_gt4095_hi; |
| 997 | u32 tx_stat_gt9216_lo; |
| 998 | u32 tx_stat_gt9216_hi; |
| 999 | u32 tx_stat_gt16383_lo; |
| 1000 | u32 tx_stat_gt16383_hi; |
| 1001 | u32 tx_stat_gtmax_lo; |
| 1002 | u32 tx_stat_gtmax_hi; |
| 1003 | u32 tx_stat_gtufl_lo; |
| 1004 | u32 tx_stat_gtufl_hi; |
| 1005 | u32 tx_stat_gterr_lo; |
| 1006 | u32 tx_stat_gterr_hi; |
| 1007 | u32 tx_stat_gtbyt_lo; |
| 1008 | u32 tx_stat_gtbyt_hi; |
| 1009 | |
| 1010 | u32 rx_stat_gr64_lo; |
| 1011 | u32 rx_stat_gr64_hi; |
| 1012 | u32 rx_stat_gr127_lo; |
| 1013 | u32 rx_stat_gr127_hi; |
| 1014 | u32 rx_stat_gr255_lo; |
| 1015 | u32 rx_stat_gr255_hi; |
| 1016 | u32 rx_stat_gr511_lo; |
| 1017 | u32 rx_stat_gr511_hi; |
| 1018 | u32 rx_stat_gr1023_lo; |
| 1019 | u32 rx_stat_gr1023_hi; |
| 1020 | u32 rx_stat_gr1518_lo; |
| 1021 | u32 rx_stat_gr1518_hi; |
| 1022 | u32 rx_stat_gr2047_lo; |
| 1023 | u32 rx_stat_gr2047_hi; |
| 1024 | u32 rx_stat_gr4095_lo; |
| 1025 | u32 rx_stat_gr4095_hi; |
| 1026 | u32 rx_stat_gr9216_lo; |
| 1027 | u32 rx_stat_gr9216_hi; |
| 1028 | u32 rx_stat_gr16383_lo; |
| 1029 | u32 rx_stat_gr16383_hi; |
| 1030 | u32 rx_stat_grmax_lo; |
| 1031 | u32 rx_stat_grmax_hi; |
| 1032 | u32 rx_stat_grpkt_lo; |
| 1033 | u32 rx_stat_grpkt_hi; |
| 1034 | u32 rx_stat_grfcs_lo; |
| 1035 | u32 rx_stat_grfcs_hi; |
| 1036 | u32 rx_stat_grmca_lo; |
| 1037 | u32 rx_stat_grmca_hi; |
| 1038 | u32 rx_stat_grbca_lo; |
| 1039 | u32 rx_stat_grbca_hi; |
| 1040 | u32 rx_stat_grxcf_lo; |
| 1041 | u32 rx_stat_grxcf_hi; |
| 1042 | u32 rx_stat_grxpf_lo; |
| 1043 | u32 rx_stat_grxpf_hi; |
| 1044 | u32 rx_stat_grxuo_lo; |
| 1045 | u32 rx_stat_grxuo_hi; |
| 1046 | u32 rx_stat_grjbr_lo; |
| 1047 | u32 rx_stat_grjbr_hi; |
| 1048 | u32 rx_stat_grovr_lo; |
| 1049 | u32 rx_stat_grovr_hi; |
| 1050 | u32 rx_stat_grflr_lo; |
| 1051 | u32 rx_stat_grflr_hi; |
| 1052 | u32 rx_stat_grmeg_lo; |
| 1053 | u32 rx_stat_grmeg_hi; |
| 1054 | u32 rx_stat_grmeb_lo; |
| 1055 | u32 rx_stat_grmeb_hi; |
| 1056 | u32 rx_stat_grbyt_lo; |
| 1057 | u32 rx_stat_grbyt_hi; |
| 1058 | u32 rx_stat_grund_lo; |
| 1059 | u32 rx_stat_grund_hi; |
| 1060 | u32 rx_stat_grfrg_lo; |
| 1061 | u32 rx_stat_grfrg_hi; |
| 1062 | u32 rx_stat_grerb_lo; |
| 1063 | u32 rx_stat_grerb_hi; |
| 1064 | u32 rx_stat_grfre_lo; |
| 1065 | u32 rx_stat_grfre_hi; |
| 1066 | u32 rx_stat_gripj_lo; |
| 1067 | u32 rx_stat_gripj_hi; |
| 1068 | }; |
| 1069 | |
| 1070 | |
| 1071 | union mac_stats { |
| 1072 | struct emac_stats emac_stats; |
| 1073 | struct bmac_stats bmac_stats; |
| 1074 | }; |
| 1075 | |
| 1076 | |
| 1077 | struct mac_stx { |
| 1078 | /* in_bad_octets */ |
| 1079 | u32 rx_stat_ifhcinbadoctets_hi; |
| 1080 | u32 rx_stat_ifhcinbadoctets_lo; |
| 1081 | |
| 1082 | /* out_bad_octets */ |
| 1083 | u32 tx_stat_ifhcoutbadoctets_hi; |
| 1084 | u32 tx_stat_ifhcoutbadoctets_lo; |
| 1085 | |
| 1086 | /* crc_receive_errors */ |
| 1087 | u32 rx_stat_dot3statsfcserrors_hi; |
| 1088 | u32 rx_stat_dot3statsfcserrors_lo; |
| 1089 | /* alignment_errors */ |
| 1090 | u32 rx_stat_dot3statsalignmenterrors_hi; |
| 1091 | u32 rx_stat_dot3statsalignmenterrors_lo; |
| 1092 | /* carrier_sense_errors */ |
| 1093 | u32 rx_stat_dot3statscarriersenseerrors_hi; |
| 1094 | u32 rx_stat_dot3statscarriersenseerrors_lo; |
| 1095 | /* false_carrier_detections */ |
| 1096 | u32 rx_stat_falsecarriererrors_hi; |
| 1097 | u32 rx_stat_falsecarriererrors_lo; |
| 1098 | |
| 1099 | /* runt_packets_received */ |
| 1100 | u32 rx_stat_etherstatsundersizepkts_hi; |
| 1101 | u32 rx_stat_etherstatsundersizepkts_lo; |
| 1102 | /* jabber_packets_received */ |
| 1103 | u32 rx_stat_dot3statsframestoolong_hi; |
| 1104 | u32 rx_stat_dot3statsframestoolong_lo; |
| 1105 | |
| 1106 | /* error_runt_packets_received */ |
| 1107 | u32 rx_stat_etherstatsfragments_hi; |
| 1108 | u32 rx_stat_etherstatsfragments_lo; |
| 1109 | /* error_jabber_packets_received */ |
| 1110 | u32 rx_stat_etherstatsjabbers_hi; |
| 1111 | u32 rx_stat_etherstatsjabbers_lo; |
| 1112 | |
| 1113 | /* control_frames_received */ |
| 1114 | u32 rx_stat_maccontrolframesreceived_hi; |
| 1115 | u32 rx_stat_maccontrolframesreceived_lo; |
| 1116 | u32 rx_stat_bmac_xpf_hi; |
| 1117 | u32 rx_stat_bmac_xpf_lo; |
| 1118 | u32 rx_stat_bmac_xcf_hi; |
| 1119 | u32 rx_stat_bmac_xcf_lo; |
| 1120 | |
| 1121 | /* xoff_state_entered */ |
| 1122 | u32 rx_stat_xoffstateentered_hi; |
| 1123 | u32 rx_stat_xoffstateentered_lo; |
| 1124 | /* pause_xon_frames_received */ |
| 1125 | u32 rx_stat_xonpauseframesreceived_hi; |
| 1126 | u32 rx_stat_xonpauseframesreceived_lo; |
| 1127 | /* pause_xoff_frames_received */ |
| 1128 | u32 rx_stat_xoffpauseframesreceived_hi; |
| 1129 | u32 rx_stat_xoffpauseframesreceived_lo; |
| 1130 | /* pause_xon_frames_transmitted */ |
| 1131 | u32 tx_stat_outxonsent_hi; |
| 1132 | u32 tx_stat_outxonsent_lo; |
| 1133 | /* pause_xoff_frames_transmitted */ |
| 1134 | u32 tx_stat_outxoffsent_hi; |
| 1135 | u32 tx_stat_outxoffsent_lo; |
| 1136 | /* flow_control_done */ |
| 1137 | u32 tx_stat_flowcontroldone_hi; |
| 1138 | u32 tx_stat_flowcontroldone_lo; |
| 1139 | |
| 1140 | /* ether_stats_collisions */ |
| 1141 | u32 tx_stat_etherstatscollisions_hi; |
| 1142 | u32 tx_stat_etherstatscollisions_lo; |
| 1143 | /* single_collision_transmit_frames */ |
| 1144 | u32 tx_stat_dot3statssinglecollisionframes_hi; |
| 1145 | u32 tx_stat_dot3statssinglecollisionframes_lo; |
| 1146 | /* multiple_collision_transmit_frames */ |
| 1147 | u32 tx_stat_dot3statsmultiplecollisionframes_hi; |
| 1148 | u32 tx_stat_dot3statsmultiplecollisionframes_lo; |
| 1149 | /* deferred_transmissions */ |
| 1150 | u32 tx_stat_dot3statsdeferredtransmissions_hi; |
| 1151 | u32 tx_stat_dot3statsdeferredtransmissions_lo; |
| 1152 | /* excessive_collision_frames */ |
| 1153 | u32 tx_stat_dot3statsexcessivecollisions_hi; |
| 1154 | u32 tx_stat_dot3statsexcessivecollisions_lo; |
| 1155 | /* late_collision_frames */ |
| 1156 | u32 tx_stat_dot3statslatecollisions_hi; |
| 1157 | u32 tx_stat_dot3statslatecollisions_lo; |
| 1158 | |
| 1159 | /* frames_transmitted_64_bytes */ |
| 1160 | u32 tx_stat_etherstatspkts64octets_hi; |
| 1161 | u32 tx_stat_etherstatspkts64octets_lo; |
| 1162 | /* frames_transmitted_65_127_bytes */ |
| 1163 | u32 tx_stat_etherstatspkts65octetsto127octets_hi; |
| 1164 | u32 tx_stat_etherstatspkts65octetsto127octets_lo; |
| 1165 | /* frames_transmitted_128_255_bytes */ |
| 1166 | u32 tx_stat_etherstatspkts128octetsto255octets_hi; |
| 1167 | u32 tx_stat_etherstatspkts128octetsto255octets_lo; |
| 1168 | /* frames_transmitted_256_511_bytes */ |
| 1169 | u32 tx_stat_etherstatspkts256octetsto511octets_hi; |
| 1170 | u32 tx_stat_etherstatspkts256octetsto511octets_lo; |
| 1171 | /* frames_transmitted_512_1023_bytes */ |
| 1172 | u32 tx_stat_etherstatspkts512octetsto1023octets_hi; |
| 1173 | u32 tx_stat_etherstatspkts512octetsto1023octets_lo; |
| 1174 | /* frames_transmitted_1024_1522_bytes */ |
| 1175 | u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; |
| 1176 | u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; |
| 1177 | /* frames_transmitted_1523_9022_bytes */ |
| 1178 | u32 tx_stat_etherstatspktsover1522octets_hi; |
| 1179 | u32 tx_stat_etherstatspktsover1522octets_lo; |
| 1180 | u32 tx_stat_bmac_2047_hi; |
| 1181 | u32 tx_stat_bmac_2047_lo; |
| 1182 | u32 tx_stat_bmac_4095_hi; |
| 1183 | u32 tx_stat_bmac_4095_lo; |
| 1184 | u32 tx_stat_bmac_9216_hi; |
| 1185 | u32 tx_stat_bmac_9216_lo; |
| 1186 | u32 tx_stat_bmac_16383_hi; |
| 1187 | u32 tx_stat_bmac_16383_lo; |
| 1188 | |
| 1189 | /* internal_mac_transmit_errors */ |
| 1190 | u32 tx_stat_dot3statsinternalmactransmiterrors_hi; |
| 1191 | u32 tx_stat_dot3statsinternalmactransmiterrors_lo; |
| 1192 | |
| 1193 | /* if_out_discards */ |
| 1194 | u32 tx_stat_bmac_ufl_hi; |
| 1195 | u32 tx_stat_bmac_ufl_lo; |
| 1196 | }; |
| 1197 | |
| 1198 | |
| 1199 | #define MAC_STX_IDX_MAX 2 |
| 1200 | |
| 1201 | struct host_port_stats { |
| 1202 | u32 host_port_stats_start; |
| 1203 | |
| 1204 | struct mac_stx mac_stx[MAC_STX_IDX_MAX]; |
| 1205 | |
| 1206 | u32 brb_drop_hi; |
| 1207 | u32 brb_drop_lo; |
| 1208 | |
| 1209 | u32 host_port_stats_end; |
| 1210 | }; |
| 1211 | |
| 1212 | |
| 1213 | struct host_func_stats { |
| 1214 | u32 host_func_stats_start; |
| 1215 | |
| 1216 | u32 total_bytes_received_hi; |
| 1217 | u32 total_bytes_received_lo; |
| 1218 | |
| 1219 | u32 total_bytes_transmitted_hi; |
| 1220 | u32 total_bytes_transmitted_lo; |
| 1221 | |
| 1222 | u32 total_unicast_packets_received_hi; |
| 1223 | u32 total_unicast_packets_received_lo; |
| 1224 | |
| 1225 | u32 total_multicast_packets_received_hi; |
| 1226 | u32 total_multicast_packets_received_lo; |
| 1227 | |
| 1228 | u32 total_broadcast_packets_received_hi; |
| 1229 | u32 total_broadcast_packets_received_lo; |
| 1230 | |
| 1231 | u32 total_unicast_packets_transmitted_hi; |
| 1232 | u32 total_unicast_packets_transmitted_lo; |
| 1233 | |
| 1234 | u32 total_multicast_packets_transmitted_hi; |
| 1235 | u32 total_multicast_packets_transmitted_lo; |
| 1236 | |
| 1237 | u32 total_broadcast_packets_transmitted_hi; |
| 1238 | u32 total_broadcast_packets_transmitted_lo; |
| 1239 | |
| 1240 | u32 valid_bytes_received_hi; |
| 1241 | u32 valid_bytes_received_lo; |
| 1242 | |
| 1243 | u32 host_func_stats_end; |
| 1244 | }; |
| 1245 | |
| 1246 | |
| 1247 | #define BCM_5710_FW_MAJOR_VERSION 5 |
| 1248 | #define BCM_5710_FW_MINOR_VERSION 0 |
| 1249 | #define BCM_5710_FW_REVISION_VERSION 21 |
| 1250 | #define BCM_5710_FW_ENGINEERING_VERSION 0 |
| 1251 | #define BCM_5710_FW_COMPILE_FLAGS 1 |
| 1252 | |
| 1253 | |
| 1254 | /* |
| 1255 | * attention bits |
| 1256 | */ |
| 1257 | struct atten_def_status_block { |
| 1258 | __le32 attn_bits; |
| 1259 | __le32 attn_bits_ack; |
| 1260 | u8 status_block_id; |
| 1261 | u8 reserved0; |
| 1262 | __le16 attn_bits_index; |
| 1263 | __le32 reserved1; |
| 1264 | }; |
| 1265 | |
| 1266 | |
| 1267 | /* |
| 1268 | * common data for all protocols |
| 1269 | */ |
| 1270 | struct doorbell_hdr { |
| 1271 | u8 header; |
| 1272 | #define DOORBELL_HDR_RX (0x1<<0) |
| 1273 | #define DOORBELL_HDR_RX_SHIFT 0 |
| 1274 | #define DOORBELL_HDR_DB_TYPE (0x1<<1) |
| 1275 | #define DOORBELL_HDR_DB_TYPE_SHIFT 1 |
| 1276 | #define DOORBELL_HDR_DPM_SIZE (0x3<<2) |
| 1277 | #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 |
| 1278 | #define DOORBELL_HDR_CONN_TYPE (0xF<<4) |
| 1279 | #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 |
| 1280 | }; |
| 1281 | |
| 1282 | /* |
| 1283 | * doorbell message sent to the chip |
| 1284 | */ |
| 1285 | struct doorbell { |
| 1286 | #if defined(__BIG_ENDIAN) |
| 1287 | u16 zero_fill2; |
| 1288 | u8 zero_fill1; |
| 1289 | struct doorbell_hdr header; |
| 1290 | #elif defined(__LITTLE_ENDIAN) |
| 1291 | struct doorbell_hdr header; |
| 1292 | u8 zero_fill1; |
| 1293 | u16 zero_fill2; |
| 1294 | #endif |
| 1295 | }; |
| 1296 | |
| 1297 | |
| 1298 | /* |
| 1299 | * doorbell message sent to the chip |
| 1300 | */ |
| 1301 | struct doorbell_set_prod { |
| 1302 | #if defined(__BIG_ENDIAN) |
| 1303 | u16 prod; |
| 1304 | u8 zero_fill1; |
| 1305 | struct doorbell_hdr header; |
| 1306 | #elif defined(__LITTLE_ENDIAN) |
| 1307 | struct doorbell_hdr header; |
| 1308 | u8 zero_fill1; |
| 1309 | u16 prod; |
| 1310 | #endif |
| 1311 | }; |
| 1312 | |
| 1313 | |
| 1314 | /* |
| 1315 | * IGU driver acknowledgement register |
| 1316 | */ |
| 1317 | struct igu_ack_register { |
| 1318 | #if defined(__BIG_ENDIAN) |
| 1319 | u16 sb_id_and_flags; |
| 1320 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) |
| 1321 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 |
| 1322 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) |
| 1323 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 |
| 1324 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) |
| 1325 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 |
| 1326 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) |
| 1327 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 |
| 1328 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) |
| 1329 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 |
| 1330 | u16 status_block_index; |
| 1331 | #elif defined(__LITTLE_ENDIAN) |
| 1332 | u16 status_block_index; |
| 1333 | u16 sb_id_and_flags; |
| 1334 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) |
| 1335 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 |
| 1336 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) |
| 1337 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 |
| 1338 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) |
| 1339 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 |
| 1340 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) |
| 1341 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 |
| 1342 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) |
| 1343 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 |
| 1344 | #endif |
| 1345 | }; |
| 1346 | |
| 1347 | |
| 1348 | /* |
| 1349 | * IGU driver acknowledgement register |
| 1350 | */ |
| 1351 | struct igu_backward_compatible { |
| 1352 | u32 sb_id_and_flags; |
| 1353 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) |
| 1354 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 |
| 1355 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) |
| 1356 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 |
| 1357 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) |
| 1358 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 |
| 1359 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) |
| 1360 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 |
| 1361 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) |
| 1362 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 |
| 1363 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) |
| 1364 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 |
| 1365 | u32 reserved_2; |
| 1366 | }; |
| 1367 | |
| 1368 | |
| 1369 | /* |
| 1370 | * IGU driver acknowledgement register |
| 1371 | */ |
| 1372 | struct igu_regular { |
| 1373 | u32 sb_id_and_flags; |
| 1374 | #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) |
| 1375 | #define IGU_REGULAR_SB_INDEX_SHIFT 0 |
| 1376 | #define IGU_REGULAR_RESERVED0 (0x1<<20) |
| 1377 | #define IGU_REGULAR_RESERVED0_SHIFT 20 |
| 1378 | #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) |
| 1379 | #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 |
| 1380 | #define IGU_REGULAR_BUPDATE (0x1<<24) |
| 1381 | #define IGU_REGULAR_BUPDATE_SHIFT 24 |
| 1382 | #define IGU_REGULAR_ENABLE_INT (0x3<<25) |
| 1383 | #define IGU_REGULAR_ENABLE_INT_SHIFT 25 |
| 1384 | #define IGU_REGULAR_RESERVED_1 (0x1<<27) |
| 1385 | #define IGU_REGULAR_RESERVED_1_SHIFT 27 |
| 1386 | #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) |
| 1387 | #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 |
| 1388 | #define IGU_REGULAR_CLEANUP_SET (0x1<<30) |
| 1389 | #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 |
| 1390 | #define IGU_REGULAR_BCLEANUP (0x1<<31) |
| 1391 | #define IGU_REGULAR_BCLEANUP_SHIFT 31 |
| 1392 | u32 reserved_2; |
| 1393 | }; |
| 1394 | |
| 1395 | /* |
| 1396 | * IGU driver acknowledgement register |
| 1397 | */ |
| 1398 | union igu_consprod_reg { |
| 1399 | struct igu_regular regular; |
| 1400 | struct igu_backward_compatible backward_compatible; |
| 1401 | }; |
| 1402 | |
| 1403 | |
| 1404 | /* |
| 1405 | * Parser parsing flags field |
| 1406 | */ |
| 1407 | struct parsing_flags { |
| 1408 | __le16 flags; |
| 1409 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) |
| 1410 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 |
| 1411 | #define PARSING_FLAGS_VLAN (0x1<<1) |
| 1412 | #define PARSING_FLAGS_VLAN_SHIFT 1 |
| 1413 | #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) |
| 1414 | #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 |
| 1415 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) |
| 1416 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 |
| 1417 | #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) |
| 1418 | #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 |
| 1419 | #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) |
| 1420 | #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 |
| 1421 | #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) |
| 1422 | #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 |
| 1423 | #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) |
| 1424 | #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 |
| 1425 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) |
| 1426 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 |
| 1427 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) |
| 1428 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 |
| 1429 | #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) |
| 1430 | #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 |
| 1431 | #define PARSING_FLAGS_LLC_SNAP (0x1<<13) |
| 1432 | #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 |
| 1433 | #define PARSING_FLAGS_RESERVED0 (0x3<<14) |
| 1434 | #define PARSING_FLAGS_RESERVED0_SHIFT 14 |
| 1435 | }; |
| 1436 | |
| 1437 | |
| 1438 | struct regpair { |
| 1439 | __le32 lo; |
| 1440 | __le32 hi; |
| 1441 | }; |
| 1442 | |
| 1443 | |
| 1444 | /* |
| 1445 | * dmae command structure |
| 1446 | */ |
| 1447 | struct dmae_command { |
| 1448 | u32 opcode; |
| 1449 | #define DMAE_COMMAND_SRC (0x1<<0) |
| 1450 | #define DMAE_COMMAND_SRC_SHIFT 0 |
| 1451 | #define DMAE_COMMAND_DST (0x3<<1) |
| 1452 | #define DMAE_COMMAND_DST_SHIFT 1 |
| 1453 | #define DMAE_COMMAND_C_DST (0x1<<3) |
| 1454 | #define DMAE_COMMAND_C_DST_SHIFT 3 |
| 1455 | #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) |
| 1456 | #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 |
| 1457 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) |
| 1458 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 |
| 1459 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) |
| 1460 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 |
| 1461 | #define DMAE_COMMAND_ENDIANITY (0x3<<9) |
| 1462 | #define DMAE_COMMAND_ENDIANITY_SHIFT 9 |
| 1463 | #define DMAE_COMMAND_PORT (0x1<<11) |
| 1464 | #define DMAE_COMMAND_PORT_SHIFT 11 |
| 1465 | #define DMAE_COMMAND_CRC_RESET (0x1<<12) |
| 1466 | #define DMAE_COMMAND_CRC_RESET_SHIFT 12 |
| 1467 | #define DMAE_COMMAND_SRC_RESET (0x1<<13) |
| 1468 | #define DMAE_COMMAND_SRC_RESET_SHIFT 13 |
| 1469 | #define DMAE_COMMAND_DST_RESET (0x1<<14) |
| 1470 | #define DMAE_COMMAND_DST_RESET_SHIFT 14 |
| 1471 | #define DMAE_COMMAND_E1HVN (0x3<<15) |
| 1472 | #define DMAE_COMMAND_E1HVN_SHIFT 15 |
| 1473 | #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17) |
| 1474 | #define DMAE_COMMAND_RESERVED0_SHIFT 17 |
| 1475 | u32 src_addr_lo; |
| 1476 | u32 src_addr_hi; |
| 1477 | u32 dst_addr_lo; |
| 1478 | u32 dst_addr_hi; |
| 1479 | #if defined(__BIG_ENDIAN) |
| 1480 | u16 reserved1; |
| 1481 | u16 len; |
| 1482 | #elif defined(__LITTLE_ENDIAN) |
| 1483 | u16 len; |
| 1484 | u16 reserved1; |
| 1485 | #endif |
| 1486 | u32 comp_addr_lo; |
| 1487 | u32 comp_addr_hi; |
| 1488 | u32 comp_val; |
| 1489 | u32 crc32; |
| 1490 | u32 crc32_c; |
| 1491 | #if defined(__BIG_ENDIAN) |
| 1492 | u16 crc16_c; |
| 1493 | u16 crc16; |
| 1494 | #elif defined(__LITTLE_ENDIAN) |
| 1495 | u16 crc16; |
| 1496 | u16 crc16_c; |
| 1497 | #endif |
| 1498 | #if defined(__BIG_ENDIAN) |
| 1499 | u16 reserved2; |
| 1500 | u16 crc_t10; |
| 1501 | #elif defined(__LITTLE_ENDIAN) |
| 1502 | u16 crc_t10; |
| 1503 | u16 reserved2; |
| 1504 | #endif |
| 1505 | #if defined(__BIG_ENDIAN) |
| 1506 | u16 xsum8; |
| 1507 | u16 xsum16; |
| 1508 | #elif defined(__LITTLE_ENDIAN) |
| 1509 | u16 xsum16; |
| 1510 | u16 xsum8; |
| 1511 | #endif |
| 1512 | }; |
| 1513 | |
| 1514 | |
| 1515 | struct double_regpair { |
| 1516 | u32 regpair0_lo; |
| 1517 | u32 regpair0_hi; |
| 1518 | u32 regpair1_lo; |
| 1519 | u32 regpair1_hi; |
| 1520 | }; |
| 1521 | |
| 1522 | |
| 1523 | /* |
| 1524 | * The eth storm context of Ustorm (configuration part) |
| 1525 | */ |
| 1526 | struct ustorm_eth_st_context_config { |
| 1527 | #if defined(__BIG_ENDIAN) |
| 1528 | u8 flags; |
| 1529 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0) |
| 1530 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0 |
| 1531 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1) |
| 1532 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1 |
| 1533 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2) |
| 1534 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2 |
| 1535 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3) |
| 1536 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3 |
| 1537 | #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4) |
| 1538 | #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4 |
| 1539 | u8 status_block_id; |
| 1540 | u8 clientId; |
| 1541 | u8 sb_index_numbers; |
| 1542 | #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0) |
| 1543 | #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0 |
| 1544 | #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4) |
| 1545 | #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4 |
| 1546 | #elif defined(__LITTLE_ENDIAN) |
| 1547 | u8 sb_index_numbers; |
| 1548 | #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0) |
| 1549 | #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0 |
| 1550 | #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4) |
| 1551 | #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4 |
| 1552 | u8 clientId; |
| 1553 | u8 status_block_id; |
| 1554 | u8 flags; |
| 1555 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0) |
| 1556 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0 |
| 1557 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1) |
| 1558 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1 |
| 1559 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2) |
| 1560 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2 |
| 1561 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3) |
| 1562 | #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3 |
| 1563 | #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4) |
| 1564 | #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4 |
| 1565 | #endif |
| 1566 | #if defined(__BIG_ENDIAN) |
| 1567 | u16 bd_buff_size; |
| 1568 | u8 statistics_counter_id; |
| 1569 | u8 mc_alignment_log_size; |
| 1570 | #elif defined(__LITTLE_ENDIAN) |
| 1571 | u8 mc_alignment_log_size; |
| 1572 | u8 statistics_counter_id; |
| 1573 | u16 bd_buff_size; |
| 1574 | #endif |
| 1575 | #if defined(__BIG_ENDIAN) |
| 1576 | u8 __local_sge_prod; |
| 1577 | u8 __local_bd_prod; |
| 1578 | u16 sge_buff_size; |
| 1579 | #elif defined(__LITTLE_ENDIAN) |
| 1580 | u16 sge_buff_size; |
| 1581 | u8 __local_bd_prod; |
| 1582 | u8 __local_sge_prod; |
| 1583 | #endif |
| 1584 | #if defined(__BIG_ENDIAN) |
| 1585 | u16 __sdm_bd_expected_counter; |
| 1586 | u8 cstorm_agg_int; |
| 1587 | u8 __expected_bds_on_ram; |
| 1588 | #elif defined(__LITTLE_ENDIAN) |
| 1589 | u8 __expected_bds_on_ram; |
| 1590 | u8 cstorm_agg_int; |
| 1591 | u16 __sdm_bd_expected_counter; |
| 1592 | #endif |
| 1593 | #if defined(__BIG_ENDIAN) |
| 1594 | u16 __ring_data_ram_addr; |
| 1595 | u16 __hc_cstorm_ram_addr; |
| 1596 | #elif defined(__LITTLE_ENDIAN) |
| 1597 | u16 __hc_cstorm_ram_addr; |
| 1598 | u16 __ring_data_ram_addr; |
| 1599 | #endif |
| 1600 | #if defined(__BIG_ENDIAN) |
| 1601 | u8 reserved1; |
| 1602 | u8 max_sges_for_packet; |
| 1603 | u16 __bd_ring_ram_addr; |
| 1604 | #elif defined(__LITTLE_ENDIAN) |
| 1605 | u16 __bd_ring_ram_addr; |
| 1606 | u8 max_sges_for_packet; |
| 1607 | u8 reserved1; |
| 1608 | #endif |
| 1609 | u32 bd_page_base_lo; |
| 1610 | u32 bd_page_base_hi; |
| 1611 | u32 sge_page_base_lo; |
| 1612 | u32 sge_page_base_hi; |
| 1613 | struct regpair reserved2; |
| 1614 | }; |
| 1615 | |
| 1616 | /* |
| 1617 | * The eth Rx Buffer Descriptor |
| 1618 | */ |
| 1619 | struct eth_rx_bd { |
| 1620 | __le32 addr_lo; |
| 1621 | __le32 addr_hi; |
| 1622 | }; |
| 1623 | |
| 1624 | /* |
| 1625 | * The eth Rx SGE Descriptor |
| 1626 | */ |
| 1627 | struct eth_rx_sge { |
| 1628 | __le32 addr_lo; |
| 1629 | __le32 addr_hi; |
| 1630 | }; |
| 1631 | |
| 1632 | /* |
| 1633 | * Local BDs and SGEs rings (in ETH) |
| 1634 | */ |
| 1635 | struct eth_local_rx_rings { |
| 1636 | struct eth_rx_bd __local_bd_ring[8]; |
| 1637 | struct eth_rx_sge __local_sge_ring[10]; |
| 1638 | }; |
| 1639 | |
| 1640 | /* |
| 1641 | * The eth storm context of Ustorm |
| 1642 | */ |
| 1643 | struct ustorm_eth_st_context { |
| 1644 | struct ustorm_eth_st_context_config common; |
| 1645 | struct eth_local_rx_rings __rings; |
| 1646 | }; |
| 1647 | |
| 1648 | /* |
| 1649 | * The eth storm context of Tstorm |
| 1650 | */ |
| 1651 | struct tstorm_eth_st_context { |
| 1652 | u32 __reserved0[28]; |
| 1653 | }; |
| 1654 | |
| 1655 | /* |
| 1656 | * The eth aggregative context section of Xstorm |
| 1657 | */ |
| 1658 | struct xstorm_eth_extra_ag_context_section { |
| 1659 | #if defined(__BIG_ENDIAN) |
| 1660 | u8 __tcp_agg_vars1; |
| 1661 | u8 __reserved50; |
| 1662 | u16 __mss; |
| 1663 | #elif defined(__LITTLE_ENDIAN) |
| 1664 | u16 __mss; |
| 1665 | u8 __reserved50; |
| 1666 | u8 __tcp_agg_vars1; |
| 1667 | #endif |
| 1668 | u32 __snd_nxt; |
| 1669 | u32 __tx_wnd; |
| 1670 | u32 __snd_una; |
| 1671 | u32 __reserved53; |
| 1672 | #if defined(__BIG_ENDIAN) |
| 1673 | u8 __agg_val8_th; |
| 1674 | u8 __agg_val8; |
| 1675 | u16 __tcp_agg_vars2; |
| 1676 | #elif defined(__LITTLE_ENDIAN) |
| 1677 | u16 __tcp_agg_vars2; |
| 1678 | u8 __agg_val8; |
| 1679 | u8 __agg_val8_th; |
| 1680 | #endif |
| 1681 | u32 __reserved58; |
| 1682 | u32 __reserved59; |
| 1683 | u32 __reserved60; |
| 1684 | u32 __reserved61; |
| 1685 | #if defined(__BIG_ENDIAN) |
| 1686 | u16 __agg_val7_th; |
| 1687 | u16 __agg_val7; |
| 1688 | #elif defined(__LITTLE_ENDIAN) |
| 1689 | u16 __agg_val7; |
| 1690 | u16 __agg_val7_th; |
| 1691 | #endif |
| 1692 | #if defined(__BIG_ENDIAN) |
| 1693 | u8 __tcp_agg_vars5; |
| 1694 | u8 __tcp_agg_vars4; |
| 1695 | u8 __tcp_agg_vars3; |
| 1696 | u8 __reserved62; |
| 1697 | #elif defined(__LITTLE_ENDIAN) |
| 1698 | u8 __reserved62; |
| 1699 | u8 __tcp_agg_vars3; |
| 1700 | u8 __tcp_agg_vars4; |
| 1701 | u8 __tcp_agg_vars5; |
| 1702 | #endif |
| 1703 | u32 __tcp_agg_vars6; |
| 1704 | #if defined(__BIG_ENDIAN) |
| 1705 | u16 __agg_misc6; |
| 1706 | u16 __tcp_agg_vars7; |
| 1707 | #elif defined(__LITTLE_ENDIAN) |
| 1708 | u16 __tcp_agg_vars7; |
| 1709 | u16 __agg_misc6; |
| 1710 | #endif |
| 1711 | u32 __agg_val10; |
| 1712 | u32 __agg_val10_th; |
| 1713 | #if defined(__BIG_ENDIAN) |
| 1714 | u16 __reserved3; |
| 1715 | u8 __reserved2; |
| 1716 | u8 __da_only_cnt; |
| 1717 | #elif defined(__LITTLE_ENDIAN) |
| 1718 | u8 __da_only_cnt; |
| 1719 | u8 __reserved2; |
| 1720 | u16 __reserved3; |
| 1721 | #endif |
| 1722 | }; |
| 1723 | |
| 1724 | /* |
| 1725 | * The eth aggregative context of Xstorm |
| 1726 | */ |
| 1727 | struct xstorm_eth_ag_context { |
| 1728 | #if defined(__BIG_ENDIAN) |
| 1729 | u16 agg_val1; |
| 1730 | u8 __agg_vars1; |
| 1731 | u8 __state; |
| 1732 | #elif defined(__LITTLE_ENDIAN) |
| 1733 | u8 __state; |
| 1734 | u8 __agg_vars1; |
| 1735 | u16 agg_val1; |
| 1736 | #endif |
| 1737 | #if defined(__BIG_ENDIAN) |
| 1738 | u8 cdu_reserved; |
| 1739 | u8 __agg_vars4; |
| 1740 | u8 __agg_vars3; |
| 1741 | u8 __agg_vars2; |
| 1742 | #elif defined(__LITTLE_ENDIAN) |
| 1743 | u8 __agg_vars2; |
| 1744 | u8 __agg_vars3; |
| 1745 | u8 __agg_vars4; |
| 1746 | u8 cdu_reserved; |
| 1747 | #endif |
| 1748 | u32 __bd_prod; |
| 1749 | #if defined(__BIG_ENDIAN) |
| 1750 | u16 __agg_vars5; |
| 1751 | u16 __agg_val4_th; |
| 1752 | #elif defined(__LITTLE_ENDIAN) |
| 1753 | u16 __agg_val4_th; |
| 1754 | u16 __agg_vars5; |
| 1755 | #endif |
| 1756 | struct xstorm_eth_extra_ag_context_section __extra_section; |
| 1757 | #if defined(__BIG_ENDIAN) |
| 1758 | u16 __agg_vars7; |
| 1759 | u8 __agg_val3_th; |
| 1760 | u8 __agg_vars6; |
| 1761 | #elif defined(__LITTLE_ENDIAN) |
| 1762 | u8 __agg_vars6; |
| 1763 | u8 __agg_val3_th; |
| 1764 | u16 __agg_vars7; |
| 1765 | #endif |
| 1766 | #if defined(__BIG_ENDIAN) |
| 1767 | u16 __agg_val11_th; |
| 1768 | u16 __agg_val11; |
| 1769 | #elif defined(__LITTLE_ENDIAN) |
| 1770 | u16 __agg_val11; |
| 1771 | u16 __agg_val11_th; |
| 1772 | #endif |
| 1773 | #if defined(__BIG_ENDIAN) |
| 1774 | u8 __reserved1; |
| 1775 | u8 __agg_val6_th; |
| 1776 | u16 __agg_val9; |
| 1777 | #elif defined(__LITTLE_ENDIAN) |
| 1778 | u16 __agg_val9; |
| 1779 | u8 __agg_val6_th; |
| 1780 | u8 __reserved1; |
| 1781 | #endif |
| 1782 | #if defined(__BIG_ENDIAN) |
| 1783 | u16 __agg_val2_th; |
| 1784 | u16 __agg_val2; |
| 1785 | #elif defined(__LITTLE_ENDIAN) |
| 1786 | u16 __agg_val2; |
| 1787 | u16 __agg_val2_th; |
| 1788 | #endif |
| 1789 | u32 __agg_vars8; |
| 1790 | #if defined(__BIG_ENDIAN) |
| 1791 | u16 __agg_misc0; |
| 1792 | u16 __agg_val4; |
| 1793 | #elif defined(__LITTLE_ENDIAN) |
| 1794 | u16 __agg_val4; |
| 1795 | u16 __agg_misc0; |
| 1796 | #endif |
| 1797 | #if defined(__BIG_ENDIAN) |
| 1798 | u8 __agg_val3; |
| 1799 | u8 __agg_val6; |
| 1800 | u8 __agg_val5_th; |
| 1801 | u8 __agg_val5; |
| 1802 | #elif defined(__LITTLE_ENDIAN) |
| 1803 | u8 __agg_val5; |
| 1804 | u8 __agg_val5_th; |
| 1805 | u8 __agg_val6; |
| 1806 | u8 __agg_val3; |
| 1807 | #endif |
| 1808 | #if defined(__BIG_ENDIAN) |
| 1809 | u16 __agg_misc1; |
| 1810 | u16 __bd_ind_max_val; |
| 1811 | #elif defined(__LITTLE_ENDIAN) |
| 1812 | u16 __bd_ind_max_val; |
| 1813 | u16 __agg_misc1; |
| 1814 | #endif |
| 1815 | u32 __reserved57; |
| 1816 | u32 __agg_misc4; |
| 1817 | u32 __agg_misc5; |
| 1818 | }; |
| 1819 | |
| 1820 | /* |
| 1821 | * The eth extra aggregative context section of Tstorm |
| 1822 | */ |
| 1823 | struct tstorm_eth_extra_ag_context_section { |
| 1824 | u32 __agg_val1; |
| 1825 | #if defined(__BIG_ENDIAN) |
| 1826 | u8 __tcp_agg_vars2; |
| 1827 | u8 __agg_val3; |
| 1828 | u16 __agg_val2; |
| 1829 | #elif defined(__LITTLE_ENDIAN) |
| 1830 | u16 __agg_val2; |
| 1831 | u8 __agg_val3; |
| 1832 | u8 __tcp_agg_vars2; |
| 1833 | #endif |
| 1834 | #if defined(__BIG_ENDIAN) |
| 1835 | u16 __agg_val5; |
| 1836 | u8 __agg_val6; |
| 1837 | u8 __tcp_agg_vars3; |
| 1838 | #elif defined(__LITTLE_ENDIAN) |
| 1839 | u8 __tcp_agg_vars3; |
| 1840 | u8 __agg_val6; |
| 1841 | u16 __agg_val5; |
| 1842 | #endif |
| 1843 | u32 __reserved63; |
| 1844 | u32 __reserved64; |
| 1845 | u32 __reserved65; |
| 1846 | u32 __reserved66; |
| 1847 | u32 __reserved67; |
| 1848 | u32 __tcp_agg_vars1; |
| 1849 | u32 __reserved61; |
| 1850 | u32 __reserved62; |
| 1851 | u32 __reserved2; |
| 1852 | }; |
| 1853 | |
| 1854 | /* |
| 1855 | * The eth aggregative context of Tstorm |
| 1856 | */ |
| 1857 | struct tstorm_eth_ag_context { |
| 1858 | #if defined(__BIG_ENDIAN) |
| 1859 | u16 __reserved54; |
| 1860 | u8 __agg_vars1; |
| 1861 | u8 __state; |
| 1862 | #elif defined(__LITTLE_ENDIAN) |
| 1863 | u8 __state; |
| 1864 | u8 __agg_vars1; |
| 1865 | u16 __reserved54; |
| 1866 | #endif |
| 1867 | #if defined(__BIG_ENDIAN) |
| 1868 | u16 __agg_val4; |
| 1869 | u16 __agg_vars2; |
| 1870 | #elif defined(__LITTLE_ENDIAN) |
| 1871 | u16 __agg_vars2; |
| 1872 | u16 __agg_val4; |
| 1873 | #endif |
| 1874 | struct tstorm_eth_extra_ag_context_section __extra_section; |
| 1875 | }; |
| 1876 | |
| 1877 | /* |
| 1878 | * The eth aggregative context of Cstorm |
| 1879 | */ |
| 1880 | struct cstorm_eth_ag_context { |
| 1881 | u32 __agg_vars1; |
| 1882 | #if defined(__BIG_ENDIAN) |
| 1883 | u8 __aux1_th; |
| 1884 | u8 __aux1_val; |
| 1885 | u16 __agg_vars2; |
| 1886 | #elif defined(__LITTLE_ENDIAN) |
| 1887 | u16 __agg_vars2; |
| 1888 | u8 __aux1_val; |
| 1889 | u8 __aux1_th; |
| 1890 | #endif |
| 1891 | u32 __num_of_treated_packet; |
| 1892 | u32 __last_packet_treated; |
| 1893 | #if defined(__BIG_ENDIAN) |
| 1894 | u16 __reserved58; |
| 1895 | u16 __reserved57; |
| 1896 | #elif defined(__LITTLE_ENDIAN) |
| 1897 | u16 __reserved57; |
| 1898 | u16 __reserved58; |
| 1899 | #endif |
| 1900 | #if defined(__BIG_ENDIAN) |
| 1901 | u8 __reserved62; |
| 1902 | u8 __reserved61; |
| 1903 | u8 __reserved60; |
| 1904 | u8 __reserved59; |
| 1905 | #elif defined(__LITTLE_ENDIAN) |
| 1906 | u8 __reserved59; |
| 1907 | u8 __reserved60; |
| 1908 | u8 __reserved61; |
| 1909 | u8 __reserved62; |
| 1910 | #endif |
| 1911 | #if defined(__BIG_ENDIAN) |
| 1912 | u16 __reserved64; |
| 1913 | u16 __reserved63; |
| 1914 | #elif defined(__LITTLE_ENDIAN) |
| 1915 | u16 __reserved63; |
| 1916 | u16 __reserved64; |
| 1917 | #endif |
| 1918 | u32 __reserved65; |
| 1919 | #if defined(__BIG_ENDIAN) |
| 1920 | u16 __agg_vars3; |
| 1921 | u16 __rq_inv_cnt; |
| 1922 | #elif defined(__LITTLE_ENDIAN) |
| 1923 | u16 __rq_inv_cnt; |
| 1924 | u16 __agg_vars3; |
| 1925 | #endif |
| 1926 | #if defined(__BIG_ENDIAN) |
| 1927 | u16 __packet_index_th; |
| 1928 | u16 __packet_index; |
| 1929 | #elif defined(__LITTLE_ENDIAN) |
| 1930 | u16 __packet_index; |
| 1931 | u16 __packet_index_th; |
| 1932 | #endif |
| 1933 | }; |
| 1934 | |
| 1935 | /* |
| 1936 | * The eth aggregative context of Ustorm |
| 1937 | */ |
| 1938 | struct ustorm_eth_ag_context { |
| 1939 | #if defined(__BIG_ENDIAN) |
| 1940 | u8 __aux_counter_flags; |
| 1941 | u8 __agg_vars2; |
| 1942 | u8 __agg_vars1; |
| 1943 | u8 __state; |
| 1944 | #elif defined(__LITTLE_ENDIAN) |
| 1945 | u8 __state; |
| 1946 | u8 __agg_vars1; |
| 1947 | u8 __agg_vars2; |
| 1948 | u8 __aux_counter_flags; |
| 1949 | #endif |
| 1950 | #if defined(__BIG_ENDIAN) |
| 1951 | u8 cdu_usage; |
| 1952 | u8 __agg_misc2; |
| 1953 | u16 __agg_misc1; |
| 1954 | #elif defined(__LITTLE_ENDIAN) |
| 1955 | u16 __agg_misc1; |
| 1956 | u8 __agg_misc2; |
| 1957 | u8 cdu_usage; |
| 1958 | #endif |
| 1959 | u32 __agg_misc4; |
| 1960 | #if defined(__BIG_ENDIAN) |
| 1961 | u8 __agg_val3_th; |
| 1962 | u8 __agg_val3; |
| 1963 | u16 __agg_misc3; |
| 1964 | #elif defined(__LITTLE_ENDIAN) |
| 1965 | u16 __agg_misc3; |
| 1966 | u8 __agg_val3; |
| 1967 | u8 __agg_val3_th; |
| 1968 | #endif |
| 1969 | u32 __agg_val1; |
| 1970 | u32 __agg_misc4_th; |
| 1971 | #if defined(__BIG_ENDIAN) |
| 1972 | u16 __agg_val2_th; |
| 1973 | u16 __agg_val2; |
| 1974 | #elif defined(__LITTLE_ENDIAN) |
| 1975 | u16 __agg_val2; |
| 1976 | u16 __agg_val2_th; |
| 1977 | #endif |
| 1978 | #if defined(__BIG_ENDIAN) |
| 1979 | u16 __reserved2; |
| 1980 | u8 __decision_rules; |
| 1981 | u8 __decision_rule_enable_bits; |
| 1982 | #elif defined(__LITTLE_ENDIAN) |
| 1983 | u8 __decision_rule_enable_bits; |
| 1984 | u8 __decision_rules; |
| 1985 | u16 __reserved2; |
| 1986 | #endif |
| 1987 | }; |
| 1988 | |
| 1989 | /* |
| 1990 | * Timers connection context |
| 1991 | */ |
| 1992 | struct timers_block_context { |
| 1993 | u32 __reserved_0; |
| 1994 | u32 __reserved_1; |
| 1995 | u32 __reserved_2; |
| 1996 | u32 flags; |
| 1997 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) |
| 1998 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 |
| 1999 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) |
| 2000 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 |
| 2001 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) |
| 2002 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 |
| 2003 | }; |
| 2004 | |
| 2005 | /* |
| 2006 | * structure for easy accessibility to assembler |
| 2007 | */ |
| 2008 | struct eth_tx_bd_flags { |
| 2009 | u8 as_bitfield; |
| 2010 | #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0) |
| 2011 | #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0 |
| 2012 | #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1) |
| 2013 | #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1 |
| 2014 | #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<2) |
| 2015 | #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 2 |
| 2016 | #define ETH_TX_BD_FLAGS_END_BD (0x1<<3) |
| 2017 | #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3 |
| 2018 | #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) |
| 2019 | #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 |
| 2020 | #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5) |
| 2021 | #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5 |
| 2022 | #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) |
| 2023 | #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 |
| 2024 | #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) |
| 2025 | #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 |
| 2026 | }; |
| 2027 | |
| 2028 | /* |
| 2029 | * The eth Tx Buffer Descriptor |
| 2030 | */ |
| 2031 | struct eth_tx_start_bd { |
| 2032 | __le32 addr_lo; |
| 2033 | __le32 addr_hi; |
| 2034 | __le16 nbd; |
| 2035 | __le16 nbytes; |
| 2036 | __le16 vlan; |
| 2037 | struct eth_tx_bd_flags bd_flags; |
| 2038 | u8 general_data; |
| 2039 | #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0) |
| 2040 | #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 |
| 2041 | #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) |
| 2042 | #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 |
| 2043 | }; |
| 2044 | |
| 2045 | /* |
| 2046 | * Tx regular BD structure |
| 2047 | */ |
| 2048 | struct eth_tx_bd { |
| 2049 | u32 addr_lo; |
| 2050 | u32 addr_hi; |
| 2051 | u16 total_pkt_bytes; |
| 2052 | u16 nbytes; |
| 2053 | u8 reserved[4]; |
| 2054 | }; |
| 2055 | |
| 2056 | /* |
| 2057 | * Tx parsing BD structure for ETH,Relevant in START |
| 2058 | */ |
| 2059 | struct eth_tx_parse_bd { |
| 2060 | u8 global_data; |
| 2061 | #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0) |
| 2062 | #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0 |
| 2063 | #define ETH_TX_PARSE_BD_UDP_CS_FLG (0x1<<4) |
| 2064 | #define ETH_TX_PARSE_BD_UDP_CS_FLG_SHIFT 4 |
| 2065 | #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5) |
| 2066 | #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 |
| 2067 | #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6) |
| 2068 | #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6 |
| 2069 | #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7) |
| 2070 | #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7 |
| 2071 | u8 tcp_flags; |
| 2072 | #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0) |
| 2073 | #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0 |
| 2074 | #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1) |
| 2075 | #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1 |
| 2076 | #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2) |
| 2077 | #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2 |
| 2078 | #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3) |
| 2079 | #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3 |
| 2080 | #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4) |
| 2081 | #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4 |
| 2082 | #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5) |
| 2083 | #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5 |
| 2084 | #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6) |
| 2085 | #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6 |
| 2086 | #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7) |
| 2087 | #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7 |
| 2088 | u8 ip_hlen; |
| 2089 | s8 reserved; |
| 2090 | __le16 total_hlen; |
| 2091 | __le16 tcp_pseudo_csum; |
| 2092 | __le16 lso_mss; |
| 2093 | __le16 ip_id; |
| 2094 | __le32 tcp_send_seq; |
| 2095 | }; |
| 2096 | |
| 2097 | /* |
| 2098 | * The last BD in the BD memory will hold a pointer to the next BD memory |
| 2099 | */ |
| 2100 | struct eth_tx_next_bd { |
| 2101 | __le32 addr_lo; |
| 2102 | __le32 addr_hi; |
| 2103 | u8 reserved[8]; |
| 2104 | }; |
| 2105 | |
| 2106 | /* |
| 2107 | * union for 4 Bd types |
| 2108 | */ |
| 2109 | union eth_tx_bd_types { |
| 2110 | struct eth_tx_start_bd start_bd; |
| 2111 | struct eth_tx_bd reg_bd; |
| 2112 | struct eth_tx_parse_bd parse_bd; |
| 2113 | struct eth_tx_next_bd next_bd; |
| 2114 | }; |
| 2115 | |
| 2116 | /* |
| 2117 | * The eth storm context of Xstorm |
| 2118 | */ |
| 2119 | struct xstorm_eth_st_context { |
| 2120 | u32 tx_bd_page_base_lo; |
| 2121 | u32 tx_bd_page_base_hi; |
| 2122 | #if defined(__BIG_ENDIAN) |
| 2123 | u16 tx_bd_cons; |
| 2124 | u8 statistics_data; |
| 2125 | #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0) |
| 2126 | #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0 |
| 2127 | #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7) |
| 2128 | #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7 |
| 2129 | u8 __local_tx_bd_prod; |
| 2130 | #elif defined(__LITTLE_ENDIAN) |
| 2131 | u8 __local_tx_bd_prod; |
| 2132 | u8 statistics_data; |
| 2133 | #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0) |
| 2134 | #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0 |
| 2135 | #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7) |
| 2136 | #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7 |
| 2137 | u16 tx_bd_cons; |
| 2138 | #endif |
| 2139 | u32 __reserved1; |
| 2140 | u32 __reserved2; |
| 2141 | #if defined(__BIG_ENDIAN) |
| 2142 | u8 __ram_cache_index; |
| 2143 | u8 __double_buffer_client; |
| 2144 | u16 __pkt_cons; |
| 2145 | #elif defined(__LITTLE_ENDIAN) |
| 2146 | u16 __pkt_cons; |
| 2147 | u8 __double_buffer_client; |
| 2148 | u8 __ram_cache_index; |
| 2149 | #endif |
| 2150 | #if defined(__BIG_ENDIAN) |
| 2151 | u16 __statistics_address; |
| 2152 | u16 __gso_next; |
| 2153 | #elif defined(__LITTLE_ENDIAN) |
| 2154 | u16 __gso_next; |
| 2155 | u16 __statistics_address; |
| 2156 | #endif |
| 2157 | #if defined(__BIG_ENDIAN) |
| 2158 | u8 __local_tx_bd_cons; |
| 2159 | u8 safc_group_num; |
| 2160 | u8 safc_group_en; |
| 2161 | u8 __is_eth_conn; |
| 2162 | #elif defined(__LITTLE_ENDIAN) |
| 2163 | u8 __is_eth_conn; |
| 2164 | u8 safc_group_en; |
| 2165 | u8 safc_group_num; |
| 2166 | u8 __local_tx_bd_cons; |
| 2167 | #endif |
| 2168 | union eth_tx_bd_types __bds[13]; |
| 2169 | }; |
| 2170 | |
| 2171 | /* |
| 2172 | * The eth storm context of Cstorm |
| 2173 | */ |
| 2174 | struct cstorm_eth_st_context { |
| 2175 | #if defined(__BIG_ENDIAN) |
| 2176 | u16 __reserved0; |
| 2177 | u8 sb_index_number; |
| 2178 | u8 status_block_id; |
| 2179 | #elif defined(__LITTLE_ENDIAN) |
| 2180 | u8 status_block_id; |
| 2181 | u8 sb_index_number; |
| 2182 | u16 __reserved0; |
| 2183 | #endif |
| 2184 | u32 __reserved1[3]; |
| 2185 | }; |
| 2186 | |
| 2187 | /* |
| 2188 | * Ethernet connection context |
| 2189 | */ |
| 2190 | struct eth_context { |
| 2191 | struct ustorm_eth_st_context ustorm_st_context; |
| 2192 | struct tstorm_eth_st_context tstorm_st_context; |
| 2193 | struct xstorm_eth_ag_context xstorm_ag_context; |
| 2194 | struct tstorm_eth_ag_context tstorm_ag_context; |
| 2195 | struct cstorm_eth_ag_context cstorm_ag_context; |
| 2196 | struct ustorm_eth_ag_context ustorm_ag_context; |
| 2197 | struct timers_block_context timers_context; |
| 2198 | struct xstorm_eth_st_context xstorm_st_context; |
| 2199 | struct cstorm_eth_st_context cstorm_st_context; |
| 2200 | }; |
| 2201 | |
| 2202 | |
| 2203 | /* |
| 2204 | * Ethernet doorbell |
| 2205 | */ |
| 2206 | struct eth_tx_doorbell { |
| 2207 | #if defined(__BIG_ENDIAN) |
| 2208 | u16 npackets; |
| 2209 | u8 params; |
| 2210 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) |
| 2211 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 |
| 2212 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) |
| 2213 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 |
| 2214 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) |
| 2215 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 |
| 2216 | struct doorbell_hdr hdr; |
| 2217 | #elif defined(__LITTLE_ENDIAN) |
| 2218 | struct doorbell_hdr hdr; |
| 2219 | u8 params; |
| 2220 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) |
| 2221 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 |
| 2222 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) |
| 2223 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 |
| 2224 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) |
| 2225 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 |
| 2226 | u16 npackets; |
| 2227 | #endif |
| 2228 | }; |
| 2229 | |
| 2230 | |
| 2231 | /* |
| 2232 | * cstorm default status block, generated by ustorm |
| 2233 | */ |
| 2234 | struct cstorm_def_status_block_u { |
| 2235 | __le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES]; |
| 2236 | __le16 status_block_index; |
| 2237 | u8 func; |
| 2238 | u8 status_block_id; |
| 2239 | __le32 __flags; |
| 2240 | }; |
| 2241 | |
| 2242 | /* |
| 2243 | * cstorm default status block, generated by cstorm |
| 2244 | */ |
| 2245 | struct cstorm_def_status_block_c { |
| 2246 | __le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES]; |
| 2247 | __le16 status_block_index; |
| 2248 | u8 func; |
| 2249 | u8 status_block_id; |
| 2250 | __le32 __flags; |
| 2251 | }; |
| 2252 | |
| 2253 | /* |
| 2254 | * xstorm status block |
| 2255 | */ |
| 2256 | struct xstorm_def_status_block { |
| 2257 | __le16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES]; |
| 2258 | __le16 status_block_index; |
| 2259 | u8 func; |
| 2260 | u8 status_block_id; |
| 2261 | __le32 __flags; |
| 2262 | }; |
| 2263 | |
| 2264 | /* |
| 2265 | * tstorm status block |
| 2266 | */ |
| 2267 | struct tstorm_def_status_block { |
| 2268 | __le16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES]; |
| 2269 | __le16 status_block_index; |
| 2270 | u8 func; |
| 2271 | u8 status_block_id; |
| 2272 | __le32 __flags; |
| 2273 | }; |
| 2274 | |
| 2275 | /* |
| 2276 | * host status block |
| 2277 | */ |
| 2278 | struct host_def_status_block { |
| 2279 | struct atten_def_status_block atten_status_block; |
| 2280 | struct cstorm_def_status_block_u u_def_status_block; |
| 2281 | struct cstorm_def_status_block_c c_def_status_block; |
| 2282 | struct xstorm_def_status_block x_def_status_block; |
| 2283 | struct tstorm_def_status_block t_def_status_block; |
| 2284 | }; |
| 2285 | |
| 2286 | |
| 2287 | /* |
| 2288 | * cstorm status block, generated by ustorm |
| 2289 | */ |
| 2290 | struct cstorm_status_block_u { |
| 2291 | __le16 index_values[HC_USTORM_SB_NUM_INDICES]; |
| 2292 | __le16 status_block_index; |
| 2293 | u8 func; |
| 2294 | u8 status_block_id; |
| 2295 | __le32 __flags; |
| 2296 | }; |
| 2297 | |
| 2298 | /* |
| 2299 | * cstorm status block, generated by cstorm |
| 2300 | */ |
| 2301 | struct cstorm_status_block_c { |
| 2302 | __le16 index_values[HC_CSTORM_SB_NUM_INDICES]; |
| 2303 | __le16 status_block_index; |
| 2304 | u8 func; |
| 2305 | u8 status_block_id; |
| 2306 | __le32 __flags; |
| 2307 | }; |
| 2308 | |
| 2309 | /* |
| 2310 | * host status block |
| 2311 | */ |
| 2312 | struct host_status_block { |
| 2313 | struct cstorm_status_block_u u_status_block; |
| 2314 | struct cstorm_status_block_c c_status_block; |
| 2315 | }; |
| 2316 | |
| 2317 | |
| 2318 | /* |
| 2319 | * The data for RSS setup ramrod |
| 2320 | */ |
| 2321 | struct eth_client_setup_ramrod_data { |
| 2322 | u32 client_id; |
| 2323 | u8 is_rdma; |
| 2324 | u8 is_fcoe; |
| 2325 | u16 reserved1; |
| 2326 | }; |
| 2327 | |
| 2328 | |
| 2329 | /* |
| 2330 | * regular eth FP CQE parameters struct |
| 2331 | */ |
| 2332 | struct eth_fast_path_rx_cqe { |
| 2333 | u8 type_error_flags; |
| 2334 | #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0) |
| 2335 | #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 |
| 2336 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1) |
| 2337 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1 |
| 2338 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2) |
| 2339 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2 |
| 2340 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3) |
| 2341 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3 |
| 2342 | #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4) |
| 2343 | #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4 |
| 2344 | #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5) |
| 2345 | #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5 |
| 2346 | #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) |
| 2347 | #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 |
| 2348 | u8 status_flags; |
| 2349 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) |
| 2350 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 |
| 2351 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) |
| 2352 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 |
| 2353 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) |
| 2354 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 |
| 2355 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) |
| 2356 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 |
| 2357 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) |
| 2358 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 |
| 2359 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) |
| 2360 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 |
| 2361 | u8 placement_offset; |
| 2362 | u8 queue_index; |
| 2363 | __le32 rss_hash_result; |
| 2364 | __le16 vlan_tag; |
| 2365 | __le16 pkt_len; |
| 2366 | __le16 len_on_bd; |
| 2367 | struct parsing_flags pars_flags; |
| 2368 | __le16 sgl[8]; |
| 2369 | }; |
| 2370 | |
| 2371 | |
| 2372 | /* |
| 2373 | * The data for RSS setup ramrod |
| 2374 | */ |
| 2375 | struct eth_halt_ramrod_data { |
| 2376 | u32 client_id; |
| 2377 | u32 reserved0; |
| 2378 | }; |
| 2379 | |
| 2380 | |
| 2381 | /* |
| 2382 | * The data for statistics query ramrod |
| 2383 | */ |
| 2384 | struct eth_query_ramrod_data { |
| 2385 | #if defined(__BIG_ENDIAN) |
| 2386 | u8 reserved0; |
| 2387 | u8 collect_port; |
| 2388 | u16 drv_counter; |
| 2389 | #elif defined(__LITTLE_ENDIAN) |
| 2390 | u16 drv_counter; |
| 2391 | u8 collect_port; |
| 2392 | u8 reserved0; |
| 2393 | #endif |
| 2394 | u32 ctr_id_vector; |
| 2395 | }; |
| 2396 | |
| 2397 | |
| 2398 | /* |
| 2399 | * Place holder for ramrods protocol specific data |
| 2400 | */ |
| 2401 | struct ramrod_data { |
| 2402 | __le32 data_lo; |
| 2403 | __le32 data_hi; |
| 2404 | }; |
| 2405 | |
| 2406 | /* |
| 2407 | * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) |
| 2408 | */ |
| 2409 | union eth_ramrod_data { |
| 2410 | struct ramrod_data general; |
| 2411 | }; |
| 2412 | |
| 2413 | |
| 2414 | /* |
| 2415 | * Eth Rx Cqe structure- general structure for ramrods |
| 2416 | */ |
| 2417 | struct common_ramrod_eth_rx_cqe { |
| 2418 | u8 ramrod_type; |
| 2419 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0) |
| 2420 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 |
| 2421 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1) |
| 2422 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1 |
| 2423 | u8 conn_type; |
| 2424 | __le16 reserved1; |
| 2425 | __le32 conn_and_cmd_data; |
| 2426 | #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) |
| 2427 | #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 |
| 2428 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) |
| 2429 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 |
| 2430 | struct ramrod_data protocol_data; |
| 2431 | __le32 reserved2[4]; |
| 2432 | }; |
| 2433 | |
| 2434 | /* |
| 2435 | * Rx Last CQE in page (in ETH) |
| 2436 | */ |
| 2437 | struct eth_rx_cqe_next_page { |
| 2438 | __le32 addr_lo; |
| 2439 | __le32 addr_hi; |
| 2440 | __le32 reserved[6]; |
| 2441 | }; |
| 2442 | |
| 2443 | /* |
| 2444 | * union for all eth rx cqe types (fix their sizes) |
| 2445 | */ |
| 2446 | union eth_rx_cqe { |
| 2447 | struct eth_fast_path_rx_cqe fast_path_cqe; |
| 2448 | struct common_ramrod_eth_rx_cqe ramrod_cqe; |
| 2449 | struct eth_rx_cqe_next_page next_page_cqe; |
| 2450 | }; |
| 2451 | |
| 2452 | |
| 2453 | /* |
| 2454 | * common data for all protocols |
| 2455 | */ |
| 2456 | struct spe_hdr { |
| 2457 | __le32 conn_and_cmd_data; |
| 2458 | #define SPE_HDR_CID (0xFFFFFF<<0) |
| 2459 | #define SPE_HDR_CID_SHIFT 0 |
| 2460 | #define SPE_HDR_CMD_ID (0xFF<<24) |
| 2461 | #define SPE_HDR_CMD_ID_SHIFT 24 |
| 2462 | __le16 type; |
| 2463 | #define SPE_HDR_CONN_TYPE (0xFF<<0) |
| 2464 | #define SPE_HDR_CONN_TYPE_SHIFT 0 |
| 2465 | #define SPE_HDR_COMMON_RAMROD (0xFF<<8) |
| 2466 | #define SPE_HDR_COMMON_RAMROD_SHIFT 8 |
| 2467 | __le16 reserved; |
| 2468 | }; |
| 2469 | |
| 2470 | /* |
| 2471 | * Ethernet slow path element |
| 2472 | */ |
| 2473 | union eth_specific_data { |
| 2474 | u8 protocol_data[8]; |
| 2475 | struct regpair mac_config_addr; |
| 2476 | struct eth_client_setup_ramrod_data client_setup_ramrod_data; |
| 2477 | struct eth_halt_ramrod_data halt_ramrod_data; |
| 2478 | struct regpair leading_cqe_addr; |
| 2479 | struct regpair update_data_addr; |
| 2480 | struct eth_query_ramrod_data query_ramrod_data; |
| 2481 | }; |
| 2482 | |
| 2483 | /* |
| 2484 | * Ethernet slow path element |
| 2485 | */ |
| 2486 | struct eth_spe { |
| 2487 | struct spe_hdr hdr; |
| 2488 | union eth_specific_data data; |
| 2489 | }; |
| 2490 | |
| 2491 | |
| 2492 | /* |
| 2493 | * array of 13 bds as appears in the eth xstorm context |
| 2494 | */ |
| 2495 | struct eth_tx_bds_array { |
| 2496 | union eth_tx_bd_types bds[13]; |
| 2497 | }; |
| 2498 | |
| 2499 | |
| 2500 | /* |
| 2501 | * Common configuration parameters per function in Tstorm |
| 2502 | */ |
| 2503 | struct tstorm_eth_function_common_config { |
| 2504 | #if defined(__BIG_ENDIAN) |
| 2505 | u8 leading_client_id; |
| 2506 | u8 rss_result_mask; |
| 2507 | u16 config_flags; |
| 2508 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) |
| 2509 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 |
| 2510 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) |
| 2511 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 |
| 2512 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) |
| 2513 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 |
| 2514 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) |
| 2515 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 |
| 2516 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) |
| 2517 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 |
| 2518 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7) |
| 2519 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7 |
| 2520 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8) |
| 2521 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8 |
| 2522 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9) |
| 2523 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9 |
| 2524 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10) |
| 2525 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10 |
| 2526 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11) |
| 2527 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11 |
| 2528 | #elif defined(__LITTLE_ENDIAN) |
| 2529 | u16 config_flags; |
| 2530 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) |
| 2531 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 |
| 2532 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) |
| 2533 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 |
| 2534 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) |
| 2535 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 |
| 2536 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) |
| 2537 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 |
| 2538 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) |
| 2539 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 |
| 2540 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7) |
| 2541 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7 |
| 2542 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8) |
| 2543 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8 |
| 2544 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9) |
| 2545 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9 |
| 2546 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10) |
| 2547 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10 |
| 2548 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11) |
| 2549 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11 |
| 2550 | u8 rss_result_mask; |
| 2551 | u8 leading_client_id; |
| 2552 | #endif |
| 2553 | u16 vlan_id[2]; |
| 2554 | }; |
| 2555 | |
| 2556 | /* |
| 2557 | * RSS idirection table update configuration |
| 2558 | */ |
| 2559 | struct rss_update_config { |
| 2560 | #if defined(__BIG_ENDIAN) |
| 2561 | u16 toe_rss_bitmap; |
| 2562 | u16 flags; |
| 2563 | #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0) |
| 2564 | #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0 |
| 2565 | #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1) |
| 2566 | #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1 |
| 2567 | #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2) |
| 2568 | #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2 |
| 2569 | #elif defined(__LITTLE_ENDIAN) |
| 2570 | u16 flags; |
| 2571 | #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0) |
| 2572 | #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0 |
| 2573 | #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1) |
| 2574 | #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1 |
| 2575 | #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2) |
| 2576 | #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2 |
| 2577 | u16 toe_rss_bitmap; |
| 2578 | #endif |
| 2579 | u32 reserved1; |
| 2580 | }; |
| 2581 | |
| 2582 | /* |
| 2583 | * parameters for eth update ramrod |
| 2584 | */ |
| 2585 | struct eth_update_ramrod_data { |
| 2586 | struct tstorm_eth_function_common_config func_config; |
| 2587 | u8 indirectionTable[128]; |
| 2588 | struct rss_update_config rss_config; |
| 2589 | }; |
| 2590 | |
| 2591 | |
| 2592 | /* |
| 2593 | * MAC filtering configuration command header |
| 2594 | */ |
| 2595 | struct mac_configuration_hdr { |
| 2596 | u8 length; |
| 2597 | u8 offset; |
| 2598 | u16 client_id; |
| 2599 | u32 reserved1; |
| 2600 | }; |
| 2601 | |
| 2602 | /* |
| 2603 | * MAC address in list for ramrod |
| 2604 | */ |
| 2605 | struct tstorm_cam_entry { |
| 2606 | __le16 lsb_mac_addr; |
| 2607 | __le16 middle_mac_addr; |
| 2608 | __le16 msb_mac_addr; |
| 2609 | __le16 flags; |
| 2610 | #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0) |
| 2611 | #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0 |
| 2612 | #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1) |
| 2613 | #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1 |
| 2614 | #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4) |
| 2615 | #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4 |
| 2616 | }; |
| 2617 | |
| 2618 | /* |
| 2619 | * MAC filtering: CAM target table entry |
| 2620 | */ |
| 2621 | struct tstorm_cam_target_table_entry { |
| 2622 | u8 flags; |
| 2623 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0) |
| 2624 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0 |
| 2625 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1) |
| 2626 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1 |
| 2627 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2) |
| 2628 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2 |
| 2629 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3) |
| 2630 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3 |
| 2631 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4) |
| 2632 | #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4 |
| 2633 | u8 reserved1; |
| 2634 | u16 vlan_id; |
| 2635 | u32 clients_bit_vector; |
| 2636 | }; |
| 2637 | |
| 2638 | /* |
| 2639 | * MAC address in list for ramrod |
| 2640 | */ |
| 2641 | struct mac_configuration_entry { |
| 2642 | struct tstorm_cam_entry cam_entry; |
| 2643 | struct tstorm_cam_target_table_entry target_table_entry; |
| 2644 | }; |
| 2645 | |
| 2646 | /* |
| 2647 | * MAC filtering configuration command |
| 2648 | */ |
| 2649 | struct mac_configuration_cmd { |
| 2650 | struct mac_configuration_hdr hdr; |
| 2651 | struct mac_configuration_entry config_table[64]; |
| 2652 | }; |
| 2653 | |
| 2654 | |
| 2655 | /* |
| 2656 | * MAC address in list for ramrod |
| 2657 | */ |
| 2658 | struct mac_configuration_entry_e1h { |
| 2659 | __le16 lsb_mac_addr; |
| 2660 | __le16 middle_mac_addr; |
| 2661 | __le16 msb_mac_addr; |
| 2662 | __le16 vlan_id; |
| 2663 | __le16 e1hov_id; |
| 2664 | u8 reserved0; |
| 2665 | u8 flags; |
| 2666 | #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0) |
| 2667 | #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0 |
| 2668 | #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1) |
| 2669 | #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1 |
| 2670 | #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2) |
| 2671 | #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2 |
| 2672 | #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1 (0x1F<<3) |
| 2673 | #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1_SHIFT 3 |
| 2674 | u32 clients_bit_vector; |
| 2675 | }; |
| 2676 | |
| 2677 | /* |
| 2678 | * MAC filtering configuration command |
| 2679 | */ |
| 2680 | struct mac_configuration_cmd_e1h { |
| 2681 | struct mac_configuration_hdr hdr; |
| 2682 | struct mac_configuration_entry_e1h config_table[32]; |
| 2683 | }; |
| 2684 | |
| 2685 | |
| 2686 | /* |
| 2687 | * approximate-match multicast filtering for E1H per function in Tstorm |
| 2688 | */ |
| 2689 | struct tstorm_eth_approximate_match_multicast_filtering { |
| 2690 | u32 mcast_add_hash_bit_array[8]; |
| 2691 | }; |
| 2692 | |
| 2693 | |
| 2694 | /* |
| 2695 | * Configuration parameters per client in Tstorm |
| 2696 | */ |
| 2697 | struct tstorm_eth_client_config { |
| 2698 | #if defined(__BIG_ENDIAN) |
| 2699 | u8 reserved0; |
| 2700 | u8 statistics_counter_id; |
| 2701 | u16 mtu; |
| 2702 | #elif defined(__LITTLE_ENDIAN) |
| 2703 | u16 mtu; |
| 2704 | u8 statistics_counter_id; |
| 2705 | u8 reserved0; |
| 2706 | #endif |
| 2707 | #if defined(__BIG_ENDIAN) |
| 2708 | u16 drop_flags; |
| 2709 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0) |
| 2710 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 |
| 2711 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1) |
| 2712 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1 |
| 2713 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2) |
| 2714 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2 |
| 2715 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3) |
| 2716 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3 |
| 2717 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4) |
| 2718 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4 |
| 2719 | u16 config_flags; |
| 2720 | #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0) |
| 2721 | #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0 |
| 2722 | #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1) |
| 2723 | #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1 |
| 2724 | #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2) |
| 2725 | #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2 |
| 2726 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3) |
| 2727 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3 |
| 2728 | #elif defined(__LITTLE_ENDIAN) |
| 2729 | u16 config_flags; |
| 2730 | #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0) |
| 2731 | #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0 |
| 2732 | #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1) |
| 2733 | #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1 |
| 2734 | #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2) |
| 2735 | #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2 |
| 2736 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3) |
| 2737 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3 |
| 2738 | u16 drop_flags; |
| 2739 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0) |
| 2740 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0 |
| 2741 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1) |
| 2742 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1 |
| 2743 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2) |
| 2744 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2 |
| 2745 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3) |
| 2746 | #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3 |
| 2747 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4) |
| 2748 | #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4 |
| 2749 | #endif |
| 2750 | }; |
| 2751 | |
| 2752 | |
| 2753 | /* |
| 2754 | * MAC filtering configuration parameters per port in Tstorm |
| 2755 | */ |
| 2756 | struct tstorm_eth_mac_filter_config { |
| 2757 | u32 ucast_drop_all; |
| 2758 | u32 ucast_accept_all; |
| 2759 | u32 mcast_drop_all; |
| 2760 | u32 mcast_accept_all; |
| 2761 | u32 bcast_drop_all; |
| 2762 | u32 bcast_accept_all; |
| 2763 | u32 strict_vlan; |
| 2764 | u32 vlan_filter[2]; |
| 2765 | u32 reserved; |
| 2766 | }; |
| 2767 | |
| 2768 | |
| 2769 | /* |
| 2770 | * common flag to indicate existance of TPA. |
| 2771 | */ |
| 2772 | struct tstorm_eth_tpa_exist { |
| 2773 | #if defined(__BIG_ENDIAN) |
| 2774 | u16 reserved1; |
| 2775 | u8 reserved0; |
| 2776 | u8 tpa_exist; |
| 2777 | #elif defined(__LITTLE_ENDIAN) |
| 2778 | u8 tpa_exist; |
| 2779 | u8 reserved0; |
| 2780 | u16 reserved1; |
| 2781 | #endif |
| 2782 | u32 reserved2; |
| 2783 | }; |
| 2784 | |
| 2785 | |
| 2786 | /* |
| 2787 | * rx rings pause data for E1h only |
| 2788 | */ |
| 2789 | struct ustorm_eth_rx_pause_data_e1h { |
| 2790 | #if defined(__BIG_ENDIAN) |
| 2791 | u16 bd_thr_low; |
| 2792 | u16 cqe_thr_low; |
| 2793 | #elif defined(__LITTLE_ENDIAN) |
| 2794 | u16 cqe_thr_low; |
| 2795 | u16 bd_thr_low; |
| 2796 | #endif |
| 2797 | #if defined(__BIG_ENDIAN) |
| 2798 | u16 cos; |
| 2799 | u16 sge_thr_low; |
| 2800 | #elif defined(__LITTLE_ENDIAN) |
| 2801 | u16 sge_thr_low; |
| 2802 | u16 cos; |
| 2803 | #endif |
| 2804 | #if defined(__BIG_ENDIAN) |
| 2805 | u16 bd_thr_high; |
| 2806 | u16 cqe_thr_high; |
| 2807 | #elif defined(__LITTLE_ENDIAN) |
| 2808 | u16 cqe_thr_high; |
| 2809 | u16 bd_thr_high; |
| 2810 | #endif |
| 2811 | #if defined(__BIG_ENDIAN) |
| 2812 | u16 reserved0; |
| 2813 | u16 sge_thr_high; |
| 2814 | #elif defined(__LITTLE_ENDIAN) |
| 2815 | u16 sge_thr_high; |
| 2816 | u16 reserved0; |
| 2817 | #endif |
| 2818 | }; |
| 2819 | |
| 2820 | |
| 2821 | /* |
| 2822 | * Three RX producers for ETH |
| 2823 | */ |
| 2824 | struct ustorm_eth_rx_producers { |
| 2825 | #if defined(__BIG_ENDIAN) |
| 2826 | u16 bd_prod; |
| 2827 | u16 cqe_prod; |
| 2828 | #elif defined(__LITTLE_ENDIAN) |
| 2829 | u16 cqe_prod; |
| 2830 | u16 bd_prod; |
| 2831 | #endif |
| 2832 | #if defined(__BIG_ENDIAN) |
| 2833 | u16 reserved; |
| 2834 | u16 sge_prod; |
| 2835 | #elif defined(__LITTLE_ENDIAN) |
| 2836 | u16 sge_prod; |
| 2837 | u16 reserved; |
| 2838 | #endif |
| 2839 | }; |
| 2840 | |
| 2841 | |
| 2842 | /* |
| 2843 | * per-port SAFC demo variables |
| 2844 | */ |
| 2845 | struct cmng_flags_per_port { |
| 2846 | u8 con_number[NUM_OF_PROTOCOLS]; |
| 2847 | u32 cmng_enables; |
| 2848 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) |
| 2849 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 |
| 2850 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) |
| 2851 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 |
| 2852 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2) |
| 2853 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2 |
| 2854 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3) |
| 2855 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3 |
| 2856 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4) |
| 2857 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4 |
| 2858 | #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5) |
| 2859 | #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5 |
| 2860 | }; |
| 2861 | |
| 2862 | |
| 2863 | /* |
| 2864 | * per-port rate shaping variables |
| 2865 | */ |
| 2866 | struct rate_shaping_vars_per_port { |
| 2867 | u32 rs_periodic_timeout; |
| 2868 | u32 rs_threshold; |
| 2869 | }; |
| 2870 | |
| 2871 | /* |
| 2872 | * per-port fairness variables |
| 2873 | */ |
| 2874 | struct fairness_vars_per_port { |
| 2875 | u32 upper_bound; |
| 2876 | u32 fair_threshold; |
| 2877 | u32 fairness_timeout; |
| 2878 | }; |
| 2879 | |
| 2880 | /* |
| 2881 | * per-port SAFC variables |
| 2882 | */ |
| 2883 | struct safc_struct_per_port { |
| 2884 | #if defined(__BIG_ENDIAN) |
| 2885 | u16 __reserved1; |
| 2886 | u8 __reserved0; |
| 2887 | u8 safc_timeout_usec; |
| 2888 | #elif defined(__LITTLE_ENDIAN) |
| 2889 | u8 safc_timeout_usec; |
| 2890 | u8 __reserved0; |
| 2891 | u16 __reserved1; |
| 2892 | #endif |
| 2893 | u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; |
| 2894 | }; |
| 2895 | |
| 2896 | /* |
| 2897 | * Per-port congestion management variables |
| 2898 | */ |
| 2899 | struct cmng_struct_per_port { |
| 2900 | struct rate_shaping_vars_per_port rs_vars; |
| 2901 | struct fairness_vars_per_port fair_vars; |
| 2902 | struct safc_struct_per_port safc_vars; |
| 2903 | struct cmng_flags_per_port flags; |
| 2904 | }; |
| 2905 | |
| 2906 | |
| 2907 | /* |
| 2908 | * Dynamic host coalescing init parameters |
| 2909 | */ |
| 2910 | struct dynamic_hc_config { |
| 2911 | u32 threshold[3]; |
| 2912 | u8 shift_per_protocol[HC_USTORM_SB_NUM_INDICES]; |
| 2913 | u8 hc_timeout0[HC_USTORM_SB_NUM_INDICES]; |
| 2914 | u8 hc_timeout1[HC_USTORM_SB_NUM_INDICES]; |
| 2915 | u8 hc_timeout2[HC_USTORM_SB_NUM_INDICES]; |
| 2916 | u8 hc_timeout3[HC_USTORM_SB_NUM_INDICES]; |
| 2917 | }; |
| 2918 | |
| 2919 | |
| 2920 | /* |
| 2921 | * Protocol-common statistics collected by the Xstorm (per client) |
| 2922 | */ |
| 2923 | struct xstorm_per_client_stats { |
| 2924 | __le32 reserved0; |
| 2925 | __le32 unicast_pkts_sent; |
| 2926 | struct regpair unicast_bytes_sent; |
| 2927 | struct regpair multicast_bytes_sent; |
| 2928 | __le32 multicast_pkts_sent; |
| 2929 | __le32 broadcast_pkts_sent; |
| 2930 | struct regpair broadcast_bytes_sent; |
| 2931 | __le16 stats_counter; |
| 2932 | __le16 reserved1; |
| 2933 | __le32 reserved2; |
| 2934 | }; |
| 2935 | |
| 2936 | /* |
| 2937 | * Common statistics collected by the Xstorm (per port) |
| 2938 | */ |
| 2939 | struct xstorm_common_stats { |
| 2940 | struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID]; |
| 2941 | }; |
| 2942 | |
| 2943 | /* |
| 2944 | * Protocol-common statistics collected by the Tstorm (per port) |
| 2945 | */ |
| 2946 | struct tstorm_per_port_stats { |
| 2947 | __le32 mac_filter_discard; |
| 2948 | __le32 xxoverflow_discard; |
| 2949 | __le32 brb_truncate_discard; |
| 2950 | __le32 mac_discard; |
| 2951 | }; |
| 2952 | |
| 2953 | /* |
| 2954 | * Protocol-common statistics collected by the Tstorm (per client) |
| 2955 | */ |
| 2956 | struct tstorm_per_client_stats { |
| 2957 | struct regpair rcv_unicast_bytes; |
| 2958 | struct regpair rcv_broadcast_bytes; |
| 2959 | struct regpair rcv_multicast_bytes; |
| 2960 | struct regpair rcv_error_bytes; |
| 2961 | __le32 checksum_discard; |
| 2962 | __le32 packets_too_big_discard; |
| 2963 | __le32 rcv_unicast_pkts; |
| 2964 | __le32 rcv_broadcast_pkts; |
| 2965 | __le32 rcv_multicast_pkts; |
| 2966 | __le32 no_buff_discard; |
| 2967 | __le32 ttl0_discard; |
| 2968 | __le16 stats_counter; |
| 2969 | __le16 reserved0; |
| 2970 | }; |
| 2971 | |
| 2972 | /* |
| 2973 | * Protocol-common statistics collected by the Tstorm |
| 2974 | */ |
| 2975 | struct tstorm_common_stats { |
| 2976 | struct tstorm_per_port_stats port_statistics; |
| 2977 | struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID]; |
| 2978 | }; |
| 2979 | |
| 2980 | /* |
| 2981 | * Protocol-common statistics collected by the Ustorm (per client) |
| 2982 | */ |
| 2983 | struct ustorm_per_client_stats { |
| 2984 | struct regpair ucast_no_buff_bytes; |
| 2985 | struct regpair mcast_no_buff_bytes; |
| 2986 | struct regpair bcast_no_buff_bytes; |
| 2987 | __le32 ucast_no_buff_pkts; |
| 2988 | __le32 mcast_no_buff_pkts; |
| 2989 | __le32 bcast_no_buff_pkts; |
| 2990 | __le16 stats_counter; |
| 2991 | __le16 reserved0; |
| 2992 | }; |
| 2993 | |
| 2994 | /* |
| 2995 | * Protocol-common statistics collected by the Ustorm |
| 2996 | */ |
| 2997 | struct ustorm_common_stats { |
| 2998 | struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID]; |
| 2999 | }; |
| 3000 | |
| 3001 | /* |
| 3002 | * Eth statistics query structure for the eth_stats_query ramrod |
| 3003 | */ |
| 3004 | struct eth_stats_query { |
| 3005 | struct xstorm_common_stats xstorm_common; |
| 3006 | struct tstorm_common_stats tstorm_common; |
| 3007 | struct ustorm_common_stats ustorm_common; |
| 3008 | }; |
| 3009 | |
| 3010 | |
| 3011 | /* |
| 3012 | * per-vnic fairness variables |
| 3013 | */ |
| 3014 | struct fairness_vars_per_vn { |
| 3015 | u32 cos_credit_delta[MAX_COS_NUMBER]; |
| 3016 | u32 protocol_credit_delta[NUM_OF_PROTOCOLS]; |
| 3017 | u32 vn_credit_delta; |
| 3018 | u32 __reserved0; |
| 3019 | }; |
| 3020 | |
| 3021 | |
| 3022 | /* |
| 3023 | * FW version stored in the Xstorm RAM |
| 3024 | */ |
| 3025 | struct fw_version { |
| 3026 | #if defined(__BIG_ENDIAN) |
| 3027 | u8 engineering; |
| 3028 | u8 revision; |
| 3029 | u8 minor; |
| 3030 | u8 major; |
| 3031 | #elif defined(__LITTLE_ENDIAN) |
| 3032 | u8 major; |
| 3033 | u8 minor; |
| 3034 | u8 revision; |
| 3035 | u8 engineering; |
| 3036 | #endif |
| 3037 | u32 flags; |
| 3038 | #define FW_VERSION_OPTIMIZED (0x1<<0) |
| 3039 | #define FW_VERSION_OPTIMIZED_SHIFT 0 |
| 3040 | #define FW_VERSION_BIG_ENDIEN (0x1<<1) |
| 3041 | #define FW_VERSION_BIG_ENDIEN_SHIFT 1 |
| 3042 | #define FW_VERSION_CHIP_VERSION (0x3<<2) |
| 3043 | #define FW_VERSION_CHIP_VERSION_SHIFT 2 |
| 3044 | #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) |
| 3045 | #define __FW_VERSION_RESERVED_SHIFT 4 |
| 3046 | }; |
| 3047 | |
| 3048 | |
| 3049 | /* |
| 3050 | * FW version stored in first line of pram |
| 3051 | */ |
| 3052 | struct pram_fw_version { |
| 3053 | u8 major; |
| 3054 | u8 minor; |
| 3055 | u8 revision; |
| 3056 | u8 engineering; |
| 3057 | u8 flags; |
| 3058 | #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) |
| 3059 | #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 |
| 3060 | #define PRAM_FW_VERSION_STORM_ID (0x3<<1) |
| 3061 | #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 |
| 3062 | #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) |
| 3063 | #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 |
| 3064 | #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) |
| 3065 | #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 |
| 3066 | #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) |
| 3067 | #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 |
| 3068 | }; |
| 3069 | |
| 3070 | |
| 3071 | /* |
| 3072 | * The send queue element |
| 3073 | */ |
| 3074 | struct protocol_common_spe { |
| 3075 | struct spe_hdr hdr; |
| 3076 | struct regpair phy_address; |
| 3077 | }; |
| 3078 | |
| 3079 | |
| 3080 | /* |
| 3081 | * a single rate shaping counter. can be used as protocol or vnic counter |
| 3082 | */ |
| 3083 | struct rate_shaping_counter { |
| 3084 | u32 quota; |
| 3085 | #if defined(__BIG_ENDIAN) |
| 3086 | u16 __reserved0; |
| 3087 | u16 rate; |
| 3088 | #elif defined(__LITTLE_ENDIAN) |
| 3089 | u16 rate; |
| 3090 | u16 __reserved0; |
| 3091 | #endif |
| 3092 | }; |
| 3093 | |
| 3094 | |
| 3095 | /* |
| 3096 | * per-vnic rate shaping variables |
| 3097 | */ |
| 3098 | struct rate_shaping_vars_per_vn { |
| 3099 | struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS]; |
| 3100 | struct rate_shaping_counter vn_counter; |
| 3101 | }; |
| 3102 | |
| 3103 | |
| 3104 | /* |
| 3105 | * The send queue element |
| 3106 | */ |
| 3107 | struct slow_path_element { |
| 3108 | struct spe_hdr hdr; |
| 3109 | u8 protocol_data[8]; |
| 3110 | }; |
| 3111 | |
| 3112 | |
| 3113 | /* |
| 3114 | * eth/toe flags that indicate if to query |
| 3115 | */ |
| 3116 | struct stats_indication_flags { |
| 3117 | u32 collect_eth; |
| 3118 | u32 collect_toe; |
| 3119 | }; |
| 3120 | |
| 3121 | |