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be2net: variable name change
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / benet / be_cmds.c
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1/*
2 * Copyright (C) 2005 - 2010 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
19#include "be_cmds.h"
20
21static void be_mcc_notify(struct be_adapter *adapter)
22{
23 struct be_queue_info *mccq = &adapter->mcc_obj.q;
24 u32 val = 0;
25
26 if (adapter->eeh_err) {
27 dev_info(&adapter->pdev->dev,
28 "Error in Card Detected! Cannot issue commands\n");
29 return;
30 }
31
32 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
33 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
34
35 wmb();
36 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
37}
38
39/* To check if valid bit is set, check the entire word as we don't know
40 * the endianness of the data (old entry is host endian while a new entry is
41 * little endian) */
42static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
43{
44 if (compl->flags != 0) {
45 compl->flags = le32_to_cpu(compl->flags);
46 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
47 return true;
48 } else {
49 return false;
50 }
51}
52
53/* Need to reset the entire word that houses the valid bit */
54static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
55{
56 compl->flags = 0;
57}
58
59static int be_mcc_compl_process(struct be_adapter *adapter,
60 struct be_mcc_compl *compl)
61{
62 u16 compl_status, extd_status;
63
64 /* Just swap the status to host endian; mcc tag is opaquely copied
65 * from mcc_wrb */
66 be_dws_le_to_cpu(compl, 4);
67
68 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
69 CQE_STATUS_COMPL_MASK;
70
71 if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
72 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
73 adapter->flash_status = compl_status;
74 complete(&adapter->flash_compl);
75 }
76
77 if (compl_status == MCC_STATUS_SUCCESS) {
78 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
79 struct be_cmd_resp_get_stats *resp =
80 adapter->stats_cmd.va;
81 be_dws_le_to_cpu(&resp->hw_stats,
82 sizeof(resp->hw_stats));
83 netdev_stats_update(adapter);
84 adapter->stats_cmd_sent = false;
85 }
86 } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
87 (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
88 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
89 CQE_STATUS_EXTD_MASK;
90 dev_warn(&adapter->pdev->dev,
91 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
92 compl->tag0, compl_status, extd_status);
93 }
94 return compl_status;
95}
96
97/* Link state evt is a string of bytes; no need for endian swapping */
98static void be_async_link_state_process(struct be_adapter *adapter,
99 struct be_async_event_link_state *evt)
100{
101 be_link_status_update(adapter,
102 evt->port_link_status == ASYNC_EVENT_LINK_UP);
103}
104
105/* Grp5 CoS Priority evt */
106static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
107 struct be_async_event_grp5_cos_priority *evt)
108{
109 if (evt->valid) {
110 adapter->vlan_prio_bmap = evt->available_priority_bmap;
111 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
112 adapter->recommended_prio =
113 evt->reco_default_priority << VLAN_PRIO_SHIFT;
114 }
115}
116
117/* Grp5 QOS Speed evt */
118static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
119 struct be_async_event_grp5_qos_link_speed *evt)
120{
121 if (evt->physical_port == adapter->port_num) {
122 /* qos_link_speed is in units of 10 Mbps */
123 adapter->link_speed = evt->qos_link_speed * 10;
124 }
125}
126
127static void be_async_grp5_evt_process(struct be_adapter *adapter,
128 u32 trailer, struct be_mcc_compl *evt)
129{
130 u8 event_type = 0;
131
132 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
133 ASYNC_TRAILER_EVENT_TYPE_MASK;
134
135 switch (event_type) {
136 case ASYNC_EVENT_COS_PRIORITY:
137 be_async_grp5_cos_priority_process(adapter,
138 (struct be_async_event_grp5_cos_priority *)evt);
139 break;
140 case ASYNC_EVENT_QOS_SPEED:
141 be_async_grp5_qos_speed_process(adapter,
142 (struct be_async_event_grp5_qos_link_speed *)evt);
143 break;
144 default:
145 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
146 break;
147 }
148}
149
150static inline bool is_link_state_evt(u32 trailer)
151{
152 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
153 ASYNC_TRAILER_EVENT_CODE_MASK) ==
154 ASYNC_EVENT_CODE_LINK_STATE;
155}
156
157static inline bool is_grp5_evt(u32 trailer)
158{
159 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
160 ASYNC_TRAILER_EVENT_CODE_MASK) ==
161 ASYNC_EVENT_CODE_GRP_5);
162}
163
164static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
165{
166 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
167 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
168
169 if (be_mcc_compl_is_new(compl)) {
170 queue_tail_inc(mcc_cq);
171 return compl;
172 }
173 return NULL;
174}
175
176void be_async_mcc_enable(struct be_adapter *adapter)
177{
178 spin_lock_bh(&adapter->mcc_cq_lock);
179
180 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
181 adapter->mcc_obj.rearm_cq = true;
182
183 spin_unlock_bh(&adapter->mcc_cq_lock);
184}
185
186void be_async_mcc_disable(struct be_adapter *adapter)
187{
188 adapter->mcc_obj.rearm_cq = false;
189}
190
191int be_process_mcc(struct be_adapter *adapter, int *status)
192{
193 struct be_mcc_compl *compl;
194 int num = 0;
195 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
196
197 spin_lock_bh(&adapter->mcc_cq_lock);
198 while ((compl = be_mcc_compl_get(adapter))) {
199 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
200 /* Interpret flags as an async trailer */
201 if (is_link_state_evt(compl->flags))
202 be_async_link_state_process(adapter,
203 (struct be_async_event_link_state *) compl);
204 else if (is_grp5_evt(compl->flags))
205 be_async_grp5_evt_process(adapter,
206 compl->flags, compl);
207 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
208 *status = be_mcc_compl_process(adapter, compl);
209 atomic_dec(&mcc_obj->q.used);
210 }
211 be_mcc_compl_use(compl);
212 num++;
213 }
214
215 spin_unlock_bh(&adapter->mcc_cq_lock);
216 return num;
217}
218
219/* Wait till no more pending mcc requests are present */
220static int be_mcc_wait_compl(struct be_adapter *adapter)
221{
222#define mcc_timeout 120000 /* 12s timeout */
223 int i, num, status = 0;
224 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
225
226 if (adapter->eeh_err)
227 return -EIO;
228
229 for (i = 0; i < mcc_timeout; i++) {
230 num = be_process_mcc(adapter, &status);
231 if (num)
232 be_cq_notify(adapter, mcc_obj->cq.id,
233 mcc_obj->rearm_cq, num);
234
235 if (atomic_read(&mcc_obj->q.used) == 0)
236 break;
237 udelay(100);
238 }
239 if (i == mcc_timeout) {
240 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
241 return -1;
242 }
243 return status;
244}
245
246/* Notify MCC requests and wait for completion */
247static int be_mcc_notify_wait(struct be_adapter *adapter)
248{
249 be_mcc_notify(adapter);
250 return be_mcc_wait_compl(adapter);
251}
252
253static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
254{
255 int msecs = 0;
256 u32 ready;
257
258 if (adapter->eeh_err) {
259 dev_err(&adapter->pdev->dev,
260 "Error detected in card.Cannot issue commands\n");
261 return -EIO;
262 }
263
264 do {
265 ready = ioread32(db);
266 if (ready == 0xffffffff) {
267 dev_err(&adapter->pdev->dev,
268 "pci slot disconnected\n");
269 return -1;
270 }
271
272 ready &= MPU_MAILBOX_DB_RDY_MASK;
273 if (ready)
274 break;
275
276 if (msecs > 4000) {
277 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
278 be_detect_dump_ue(adapter);
279 return -1;
280 }
281
282 set_current_state(TASK_INTERRUPTIBLE);
283 schedule_timeout(msecs_to_jiffies(1));
284 msecs++;
285 } while (true);
286
287 return 0;
288}
289
290/*
291 * Insert the mailbox address into the doorbell in two steps
292 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
293 */
294static int be_mbox_notify_wait(struct be_adapter *adapter)
295{
296 int status;
297 u32 val = 0;
298 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
299 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
300 struct be_mcc_mailbox *mbox = mbox_mem->va;
301 struct be_mcc_compl *compl = &mbox->compl;
302
303 /* wait for ready to be set */
304 status = be_mbox_db_ready_wait(adapter, db);
305 if (status != 0)
306 return status;
307
308 val |= MPU_MAILBOX_DB_HI_MASK;
309 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
310 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
311 iowrite32(val, db);
312
313 /* wait for ready to be set */
314 status = be_mbox_db_ready_wait(adapter, db);
315 if (status != 0)
316 return status;
317
318 val = 0;
319 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
320 val |= (u32)(mbox_mem->dma >> 4) << 2;
321 iowrite32(val, db);
322
323 status = be_mbox_db_ready_wait(adapter, db);
324 if (status != 0)
325 return status;
326
327 /* A cq entry has been made now */
328 if (be_mcc_compl_is_new(compl)) {
329 status = be_mcc_compl_process(adapter, &mbox->compl);
330 be_mcc_compl_use(compl);
331 if (status)
332 return status;
333 } else {
334 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
335 return -1;
336 }
337 return 0;
338}
339
340static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
341{
342 u32 sem;
343
344 if (lancer_chip(adapter))
345 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
346 else
347 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
348
349 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
350 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
351 return -1;
352 else
353 return 0;
354}
355
356int be_cmd_POST(struct be_adapter *adapter)
357{
358 u16 stage;
359 int status, timeout = 0;
360
361 do {
362 status = be_POST_stage_get(adapter, &stage);
363 if (status) {
364 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
365 stage);
366 return -1;
367 } else if (stage != POST_STAGE_ARMFW_RDY) {
368 set_current_state(TASK_INTERRUPTIBLE);
369 schedule_timeout(2 * HZ);
370 timeout += 2;
371 } else {
372 return 0;
373 }
374 } while (timeout < 40);
375
376 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
377 return -1;
378}
379
380static inline void *embedded_payload(struct be_mcc_wrb *wrb)
381{
382 return wrb->payload.embedded_payload;
383}
384
385static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
386{
387 return &wrb->payload.sgl[0];
388}
389
390/* Don't touch the hdr after it's prepared */
391static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
392 bool embedded, u8 sge_cnt, u32 opcode)
393{
394 if (embedded)
395 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
396 else
397 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
398 MCC_WRB_SGE_CNT_SHIFT;
399 wrb->payload_length = payload_len;
400 wrb->tag0 = opcode;
401 be_dws_cpu_to_le(wrb, 8);
402}
403
404/* Don't touch the hdr after it's prepared */
405static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
406 u8 subsystem, u8 opcode, int cmd_len)
407{
408 req_hdr->opcode = opcode;
409 req_hdr->subsystem = subsystem;
410 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
411 req_hdr->version = 0;
412}
413
414static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
415 struct be_dma_mem *mem)
416{
417 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
418 u64 dma = (u64)mem->dma;
419
420 for (i = 0; i < buf_pages; i++) {
421 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
422 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
423 dma += PAGE_SIZE_4K;
424 }
425}
426
427/* Converts interrupt delay in microseconds to multiplier value */
428static u32 eq_delay_to_mult(u32 usec_delay)
429{
430#define MAX_INTR_RATE 651042
431 const u32 round = 10;
432 u32 multiplier;
433
434 if (usec_delay == 0)
435 multiplier = 0;
436 else {
437 u32 interrupt_rate = 1000000 / usec_delay;
438 /* Max delay, corresponding to the lowest interrupt rate */
439 if (interrupt_rate == 0)
440 multiplier = 1023;
441 else {
442 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
443 multiplier /= interrupt_rate;
444 /* Round the multiplier to the closest value.*/
445 multiplier = (multiplier + round/2) / round;
446 multiplier = min(multiplier, (u32)1023);
447 }
448 }
449 return multiplier;
450}
451
452static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
453{
454 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
455 struct be_mcc_wrb *wrb
456 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
457 memset(wrb, 0, sizeof(*wrb));
458 return wrb;
459}
460
461static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
462{
463 struct be_queue_info *mccq = &adapter->mcc_obj.q;
464 struct be_mcc_wrb *wrb;
465
466 if (atomic_read(&mccq->used) >= mccq->len) {
467 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
468 return NULL;
469 }
470
471 wrb = queue_head_node(mccq);
472 queue_head_inc(mccq);
473 atomic_inc(&mccq->used);
474 memset(wrb, 0, sizeof(*wrb));
475 return wrb;
476}
477
478/* Tell fw we're about to start firing cmds by writing a
479 * special pattern across the wrb hdr; uses mbox
480 */
481int be_cmd_fw_init(struct be_adapter *adapter)
482{
483 u8 *wrb;
484 int status;
485
486 if (mutex_lock_interruptible(&adapter->mbox_lock))
487 return -1;
488
489 wrb = (u8 *)wrb_from_mbox(adapter);
490 *wrb++ = 0xFF;
491 *wrb++ = 0x12;
492 *wrb++ = 0x34;
493 *wrb++ = 0xFF;
494 *wrb++ = 0xFF;
495 *wrb++ = 0x56;
496 *wrb++ = 0x78;
497 *wrb = 0xFF;
498
499 status = be_mbox_notify_wait(adapter);
500
501 mutex_unlock(&adapter->mbox_lock);
502 return status;
503}
504
505/* Tell fw we're done with firing cmds by writing a
506 * special pattern across the wrb hdr; uses mbox
507 */
508int be_cmd_fw_clean(struct be_adapter *adapter)
509{
510 u8 *wrb;
511 int status;
512
513 if (adapter->eeh_err)
514 return -EIO;
515
516 if (mutex_lock_interruptible(&adapter->mbox_lock))
517 return -1;
518
519 wrb = (u8 *)wrb_from_mbox(adapter);
520 *wrb++ = 0xFF;
521 *wrb++ = 0xAA;
522 *wrb++ = 0xBB;
523 *wrb++ = 0xFF;
524 *wrb++ = 0xFF;
525 *wrb++ = 0xCC;
526 *wrb++ = 0xDD;
527 *wrb = 0xFF;
528
529 status = be_mbox_notify_wait(adapter);
530
531 mutex_unlock(&adapter->mbox_lock);
532 return status;
533}
534int be_cmd_eq_create(struct be_adapter *adapter,
535 struct be_queue_info *eq, int eq_delay)
536{
537 struct be_mcc_wrb *wrb;
538 struct be_cmd_req_eq_create *req;
539 struct be_dma_mem *q_mem = &eq->dma_mem;
540 int status;
541
542 if (mutex_lock_interruptible(&adapter->mbox_lock))
543 return -1;
544
545 wrb = wrb_from_mbox(adapter);
546 req = embedded_payload(wrb);
547
548 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
549
550 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
551 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
552
553 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
554
555 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
556 /* 4byte eqe*/
557 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
558 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
559 __ilog2_u32(eq->len/256));
560 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
561 eq_delay_to_mult(eq_delay));
562 be_dws_cpu_to_le(req->context, sizeof(req->context));
563
564 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
565
566 status = be_mbox_notify_wait(adapter);
567 if (!status) {
568 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
569 eq->id = le16_to_cpu(resp->eq_id);
570 eq->created = true;
571 }
572
573 mutex_unlock(&adapter->mbox_lock);
574 return status;
575}
576
577/* Uses mbox */
578int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
579 u8 type, bool permanent, u32 if_handle)
580{
581 struct be_mcc_wrb *wrb;
582 struct be_cmd_req_mac_query *req;
583 int status;
584
585 if (mutex_lock_interruptible(&adapter->mbox_lock))
586 return -1;
587
588 wrb = wrb_from_mbox(adapter);
589 req = embedded_payload(wrb);
590
591 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
592 OPCODE_COMMON_NTWK_MAC_QUERY);
593
594 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
595 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
596
597 req->type = type;
598 if (permanent) {
599 req->permanent = 1;
600 } else {
601 req->if_id = cpu_to_le16((u16) if_handle);
602 req->permanent = 0;
603 }
604
605 status = be_mbox_notify_wait(adapter);
606 if (!status) {
607 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
608 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
609 }
610
611 mutex_unlock(&adapter->mbox_lock);
612 return status;
613}
614
615/* Uses synchronous MCCQ */
616int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
617 u32 if_id, u32 *pmac_id, u32 domain)
618{
619 struct be_mcc_wrb *wrb;
620 struct be_cmd_req_pmac_add *req;
621 int status;
622
623 spin_lock_bh(&adapter->mcc_lock);
624
625 wrb = wrb_from_mccq(adapter);
626 if (!wrb) {
627 status = -EBUSY;
628 goto err;
629 }
630 req = embedded_payload(wrb);
631
632 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
633 OPCODE_COMMON_NTWK_PMAC_ADD);
634
635 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
636 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
637
638 req->hdr.domain = domain;
639 req->if_id = cpu_to_le32(if_id);
640 memcpy(req->mac_address, mac_addr, ETH_ALEN);
641
642 status = be_mcc_notify_wait(adapter);
643 if (!status) {
644 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
645 *pmac_id = le32_to_cpu(resp->pmac_id);
646 }
647
648err:
649 spin_unlock_bh(&adapter->mcc_lock);
650 return status;
651}
652
653/* Uses synchronous MCCQ */
654int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
655{
656 struct be_mcc_wrb *wrb;
657 struct be_cmd_req_pmac_del *req;
658 int status;
659
660 spin_lock_bh(&adapter->mcc_lock);
661
662 wrb = wrb_from_mccq(adapter);
663 if (!wrb) {
664 status = -EBUSY;
665 goto err;
666 }
667 req = embedded_payload(wrb);
668
669 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
670 OPCODE_COMMON_NTWK_PMAC_DEL);
671
672 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
673 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
674
675 req->hdr.domain = dom;
676 req->if_id = cpu_to_le32(if_id);
677 req->pmac_id = cpu_to_le32(pmac_id);
678
679 status = be_mcc_notify_wait(adapter);
680
681err:
682 spin_unlock_bh(&adapter->mcc_lock);
683 return status;
684}
685
686/* Uses Mbox */
687int be_cmd_cq_create(struct be_adapter *adapter,
688 struct be_queue_info *cq, struct be_queue_info *eq,
689 bool sol_evts, bool no_delay, int coalesce_wm)
690{
691 struct be_mcc_wrb *wrb;
692 struct be_cmd_req_cq_create *req;
693 struct be_dma_mem *q_mem = &cq->dma_mem;
694 void *ctxt;
695 int status;
696
697 if (mutex_lock_interruptible(&adapter->mbox_lock))
698 return -1;
699
700 wrb = wrb_from_mbox(adapter);
701 req = embedded_payload(wrb);
702 ctxt = &req->context;
703
704 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
705 OPCODE_COMMON_CQ_CREATE);
706
707 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
708 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
709
710 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
711 if (lancer_chip(adapter)) {
712 req->hdr.version = 1;
713 req->page_size = 1; /* 1 for 4K */
714 AMAP_SET_BITS(struct amap_cq_context_lancer, coalescwm, ctxt,
715 coalesce_wm);
716 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
717 no_delay);
718 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
719 __ilog2_u32(cq->len/256));
720 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
721 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
722 ctxt, 1);
723 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
724 ctxt, eq->id);
725 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
726 } else {
727 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
728 coalesce_wm);
729 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
730 ctxt, no_delay);
731 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
732 __ilog2_u32(cq->len/256));
733 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
734 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
735 ctxt, sol_evts);
736 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
737 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
738 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
739 }
740
741 be_dws_cpu_to_le(ctxt, sizeof(req->context));
742
743 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
744
745 status = be_mbox_notify_wait(adapter);
746 if (!status) {
747 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
748 cq->id = le16_to_cpu(resp->cq_id);
749 cq->created = true;
750 }
751
752 mutex_unlock(&adapter->mbox_lock);
753
754 return status;
755}
756
757static u32 be_encoded_q_len(int q_len)
758{
759 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
760 if (len_encoded == 16)
761 len_encoded = 0;
762 return len_encoded;
763}
764
765int be_cmd_mccq_create(struct be_adapter *adapter,
766 struct be_queue_info *mccq,
767 struct be_queue_info *cq)
768{
769 struct be_mcc_wrb *wrb;
770 struct be_cmd_req_mcc_create *req;
771 struct be_dma_mem *q_mem = &mccq->dma_mem;
772 void *ctxt;
773 int status;
774
775 if (mutex_lock_interruptible(&adapter->mbox_lock))
776 return -1;
777
778 wrb = wrb_from_mbox(adapter);
779 req = embedded_payload(wrb);
780 ctxt = &req->context;
781
782 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
783 OPCODE_COMMON_MCC_CREATE_EXT);
784
785 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
786 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
787
788 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
789 if (lancer_chip(adapter)) {
790 req->hdr.version = 1;
791 req->cq_id = cpu_to_le16(cq->id);
792
793 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
794 be_encoded_q_len(mccq->len));
795 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
796 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
797 ctxt, cq->id);
798 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
799 ctxt, 1);
800
801 } else {
802 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
803 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
804 be_encoded_q_len(mccq->len));
805 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
806 }
807
808 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
809 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
810 be_dws_cpu_to_le(ctxt, sizeof(req->context));
811
812 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
813
814 status = be_mbox_notify_wait(adapter);
815 if (!status) {
816 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
817 mccq->id = le16_to_cpu(resp->id);
818 mccq->created = true;
819 }
820 mutex_unlock(&adapter->mbox_lock);
821
822 return status;
823}
824
825int be_cmd_txq_create(struct be_adapter *adapter,
826 struct be_queue_info *txq,
827 struct be_queue_info *cq)
828{
829 struct be_mcc_wrb *wrb;
830 struct be_cmd_req_eth_tx_create *req;
831 struct be_dma_mem *q_mem = &txq->dma_mem;
832 void *ctxt;
833 int status;
834
835 if (mutex_lock_interruptible(&adapter->mbox_lock))
836 return -1;
837
838 wrb = wrb_from_mbox(adapter);
839 req = embedded_payload(wrb);
840 ctxt = &req->context;
841
842 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
843 OPCODE_ETH_TX_CREATE);
844
845 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
846 sizeof(*req));
847
848 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
849 req->ulp_num = BE_ULP1_NUM;
850 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
851
852 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
853 be_encoded_q_len(txq->len));
854 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
855 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
856
857 be_dws_cpu_to_le(ctxt, sizeof(req->context));
858
859 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
860
861 status = be_mbox_notify_wait(adapter);
862 if (!status) {
863 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
864 txq->id = le16_to_cpu(resp->cid);
865 txq->created = true;
866 }
867
868 mutex_unlock(&adapter->mbox_lock);
869
870 return status;
871}
872
873/* Uses mbox */
874int be_cmd_rxq_create(struct be_adapter *adapter,
875 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
876 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
877{
878 struct be_mcc_wrb *wrb;
879 struct be_cmd_req_eth_rx_create *req;
880 struct be_dma_mem *q_mem = &rxq->dma_mem;
881 int status;
882
883 if (mutex_lock_interruptible(&adapter->mbox_lock))
884 return -1;
885
886 wrb = wrb_from_mbox(adapter);
887 req = embedded_payload(wrb);
888
889 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
890 OPCODE_ETH_RX_CREATE);
891
892 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
893 sizeof(*req));
894
895 req->cq_id = cpu_to_le16(cq_id);
896 req->frag_size = fls(frag_size) - 1;
897 req->num_pages = 2;
898 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
899 req->interface_id = cpu_to_le32(if_id);
900 req->max_frame_size = cpu_to_le16(max_frame_size);
901 req->rss_queue = cpu_to_le32(rss);
902
903 status = be_mbox_notify_wait(adapter);
904 if (!status) {
905 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
906 rxq->id = le16_to_cpu(resp->id);
907 rxq->created = true;
908 *rss_id = resp->rss_id;
909 }
910
911 mutex_unlock(&adapter->mbox_lock);
912
913 return status;
914}
915
916/* Generic destroyer function for all types of queues
917 * Uses Mbox
918 */
919int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
920 int queue_type)
921{
922 struct be_mcc_wrb *wrb;
923 struct be_cmd_req_q_destroy *req;
924 u8 subsys = 0, opcode = 0;
925 int status;
926
927 if (adapter->eeh_err)
928 return -EIO;
929
930 if (mutex_lock_interruptible(&adapter->mbox_lock))
931 return -1;
932
933 wrb = wrb_from_mbox(adapter);
934 req = embedded_payload(wrb);
935
936 switch (queue_type) {
937 case QTYPE_EQ:
938 subsys = CMD_SUBSYSTEM_COMMON;
939 opcode = OPCODE_COMMON_EQ_DESTROY;
940 break;
941 case QTYPE_CQ:
942 subsys = CMD_SUBSYSTEM_COMMON;
943 opcode = OPCODE_COMMON_CQ_DESTROY;
944 break;
945 case QTYPE_TXQ:
946 subsys = CMD_SUBSYSTEM_ETH;
947 opcode = OPCODE_ETH_TX_DESTROY;
948 break;
949 case QTYPE_RXQ:
950 subsys = CMD_SUBSYSTEM_ETH;
951 opcode = OPCODE_ETH_RX_DESTROY;
952 break;
953 case QTYPE_MCCQ:
954 subsys = CMD_SUBSYSTEM_COMMON;
955 opcode = OPCODE_COMMON_MCC_DESTROY;
956 break;
957 default:
958 BUG();
959 }
960
961 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
962
963 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
964 req->id = cpu_to_le16(q->id);
965
966 status = be_mbox_notify_wait(adapter);
967
968 mutex_unlock(&adapter->mbox_lock);
969
970 return status;
971}
972
973/* Create an rx filtering policy configuration on an i/f
974 * Uses mbox
975 */
976int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
977 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
978 u32 domain)
979{
980 struct be_mcc_wrb *wrb;
981 struct be_cmd_req_if_create *req;
982 int status;
983
984 if (mutex_lock_interruptible(&adapter->mbox_lock))
985 return -1;
986
987 wrb = wrb_from_mbox(adapter);
988 req = embedded_payload(wrb);
989
990 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
991 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
992
993 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
994 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
995
996 req->hdr.domain = domain;
997 req->capability_flags = cpu_to_le32(cap_flags);
998 req->enable_flags = cpu_to_le32(en_flags);
999 req->pmac_invalid = pmac_invalid;
1000 if (!pmac_invalid)
1001 memcpy(req->mac_addr, mac, ETH_ALEN);
1002
1003 status = be_mbox_notify_wait(adapter);
1004 if (!status) {
1005 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1006 *if_handle = le32_to_cpu(resp->interface_id);
1007 if (!pmac_invalid)
1008 *pmac_id = le32_to_cpu(resp->pmac_id);
1009 }
1010
1011 mutex_unlock(&adapter->mbox_lock);
1012 return status;
1013}
1014
1015/* Uses mbox */
1016int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1017{
1018 struct be_mcc_wrb *wrb;
1019 struct be_cmd_req_if_destroy *req;
1020 int status;
1021
1022 if (adapter->eeh_err)
1023 return -EIO;
1024
1025 if (mutex_lock_interruptible(&adapter->mbox_lock))
1026 return -1;
1027
1028 wrb = wrb_from_mbox(adapter);
1029 req = embedded_payload(wrb);
1030
1031 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1032 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1033
1034 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1035 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1036
1037 req->hdr.domain = domain;
1038 req->interface_id = cpu_to_le32(interface_id);
1039
1040 status = be_mbox_notify_wait(adapter);
1041
1042 mutex_unlock(&adapter->mbox_lock);
1043
1044 return status;
1045}
1046
1047/* Get stats is a non embedded command: the request is not embedded inside
1048 * WRB but is a separate dma memory block
1049 * Uses asynchronous MCC
1050 */
1051int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1052{
1053 struct be_mcc_wrb *wrb;
1054 struct be_cmd_req_get_stats *req;
1055 struct be_sge *sge;
1056 int status = 0;
1057
1058 spin_lock_bh(&adapter->mcc_lock);
1059
1060 wrb = wrb_from_mccq(adapter);
1061 if (!wrb) {
1062 status = -EBUSY;
1063 goto err;
1064 }
1065 req = nonemb_cmd->va;
1066 sge = nonembedded_sgl(wrb);
1067
1068 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1069 OPCODE_ETH_GET_STATISTICS);
1070
1071 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1072 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
1073 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1074 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1075 sge->len = cpu_to_le32(nonemb_cmd->size);
1076
1077 be_mcc_notify(adapter);
1078 adapter->stats_cmd_sent = true;
1079
1080err:
1081 spin_unlock_bh(&adapter->mcc_lock);
1082 return status;
1083}
1084
1085/* Uses synchronous mcc */
1086int be_cmd_link_status_query(struct be_adapter *adapter,
1087 bool *link_up, u8 *mac_speed, u16 *link_speed)
1088{
1089 struct be_mcc_wrb *wrb;
1090 struct be_cmd_req_link_status *req;
1091 int status;
1092
1093 spin_lock_bh(&adapter->mcc_lock);
1094
1095 wrb = wrb_from_mccq(adapter);
1096 if (!wrb) {
1097 status = -EBUSY;
1098 goto err;
1099 }
1100 req = embedded_payload(wrb);
1101
1102 *link_up = false;
1103
1104 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1105 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1106
1107 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1108 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1109
1110 status = be_mcc_notify_wait(adapter);
1111 if (!status) {
1112 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1113 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1114 *link_up = true;
1115 *link_speed = le16_to_cpu(resp->link_speed);
1116 *mac_speed = resp->mac_speed;
1117 }
1118 }
1119
1120err:
1121 spin_unlock_bh(&adapter->mcc_lock);
1122 return status;
1123}
1124
1125/* Uses Mbox */
1126int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1127{
1128 struct be_mcc_wrb *wrb;
1129 struct be_cmd_req_get_fw_version *req;
1130 int status;
1131
1132 if (mutex_lock_interruptible(&adapter->mbox_lock))
1133 return -1;
1134
1135 wrb = wrb_from_mbox(adapter);
1136 req = embedded_payload(wrb);
1137
1138 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1139 OPCODE_COMMON_GET_FW_VERSION);
1140
1141 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1142 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1143
1144 status = be_mbox_notify_wait(adapter);
1145 if (!status) {
1146 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1147 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1148 }
1149
1150 mutex_unlock(&adapter->mbox_lock);
1151 return status;
1152}
1153
1154/* set the EQ delay interval of an EQ to specified value
1155 * Uses async mcc
1156 */
1157int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1158{
1159 struct be_mcc_wrb *wrb;
1160 struct be_cmd_req_modify_eq_delay *req;
1161 int status = 0;
1162
1163 spin_lock_bh(&adapter->mcc_lock);
1164
1165 wrb = wrb_from_mccq(adapter);
1166 if (!wrb) {
1167 status = -EBUSY;
1168 goto err;
1169 }
1170 req = embedded_payload(wrb);
1171
1172 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1173 OPCODE_COMMON_MODIFY_EQ_DELAY);
1174
1175 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1176 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1177
1178 req->num_eq = cpu_to_le32(1);
1179 req->delay[0].eq_id = cpu_to_le32(eq_id);
1180 req->delay[0].phase = 0;
1181 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1182
1183 be_mcc_notify(adapter);
1184
1185err:
1186 spin_unlock_bh(&adapter->mcc_lock);
1187 return status;
1188}
1189
1190/* Uses sycnhronous mcc */
1191int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1192 u32 num, bool untagged, bool promiscuous)
1193{
1194 struct be_mcc_wrb *wrb;
1195 struct be_cmd_req_vlan_config *req;
1196 int status;
1197
1198 spin_lock_bh(&adapter->mcc_lock);
1199
1200 wrb = wrb_from_mccq(adapter);
1201 if (!wrb) {
1202 status = -EBUSY;
1203 goto err;
1204 }
1205 req = embedded_payload(wrb);
1206
1207 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1208 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1209
1210 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1211 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1212
1213 req->interface_id = if_id;
1214 req->promiscuous = promiscuous;
1215 req->untagged = untagged;
1216 req->num_vlan = num;
1217 if (!promiscuous) {
1218 memcpy(req->normal_vlan, vtag_array,
1219 req->num_vlan * sizeof(vtag_array[0]));
1220 }
1221
1222 status = be_mcc_notify_wait(adapter);
1223
1224err:
1225 spin_unlock_bh(&adapter->mcc_lock);
1226 return status;
1227}
1228
1229/* Uses MCC for this command as it may be called in BH context
1230 * Uses synchronous mcc
1231 */
1232int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1233{
1234 struct be_mcc_wrb *wrb;
1235 struct be_cmd_req_promiscuous_config *req;
1236 int status;
1237
1238 spin_lock_bh(&adapter->mcc_lock);
1239
1240 wrb = wrb_from_mccq(adapter);
1241 if (!wrb) {
1242 status = -EBUSY;
1243 goto err;
1244 }
1245 req = embedded_payload(wrb);
1246
1247 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1248
1249 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1250 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1251
1252 /* In FW versions X.102.149/X.101.487 and later,
1253 * the port setting associated only with the
1254 * issuing pci function will take effect
1255 */
1256 if (port_num)
1257 req->port1_promiscuous = en;
1258 else
1259 req->port0_promiscuous = en;
1260
1261 status = be_mcc_notify_wait(adapter);
1262
1263err:
1264 spin_unlock_bh(&adapter->mcc_lock);
1265 return status;
1266}
1267
1268/*
1269 * Uses MCC for this command as it may be called in BH context
1270 * (mc == NULL) => multicast promiscous
1271 */
1272int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1273 struct net_device *netdev, struct be_dma_mem *mem)
1274{
1275 struct be_mcc_wrb *wrb;
1276 struct be_cmd_req_mcast_mac_config *req = mem->va;
1277 struct be_sge *sge;
1278 int status;
1279
1280 spin_lock_bh(&adapter->mcc_lock);
1281
1282 wrb = wrb_from_mccq(adapter);
1283 if (!wrb) {
1284 status = -EBUSY;
1285 goto err;
1286 }
1287 sge = nonembedded_sgl(wrb);
1288 memset(req, 0, sizeof(*req));
1289
1290 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1291 OPCODE_COMMON_NTWK_MULTICAST_SET);
1292 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1293 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1294 sge->len = cpu_to_le32(mem->size);
1295
1296 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1297 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1298
1299 req->interface_id = if_id;
1300 if (netdev) {
1301 int i;
1302 struct netdev_hw_addr *ha;
1303
1304 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1305
1306 i = 0;
1307 netdev_for_each_mc_addr(ha, netdev)
1308 memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1309 } else {
1310 req->promiscuous = 1;
1311 }
1312
1313 status = be_mcc_notify_wait(adapter);
1314
1315err:
1316 spin_unlock_bh(&adapter->mcc_lock);
1317 return status;
1318}
1319
1320/* Uses synchrounous mcc */
1321int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1322{
1323 struct be_mcc_wrb *wrb;
1324 struct be_cmd_req_set_flow_control *req;
1325 int status;
1326
1327 spin_lock_bh(&adapter->mcc_lock);
1328
1329 wrb = wrb_from_mccq(adapter);
1330 if (!wrb) {
1331 status = -EBUSY;
1332 goto err;
1333 }
1334 req = embedded_payload(wrb);
1335
1336 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1337 OPCODE_COMMON_SET_FLOW_CONTROL);
1338
1339 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1340 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1341
1342 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1343 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1344
1345 status = be_mcc_notify_wait(adapter);
1346
1347err:
1348 spin_unlock_bh(&adapter->mcc_lock);
1349 return status;
1350}
1351
1352/* Uses sycn mcc */
1353int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1354{
1355 struct be_mcc_wrb *wrb;
1356 struct be_cmd_req_get_flow_control *req;
1357 int status;
1358
1359 spin_lock_bh(&adapter->mcc_lock);
1360
1361 wrb = wrb_from_mccq(adapter);
1362 if (!wrb) {
1363 status = -EBUSY;
1364 goto err;
1365 }
1366 req = embedded_payload(wrb);
1367
1368 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1369 OPCODE_COMMON_GET_FLOW_CONTROL);
1370
1371 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1372 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1373
1374 status = be_mcc_notify_wait(adapter);
1375 if (!status) {
1376 struct be_cmd_resp_get_flow_control *resp =
1377 embedded_payload(wrb);
1378 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1379 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1380 }
1381
1382err:
1383 spin_unlock_bh(&adapter->mcc_lock);
1384 return status;
1385}
1386
1387/* Uses mbox */
1388int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1389 u32 *mode, u32 *caps)
1390{
1391 struct be_mcc_wrb *wrb;
1392 struct be_cmd_req_query_fw_cfg *req;
1393 int status;
1394
1395 if (mutex_lock_interruptible(&adapter->mbox_lock))
1396 return -1;
1397
1398 wrb = wrb_from_mbox(adapter);
1399 req = embedded_payload(wrb);
1400
1401 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1402 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1403
1404 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1405 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1406
1407 status = be_mbox_notify_wait(adapter);
1408 if (!status) {
1409 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1410 *port_num = le32_to_cpu(resp->phys_port);
1411 *mode = le32_to_cpu(resp->function_mode);
1412 *caps = le32_to_cpu(resp->function_caps);
1413 }
1414
1415 mutex_unlock(&adapter->mbox_lock);
1416 return status;
1417}
1418
1419/* Uses mbox */
1420int be_cmd_reset_function(struct be_adapter *adapter)
1421{
1422 struct be_mcc_wrb *wrb;
1423 struct be_cmd_req_hdr *req;
1424 int status;
1425
1426 if (mutex_lock_interruptible(&adapter->mbox_lock))
1427 return -1;
1428
1429 wrb = wrb_from_mbox(adapter);
1430 req = embedded_payload(wrb);
1431
1432 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1433 OPCODE_COMMON_FUNCTION_RESET);
1434
1435 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1436 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1437
1438 status = be_mbox_notify_wait(adapter);
1439
1440 mutex_unlock(&adapter->mbox_lock);
1441 return status;
1442}
1443
1444int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1445{
1446 struct be_mcc_wrb *wrb;
1447 struct be_cmd_req_rss_config *req;
1448 u32 myhash[10];
1449 int status;
1450
1451 if (mutex_lock_interruptible(&adapter->mbox_lock))
1452 return -1;
1453
1454 wrb = wrb_from_mbox(adapter);
1455 req = embedded_payload(wrb);
1456
1457 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1458 OPCODE_ETH_RSS_CONFIG);
1459
1460 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1461 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1462
1463 req->if_id = cpu_to_le32(adapter->if_handle);
1464 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1465 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1466 memcpy(req->cpu_table, rsstable, table_size);
1467 memcpy(req->hash, myhash, sizeof(myhash));
1468 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1469
1470 status = be_mbox_notify_wait(adapter);
1471
1472 mutex_unlock(&adapter->mbox_lock);
1473 return status;
1474}
1475
1476/* Uses sync mcc */
1477int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1478 u8 bcn, u8 sts, u8 state)
1479{
1480 struct be_mcc_wrb *wrb;
1481 struct be_cmd_req_enable_disable_beacon *req;
1482 int status;
1483
1484 spin_lock_bh(&adapter->mcc_lock);
1485
1486 wrb = wrb_from_mccq(adapter);
1487 if (!wrb) {
1488 status = -EBUSY;
1489 goto err;
1490 }
1491 req = embedded_payload(wrb);
1492
1493 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1494 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1495
1496 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1497 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1498
1499 req->port_num = port_num;
1500 req->beacon_state = state;
1501 req->beacon_duration = bcn;
1502 req->status_duration = sts;
1503
1504 status = be_mcc_notify_wait(adapter);
1505
1506err:
1507 spin_unlock_bh(&adapter->mcc_lock);
1508 return status;
1509}
1510
1511/* Uses sync mcc */
1512int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1513{
1514 struct be_mcc_wrb *wrb;
1515 struct be_cmd_req_get_beacon_state *req;
1516 int status;
1517
1518 spin_lock_bh(&adapter->mcc_lock);
1519
1520 wrb = wrb_from_mccq(adapter);
1521 if (!wrb) {
1522 status = -EBUSY;
1523 goto err;
1524 }
1525 req = embedded_payload(wrb);
1526
1527 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1528 OPCODE_COMMON_GET_BEACON_STATE);
1529
1530 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1531 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1532
1533 req->port_num = port_num;
1534
1535 status = be_mcc_notify_wait(adapter);
1536 if (!status) {
1537 struct be_cmd_resp_get_beacon_state *resp =
1538 embedded_payload(wrb);
1539 *state = resp->beacon_state;
1540 }
1541
1542err:
1543 spin_unlock_bh(&adapter->mcc_lock);
1544 return status;
1545}
1546
1547int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1548 u32 flash_type, u32 flash_opcode, u32 buf_size)
1549{
1550 struct be_mcc_wrb *wrb;
1551 struct be_cmd_write_flashrom *req;
1552 struct be_sge *sge;
1553 int status;
1554
1555 spin_lock_bh(&adapter->mcc_lock);
1556 adapter->flash_status = 0;
1557
1558 wrb = wrb_from_mccq(adapter);
1559 if (!wrb) {
1560 status = -EBUSY;
1561 goto err_unlock;
1562 }
1563 req = cmd->va;
1564 sge = nonembedded_sgl(wrb);
1565
1566 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1567 OPCODE_COMMON_WRITE_FLASHROM);
1568 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1569
1570 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1571 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1572 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1573 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1574 sge->len = cpu_to_le32(cmd->size);
1575
1576 req->params.op_type = cpu_to_le32(flash_type);
1577 req->params.op_code = cpu_to_le32(flash_opcode);
1578 req->params.data_buf_size = cpu_to_le32(buf_size);
1579
1580 be_mcc_notify(adapter);
1581 spin_unlock_bh(&adapter->mcc_lock);
1582
1583 if (!wait_for_completion_timeout(&adapter->flash_compl,
1584 msecs_to_jiffies(12000)))
1585 status = -1;
1586 else
1587 status = adapter->flash_status;
1588
1589 return status;
1590
1591err_unlock:
1592 spin_unlock_bh(&adapter->mcc_lock);
1593 return status;
1594}
1595
1596int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1597 int offset)
1598{
1599 struct be_mcc_wrb *wrb;
1600 struct be_cmd_write_flashrom *req;
1601 int status;
1602
1603 spin_lock_bh(&adapter->mcc_lock);
1604
1605 wrb = wrb_from_mccq(adapter);
1606 if (!wrb) {
1607 status = -EBUSY;
1608 goto err;
1609 }
1610 req = embedded_payload(wrb);
1611
1612 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1613 OPCODE_COMMON_READ_FLASHROM);
1614
1615 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1616 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1617
1618 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1619 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1620 req->params.offset = cpu_to_le32(offset);
1621 req->params.data_buf_size = cpu_to_le32(0x4);
1622
1623 status = be_mcc_notify_wait(adapter);
1624 if (!status)
1625 memcpy(flashed_crc, req->params.data_buf, 4);
1626
1627err:
1628 spin_unlock_bh(&adapter->mcc_lock);
1629 return status;
1630}
1631
1632int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1633 struct be_dma_mem *nonemb_cmd)
1634{
1635 struct be_mcc_wrb *wrb;
1636 struct be_cmd_req_acpi_wol_magic_config *req;
1637 struct be_sge *sge;
1638 int status;
1639
1640 spin_lock_bh(&adapter->mcc_lock);
1641
1642 wrb = wrb_from_mccq(adapter);
1643 if (!wrb) {
1644 status = -EBUSY;
1645 goto err;
1646 }
1647 req = nonemb_cmd->va;
1648 sge = nonembedded_sgl(wrb);
1649
1650 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1651 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1652
1653 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1654 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1655 memcpy(req->magic_mac, mac, ETH_ALEN);
1656
1657 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1658 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1659 sge->len = cpu_to_le32(nonemb_cmd->size);
1660
1661 status = be_mcc_notify_wait(adapter);
1662
1663err:
1664 spin_unlock_bh(&adapter->mcc_lock);
1665 return status;
1666}
1667
1668int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1669 u8 loopback_type, u8 enable)
1670{
1671 struct be_mcc_wrb *wrb;
1672 struct be_cmd_req_set_lmode *req;
1673 int status;
1674
1675 spin_lock_bh(&adapter->mcc_lock);
1676
1677 wrb = wrb_from_mccq(adapter);
1678 if (!wrb) {
1679 status = -EBUSY;
1680 goto err;
1681 }
1682
1683 req = embedded_payload(wrb);
1684
1685 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1686 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1687
1688 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1689 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1690 sizeof(*req));
1691
1692 req->src_port = port_num;
1693 req->dest_port = port_num;
1694 req->loopback_type = loopback_type;
1695 req->loopback_state = enable;
1696
1697 status = be_mcc_notify_wait(adapter);
1698err:
1699 spin_unlock_bh(&adapter->mcc_lock);
1700 return status;
1701}
1702
1703int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1704 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1705{
1706 struct be_mcc_wrb *wrb;
1707 struct be_cmd_req_loopback_test *req;
1708 int status;
1709
1710 spin_lock_bh(&adapter->mcc_lock);
1711
1712 wrb = wrb_from_mccq(adapter);
1713 if (!wrb) {
1714 status = -EBUSY;
1715 goto err;
1716 }
1717
1718 req = embedded_payload(wrb);
1719
1720 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1721 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1722
1723 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1724 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1725 req->hdr.timeout = cpu_to_le32(4);
1726
1727 req->pattern = cpu_to_le64(pattern);
1728 req->src_port = cpu_to_le32(port_num);
1729 req->dest_port = cpu_to_le32(port_num);
1730 req->pkt_size = cpu_to_le32(pkt_size);
1731 req->num_pkts = cpu_to_le32(num_pkts);
1732 req->loopback_type = cpu_to_le32(loopback_type);
1733
1734 status = be_mcc_notify_wait(adapter);
1735 if (!status) {
1736 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1737 status = le32_to_cpu(resp->status);
1738 }
1739
1740err:
1741 spin_unlock_bh(&adapter->mcc_lock);
1742 return status;
1743}
1744
1745int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1746 u32 byte_cnt, struct be_dma_mem *cmd)
1747{
1748 struct be_mcc_wrb *wrb;
1749 struct be_cmd_req_ddrdma_test *req;
1750 struct be_sge *sge;
1751 int status;
1752 int i, j = 0;
1753
1754 spin_lock_bh(&adapter->mcc_lock);
1755
1756 wrb = wrb_from_mccq(adapter);
1757 if (!wrb) {
1758 status = -EBUSY;
1759 goto err;
1760 }
1761 req = cmd->va;
1762 sge = nonembedded_sgl(wrb);
1763 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1764 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1765 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1766 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1767
1768 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1769 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1770 sge->len = cpu_to_le32(cmd->size);
1771
1772 req->pattern = cpu_to_le64(pattern);
1773 req->byte_count = cpu_to_le32(byte_cnt);
1774 for (i = 0; i < byte_cnt; i++) {
1775 req->snd_buff[i] = (u8)(pattern >> (j*8));
1776 j++;
1777 if (j > 7)
1778 j = 0;
1779 }
1780
1781 status = be_mcc_notify_wait(adapter);
1782
1783 if (!status) {
1784 struct be_cmd_resp_ddrdma_test *resp;
1785 resp = cmd->va;
1786 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1787 resp->snd_err) {
1788 status = -1;
1789 }
1790 }
1791
1792err:
1793 spin_unlock_bh(&adapter->mcc_lock);
1794 return status;
1795}
1796
1797int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1798 struct be_dma_mem *nonemb_cmd)
1799{
1800 struct be_mcc_wrb *wrb;
1801 struct be_cmd_req_seeprom_read *req;
1802 struct be_sge *sge;
1803 int status;
1804
1805 spin_lock_bh(&adapter->mcc_lock);
1806
1807 wrb = wrb_from_mccq(adapter);
1808 if (!wrb) {
1809 status = -EBUSY;
1810 goto err;
1811 }
1812 req = nonemb_cmd->va;
1813 sge = nonembedded_sgl(wrb);
1814
1815 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1816 OPCODE_COMMON_SEEPROM_READ);
1817
1818 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1819 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1820
1821 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1822 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1823 sge->len = cpu_to_le32(nonemb_cmd->size);
1824
1825 status = be_mcc_notify_wait(adapter);
1826
1827err:
1828 spin_unlock_bh(&adapter->mcc_lock);
1829 return status;
1830}
1831
1832int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
1833{
1834 struct be_mcc_wrb *wrb;
1835 struct be_cmd_req_get_phy_info *req;
1836 struct be_sge *sge;
1837 int status;
1838
1839 spin_lock_bh(&adapter->mcc_lock);
1840
1841 wrb = wrb_from_mccq(adapter);
1842 if (!wrb) {
1843 status = -EBUSY;
1844 goto err;
1845 }
1846
1847 req = cmd->va;
1848 sge = nonembedded_sgl(wrb);
1849
1850 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1851 OPCODE_COMMON_GET_PHY_DETAILS);
1852
1853 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1854 OPCODE_COMMON_GET_PHY_DETAILS,
1855 sizeof(*req));
1856
1857 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1858 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1859 sge->len = cpu_to_le32(cmd->size);
1860
1861 status = be_mcc_notify_wait(adapter);
1862err:
1863 spin_unlock_bh(&adapter->mcc_lock);
1864 return status;
1865}
1866
1867int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
1868{
1869 struct be_mcc_wrb *wrb;
1870 struct be_cmd_req_set_qos *req;
1871 int status;
1872
1873 spin_lock_bh(&adapter->mcc_lock);
1874
1875 wrb = wrb_from_mccq(adapter);
1876 if (!wrb) {
1877 status = -EBUSY;
1878 goto err;
1879 }
1880
1881 req = embedded_payload(wrb);
1882
1883 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1884 OPCODE_COMMON_SET_QOS);
1885
1886 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1887 OPCODE_COMMON_SET_QOS, sizeof(*req));
1888
1889 req->hdr.domain = domain;
1890 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
1891 req->max_bps_nic = cpu_to_le32(bps);
1892
1893 status = be_mcc_notify_wait(adapter);
1894
1895err:
1896 spin_unlock_bh(&adapter->mcc_lock);
1897 return status;
1898}
kernel source for telekom puls (alcatel/mediatek)