| 1 | /* Generic NS8390 register definitions. */ |
| 2 | /* This file is part of Donald Becker's 8390 drivers, and is distributed |
| 3 | under the same license. Auto-loading of 8390.o only in v2.2 - Paul G. |
| 4 | Some of these names and comments originated from the Crynwr |
| 5 | packet drivers, which are distributed under the GPL. */ |
| 6 | |
| 7 | #ifndef _8390_h |
| 8 | #define _8390_h |
| 9 | |
| 10 | #include <linux/if_ether.h> |
| 11 | #include <linux/ioport.h> |
| 12 | #include <linux/skbuff.h> |
| 13 | |
| 14 | #define TX_PAGES 12 /* Two Tx slots */ |
| 15 | |
| 16 | #define ETHER_ADDR_LEN 6 |
| 17 | |
| 18 | /* The 8390 specific per-packet-header format. */ |
| 19 | struct e8390_pkt_hdr { |
| 20 | unsigned char status; /* status */ |
| 21 | unsigned char next; /* pointer to next packet. */ |
| 22 | unsigned short count; /* header + packet length in bytes */ |
| 23 | }; |
| 24 | |
| 25 | #ifdef notdef |
| 26 | extern int ei_debug; |
| 27 | #else |
| 28 | #define ei_debug 1 |
| 29 | #endif |
| 30 | |
| 31 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 32 | extern void ei_poll(struct net_device *dev); |
| 33 | extern void eip_poll(struct net_device *dev); |
| 34 | #endif |
| 35 | |
| 36 | |
| 37 | /* Without I/O delay - non ISA or later chips */ |
| 38 | extern void NS8390_init(struct net_device *dev, int startp); |
| 39 | extern int ei_open(struct net_device *dev); |
| 40 | extern int ei_close(struct net_device *dev); |
| 41 | extern irqreturn_t ei_interrupt(int irq, void *dev_id); |
| 42 | extern void ei_tx_timeout(struct net_device *dev); |
| 43 | extern netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev); |
| 44 | extern void ei_set_multicast_list(struct net_device *dev); |
| 45 | extern struct net_device_stats *ei_get_stats(struct net_device *dev); |
| 46 | |
| 47 | extern const struct net_device_ops ei_netdev_ops; |
| 48 | |
| 49 | extern struct net_device *__alloc_ei_netdev(int size); |
| 50 | static inline struct net_device *alloc_ei_netdev(void) |
| 51 | { |
| 52 | return __alloc_ei_netdev(0); |
| 53 | } |
| 54 | |
| 55 | /* With I/O delay form */ |
| 56 | extern void NS8390p_init(struct net_device *dev, int startp); |
| 57 | extern int eip_open(struct net_device *dev); |
| 58 | extern int eip_close(struct net_device *dev); |
| 59 | extern irqreturn_t eip_interrupt(int irq, void *dev_id); |
| 60 | extern void eip_tx_timeout(struct net_device *dev); |
| 61 | extern netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev); |
| 62 | extern void eip_set_multicast_list(struct net_device *dev); |
| 63 | extern struct net_device_stats *eip_get_stats(struct net_device *dev); |
| 64 | |
| 65 | extern const struct net_device_ops eip_netdev_ops; |
| 66 | |
| 67 | extern struct net_device *__alloc_eip_netdev(int size); |
| 68 | static inline struct net_device *alloc_eip_netdev(void) |
| 69 | { |
| 70 | return __alloc_eip_netdev(0); |
| 71 | } |
| 72 | |
| 73 | /* You have one of these per-board */ |
| 74 | struct ei_device { |
| 75 | const char *name; |
| 76 | void (*reset_8390)(struct net_device *); |
| 77 | void (*get_8390_hdr)(struct net_device *, struct e8390_pkt_hdr *, int); |
| 78 | void (*block_output)(struct net_device *, int, const unsigned char *, int); |
| 79 | void (*block_input)(struct net_device *, int, struct sk_buff *, int); |
| 80 | unsigned long rmem_start; |
| 81 | unsigned long rmem_end; |
| 82 | void __iomem *mem; |
| 83 | unsigned char mcfilter[8]; |
| 84 | unsigned open:1; |
| 85 | unsigned word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */ |
| 86 | unsigned bigendian:1; /* 16-bit big endian mode. Do NOT */ |
| 87 | /* set this on random 8390 clones! */ |
| 88 | unsigned txing:1; /* Transmit Active */ |
| 89 | unsigned irqlock:1; /* 8390's intrs disabled when '1'. */ |
| 90 | unsigned dmaing:1; /* Remote DMA Active */ |
| 91 | unsigned char tx_start_page, rx_start_page, stop_page; |
| 92 | unsigned char current_page; /* Read pointer in buffer */ |
| 93 | unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */ |
| 94 | unsigned char txqueue; /* Tx Packet buffer queue length. */ |
| 95 | short tx1, tx2; /* Packet lengths for ping-pong tx. */ |
| 96 | short lasttx; /* Alpha version consistency check. */ |
| 97 | unsigned char reg0; /* Register '0' in a WD8013 */ |
| 98 | unsigned char reg5; /* Register '5' in a WD8013 */ |
| 99 | unsigned char saved_irq; /* Original dev->irq value. */ |
| 100 | u32 *reg_offset; /* Register mapping table */ |
| 101 | spinlock_t page_lock; /* Page register locks */ |
| 102 | unsigned long priv; /* Private field to store bus IDs etc. */ |
| 103 | #ifdef AX88796_PLATFORM |
| 104 | unsigned char rxcr_base; /* default value for RXCR */ |
| 105 | #endif |
| 106 | }; |
| 107 | |
| 108 | /* The maximum number of 8390 interrupt service routines called per IRQ. */ |
| 109 | #define MAX_SERVICE 12 |
| 110 | |
| 111 | /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */ |
| 112 | #define TX_TIMEOUT (20*HZ/100) |
| 113 | |
| 114 | #define ei_status (*(struct ei_device *)netdev_priv(dev)) |
| 115 | |
| 116 | /* Some generic ethernet register configurations. */ |
| 117 | #define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */ |
| 118 | #define E8390_RX_IRQ_MASK 0x5 |
| 119 | |
| 120 | #ifdef AX88796_PLATFORM |
| 121 | #define E8390_RXCONFIG (ei_status.rxcr_base | 0x04) |
| 122 | #define E8390_RXOFF (ei_status.rxcr_base | 0x20) |
| 123 | #else |
| 124 | #define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */ |
| 125 | #define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */ |
| 126 | #endif |
| 127 | |
| 128 | #define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */ |
| 129 | #define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */ |
| 130 | |
| 131 | |
| 132 | /* Register accessed at EN_CMD, the 8390 base addr. */ |
| 133 | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
| 134 | #define E8390_START 0x02 /* Start the chip, clear reset */ |
| 135 | #define E8390_TRANS 0x04 /* Transmit a frame */ |
| 136 | #define E8390_RREAD 0x08 /* Remote read */ |
| 137 | #define E8390_RWRITE 0x10 /* Remote write */ |
| 138 | #define E8390_NODMA 0x20 /* Remote DMA */ |
| 139 | #define E8390_PAGE0 0x00 /* Select page chip registers */ |
| 140 | #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
| 141 | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
| 142 | |
| 143 | /* |
| 144 | * Only generate indirect loads given a machine that needs them. |
| 145 | * - removed AMIGA_PCMCIA from this list, handled as ISA io now |
| 146 | * - the _p for generates no delay by default 8390p.c overrides this. |
| 147 | */ |
| 148 | |
| 149 | #ifndef ei_inb |
| 150 | #define ei_inb(_p) inb(_p) |
| 151 | #define ei_outb(_v,_p) outb(_v,_p) |
| 152 | #define ei_inb_p(_p) inb(_p) |
| 153 | #define ei_outb_p(_v,_p) outb(_v,_p) |
| 154 | #endif |
| 155 | |
| 156 | #ifndef EI_SHIFT |
| 157 | #define EI_SHIFT(x) (x) |
| 158 | #endif |
| 159 | |
| 160 | #define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */ |
| 161 | /* Page 0 register offsets. */ |
| 162 | #define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */ |
| 163 | #define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */ |
| 164 | #define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */ |
| 165 | #define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */ |
| 166 | #define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */ |
| 167 | #define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */ |
| 168 | #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */ |
| 169 | #define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */ |
| 170 | #define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */ |
| 171 | #define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */ |
| 172 | #define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */ |
| 173 | #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ |
| 174 | #define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */ |
| 175 | #define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */ |
| 176 | #define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */ |
| 177 | #define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */ |
| 178 | #define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */ |
| 179 | #define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */ |
| 180 | #define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */ |
| 181 | #define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */ |
| 182 | #define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */ |
| 183 | #define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */ |
| 184 | #define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */ |
| 185 | #define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */ |
| 186 | #define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */ |
| 187 | #define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */ |
| 188 | |
| 189 | /* Bits in EN0_ISR - Interrupt status register */ |
| 190 | #define ENISR_RX 0x01 /* Receiver, no error */ |
| 191 | #define ENISR_TX 0x02 /* Transmitter, no error */ |
| 192 | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
| 193 | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
| 194 | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
| 195 | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
| 196 | #define ENISR_RDC 0x40 /* remote dma complete */ |
| 197 | #define ENISR_RESET 0x80 /* Reset completed */ |
| 198 | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
| 199 | |
| 200 | /* Bits in EN0_DCFG - Data config register */ |
| 201 | #define ENDCFG_WTS 0x01 /* word transfer mode selection */ |
| 202 | #define ENDCFG_BOS 0x02 /* byte order selection */ |
| 203 | |
| 204 | /* Page 1 register offsets. */ |
| 205 | #define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */ |
| 206 | #define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */ |
| 207 | #define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */ |
| 208 | #define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */ |
| 209 | #define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */ |
| 210 | |
| 211 | /* Bits in received packet status byte and EN0_RSR*/ |
| 212 | #define ENRSR_RXOK 0x01 /* Received a good packet */ |
| 213 | #define ENRSR_CRC 0x02 /* CRC error */ |
| 214 | #define ENRSR_FAE 0x04 /* frame alignment error */ |
| 215 | #define ENRSR_FO 0x08 /* FIFO overrun */ |
| 216 | #define ENRSR_MPA 0x10 /* missed pkt */ |
| 217 | #define ENRSR_PHY 0x20 /* physical/multicast address */ |
| 218 | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
| 219 | #define ENRSR_DEF 0x80 /* deferring */ |
| 220 | |
| 221 | /* Transmitted packet status, EN0_TSR. */ |
| 222 | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
| 223 | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
| 224 | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
| 225 | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
| 226 | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
| 227 | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
| 228 | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
| 229 | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
| 230 | |
| 231 | #endif /* _8390_h */ |