| 1 | /* |
| 2 | * drivers/mmc/host/omap_hsmmc.c |
| 3 | * |
| 4 | * Driver for OMAP2430/3430 MMC controller. |
| 5 | * |
| 6 | * Copyright (C) 2007 Texas Instruments. |
| 7 | * |
| 8 | * Authors: |
| 9 | * Syed Mohammed Khasim <x0khasim@ti.com> |
| 10 | * Madhusudhan <madhu.cr@ti.com> |
| 11 | * Mohit Jalori <mjalori@ti.com> |
| 12 | * |
| 13 | * This file is licensed under the terms of the GNU General Public License |
| 14 | * version 2. This program is licensed "as is" without any warranty of any |
| 15 | * kind, whether express or implied. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/debugfs.h> |
| 22 | #include <linux/dmaengine.h> |
| 23 | #include <linux/seq_file.h> |
| 24 | #include <linux/sizes.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/dma-mapping.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/timer.h> |
| 30 | #include <linux/clk.h> |
| 31 | #include <linux/of.h> |
| 32 | #include <linux/of_irq.h> |
| 33 | #include <linux/of_gpio.h> |
| 34 | #include <linux/of_device.h> |
| 35 | #include <linux/mmc/host.h> |
| 36 | #include <linux/mmc/core.h> |
| 37 | #include <linux/mmc/mmc.h> |
| 38 | #include <linux/mmc/slot-gpio.h> |
| 39 | #include <linux/io.h> |
| 40 | #include <linux/irq.h> |
| 41 | #include <linux/gpio.h> |
| 42 | #include <linux/regulator/consumer.h> |
| 43 | #include <linux/pinctrl/consumer.h> |
| 44 | #include <linux/pm_runtime.h> |
| 45 | #include <linux/pm_wakeirq.h> |
| 46 | #include <linux/platform_data/hsmmc-omap.h> |
| 47 | |
| 48 | /* OMAP HSMMC Host Controller Registers */ |
| 49 | #define OMAP_HSMMC_SYSSTATUS 0x0014 |
| 50 | #define OMAP_HSMMC_CON 0x002C |
| 51 | #define OMAP_HSMMC_SDMASA 0x0100 |
| 52 | #define OMAP_HSMMC_BLK 0x0104 |
| 53 | #define OMAP_HSMMC_ARG 0x0108 |
| 54 | #define OMAP_HSMMC_CMD 0x010C |
| 55 | #define OMAP_HSMMC_RSP10 0x0110 |
| 56 | #define OMAP_HSMMC_RSP32 0x0114 |
| 57 | #define OMAP_HSMMC_RSP54 0x0118 |
| 58 | #define OMAP_HSMMC_RSP76 0x011C |
| 59 | #define OMAP_HSMMC_DATA 0x0120 |
| 60 | #define OMAP_HSMMC_PSTATE 0x0124 |
| 61 | #define OMAP_HSMMC_HCTL 0x0128 |
| 62 | #define OMAP_HSMMC_SYSCTL 0x012C |
| 63 | #define OMAP_HSMMC_STAT 0x0130 |
| 64 | #define OMAP_HSMMC_IE 0x0134 |
| 65 | #define OMAP_HSMMC_ISE 0x0138 |
| 66 | #define OMAP_HSMMC_AC12 0x013C |
| 67 | #define OMAP_HSMMC_CAPA 0x0140 |
| 68 | |
| 69 | #define VS18 (1 << 26) |
| 70 | #define VS30 (1 << 25) |
| 71 | #define HSS (1 << 21) |
| 72 | #define SDVS18 (0x5 << 9) |
| 73 | #define SDVS30 (0x6 << 9) |
| 74 | #define SDVS33 (0x7 << 9) |
| 75 | #define SDVS_MASK 0x00000E00 |
| 76 | #define SDVSCLR 0xFFFFF1FF |
| 77 | #define SDVSDET 0x00000400 |
| 78 | #define AUTOIDLE 0x1 |
| 79 | #define SDBP (1 << 8) |
| 80 | #define DTO 0xe |
| 81 | #define ICE 0x1 |
| 82 | #define ICS 0x2 |
| 83 | #define CEN (1 << 2) |
| 84 | #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ |
| 85 | #define CLKD_MASK 0x0000FFC0 |
| 86 | #define CLKD_SHIFT 6 |
| 87 | #define DTO_MASK 0x000F0000 |
| 88 | #define DTO_SHIFT 16 |
| 89 | #define INIT_STREAM (1 << 1) |
| 90 | #define ACEN_ACMD23 (2 << 2) |
| 91 | #define DP_SELECT (1 << 21) |
| 92 | #define DDIR (1 << 4) |
| 93 | #define DMAE 0x1 |
| 94 | #define MSBS (1 << 5) |
| 95 | #define BCE (1 << 1) |
| 96 | #define FOUR_BIT (1 << 1) |
| 97 | #define HSPE (1 << 2) |
| 98 | #define IWE (1 << 24) |
| 99 | #define DDR (1 << 19) |
| 100 | #define CLKEXTFREE (1 << 16) |
| 101 | #define CTPL (1 << 11) |
| 102 | #define DW8 (1 << 5) |
| 103 | #define OD 0x1 |
| 104 | #define STAT_CLEAR 0xFFFFFFFF |
| 105 | #define INIT_STREAM_CMD 0x00000000 |
| 106 | #define DUAL_VOLT_OCR_BIT 7 |
| 107 | #define SRC (1 << 25) |
| 108 | #define SRD (1 << 26) |
| 109 | #define SOFTRESET (1 << 1) |
| 110 | |
| 111 | /* PSTATE */ |
| 112 | #define DLEV_DAT(x) (1 << (20 + (x))) |
| 113 | |
| 114 | /* Interrupt masks for IE and ISE register */ |
| 115 | #define CC_EN (1 << 0) |
| 116 | #define TC_EN (1 << 1) |
| 117 | #define BWR_EN (1 << 4) |
| 118 | #define BRR_EN (1 << 5) |
| 119 | #define CIRQ_EN (1 << 8) |
| 120 | #define ERR_EN (1 << 15) |
| 121 | #define CTO_EN (1 << 16) |
| 122 | #define CCRC_EN (1 << 17) |
| 123 | #define CEB_EN (1 << 18) |
| 124 | #define CIE_EN (1 << 19) |
| 125 | #define DTO_EN (1 << 20) |
| 126 | #define DCRC_EN (1 << 21) |
| 127 | #define DEB_EN (1 << 22) |
| 128 | #define ACE_EN (1 << 24) |
| 129 | #define CERR_EN (1 << 28) |
| 130 | #define BADA_EN (1 << 29) |
| 131 | |
| 132 | #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ |
| 133 | DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ |
| 134 | BRR_EN | BWR_EN | TC_EN | CC_EN) |
| 135 | |
| 136 | #define CNI (1 << 7) |
| 137 | #define ACIE (1 << 4) |
| 138 | #define ACEB (1 << 3) |
| 139 | #define ACCE (1 << 2) |
| 140 | #define ACTO (1 << 1) |
| 141 | #define ACNE (1 << 0) |
| 142 | |
| 143 | #define MMC_AUTOSUSPEND_DELAY 100 |
| 144 | #define MMC_TIMEOUT_MS 20 /* 20 mSec */ |
| 145 | #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ |
| 146 | #define OMAP_MMC_MIN_CLOCK 400000 |
| 147 | #define OMAP_MMC_MAX_CLOCK 52000000 |
| 148 | #define DRIVER_NAME "omap_hsmmc" |
| 149 | |
| 150 | #define VDD_1V8 1800000 /* 180000 uV */ |
| 151 | #define VDD_3V0 3000000 /* 300000 uV */ |
| 152 | #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) |
| 153 | |
| 154 | /* |
| 155 | * One controller can have multiple slots, like on some omap boards using |
| 156 | * omap.c controller driver. Luckily this is not currently done on any known |
| 157 | * omap_hsmmc.c device. |
| 158 | */ |
| 159 | #define mmc_pdata(host) host->pdata |
| 160 | |
| 161 | /* |
| 162 | * MMC Host controller read/write API's |
| 163 | */ |
| 164 | #define OMAP_HSMMC_READ(base, reg) \ |
| 165 | __raw_readl((base) + OMAP_HSMMC_##reg) |
| 166 | |
| 167 | #define OMAP_HSMMC_WRITE(base, reg, val) \ |
| 168 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) |
| 169 | |
| 170 | struct omap_hsmmc_next { |
| 171 | unsigned int dma_len; |
| 172 | s32 cookie; |
| 173 | }; |
| 174 | |
| 175 | struct omap_hsmmc_host { |
| 176 | struct device *dev; |
| 177 | struct mmc_host *mmc; |
| 178 | struct mmc_request *mrq; |
| 179 | struct mmc_command *cmd; |
| 180 | struct mmc_data *data; |
| 181 | struct clk *fclk; |
| 182 | struct clk *dbclk; |
| 183 | struct regulator *pbias; |
| 184 | bool pbias_enabled; |
| 185 | void __iomem *base; |
| 186 | int vqmmc_enabled; |
| 187 | resource_size_t mapbase; |
| 188 | spinlock_t irq_lock; /* Prevent races with irq handler */ |
| 189 | unsigned int dma_len; |
| 190 | unsigned int dma_sg_idx; |
| 191 | unsigned char bus_mode; |
| 192 | unsigned char power_mode; |
| 193 | int suspended; |
| 194 | u32 con; |
| 195 | u32 hctl; |
| 196 | u32 sysctl; |
| 197 | u32 capa; |
| 198 | int irq; |
| 199 | int wake_irq; |
| 200 | int use_dma, dma_ch; |
| 201 | struct dma_chan *tx_chan; |
| 202 | struct dma_chan *rx_chan; |
| 203 | int response_busy; |
| 204 | int context_loss; |
| 205 | int protect_card; |
| 206 | int reqs_blocked; |
| 207 | int req_in_progress; |
| 208 | unsigned long clk_rate; |
| 209 | unsigned int flags; |
| 210 | #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ |
| 211 | #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ |
| 212 | struct omap_hsmmc_next next_data; |
| 213 | struct omap_hsmmc_platform_data *pdata; |
| 214 | |
| 215 | /* return MMC cover switch state, can be NULL if not supported. |
| 216 | * |
| 217 | * possible return values: |
| 218 | * 0 - closed |
| 219 | * 1 - open |
| 220 | */ |
| 221 | int (*get_cover_state)(struct device *dev); |
| 222 | |
| 223 | int (*card_detect)(struct device *dev); |
| 224 | }; |
| 225 | |
| 226 | struct omap_mmc_of_data { |
| 227 | u32 reg_offset; |
| 228 | u8 controller_flags; |
| 229 | }; |
| 230 | |
| 231 | static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); |
| 232 | |
| 233 | static int omap_hsmmc_card_detect(struct device *dev) |
| 234 | { |
| 235 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
| 236 | |
| 237 | return mmc_gpio_get_cd(host->mmc); |
| 238 | } |
| 239 | |
| 240 | static int omap_hsmmc_get_cover_state(struct device *dev) |
| 241 | { |
| 242 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
| 243 | |
| 244 | return mmc_gpio_get_cd(host->mmc); |
| 245 | } |
| 246 | |
| 247 | static int omap_hsmmc_enable_supply(struct mmc_host *mmc) |
| 248 | { |
| 249 | int ret; |
| 250 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 251 | struct mmc_ios *ios = &mmc->ios; |
| 252 | |
| 253 | if (!IS_ERR(mmc->supply.vmmc)) { |
| 254 | ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); |
| 255 | if (ret) |
| 256 | return ret; |
| 257 | } |
| 258 | |
| 259 | /* Enable interface voltage rail, if needed */ |
| 260 | if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { |
| 261 | ret = regulator_enable(mmc->supply.vqmmc); |
| 262 | if (ret) { |
| 263 | dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); |
| 264 | goto err_vqmmc; |
| 265 | } |
| 266 | host->vqmmc_enabled = 1; |
| 267 | } |
| 268 | |
| 269 | return 0; |
| 270 | |
| 271 | err_vqmmc: |
| 272 | if (!IS_ERR(mmc->supply.vmmc)) |
| 273 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
| 274 | |
| 275 | return ret; |
| 276 | } |
| 277 | |
| 278 | static int omap_hsmmc_disable_supply(struct mmc_host *mmc) |
| 279 | { |
| 280 | int ret; |
| 281 | int status; |
| 282 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 283 | |
| 284 | if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { |
| 285 | ret = regulator_disable(mmc->supply.vqmmc); |
| 286 | if (ret) { |
| 287 | dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); |
| 288 | return ret; |
| 289 | } |
| 290 | host->vqmmc_enabled = 0; |
| 291 | } |
| 292 | |
| 293 | if (!IS_ERR(mmc->supply.vmmc)) { |
| 294 | ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
| 295 | if (ret) |
| 296 | goto err_set_ocr; |
| 297 | } |
| 298 | |
| 299 | return 0; |
| 300 | |
| 301 | err_set_ocr: |
| 302 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 303 | status = regulator_enable(mmc->supply.vqmmc); |
| 304 | if (status) |
| 305 | dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); |
| 306 | } |
| 307 | |
| 308 | return ret; |
| 309 | } |
| 310 | |
| 311 | static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, |
| 312 | int vdd) |
| 313 | { |
| 314 | int ret; |
| 315 | |
| 316 | if (IS_ERR(host->pbias)) |
| 317 | return 0; |
| 318 | |
| 319 | if (power_on) { |
| 320 | if (vdd <= VDD_165_195) |
| 321 | ret = regulator_set_voltage(host->pbias, VDD_1V8, |
| 322 | VDD_1V8); |
| 323 | else |
| 324 | ret = regulator_set_voltage(host->pbias, VDD_3V0, |
| 325 | VDD_3V0); |
| 326 | if (ret < 0) { |
| 327 | dev_err(host->dev, "pbias set voltage fail\n"); |
| 328 | return ret; |
| 329 | } |
| 330 | |
| 331 | if (host->pbias_enabled == 0) { |
| 332 | ret = regulator_enable(host->pbias); |
| 333 | if (ret) { |
| 334 | dev_err(host->dev, "pbias reg enable fail\n"); |
| 335 | return ret; |
| 336 | } |
| 337 | host->pbias_enabled = 1; |
| 338 | } |
| 339 | } else { |
| 340 | if (host->pbias_enabled == 1) { |
| 341 | ret = regulator_disable(host->pbias); |
| 342 | if (ret) { |
| 343 | dev_err(host->dev, "pbias reg disable fail\n"); |
| 344 | return ret; |
| 345 | } |
| 346 | host->pbias_enabled = 0; |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | return 0; |
| 351 | } |
| 352 | |
| 353 | static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on, |
| 354 | int vdd) |
| 355 | { |
| 356 | struct mmc_host *mmc = host->mmc; |
| 357 | int ret = 0; |
| 358 | |
| 359 | /* |
| 360 | * If we don't see a Vcc regulator, assume it's a fixed |
| 361 | * voltage always-on regulator. |
| 362 | */ |
| 363 | if (IS_ERR(mmc->supply.vmmc)) |
| 364 | return 0; |
| 365 | |
| 366 | ret = omap_hsmmc_set_pbias(host, false, 0); |
| 367 | if (ret) |
| 368 | return ret; |
| 369 | |
| 370 | /* |
| 371 | * Assume Vcc regulator is used only to power the card ... OMAP |
| 372 | * VDDS is used to power the pins, optionally with a transceiver to |
| 373 | * support cards using voltages other than VDDS (1.8V nominal). When a |
| 374 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. |
| 375 | * |
| 376 | * In some cases this regulator won't support enable/disable; |
| 377 | * e.g. it's a fixed rail for a WLAN chip. |
| 378 | * |
| 379 | * In other cases vcc_aux switches interface power. Example, for |
| 380 | * eMMC cards it represents VccQ. Sometimes transceivers or SDIO |
| 381 | * chips/cards need an interface voltage rail too. |
| 382 | */ |
| 383 | if (power_on) { |
| 384 | ret = omap_hsmmc_enable_supply(mmc); |
| 385 | if (ret) |
| 386 | return ret; |
| 387 | |
| 388 | ret = omap_hsmmc_set_pbias(host, true, vdd); |
| 389 | if (ret) |
| 390 | goto err_set_voltage; |
| 391 | } else { |
| 392 | ret = omap_hsmmc_disable_supply(mmc); |
| 393 | if (ret) |
| 394 | return ret; |
| 395 | } |
| 396 | |
| 397 | return 0; |
| 398 | |
| 399 | err_set_voltage: |
| 400 | omap_hsmmc_disable_supply(mmc); |
| 401 | |
| 402 | return ret; |
| 403 | } |
| 404 | |
| 405 | static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) |
| 406 | { |
| 407 | int ret; |
| 408 | |
| 409 | if (IS_ERR(reg)) |
| 410 | return 0; |
| 411 | |
| 412 | if (regulator_is_enabled(reg)) { |
| 413 | ret = regulator_enable(reg); |
| 414 | if (ret) |
| 415 | return ret; |
| 416 | |
| 417 | ret = regulator_disable(reg); |
| 418 | if (ret) |
| 419 | return ret; |
| 420 | } |
| 421 | |
| 422 | return 0; |
| 423 | } |
| 424 | |
| 425 | static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) |
| 426 | { |
| 427 | struct mmc_host *mmc = host->mmc; |
| 428 | int ret; |
| 429 | |
| 430 | /* |
| 431 | * disable regulators enabled during boot and get the usecount |
| 432 | * right so that regulators can be enabled/disabled by checking |
| 433 | * the return value of regulator_is_enabled |
| 434 | */ |
| 435 | ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); |
| 436 | if (ret) { |
| 437 | dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); |
| 438 | return ret; |
| 439 | } |
| 440 | |
| 441 | ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); |
| 442 | if (ret) { |
| 443 | dev_err(host->dev, |
| 444 | "fail to disable boot enabled vmmc_aux reg\n"); |
| 445 | return ret; |
| 446 | } |
| 447 | |
| 448 | ret = omap_hsmmc_disable_boot_regulator(host->pbias); |
| 449 | if (ret) { |
| 450 | dev_err(host->dev, |
| 451 | "failed to disable boot enabled pbias reg\n"); |
| 452 | return ret; |
| 453 | } |
| 454 | |
| 455 | return 0; |
| 456 | } |
| 457 | |
| 458 | static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) |
| 459 | { |
| 460 | int ret; |
| 461 | struct mmc_host *mmc = host->mmc; |
| 462 | |
| 463 | |
| 464 | ret = mmc_regulator_get_supply(mmc); |
| 465 | if (ret == -EPROBE_DEFER) |
| 466 | return ret; |
| 467 | |
| 468 | /* Allow an aux regulator */ |
| 469 | if (IS_ERR(mmc->supply.vqmmc)) { |
| 470 | mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, |
| 471 | "vmmc_aux"); |
| 472 | if (IS_ERR(mmc->supply.vqmmc)) { |
| 473 | ret = PTR_ERR(mmc->supply.vqmmc); |
| 474 | if ((ret != -ENODEV) && host->dev->of_node) |
| 475 | return ret; |
| 476 | dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", |
| 477 | PTR_ERR(mmc->supply.vqmmc)); |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | host->pbias = devm_regulator_get_optional(host->dev, "pbias"); |
| 482 | if (IS_ERR(host->pbias)) { |
| 483 | ret = PTR_ERR(host->pbias); |
| 484 | if ((ret != -ENODEV) && host->dev->of_node) { |
| 485 | dev_err(host->dev, |
| 486 | "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); |
| 487 | return ret; |
| 488 | } |
| 489 | dev_dbg(host->dev, "unable to get pbias regulator %ld\n", |
| 490 | PTR_ERR(host->pbias)); |
| 491 | } |
| 492 | |
| 493 | /* For eMMC do not power off when not in sleep state */ |
| 494 | if (mmc_pdata(host)->no_regulator_off_init) |
| 495 | return 0; |
| 496 | |
| 497 | ret = omap_hsmmc_disable_boot_regulators(host); |
| 498 | if (ret) |
| 499 | return ret; |
| 500 | |
| 501 | return 0; |
| 502 | } |
| 503 | |
| 504 | static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); |
| 505 | |
| 506 | static int omap_hsmmc_gpio_init(struct mmc_host *mmc, |
| 507 | struct omap_hsmmc_host *host, |
| 508 | struct omap_hsmmc_platform_data *pdata) |
| 509 | { |
| 510 | int ret; |
| 511 | |
| 512 | if (gpio_is_valid(pdata->gpio_cod)) { |
| 513 | ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); |
| 514 | if (ret) |
| 515 | return ret; |
| 516 | |
| 517 | host->get_cover_state = omap_hsmmc_get_cover_state; |
| 518 | mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); |
| 519 | } else if (gpio_is_valid(pdata->gpio_cd)) { |
| 520 | ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); |
| 521 | if (ret) |
| 522 | return ret; |
| 523 | |
| 524 | host->card_detect = omap_hsmmc_card_detect; |
| 525 | } |
| 526 | |
| 527 | if (gpio_is_valid(pdata->gpio_wp)) { |
| 528 | ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); |
| 529 | if (ret) |
| 530 | return ret; |
| 531 | } |
| 532 | |
| 533 | return 0; |
| 534 | } |
| 535 | |
| 536 | /* |
| 537 | * Start clock to the card |
| 538 | */ |
| 539 | static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) |
| 540 | { |
| 541 | OMAP_HSMMC_WRITE(host->base, SYSCTL, |
| 542 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); |
| 543 | } |
| 544 | |
| 545 | /* |
| 546 | * Stop clock to the card |
| 547 | */ |
| 548 | static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) |
| 549 | { |
| 550 | OMAP_HSMMC_WRITE(host->base, SYSCTL, |
| 551 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); |
| 552 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) |
| 553 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); |
| 554 | } |
| 555 | |
| 556 | static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, |
| 557 | struct mmc_command *cmd) |
| 558 | { |
| 559 | u32 irq_mask = INT_EN_MASK; |
| 560 | unsigned long flags; |
| 561 | |
| 562 | if (host->use_dma) |
| 563 | irq_mask &= ~(BRR_EN | BWR_EN); |
| 564 | |
| 565 | /* Disable timeout for erases */ |
| 566 | if (cmd->opcode == MMC_ERASE) |
| 567 | irq_mask &= ~DTO_EN; |
| 568 | |
| 569 | spin_lock_irqsave(&host->irq_lock, flags); |
| 570 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
| 571 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); |
| 572 | |
| 573 | /* latch pending CIRQ, but don't signal MMC core */ |
| 574 | if (host->flags & HSMMC_SDIO_IRQ_ENABLED) |
| 575 | irq_mask |= CIRQ_EN; |
| 576 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); |
| 577 | spin_unlock_irqrestore(&host->irq_lock, flags); |
| 578 | } |
| 579 | |
| 580 | static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) |
| 581 | { |
| 582 | u32 irq_mask = 0; |
| 583 | unsigned long flags; |
| 584 | |
| 585 | spin_lock_irqsave(&host->irq_lock, flags); |
| 586 | /* no transfer running but need to keep cirq if enabled */ |
| 587 | if (host->flags & HSMMC_SDIO_IRQ_ENABLED) |
| 588 | irq_mask |= CIRQ_EN; |
| 589 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); |
| 590 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); |
| 591 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
| 592 | spin_unlock_irqrestore(&host->irq_lock, flags); |
| 593 | } |
| 594 | |
| 595 | /* Calculate divisor for the given clock frequency */ |
| 596 | static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) |
| 597 | { |
| 598 | u16 dsor = 0; |
| 599 | |
| 600 | if (ios->clock) { |
| 601 | dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); |
| 602 | if (dsor > CLKD_MAX) |
| 603 | dsor = CLKD_MAX; |
| 604 | } |
| 605 | |
| 606 | return dsor; |
| 607 | } |
| 608 | |
| 609 | static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) |
| 610 | { |
| 611 | struct mmc_ios *ios = &host->mmc->ios; |
| 612 | unsigned long regval; |
| 613 | unsigned long timeout; |
| 614 | unsigned long clkdiv; |
| 615 | |
| 616 | dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); |
| 617 | |
| 618 | omap_hsmmc_stop_clock(host); |
| 619 | |
| 620 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); |
| 621 | regval = regval & ~(CLKD_MASK | DTO_MASK); |
| 622 | clkdiv = calc_divisor(host, ios); |
| 623 | regval = regval | (clkdiv << 6) | (DTO << 16); |
| 624 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); |
| 625 | OMAP_HSMMC_WRITE(host->base, SYSCTL, |
| 626 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); |
| 627 | |
| 628 | /* Wait till the ICS bit is set */ |
| 629 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); |
| 630 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS |
| 631 | && time_before(jiffies, timeout)) |
| 632 | cpu_relax(); |
| 633 | |
| 634 | /* |
| 635 | * Enable High-Speed Support |
| 636 | * Pre-Requisites |
| 637 | * - Controller should support High-Speed-Enable Bit |
| 638 | * - Controller should not be using DDR Mode |
| 639 | * - Controller should advertise that it supports High Speed |
| 640 | * in capabilities register |
| 641 | * - MMC/SD clock coming out of controller > 25MHz |
| 642 | */ |
| 643 | if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && |
| 644 | (ios->timing != MMC_TIMING_MMC_DDR52) && |
| 645 | (ios->timing != MMC_TIMING_UHS_DDR50) && |
| 646 | ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { |
| 647 | regval = OMAP_HSMMC_READ(host->base, HCTL); |
| 648 | if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) |
| 649 | regval |= HSPE; |
| 650 | else |
| 651 | regval &= ~HSPE; |
| 652 | |
| 653 | OMAP_HSMMC_WRITE(host->base, HCTL, regval); |
| 654 | } |
| 655 | |
| 656 | omap_hsmmc_start_clock(host); |
| 657 | } |
| 658 | |
| 659 | static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) |
| 660 | { |
| 661 | struct mmc_ios *ios = &host->mmc->ios; |
| 662 | u32 con; |
| 663 | |
| 664 | con = OMAP_HSMMC_READ(host->base, CON); |
| 665 | if (ios->timing == MMC_TIMING_MMC_DDR52 || |
| 666 | ios->timing == MMC_TIMING_UHS_DDR50) |
| 667 | con |= DDR; /* configure in DDR mode */ |
| 668 | else |
| 669 | con &= ~DDR; |
| 670 | switch (ios->bus_width) { |
| 671 | case MMC_BUS_WIDTH_8: |
| 672 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); |
| 673 | break; |
| 674 | case MMC_BUS_WIDTH_4: |
| 675 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
| 676 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 677 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); |
| 678 | break; |
| 679 | case MMC_BUS_WIDTH_1: |
| 680 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
| 681 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 682 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); |
| 683 | break; |
| 684 | } |
| 685 | } |
| 686 | |
| 687 | static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) |
| 688 | { |
| 689 | struct mmc_ios *ios = &host->mmc->ios; |
| 690 | u32 con; |
| 691 | |
| 692 | con = OMAP_HSMMC_READ(host->base, CON); |
| 693 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) |
| 694 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); |
| 695 | else |
| 696 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); |
| 697 | } |
| 698 | |
| 699 | #ifdef CONFIG_PM |
| 700 | |
| 701 | /* |
| 702 | * Restore the MMC host context, if it was lost as result of a |
| 703 | * power state change. |
| 704 | */ |
| 705 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
| 706 | { |
| 707 | struct mmc_ios *ios = &host->mmc->ios; |
| 708 | u32 hctl, capa; |
| 709 | unsigned long timeout; |
| 710 | |
| 711 | if (host->con == OMAP_HSMMC_READ(host->base, CON) && |
| 712 | host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && |
| 713 | host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && |
| 714 | host->capa == OMAP_HSMMC_READ(host->base, CAPA)) |
| 715 | return 0; |
| 716 | |
| 717 | host->context_loss++; |
| 718 | |
| 719 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
| 720 | if (host->power_mode != MMC_POWER_OFF && |
| 721 | (1 << ios->vdd) <= MMC_VDD_23_24) |
| 722 | hctl = SDVS18; |
| 723 | else |
| 724 | hctl = SDVS30; |
| 725 | capa = VS30 | VS18; |
| 726 | } else { |
| 727 | hctl = SDVS18; |
| 728 | capa = VS18; |
| 729 | } |
| 730 | |
| 731 | if (host->mmc->caps & MMC_CAP_SDIO_IRQ) |
| 732 | hctl |= IWE; |
| 733 | |
| 734 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 735 | OMAP_HSMMC_READ(host->base, HCTL) | hctl); |
| 736 | |
| 737 | OMAP_HSMMC_WRITE(host->base, CAPA, |
| 738 | OMAP_HSMMC_READ(host->base, CAPA) | capa); |
| 739 | |
| 740 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 741 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); |
| 742 | |
| 743 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); |
| 744 | while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP |
| 745 | && time_before(jiffies, timeout)) |
| 746 | ; |
| 747 | |
| 748 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
| 749 | OMAP_HSMMC_WRITE(host->base, IE, 0); |
| 750 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
| 751 | |
| 752 | /* Do not initialize card-specific things if the power is off */ |
| 753 | if (host->power_mode == MMC_POWER_OFF) |
| 754 | goto out; |
| 755 | |
| 756 | omap_hsmmc_set_bus_width(host); |
| 757 | |
| 758 | omap_hsmmc_set_clock(host); |
| 759 | |
| 760 | omap_hsmmc_set_bus_mode(host); |
| 761 | |
| 762 | out: |
| 763 | dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", |
| 764 | host->context_loss); |
| 765 | return 0; |
| 766 | } |
| 767 | |
| 768 | /* |
| 769 | * Save the MMC host context (store the number of power state changes so far). |
| 770 | */ |
| 771 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
| 772 | { |
| 773 | host->con = OMAP_HSMMC_READ(host->base, CON); |
| 774 | host->hctl = OMAP_HSMMC_READ(host->base, HCTL); |
| 775 | host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); |
| 776 | host->capa = OMAP_HSMMC_READ(host->base, CAPA); |
| 777 | } |
| 778 | |
| 779 | #else |
| 780 | |
| 781 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
| 782 | { |
| 783 | return 0; |
| 784 | } |
| 785 | |
| 786 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
| 787 | { |
| 788 | } |
| 789 | |
| 790 | #endif |
| 791 | |
| 792 | /* |
| 793 | * Send init stream sequence to card |
| 794 | * before sending IDLE command |
| 795 | */ |
| 796 | static void send_init_stream(struct omap_hsmmc_host *host) |
| 797 | { |
| 798 | int reg = 0; |
| 799 | unsigned long timeout; |
| 800 | |
| 801 | if (host->protect_card) |
| 802 | return; |
| 803 | |
| 804 | disable_irq(host->irq); |
| 805 | |
| 806 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); |
| 807 | OMAP_HSMMC_WRITE(host->base, CON, |
| 808 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); |
| 809 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); |
| 810 | |
| 811 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); |
| 812 | while ((reg != CC_EN) && time_before(jiffies, timeout)) |
| 813 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; |
| 814 | |
| 815 | OMAP_HSMMC_WRITE(host->base, CON, |
| 816 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); |
| 817 | |
| 818 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
| 819 | OMAP_HSMMC_READ(host->base, STAT); |
| 820 | |
| 821 | enable_irq(host->irq); |
| 822 | } |
| 823 | |
| 824 | static inline |
| 825 | int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) |
| 826 | { |
| 827 | int r = 1; |
| 828 | |
| 829 | if (host->get_cover_state) |
| 830 | r = host->get_cover_state(host->dev); |
| 831 | return r; |
| 832 | } |
| 833 | |
| 834 | static ssize_t |
| 835 | omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, |
| 836 | char *buf) |
| 837 | { |
| 838 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); |
| 839 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 840 | |
| 841 | return sprintf(buf, "%s\n", |
| 842 | omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); |
| 843 | } |
| 844 | |
| 845 | static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); |
| 846 | |
| 847 | static ssize_t |
| 848 | omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, |
| 849 | char *buf) |
| 850 | { |
| 851 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); |
| 852 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 853 | |
| 854 | return sprintf(buf, "%s\n", mmc_pdata(host)->name); |
| 855 | } |
| 856 | |
| 857 | static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); |
| 858 | |
| 859 | /* |
| 860 | * Configure the response type and send the cmd. |
| 861 | */ |
| 862 | static void |
| 863 | omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, |
| 864 | struct mmc_data *data) |
| 865 | { |
| 866 | int cmdreg = 0, resptype = 0, cmdtype = 0; |
| 867 | |
| 868 | dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", |
| 869 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); |
| 870 | host->cmd = cmd; |
| 871 | |
| 872 | omap_hsmmc_enable_irq(host, cmd); |
| 873 | |
| 874 | host->response_busy = 0; |
| 875 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 876 | if (cmd->flags & MMC_RSP_136) |
| 877 | resptype = 1; |
| 878 | else if (cmd->flags & MMC_RSP_BUSY) { |
| 879 | resptype = 3; |
| 880 | host->response_busy = 1; |
| 881 | } else |
| 882 | resptype = 2; |
| 883 | } |
| 884 | |
| 885 | /* |
| 886 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on |
| 887 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need |
| 888 | * a val of 0x3, rest 0x0. |
| 889 | */ |
| 890 | if (cmd == host->mrq->stop) |
| 891 | cmdtype = 0x3; |
| 892 | |
| 893 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); |
| 894 | |
| 895 | if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && |
| 896 | host->mrq->sbc) { |
| 897 | cmdreg |= ACEN_ACMD23; |
| 898 | OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); |
| 899 | } |
| 900 | if (data) { |
| 901 | cmdreg |= DP_SELECT | MSBS | BCE; |
| 902 | if (data->flags & MMC_DATA_READ) |
| 903 | cmdreg |= DDIR; |
| 904 | else |
| 905 | cmdreg &= ~(DDIR); |
| 906 | } |
| 907 | |
| 908 | if (host->use_dma) |
| 909 | cmdreg |= DMAE; |
| 910 | |
| 911 | host->req_in_progress = 1; |
| 912 | |
| 913 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
| 914 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); |
| 915 | } |
| 916 | |
| 917 | static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, |
| 918 | struct mmc_data *data) |
| 919 | { |
| 920 | return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; |
| 921 | } |
| 922 | |
| 923 | static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) |
| 924 | { |
| 925 | int dma_ch; |
| 926 | unsigned long flags; |
| 927 | |
| 928 | spin_lock_irqsave(&host->irq_lock, flags); |
| 929 | host->req_in_progress = 0; |
| 930 | dma_ch = host->dma_ch; |
| 931 | spin_unlock_irqrestore(&host->irq_lock, flags); |
| 932 | |
| 933 | omap_hsmmc_disable_irq(host); |
| 934 | /* Do not complete the request if DMA is still in progress */ |
| 935 | if (mrq->data && host->use_dma && dma_ch != -1) |
| 936 | return; |
| 937 | host->mrq = NULL; |
| 938 | mmc_request_done(host->mmc, mrq); |
| 939 | } |
| 940 | |
| 941 | /* |
| 942 | * Notify the transfer complete to MMC core |
| 943 | */ |
| 944 | static void |
| 945 | omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) |
| 946 | { |
| 947 | if (!data) { |
| 948 | struct mmc_request *mrq = host->mrq; |
| 949 | |
| 950 | /* TC before CC from CMD6 - don't know why, but it happens */ |
| 951 | if (host->cmd && host->cmd->opcode == 6 && |
| 952 | host->response_busy) { |
| 953 | host->response_busy = 0; |
| 954 | return; |
| 955 | } |
| 956 | |
| 957 | omap_hsmmc_request_done(host, mrq); |
| 958 | return; |
| 959 | } |
| 960 | |
| 961 | host->data = NULL; |
| 962 | |
| 963 | if (!data->error) |
| 964 | data->bytes_xfered += data->blocks * (data->blksz); |
| 965 | else |
| 966 | data->bytes_xfered = 0; |
| 967 | |
| 968 | if (data->stop && (data->error || !host->mrq->sbc)) |
| 969 | omap_hsmmc_start_command(host, data->stop, NULL); |
| 970 | else |
| 971 | omap_hsmmc_request_done(host, data->mrq); |
| 972 | } |
| 973 | |
| 974 | /* |
| 975 | * Notify the core about command completion |
| 976 | */ |
| 977 | static void |
| 978 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
| 979 | { |
| 980 | if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && |
| 981 | !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { |
| 982 | host->cmd = NULL; |
| 983 | omap_hsmmc_start_dma_transfer(host); |
| 984 | omap_hsmmc_start_command(host, host->mrq->cmd, |
| 985 | host->mrq->data); |
| 986 | return; |
| 987 | } |
| 988 | |
| 989 | host->cmd = NULL; |
| 990 | |
| 991 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 992 | if (cmd->flags & MMC_RSP_136) { |
| 993 | /* response type 2 */ |
| 994 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); |
| 995 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); |
| 996 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); |
| 997 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); |
| 998 | } else { |
| 999 | /* response types 1, 1b, 3, 4, 5, 6 */ |
| 1000 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); |
| 1001 | } |
| 1002 | } |
| 1003 | if ((host->data == NULL && !host->response_busy) || cmd->error) |
| 1004 | omap_hsmmc_request_done(host, host->mrq); |
| 1005 | } |
| 1006 | |
| 1007 | /* |
| 1008 | * DMA clean up for command errors |
| 1009 | */ |
| 1010 | static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) |
| 1011 | { |
| 1012 | int dma_ch; |
| 1013 | unsigned long flags; |
| 1014 | |
| 1015 | host->data->error = errno; |
| 1016 | |
| 1017 | spin_lock_irqsave(&host->irq_lock, flags); |
| 1018 | dma_ch = host->dma_ch; |
| 1019 | host->dma_ch = -1; |
| 1020 | spin_unlock_irqrestore(&host->irq_lock, flags); |
| 1021 | |
| 1022 | if (host->use_dma && dma_ch != -1) { |
| 1023 | struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); |
| 1024 | |
| 1025 | dmaengine_terminate_all(chan); |
| 1026 | dma_unmap_sg(chan->device->dev, |
| 1027 | host->data->sg, host->data->sg_len, |
| 1028 | mmc_get_dma_dir(host->data)); |
| 1029 | |
| 1030 | host->data->host_cookie = 0; |
| 1031 | } |
| 1032 | host->data = NULL; |
| 1033 | } |
| 1034 | |
| 1035 | /* |
| 1036 | * Readable error output |
| 1037 | */ |
| 1038 | #ifdef CONFIG_MMC_DEBUG |
| 1039 | static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) |
| 1040 | { |
| 1041 | /* --- means reserved bit without definition at documentation */ |
| 1042 | static const char *omap_hsmmc_status_bits[] = { |
| 1043 | "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , |
| 1044 | "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", |
| 1045 | "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , |
| 1046 | "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" |
| 1047 | }; |
| 1048 | char res[256]; |
| 1049 | char *buf = res; |
| 1050 | int len, i; |
| 1051 | |
| 1052 | len = sprintf(buf, "MMC IRQ 0x%x :", status); |
| 1053 | buf += len; |
| 1054 | |
| 1055 | for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) |
| 1056 | if (status & (1 << i)) { |
| 1057 | len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); |
| 1058 | buf += len; |
| 1059 | } |
| 1060 | |
| 1061 | dev_vdbg(mmc_dev(host->mmc), "%s\n", res); |
| 1062 | } |
| 1063 | #else |
| 1064 | static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, |
| 1065 | u32 status) |
| 1066 | { |
| 1067 | } |
| 1068 | #endif /* CONFIG_MMC_DEBUG */ |
| 1069 | |
| 1070 | /* |
| 1071 | * MMC controller internal state machines reset |
| 1072 | * |
| 1073 | * Used to reset command or data internal state machines, using respectively |
| 1074 | * SRC or SRD bit of SYSCTL register |
| 1075 | * Can be called from interrupt context |
| 1076 | */ |
| 1077 | static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, |
| 1078 | unsigned long bit) |
| 1079 | { |
| 1080 | unsigned long i = 0; |
| 1081 | unsigned long limit = MMC_TIMEOUT_US; |
| 1082 | |
| 1083 | OMAP_HSMMC_WRITE(host->base, SYSCTL, |
| 1084 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); |
| 1085 | |
| 1086 | /* |
| 1087 | * OMAP4 ES2 and greater has an updated reset logic. |
| 1088 | * Monitor a 0->1 transition first |
| 1089 | */ |
| 1090 | if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { |
| 1091 | while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) |
| 1092 | && (i++ < limit)) |
| 1093 | udelay(1); |
| 1094 | } |
| 1095 | i = 0; |
| 1096 | |
| 1097 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && |
| 1098 | (i++ < limit)) |
| 1099 | udelay(1); |
| 1100 | |
| 1101 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) |
| 1102 | dev_err(mmc_dev(host->mmc), |
| 1103 | "Timeout waiting on controller reset in %s\n", |
| 1104 | __func__); |
| 1105 | } |
| 1106 | |
| 1107 | static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, |
| 1108 | int err, int end_cmd) |
| 1109 | { |
| 1110 | if (end_cmd) { |
| 1111 | omap_hsmmc_reset_controller_fsm(host, SRC); |
| 1112 | if (host->cmd) |
| 1113 | host->cmd->error = err; |
| 1114 | } |
| 1115 | |
| 1116 | if (host->data) { |
| 1117 | omap_hsmmc_reset_controller_fsm(host, SRD); |
| 1118 | omap_hsmmc_dma_cleanup(host, err); |
| 1119 | } else if (host->mrq && host->mrq->cmd) |
| 1120 | host->mrq->cmd->error = err; |
| 1121 | } |
| 1122 | |
| 1123 | static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) |
| 1124 | { |
| 1125 | struct mmc_data *data; |
| 1126 | int end_cmd = 0, end_trans = 0; |
| 1127 | int error = 0; |
| 1128 | |
| 1129 | data = host->data; |
| 1130 | dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); |
| 1131 | |
| 1132 | if (status & ERR_EN) { |
| 1133 | omap_hsmmc_dbg_report_irq(host, status); |
| 1134 | |
| 1135 | if (status & (CTO_EN | CCRC_EN | CEB_EN)) |
| 1136 | end_cmd = 1; |
| 1137 | if (host->data || host->response_busy) { |
| 1138 | end_trans = !end_cmd; |
| 1139 | host->response_busy = 0; |
| 1140 | } |
| 1141 | if (status & (CTO_EN | DTO_EN)) |
| 1142 | hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); |
| 1143 | else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | |
| 1144 | BADA_EN)) |
| 1145 | hsmmc_command_incomplete(host, -EILSEQ, end_cmd); |
| 1146 | |
| 1147 | if (status & ACE_EN) { |
| 1148 | u32 ac12; |
| 1149 | ac12 = OMAP_HSMMC_READ(host->base, AC12); |
| 1150 | if (!(ac12 & ACNE) && host->mrq->sbc) { |
| 1151 | end_cmd = 1; |
| 1152 | if (ac12 & ACTO) |
| 1153 | error = -ETIMEDOUT; |
| 1154 | else if (ac12 & (ACCE | ACEB | ACIE)) |
| 1155 | error = -EILSEQ; |
| 1156 | host->mrq->sbc->error = error; |
| 1157 | hsmmc_command_incomplete(host, error, end_cmd); |
| 1158 | } |
| 1159 | dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); |
| 1160 | } |
| 1161 | } |
| 1162 | |
| 1163 | OMAP_HSMMC_WRITE(host->base, STAT, status); |
| 1164 | if (end_cmd || ((status & CC_EN) && host->cmd)) |
| 1165 | omap_hsmmc_cmd_done(host, host->cmd); |
| 1166 | if ((end_trans || (status & TC_EN)) && host->mrq) |
| 1167 | omap_hsmmc_xfer_done(host, data); |
| 1168 | } |
| 1169 | |
| 1170 | /* |
| 1171 | * MMC controller IRQ handler |
| 1172 | */ |
| 1173 | static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) |
| 1174 | { |
| 1175 | struct omap_hsmmc_host *host = dev_id; |
| 1176 | int status; |
| 1177 | |
| 1178 | status = OMAP_HSMMC_READ(host->base, STAT); |
| 1179 | while (status & (INT_EN_MASK | CIRQ_EN)) { |
| 1180 | if (host->req_in_progress) |
| 1181 | omap_hsmmc_do_irq(host, status); |
| 1182 | |
| 1183 | if (status & CIRQ_EN) |
| 1184 | mmc_signal_sdio_irq(host->mmc); |
| 1185 | |
| 1186 | /* Flush posted write */ |
| 1187 | status = OMAP_HSMMC_READ(host->base, STAT); |
| 1188 | } |
| 1189 | |
| 1190 | return IRQ_HANDLED; |
| 1191 | } |
| 1192 | |
| 1193 | static void set_sd_bus_power(struct omap_hsmmc_host *host) |
| 1194 | { |
| 1195 | unsigned long i; |
| 1196 | |
| 1197 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 1198 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); |
| 1199 | for (i = 0; i < loops_per_jiffy; i++) { |
| 1200 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) |
| 1201 | break; |
| 1202 | cpu_relax(); |
| 1203 | } |
| 1204 | } |
| 1205 | |
| 1206 | /* |
| 1207 | * Switch MMC interface voltage ... only relevant for MMC1. |
| 1208 | * |
| 1209 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. |
| 1210 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. |
| 1211 | * Some chips, like eMMC ones, use internal transceivers. |
| 1212 | */ |
| 1213 | static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) |
| 1214 | { |
| 1215 | u32 reg_val = 0; |
| 1216 | int ret; |
| 1217 | |
| 1218 | /* Disable the clocks */ |
| 1219 | if (host->dbclk) |
| 1220 | clk_disable_unprepare(host->dbclk); |
| 1221 | |
| 1222 | /* Turn the power off */ |
| 1223 | ret = omap_hsmmc_set_power(host, 0, 0); |
| 1224 | |
| 1225 | /* Turn the power ON with given VDD 1.8 or 3.0v */ |
| 1226 | if (!ret) |
| 1227 | ret = omap_hsmmc_set_power(host, 1, vdd); |
| 1228 | if (host->dbclk) |
| 1229 | clk_prepare_enable(host->dbclk); |
| 1230 | |
| 1231 | if (ret != 0) |
| 1232 | goto err; |
| 1233 | |
| 1234 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 1235 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); |
| 1236 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); |
| 1237 | |
| 1238 | /* |
| 1239 | * If a MMC dual voltage card is detected, the set_ios fn calls |
| 1240 | * this fn with VDD bit set for 1.8V. Upon card removal from the |
| 1241 | * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
| 1242 | * |
| 1243 | * Cope with a bit of slop in the range ... per data sheets: |
| 1244 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, |
| 1245 | * but recommended values are 1.71V to 1.89V |
| 1246 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, |
| 1247 | * but recommended values are 2.7V to 3.3V |
| 1248 | * |
| 1249 | * Board setup code shouldn't permit anything very out-of-range. |
| 1250 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the |
| 1251 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. |
| 1252 | */ |
| 1253 | if ((1 << vdd) <= MMC_VDD_23_24) |
| 1254 | reg_val |= SDVS18; |
| 1255 | else |
| 1256 | reg_val |= SDVS30; |
| 1257 | |
| 1258 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); |
| 1259 | set_sd_bus_power(host); |
| 1260 | |
| 1261 | return 0; |
| 1262 | err: |
| 1263 | dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); |
| 1264 | return ret; |
| 1265 | } |
| 1266 | |
| 1267 | /* Protect the card while the cover is open */ |
| 1268 | static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) |
| 1269 | { |
| 1270 | if (!host->get_cover_state) |
| 1271 | return; |
| 1272 | |
| 1273 | host->reqs_blocked = 0; |
| 1274 | if (host->get_cover_state(host->dev)) { |
| 1275 | if (host->protect_card) { |
| 1276 | dev_info(host->dev, "%s: cover is closed, " |
| 1277 | "card is now accessible\n", |
| 1278 | mmc_hostname(host->mmc)); |
| 1279 | host->protect_card = 0; |
| 1280 | } |
| 1281 | } else { |
| 1282 | if (!host->protect_card) { |
| 1283 | dev_info(host->dev, "%s: cover is open, " |
| 1284 | "card is now inaccessible\n", |
| 1285 | mmc_hostname(host->mmc)); |
| 1286 | host->protect_card = 1; |
| 1287 | } |
| 1288 | } |
| 1289 | } |
| 1290 | |
| 1291 | /* |
| 1292 | * irq handler when (cell-phone) cover is mounted/removed |
| 1293 | */ |
| 1294 | static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) |
| 1295 | { |
| 1296 | struct omap_hsmmc_host *host = dev_id; |
| 1297 | |
| 1298 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); |
| 1299 | |
| 1300 | omap_hsmmc_protect_card(host); |
| 1301 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); |
| 1302 | return IRQ_HANDLED; |
| 1303 | } |
| 1304 | |
| 1305 | static void omap_hsmmc_dma_callback(void *param) |
| 1306 | { |
| 1307 | struct omap_hsmmc_host *host = param; |
| 1308 | struct dma_chan *chan; |
| 1309 | struct mmc_data *data; |
| 1310 | int req_in_progress; |
| 1311 | |
| 1312 | spin_lock_irq(&host->irq_lock); |
| 1313 | if (host->dma_ch < 0) { |
| 1314 | spin_unlock_irq(&host->irq_lock); |
| 1315 | return; |
| 1316 | } |
| 1317 | |
| 1318 | data = host->mrq->data; |
| 1319 | chan = omap_hsmmc_get_dma_chan(host, data); |
| 1320 | if (!data->host_cookie) |
| 1321 | dma_unmap_sg(chan->device->dev, |
| 1322 | data->sg, data->sg_len, |
| 1323 | mmc_get_dma_dir(data)); |
| 1324 | |
| 1325 | req_in_progress = host->req_in_progress; |
| 1326 | host->dma_ch = -1; |
| 1327 | spin_unlock_irq(&host->irq_lock); |
| 1328 | |
| 1329 | /* If DMA has finished after TC, complete the request */ |
| 1330 | if (!req_in_progress) { |
| 1331 | struct mmc_request *mrq = host->mrq; |
| 1332 | |
| 1333 | host->mrq = NULL; |
| 1334 | mmc_request_done(host->mmc, mrq); |
| 1335 | } |
| 1336 | } |
| 1337 | |
| 1338 | static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, |
| 1339 | struct mmc_data *data, |
| 1340 | struct omap_hsmmc_next *next, |
| 1341 | struct dma_chan *chan) |
| 1342 | { |
| 1343 | int dma_len; |
| 1344 | |
| 1345 | if (!next && data->host_cookie && |
| 1346 | data->host_cookie != host->next_data.cookie) { |
| 1347 | dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" |
| 1348 | " host->next_data.cookie %d\n", |
| 1349 | __func__, data->host_cookie, host->next_data.cookie); |
| 1350 | data->host_cookie = 0; |
| 1351 | } |
| 1352 | |
| 1353 | /* Check if next job is already prepared */ |
| 1354 | if (next || data->host_cookie != host->next_data.cookie) { |
| 1355 | dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, |
| 1356 | mmc_get_dma_dir(data)); |
| 1357 | |
| 1358 | } else { |
| 1359 | dma_len = host->next_data.dma_len; |
| 1360 | host->next_data.dma_len = 0; |
| 1361 | } |
| 1362 | |
| 1363 | |
| 1364 | if (dma_len == 0) |
| 1365 | return -EINVAL; |
| 1366 | |
| 1367 | if (next) { |
| 1368 | next->dma_len = dma_len; |
| 1369 | data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; |
| 1370 | } else |
| 1371 | host->dma_len = dma_len; |
| 1372 | |
| 1373 | return 0; |
| 1374 | } |
| 1375 | |
| 1376 | /* |
| 1377 | * Routine to configure and start DMA for the MMC card |
| 1378 | */ |
| 1379 | static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, |
| 1380 | struct mmc_request *req) |
| 1381 | { |
| 1382 | struct dma_async_tx_descriptor *tx; |
| 1383 | int ret = 0, i; |
| 1384 | struct mmc_data *data = req->data; |
| 1385 | struct dma_chan *chan; |
| 1386 | struct dma_slave_config cfg = { |
| 1387 | .src_addr = host->mapbase + OMAP_HSMMC_DATA, |
| 1388 | .dst_addr = host->mapbase + OMAP_HSMMC_DATA, |
| 1389 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 1390 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 1391 | .src_maxburst = data->blksz / 4, |
| 1392 | .dst_maxburst = data->blksz / 4, |
| 1393 | }; |
| 1394 | |
| 1395 | /* Sanity check: all the SG entries must be aligned by block size. */ |
| 1396 | for (i = 0; i < data->sg_len; i++) { |
| 1397 | struct scatterlist *sgl; |
| 1398 | |
| 1399 | sgl = data->sg + i; |
| 1400 | if (sgl->length % data->blksz) |
| 1401 | return -EINVAL; |
| 1402 | } |
| 1403 | if ((data->blksz % 4) != 0) |
| 1404 | /* REVISIT: The MMC buffer increments only when MSB is written. |
| 1405 | * Return error for blksz which is non multiple of four. |
| 1406 | */ |
| 1407 | return -EINVAL; |
| 1408 | |
| 1409 | BUG_ON(host->dma_ch != -1); |
| 1410 | |
| 1411 | chan = omap_hsmmc_get_dma_chan(host, data); |
| 1412 | |
| 1413 | ret = dmaengine_slave_config(chan, &cfg); |
| 1414 | if (ret) |
| 1415 | return ret; |
| 1416 | |
| 1417 | ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); |
| 1418 | if (ret) |
| 1419 | return ret; |
| 1420 | |
| 1421 | tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, |
| 1422 | data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, |
| 1423 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 1424 | if (!tx) { |
| 1425 | dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); |
| 1426 | /* FIXME: cleanup */ |
| 1427 | return -1; |
| 1428 | } |
| 1429 | |
| 1430 | tx->callback = omap_hsmmc_dma_callback; |
| 1431 | tx->callback_param = host; |
| 1432 | |
| 1433 | /* Does not fail */ |
| 1434 | dmaengine_submit(tx); |
| 1435 | |
| 1436 | host->dma_ch = 1; |
| 1437 | |
| 1438 | return 0; |
| 1439 | } |
| 1440 | |
| 1441 | static void set_data_timeout(struct omap_hsmmc_host *host, |
| 1442 | unsigned long long timeout_ns, |
| 1443 | unsigned int timeout_clks) |
| 1444 | { |
| 1445 | unsigned long long timeout = timeout_ns; |
| 1446 | unsigned int cycle_ns; |
| 1447 | uint32_t reg, clkd, dto = 0; |
| 1448 | |
| 1449 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); |
| 1450 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; |
| 1451 | if (clkd == 0) |
| 1452 | clkd = 1; |
| 1453 | |
| 1454 | cycle_ns = 1000000000 / (host->clk_rate / clkd); |
| 1455 | do_div(timeout, cycle_ns); |
| 1456 | timeout += timeout_clks; |
| 1457 | if (timeout) { |
| 1458 | while ((timeout & 0x80000000) == 0) { |
| 1459 | dto += 1; |
| 1460 | timeout <<= 1; |
| 1461 | } |
| 1462 | dto = 31 - dto; |
| 1463 | timeout <<= 1; |
| 1464 | if (timeout && dto) |
| 1465 | dto += 1; |
| 1466 | if (dto >= 13) |
| 1467 | dto -= 13; |
| 1468 | else |
| 1469 | dto = 0; |
| 1470 | if (dto > 14) |
| 1471 | dto = 14; |
| 1472 | } |
| 1473 | |
| 1474 | reg &= ~DTO_MASK; |
| 1475 | reg |= dto << DTO_SHIFT; |
| 1476 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); |
| 1477 | } |
| 1478 | |
| 1479 | static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) |
| 1480 | { |
| 1481 | struct mmc_request *req = host->mrq; |
| 1482 | struct dma_chan *chan; |
| 1483 | |
| 1484 | if (!req->data) |
| 1485 | return; |
| 1486 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) |
| 1487 | | (req->data->blocks << 16)); |
| 1488 | set_data_timeout(host, req->data->timeout_ns, |
| 1489 | req->data->timeout_clks); |
| 1490 | chan = omap_hsmmc_get_dma_chan(host, req->data); |
| 1491 | dma_async_issue_pending(chan); |
| 1492 | } |
| 1493 | |
| 1494 | /* |
| 1495 | * Configure block length for MMC/SD cards and initiate the transfer. |
| 1496 | */ |
| 1497 | static int |
| 1498 | omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) |
| 1499 | { |
| 1500 | int ret; |
| 1501 | unsigned long long timeout; |
| 1502 | |
| 1503 | host->data = req->data; |
| 1504 | |
| 1505 | if (req->data == NULL) { |
| 1506 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
| 1507 | if (req->cmd->flags & MMC_RSP_BUSY) { |
| 1508 | timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; |
| 1509 | |
| 1510 | /* |
| 1511 | * Set an arbitrary 100ms data timeout for commands with |
| 1512 | * busy signal and no indication of busy_timeout. |
| 1513 | */ |
| 1514 | if (!timeout) |
| 1515 | timeout = 100000000U; |
| 1516 | |
| 1517 | set_data_timeout(host, timeout, 0); |
| 1518 | } |
| 1519 | return 0; |
| 1520 | } |
| 1521 | |
| 1522 | if (host->use_dma) { |
| 1523 | ret = omap_hsmmc_setup_dma_transfer(host, req); |
| 1524 | if (ret != 0) { |
| 1525 | dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); |
| 1526 | return ret; |
| 1527 | } |
| 1528 | } |
| 1529 | return 0; |
| 1530 | } |
| 1531 | |
| 1532 | static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 1533 | int err) |
| 1534 | { |
| 1535 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 1536 | struct mmc_data *data = mrq->data; |
| 1537 | |
| 1538 | if (host->use_dma && data->host_cookie) { |
| 1539 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); |
| 1540 | |
| 1541 | dma_unmap_sg(c->device->dev, data->sg, data->sg_len, |
| 1542 | mmc_get_dma_dir(data)); |
| 1543 | data->host_cookie = 0; |
| 1544 | } |
| 1545 | } |
| 1546 | |
| 1547 | static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) |
| 1548 | { |
| 1549 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 1550 | |
| 1551 | if (mrq->data->host_cookie) { |
| 1552 | mrq->data->host_cookie = 0; |
| 1553 | return ; |
| 1554 | } |
| 1555 | |
| 1556 | if (host->use_dma) { |
| 1557 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); |
| 1558 | |
| 1559 | if (omap_hsmmc_pre_dma_transfer(host, mrq->data, |
| 1560 | &host->next_data, c)) |
| 1561 | mrq->data->host_cookie = 0; |
| 1562 | } |
| 1563 | } |
| 1564 | |
| 1565 | /* |
| 1566 | * Request function. for read/write operation |
| 1567 | */ |
| 1568 | static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) |
| 1569 | { |
| 1570 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 1571 | int err; |
| 1572 | |
| 1573 | BUG_ON(host->req_in_progress); |
| 1574 | BUG_ON(host->dma_ch != -1); |
| 1575 | if (host->protect_card) { |
| 1576 | if (host->reqs_blocked < 3) { |
| 1577 | /* |
| 1578 | * Ensure the controller is left in a consistent |
| 1579 | * state by resetting the command and data state |
| 1580 | * machines. |
| 1581 | */ |
| 1582 | omap_hsmmc_reset_controller_fsm(host, SRD); |
| 1583 | omap_hsmmc_reset_controller_fsm(host, SRC); |
| 1584 | host->reqs_blocked += 1; |
| 1585 | } |
| 1586 | req->cmd->error = -EBADF; |
| 1587 | if (req->data) |
| 1588 | req->data->error = -EBADF; |
| 1589 | req->cmd->retries = 0; |
| 1590 | mmc_request_done(mmc, req); |
| 1591 | return; |
| 1592 | } else if (host->reqs_blocked) |
| 1593 | host->reqs_blocked = 0; |
| 1594 | WARN_ON(host->mrq != NULL); |
| 1595 | host->mrq = req; |
| 1596 | host->clk_rate = clk_get_rate(host->fclk); |
| 1597 | err = omap_hsmmc_prepare_data(host, req); |
| 1598 | if (err) { |
| 1599 | req->cmd->error = err; |
| 1600 | if (req->data) |
| 1601 | req->data->error = err; |
| 1602 | host->mrq = NULL; |
| 1603 | mmc_request_done(mmc, req); |
| 1604 | return; |
| 1605 | } |
| 1606 | if (req->sbc && !(host->flags & AUTO_CMD23)) { |
| 1607 | omap_hsmmc_start_command(host, req->sbc, NULL); |
| 1608 | return; |
| 1609 | } |
| 1610 | |
| 1611 | omap_hsmmc_start_dma_transfer(host); |
| 1612 | omap_hsmmc_start_command(host, req->cmd, req->data); |
| 1613 | } |
| 1614 | |
| 1615 | /* Routine to configure clock values. Exposed API to core */ |
| 1616 | static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1617 | { |
| 1618 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 1619 | int do_send_init_stream = 0; |
| 1620 | |
| 1621 | if (ios->power_mode != host->power_mode) { |
| 1622 | switch (ios->power_mode) { |
| 1623 | case MMC_POWER_OFF: |
| 1624 | omap_hsmmc_set_power(host, 0, 0); |
| 1625 | break; |
| 1626 | case MMC_POWER_UP: |
| 1627 | omap_hsmmc_set_power(host, 1, ios->vdd); |
| 1628 | break; |
| 1629 | case MMC_POWER_ON: |
| 1630 | do_send_init_stream = 1; |
| 1631 | break; |
| 1632 | } |
| 1633 | host->power_mode = ios->power_mode; |
| 1634 | } |
| 1635 | |
| 1636 | /* FIXME: set registers based only on changes to ios */ |
| 1637 | |
| 1638 | omap_hsmmc_set_bus_width(host); |
| 1639 | |
| 1640 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
| 1641 | /* Only MMC1 can interface at 3V without some flavor |
| 1642 | * of external transceiver; but they all handle 1.8V. |
| 1643 | */ |
| 1644 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
| 1645 | (ios->vdd == DUAL_VOLT_OCR_BIT)) { |
| 1646 | /* |
| 1647 | * The mmc_select_voltage fn of the core does |
| 1648 | * not seem to set the power_mode to |
| 1649 | * MMC_POWER_UP upon recalculating the voltage. |
| 1650 | * vdd 1.8v. |
| 1651 | */ |
| 1652 | if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) |
| 1653 | dev_dbg(mmc_dev(host->mmc), |
| 1654 | "Switch operation failed\n"); |
| 1655 | } |
| 1656 | } |
| 1657 | |
| 1658 | omap_hsmmc_set_clock(host); |
| 1659 | |
| 1660 | if (do_send_init_stream) |
| 1661 | send_init_stream(host); |
| 1662 | |
| 1663 | omap_hsmmc_set_bus_mode(host); |
| 1664 | } |
| 1665 | |
| 1666 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) |
| 1667 | { |
| 1668 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 1669 | |
| 1670 | if (!host->card_detect) |
| 1671 | return -ENOSYS; |
| 1672 | return host->card_detect(host->dev); |
| 1673 | } |
| 1674 | |
| 1675 | static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) |
| 1676 | { |
| 1677 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 1678 | |
| 1679 | if (mmc_pdata(host)->init_card) |
| 1680 | mmc_pdata(host)->init_card(card); |
| 1681 | } |
| 1682 | |
| 1683 | static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) |
| 1684 | { |
| 1685 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 1686 | u32 irq_mask, con; |
| 1687 | unsigned long flags; |
| 1688 | |
| 1689 | spin_lock_irqsave(&host->irq_lock, flags); |
| 1690 | |
| 1691 | con = OMAP_HSMMC_READ(host->base, CON); |
| 1692 | irq_mask = OMAP_HSMMC_READ(host->base, ISE); |
| 1693 | if (enable) { |
| 1694 | host->flags |= HSMMC_SDIO_IRQ_ENABLED; |
| 1695 | irq_mask |= CIRQ_EN; |
| 1696 | con |= CTPL | CLKEXTFREE; |
| 1697 | } else { |
| 1698 | host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; |
| 1699 | irq_mask &= ~CIRQ_EN; |
| 1700 | con &= ~(CTPL | CLKEXTFREE); |
| 1701 | } |
| 1702 | OMAP_HSMMC_WRITE(host->base, CON, con); |
| 1703 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); |
| 1704 | |
| 1705 | /* |
| 1706 | * if enable, piggy back detection on current request |
| 1707 | * but always disable immediately |
| 1708 | */ |
| 1709 | if (!host->req_in_progress || !enable) |
| 1710 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); |
| 1711 | |
| 1712 | /* flush posted write */ |
| 1713 | OMAP_HSMMC_READ(host->base, IE); |
| 1714 | |
| 1715 | spin_unlock_irqrestore(&host->irq_lock, flags); |
| 1716 | } |
| 1717 | |
| 1718 | static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) |
| 1719 | { |
| 1720 | int ret; |
| 1721 | |
| 1722 | /* |
| 1723 | * For omaps with wake-up path, wakeirq will be irq from pinctrl and |
| 1724 | * for other omaps, wakeirq will be from GPIO (dat line remuxed to |
| 1725 | * gpio). wakeirq is needed to detect sdio irq in runtime suspend state |
| 1726 | * with functional clock disabled. |
| 1727 | */ |
| 1728 | if (!host->dev->of_node || !host->wake_irq) |
| 1729 | return -ENODEV; |
| 1730 | |
| 1731 | ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); |
| 1732 | if (ret) { |
| 1733 | dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); |
| 1734 | goto err; |
| 1735 | } |
| 1736 | |
| 1737 | /* |
| 1738 | * Some omaps don't have wake-up path from deeper idle states |
| 1739 | * and need to remux SDIO DAT1 to GPIO for wake-up from idle. |
| 1740 | */ |
| 1741 | if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { |
| 1742 | struct pinctrl *p = devm_pinctrl_get(host->dev); |
| 1743 | if (IS_ERR(p)) { |
| 1744 | ret = PTR_ERR(p); |
| 1745 | goto err_free_irq; |
| 1746 | } |
| 1747 | if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { |
| 1748 | dev_info(host->dev, "missing default pinctrl state\n"); |
| 1749 | devm_pinctrl_put(p); |
| 1750 | ret = -EINVAL; |
| 1751 | goto err_free_irq; |
| 1752 | } |
| 1753 | |
| 1754 | if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { |
| 1755 | dev_info(host->dev, "missing idle pinctrl state\n"); |
| 1756 | devm_pinctrl_put(p); |
| 1757 | ret = -EINVAL; |
| 1758 | goto err_free_irq; |
| 1759 | } |
| 1760 | devm_pinctrl_put(p); |
| 1761 | } |
| 1762 | |
| 1763 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 1764 | OMAP_HSMMC_READ(host->base, HCTL) | IWE); |
| 1765 | return 0; |
| 1766 | |
| 1767 | err_free_irq: |
| 1768 | dev_pm_clear_wake_irq(host->dev); |
| 1769 | err: |
| 1770 | dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); |
| 1771 | host->wake_irq = 0; |
| 1772 | return ret; |
| 1773 | } |
| 1774 | |
| 1775 | static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) |
| 1776 | { |
| 1777 | u32 hctl, capa, value; |
| 1778 | |
| 1779 | /* Only MMC1 supports 3.0V */ |
| 1780 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
| 1781 | hctl = SDVS30; |
| 1782 | capa = VS30 | VS18; |
| 1783 | } else { |
| 1784 | hctl = SDVS18; |
| 1785 | capa = VS18; |
| 1786 | } |
| 1787 | |
| 1788 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; |
| 1789 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); |
| 1790 | |
| 1791 | value = OMAP_HSMMC_READ(host->base, CAPA); |
| 1792 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); |
| 1793 | |
| 1794 | /* Set SD bus power bit */ |
| 1795 | set_sd_bus_power(host); |
| 1796 | } |
| 1797 | |
| 1798 | static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, |
| 1799 | unsigned int direction, int blk_size) |
| 1800 | { |
| 1801 | /* This controller can't do multiblock reads due to hw bugs */ |
| 1802 | if (direction == MMC_DATA_READ) |
| 1803 | return 1; |
| 1804 | |
| 1805 | return blk_size; |
| 1806 | } |
| 1807 | |
| 1808 | static struct mmc_host_ops omap_hsmmc_ops = { |
| 1809 | .post_req = omap_hsmmc_post_req, |
| 1810 | .pre_req = omap_hsmmc_pre_req, |
| 1811 | .request = omap_hsmmc_request, |
| 1812 | .set_ios = omap_hsmmc_set_ios, |
| 1813 | .get_cd = omap_hsmmc_get_cd, |
| 1814 | .get_ro = mmc_gpio_get_ro, |
| 1815 | .init_card = omap_hsmmc_init_card, |
| 1816 | .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, |
| 1817 | }; |
| 1818 | |
| 1819 | #ifdef CONFIG_DEBUG_FS |
| 1820 | |
| 1821 | static int omap_hsmmc_regs_show(struct seq_file *s, void *data) |
| 1822 | { |
| 1823 | struct mmc_host *mmc = s->private; |
| 1824 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
| 1825 | |
| 1826 | seq_printf(s, "mmc%d:\n", mmc->index); |
| 1827 | seq_printf(s, "sdio irq mode\t%s\n", |
| 1828 | (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); |
| 1829 | |
| 1830 | if (mmc->caps & MMC_CAP_SDIO_IRQ) { |
| 1831 | seq_printf(s, "sdio irq \t%s\n", |
| 1832 | (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" |
| 1833 | : "disabled"); |
| 1834 | } |
| 1835 | seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); |
| 1836 | |
| 1837 | pm_runtime_get_sync(host->dev); |
| 1838 | seq_puts(s, "\nregs:\n"); |
| 1839 | seq_printf(s, "CON:\t\t0x%08x\n", |
| 1840 | OMAP_HSMMC_READ(host->base, CON)); |
| 1841 | seq_printf(s, "PSTATE:\t\t0x%08x\n", |
| 1842 | OMAP_HSMMC_READ(host->base, PSTATE)); |
| 1843 | seq_printf(s, "HCTL:\t\t0x%08x\n", |
| 1844 | OMAP_HSMMC_READ(host->base, HCTL)); |
| 1845 | seq_printf(s, "SYSCTL:\t\t0x%08x\n", |
| 1846 | OMAP_HSMMC_READ(host->base, SYSCTL)); |
| 1847 | seq_printf(s, "IE:\t\t0x%08x\n", |
| 1848 | OMAP_HSMMC_READ(host->base, IE)); |
| 1849 | seq_printf(s, "ISE:\t\t0x%08x\n", |
| 1850 | OMAP_HSMMC_READ(host->base, ISE)); |
| 1851 | seq_printf(s, "CAPA:\t\t0x%08x\n", |
| 1852 | OMAP_HSMMC_READ(host->base, CAPA)); |
| 1853 | |
| 1854 | pm_runtime_mark_last_busy(host->dev); |
| 1855 | pm_runtime_put_autosuspend(host->dev); |
| 1856 | |
| 1857 | return 0; |
| 1858 | } |
| 1859 | |
| 1860 | static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) |
| 1861 | { |
| 1862 | return single_open(file, omap_hsmmc_regs_show, inode->i_private); |
| 1863 | } |
| 1864 | |
| 1865 | static const struct file_operations mmc_regs_fops = { |
| 1866 | .open = omap_hsmmc_regs_open, |
| 1867 | .read = seq_read, |
| 1868 | .llseek = seq_lseek, |
| 1869 | .release = single_release, |
| 1870 | }; |
| 1871 | |
| 1872 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
| 1873 | { |
| 1874 | if (mmc->debugfs_root) |
| 1875 | debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, |
| 1876 | mmc, &mmc_regs_fops); |
| 1877 | } |
| 1878 | |
| 1879 | #else |
| 1880 | |
| 1881 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
| 1882 | { |
| 1883 | } |
| 1884 | |
| 1885 | #endif |
| 1886 | |
| 1887 | #ifdef CONFIG_OF |
| 1888 | static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { |
| 1889 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
| 1890 | .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, |
| 1891 | }; |
| 1892 | |
| 1893 | static const struct omap_mmc_of_data omap4_mmc_of_data = { |
| 1894 | .reg_offset = 0x100, |
| 1895 | }; |
| 1896 | static const struct omap_mmc_of_data am33xx_mmc_of_data = { |
| 1897 | .reg_offset = 0x100, |
| 1898 | .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, |
| 1899 | }; |
| 1900 | |
| 1901 | static const struct of_device_id omap_mmc_of_match[] = { |
| 1902 | { |
| 1903 | .compatible = "ti,omap2-hsmmc", |
| 1904 | }, |
| 1905 | { |
| 1906 | .compatible = "ti,omap3-pre-es3-hsmmc", |
| 1907 | .data = &omap3_pre_es3_mmc_of_data, |
| 1908 | }, |
| 1909 | { |
| 1910 | .compatible = "ti,omap3-hsmmc", |
| 1911 | }, |
| 1912 | { |
| 1913 | .compatible = "ti,omap4-hsmmc", |
| 1914 | .data = &omap4_mmc_of_data, |
| 1915 | }, |
| 1916 | { |
| 1917 | .compatible = "ti,am33xx-hsmmc", |
| 1918 | .data = &am33xx_mmc_of_data, |
| 1919 | }, |
| 1920 | {}, |
| 1921 | }; |
| 1922 | MODULE_DEVICE_TABLE(of, omap_mmc_of_match); |
| 1923 | |
| 1924 | static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) |
| 1925 | { |
| 1926 | struct omap_hsmmc_platform_data *pdata, *legacy; |
| 1927 | struct device_node *np = dev->of_node; |
| 1928 | |
| 1929 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
| 1930 | if (!pdata) |
| 1931 | return ERR_PTR(-ENOMEM); /* out of memory */ |
| 1932 | |
| 1933 | legacy = dev_get_platdata(dev); |
| 1934 | if (legacy && legacy->name) |
| 1935 | pdata->name = legacy->name; |
| 1936 | |
| 1937 | if (of_find_property(np, "ti,dual-volt", NULL)) |
| 1938 | pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; |
| 1939 | |
| 1940 | pdata->gpio_cd = -EINVAL; |
| 1941 | pdata->gpio_cod = -EINVAL; |
| 1942 | pdata->gpio_wp = -EINVAL; |
| 1943 | |
| 1944 | if (of_find_property(np, "ti,non-removable", NULL)) { |
| 1945 | pdata->nonremovable = true; |
| 1946 | pdata->no_regulator_off_init = true; |
| 1947 | } |
| 1948 | |
| 1949 | if (of_find_property(np, "ti,needs-special-reset", NULL)) |
| 1950 | pdata->features |= HSMMC_HAS_UPDATED_RESET; |
| 1951 | |
| 1952 | if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) |
| 1953 | pdata->features |= HSMMC_HAS_HSPE_SUPPORT; |
| 1954 | |
| 1955 | return pdata; |
| 1956 | } |
| 1957 | #else |
| 1958 | static inline struct omap_hsmmc_platform_data |
| 1959 | *of_get_hsmmc_pdata(struct device *dev) |
| 1960 | { |
| 1961 | return ERR_PTR(-EINVAL); |
| 1962 | } |
| 1963 | #endif |
| 1964 | |
| 1965 | static int omap_hsmmc_probe(struct platform_device *pdev) |
| 1966 | { |
| 1967 | struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; |
| 1968 | struct mmc_host *mmc; |
| 1969 | struct omap_hsmmc_host *host = NULL; |
| 1970 | struct resource *res; |
| 1971 | int ret, irq; |
| 1972 | const struct of_device_id *match; |
| 1973 | const struct omap_mmc_of_data *data; |
| 1974 | void __iomem *base; |
| 1975 | |
| 1976 | match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); |
| 1977 | if (match) { |
| 1978 | pdata = of_get_hsmmc_pdata(&pdev->dev); |
| 1979 | |
| 1980 | if (IS_ERR(pdata)) |
| 1981 | return PTR_ERR(pdata); |
| 1982 | |
| 1983 | if (match->data) { |
| 1984 | data = match->data; |
| 1985 | pdata->reg_offset = data->reg_offset; |
| 1986 | pdata->controller_flags |= data->controller_flags; |
| 1987 | } |
| 1988 | } |
| 1989 | |
| 1990 | if (pdata == NULL) { |
| 1991 | dev_err(&pdev->dev, "Platform Data is missing\n"); |
| 1992 | return -ENXIO; |
| 1993 | } |
| 1994 | |
| 1995 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1996 | irq = platform_get_irq(pdev, 0); |
| 1997 | if (res == NULL || irq < 0) |
| 1998 | return -ENXIO; |
| 1999 | |
| 2000 | base = devm_ioremap_resource(&pdev->dev, res); |
| 2001 | if (IS_ERR(base)) |
| 2002 | return PTR_ERR(base); |
| 2003 | |
| 2004 | mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); |
| 2005 | if (!mmc) { |
| 2006 | ret = -ENOMEM; |
| 2007 | goto err; |
| 2008 | } |
| 2009 | |
| 2010 | ret = mmc_of_parse(mmc); |
| 2011 | if (ret) |
| 2012 | goto err1; |
| 2013 | |
| 2014 | host = mmc_priv(mmc); |
| 2015 | host->mmc = mmc; |
| 2016 | host->pdata = pdata; |
| 2017 | host->dev = &pdev->dev; |
| 2018 | host->use_dma = 1; |
| 2019 | host->dma_ch = -1; |
| 2020 | host->irq = irq; |
| 2021 | host->mapbase = res->start + pdata->reg_offset; |
| 2022 | host->base = base + pdata->reg_offset; |
| 2023 | host->power_mode = MMC_POWER_OFF; |
| 2024 | host->next_data.cookie = 1; |
| 2025 | host->pbias_enabled = 0; |
| 2026 | host->vqmmc_enabled = 0; |
| 2027 | |
| 2028 | ret = omap_hsmmc_gpio_init(mmc, host, pdata); |
| 2029 | if (ret) |
| 2030 | goto err_gpio; |
| 2031 | |
| 2032 | platform_set_drvdata(pdev, host); |
| 2033 | |
| 2034 | if (pdev->dev.of_node) |
| 2035 | host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); |
| 2036 | |
| 2037 | mmc->ops = &omap_hsmmc_ops; |
| 2038 | |
| 2039 | mmc->f_min = OMAP_MMC_MIN_CLOCK; |
| 2040 | |
| 2041 | if (pdata->max_freq > 0) |
| 2042 | mmc->f_max = pdata->max_freq; |
| 2043 | else if (mmc->f_max == 0) |
| 2044 | mmc->f_max = OMAP_MMC_MAX_CLOCK; |
| 2045 | |
| 2046 | spin_lock_init(&host->irq_lock); |
| 2047 | |
| 2048 | host->fclk = devm_clk_get(&pdev->dev, "fck"); |
| 2049 | if (IS_ERR(host->fclk)) { |
| 2050 | ret = PTR_ERR(host->fclk); |
| 2051 | host->fclk = NULL; |
| 2052 | goto err1; |
| 2053 | } |
| 2054 | |
| 2055 | if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { |
| 2056 | dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); |
| 2057 | omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; |
| 2058 | } |
| 2059 | |
| 2060 | device_init_wakeup(&pdev->dev, true); |
| 2061 | pm_runtime_enable(host->dev); |
| 2062 | pm_runtime_get_sync(host->dev); |
| 2063 | pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); |
| 2064 | pm_runtime_use_autosuspend(host->dev); |
| 2065 | |
| 2066 | omap_hsmmc_context_save(host); |
| 2067 | |
| 2068 | host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); |
| 2069 | /* |
| 2070 | * MMC can still work without debounce clock. |
| 2071 | */ |
| 2072 | if (IS_ERR(host->dbclk)) { |
| 2073 | host->dbclk = NULL; |
| 2074 | } else if (clk_prepare_enable(host->dbclk) != 0) { |
| 2075 | dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); |
| 2076 | host->dbclk = NULL; |
| 2077 | } |
| 2078 | |
| 2079 | /* Set this to a value that allows allocating an entire descriptor |
| 2080 | * list within a page (zero order allocation). */ |
| 2081 | mmc->max_segs = 64; |
| 2082 | |
| 2083 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
| 2084 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ |
| 2085 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; |
| 2086 | |
| 2087 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
| 2088 | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE | MMC_CAP_CMD23; |
| 2089 | |
| 2090 | mmc->caps |= mmc_pdata(host)->caps; |
| 2091 | if (mmc->caps & MMC_CAP_8_BIT_DATA) |
| 2092 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
| 2093 | |
| 2094 | if (mmc_pdata(host)->nonremovable) |
| 2095 | mmc->caps |= MMC_CAP_NONREMOVABLE; |
| 2096 | |
| 2097 | mmc->pm_caps |= mmc_pdata(host)->pm_caps; |
| 2098 | |
| 2099 | omap_hsmmc_conf_bus_power(host); |
| 2100 | |
| 2101 | host->rx_chan = dma_request_chan(&pdev->dev, "rx"); |
| 2102 | if (IS_ERR(host->rx_chan)) { |
| 2103 | dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); |
| 2104 | ret = PTR_ERR(host->rx_chan); |
| 2105 | goto err_irq; |
| 2106 | } |
| 2107 | |
| 2108 | host->tx_chan = dma_request_chan(&pdev->dev, "tx"); |
| 2109 | if (IS_ERR(host->tx_chan)) { |
| 2110 | dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); |
| 2111 | ret = PTR_ERR(host->tx_chan); |
| 2112 | goto err_irq; |
| 2113 | } |
| 2114 | |
| 2115 | /* |
| 2116 | * Limit the maximum segment size to the lower of the request size |
| 2117 | * and the DMA engine device segment size limits. In reality, with |
| 2118 | * 32-bit transfers, the DMA engine can do longer segments than this |
| 2119 | * but there is no way to represent that in the DMA model - if we |
| 2120 | * increase this figure here, we get warnings from the DMA API debug. |
| 2121 | */ |
| 2122 | mmc->max_seg_size = min3(mmc->max_req_size, |
| 2123 | dma_get_max_seg_size(host->rx_chan->device->dev), |
| 2124 | dma_get_max_seg_size(host->tx_chan->device->dev)); |
| 2125 | |
| 2126 | /* Request IRQ for MMC operations */ |
| 2127 | ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, |
| 2128 | mmc_hostname(mmc), host); |
| 2129 | if (ret) { |
| 2130 | dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); |
| 2131 | goto err_irq; |
| 2132 | } |
| 2133 | |
| 2134 | ret = omap_hsmmc_reg_get(host); |
| 2135 | if (ret) |
| 2136 | goto err_irq; |
| 2137 | |
| 2138 | if (!mmc->ocr_avail) |
| 2139 | mmc->ocr_avail = mmc_pdata(host)->ocr_mask; |
| 2140 | |
| 2141 | omap_hsmmc_disable_irq(host); |
| 2142 | |
| 2143 | /* |
| 2144 | * For now, only support SDIO interrupt if we have a separate |
| 2145 | * wake-up interrupt configured from device tree. This is because |
| 2146 | * the wake-up interrupt is needed for idle state and some |
| 2147 | * platforms need special quirks. And we don't want to add new |
| 2148 | * legacy mux platform init code callbacks any longer as we |
| 2149 | * are moving to DT based booting anyways. |
| 2150 | */ |
| 2151 | ret = omap_hsmmc_configure_wake_irq(host); |
| 2152 | if (!ret) |
| 2153 | mmc->caps |= MMC_CAP_SDIO_IRQ; |
| 2154 | |
| 2155 | omap_hsmmc_protect_card(host); |
| 2156 | |
| 2157 | mmc_add_host(mmc); |
| 2158 | |
| 2159 | if (mmc_pdata(host)->name != NULL) { |
| 2160 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
| 2161 | if (ret < 0) |
| 2162 | goto err_slot_name; |
| 2163 | } |
| 2164 | if (host->get_cover_state) { |
| 2165 | ret = device_create_file(&mmc->class_dev, |
| 2166 | &dev_attr_cover_switch); |
| 2167 | if (ret < 0) |
| 2168 | goto err_slot_name; |
| 2169 | } |
| 2170 | |
| 2171 | omap_hsmmc_debugfs(mmc); |
| 2172 | pm_runtime_mark_last_busy(host->dev); |
| 2173 | pm_runtime_put_autosuspend(host->dev); |
| 2174 | |
| 2175 | return 0; |
| 2176 | |
| 2177 | err_slot_name: |
| 2178 | mmc_remove_host(mmc); |
| 2179 | err_irq: |
| 2180 | device_init_wakeup(&pdev->dev, false); |
| 2181 | if (!IS_ERR_OR_NULL(host->tx_chan)) |
| 2182 | dma_release_channel(host->tx_chan); |
| 2183 | if (!IS_ERR_OR_NULL(host->rx_chan)) |
| 2184 | dma_release_channel(host->rx_chan); |
| 2185 | pm_runtime_dont_use_autosuspend(host->dev); |
| 2186 | pm_runtime_put_sync(host->dev); |
| 2187 | pm_runtime_disable(host->dev); |
| 2188 | if (host->dbclk) |
| 2189 | clk_disable_unprepare(host->dbclk); |
| 2190 | err1: |
| 2191 | err_gpio: |
| 2192 | mmc_free_host(mmc); |
| 2193 | err: |
| 2194 | return ret; |
| 2195 | } |
| 2196 | |
| 2197 | static int omap_hsmmc_remove(struct platform_device *pdev) |
| 2198 | { |
| 2199 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
| 2200 | |
| 2201 | pm_runtime_get_sync(host->dev); |
| 2202 | mmc_remove_host(host->mmc); |
| 2203 | |
| 2204 | dma_release_channel(host->tx_chan); |
| 2205 | dma_release_channel(host->rx_chan); |
| 2206 | |
| 2207 | dev_pm_clear_wake_irq(host->dev); |
| 2208 | pm_runtime_dont_use_autosuspend(host->dev); |
| 2209 | pm_runtime_put_sync(host->dev); |
| 2210 | pm_runtime_disable(host->dev); |
| 2211 | device_init_wakeup(&pdev->dev, false); |
| 2212 | if (host->dbclk) |
| 2213 | clk_disable_unprepare(host->dbclk); |
| 2214 | |
| 2215 | mmc_free_host(host->mmc); |
| 2216 | |
| 2217 | return 0; |
| 2218 | } |
| 2219 | |
| 2220 | #ifdef CONFIG_PM_SLEEP |
| 2221 | static int omap_hsmmc_suspend(struct device *dev) |
| 2222 | { |
| 2223 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
| 2224 | |
| 2225 | if (!host) |
| 2226 | return 0; |
| 2227 | |
| 2228 | pm_runtime_get_sync(host->dev); |
| 2229 | |
| 2230 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { |
| 2231 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
| 2232 | OMAP_HSMMC_WRITE(host->base, IE, 0); |
| 2233 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
| 2234 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 2235 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); |
| 2236 | } |
| 2237 | |
| 2238 | if (host->dbclk) |
| 2239 | clk_disable_unprepare(host->dbclk); |
| 2240 | |
| 2241 | pm_runtime_put_sync(host->dev); |
| 2242 | return 0; |
| 2243 | } |
| 2244 | |
| 2245 | /* Routine to resume the MMC device */ |
| 2246 | static int omap_hsmmc_resume(struct device *dev) |
| 2247 | { |
| 2248 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
| 2249 | |
| 2250 | if (!host) |
| 2251 | return 0; |
| 2252 | |
| 2253 | pm_runtime_get_sync(host->dev); |
| 2254 | |
| 2255 | if (host->dbclk) |
| 2256 | clk_prepare_enable(host->dbclk); |
| 2257 | |
| 2258 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) |
| 2259 | omap_hsmmc_conf_bus_power(host); |
| 2260 | |
| 2261 | omap_hsmmc_protect_card(host); |
| 2262 | pm_runtime_mark_last_busy(host->dev); |
| 2263 | pm_runtime_put_autosuspend(host->dev); |
| 2264 | return 0; |
| 2265 | } |
| 2266 | #endif |
| 2267 | |
| 2268 | static int omap_hsmmc_runtime_suspend(struct device *dev) |
| 2269 | { |
| 2270 | struct omap_hsmmc_host *host; |
| 2271 | unsigned long flags; |
| 2272 | int ret = 0; |
| 2273 | |
| 2274 | host = platform_get_drvdata(to_platform_device(dev)); |
| 2275 | omap_hsmmc_context_save(host); |
| 2276 | dev_dbg(dev, "disabled\n"); |
| 2277 | |
| 2278 | spin_lock_irqsave(&host->irq_lock, flags); |
| 2279 | if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && |
| 2280 | (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { |
| 2281 | /* disable sdio irq handling to prevent race */ |
| 2282 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
| 2283 | OMAP_HSMMC_WRITE(host->base, IE, 0); |
| 2284 | |
| 2285 | if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { |
| 2286 | /* |
| 2287 | * dat1 line low, pending sdio irq |
| 2288 | * race condition: possible irq handler running on |
| 2289 | * multi-core, abort |
| 2290 | */ |
| 2291 | dev_dbg(dev, "pending sdio irq, abort suspend\n"); |
| 2292 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
| 2293 | OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); |
| 2294 | OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); |
| 2295 | pm_runtime_mark_last_busy(dev); |
| 2296 | ret = -EBUSY; |
| 2297 | goto abort; |
| 2298 | } |
| 2299 | |
| 2300 | pinctrl_pm_select_idle_state(dev); |
| 2301 | } else { |
| 2302 | pinctrl_pm_select_idle_state(dev); |
| 2303 | } |
| 2304 | |
| 2305 | abort: |
| 2306 | spin_unlock_irqrestore(&host->irq_lock, flags); |
| 2307 | return ret; |
| 2308 | } |
| 2309 | |
| 2310 | static int omap_hsmmc_runtime_resume(struct device *dev) |
| 2311 | { |
| 2312 | struct omap_hsmmc_host *host; |
| 2313 | unsigned long flags; |
| 2314 | |
| 2315 | host = platform_get_drvdata(to_platform_device(dev)); |
| 2316 | omap_hsmmc_context_restore(host); |
| 2317 | dev_dbg(dev, "enabled\n"); |
| 2318 | |
| 2319 | spin_lock_irqsave(&host->irq_lock, flags); |
| 2320 | if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && |
| 2321 | (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { |
| 2322 | |
| 2323 | pinctrl_pm_select_default_state(host->dev); |
| 2324 | |
| 2325 | /* irq lost, if pinmux incorrect */ |
| 2326 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
| 2327 | OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); |
| 2328 | OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); |
| 2329 | } else { |
| 2330 | pinctrl_pm_select_default_state(host->dev); |
| 2331 | } |
| 2332 | spin_unlock_irqrestore(&host->irq_lock, flags); |
| 2333 | return 0; |
| 2334 | } |
| 2335 | |
| 2336 | static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = { |
| 2337 | SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) |
| 2338 | .runtime_suspend = omap_hsmmc_runtime_suspend, |
| 2339 | .runtime_resume = omap_hsmmc_runtime_resume, |
| 2340 | }; |
| 2341 | |
| 2342 | static struct platform_driver omap_hsmmc_driver = { |
| 2343 | .probe = omap_hsmmc_probe, |
| 2344 | .remove = omap_hsmmc_remove, |
| 2345 | .driver = { |
| 2346 | .name = DRIVER_NAME, |
| 2347 | .pm = &omap_hsmmc_dev_pm_ops, |
| 2348 | .of_match_table = of_match_ptr(omap_mmc_of_match), |
| 2349 | }, |
| 2350 | }; |
| 2351 | |
| 2352 | module_platform_driver(omap_hsmmc_driver); |
| 2353 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); |
| 2354 | MODULE_LICENSE("GPL"); |
| 2355 | MODULE_ALIAS("platform:" DRIVER_NAME); |
| 2356 | MODULE_AUTHOR("Texas Instruments Inc"); |