projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
remove libdss from Makefile
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / irqchip / irq-gic.c
... / ...
CommitLineData
1/*
2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Interrupt architecture for the GIC:
9 *
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
12 *
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
18 *
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
22 */
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/err.h>
26#include <linux/module.h>
27#include <linux/list.h>
28#include <linux/smp.h>
29#include <linux/cpu.h>
30#include <linux/cpu_pm.h>
31#include <linux/cpumask.h>
32#include <linux/io.h>
33#include <linux/of.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
36#include <linux/acpi.h>
37#include <linux/irqdomain.h>
38#include <linux/interrupt.h>
39#include <linux/percpu.h>
40#include <linux/slab.h>
41#include <linux/irqchip.h>
42#include <linux/irqchip/chained_irq.h>
43#include <linux/irqchip/arm-gic.h>
44
45#include <asm/cputype.h>
46#include <asm/irq.h>
47#include <asm/exception.h>
48#include <asm/smp_plat.h>
49#include <asm/virt.h>
50
51#include "irq-gic-common.h"
52
53#ifdef CONFIG_ARM64
54#include <asm/cpufeature.h>
55
56static void gic_check_cpu_features(void)
57{
58 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
59 TAINT_CPU_OUT_OF_SPEC,
60 "GICv3 system registers enabled, broken firmware!\n");
61}
62#else
63#define gic_check_cpu_features() do { } while(0)
64#endif
65
66union gic_base {
67 void __iomem *common_base;
68 void __percpu * __iomem *percpu_base;
69};
70
71struct gic_chip_data {
72 struct irq_chip chip;
73 union gic_base dist_base;
74 union gic_base cpu_base;
75 void __iomem *raw_dist_base;
76 void __iomem *raw_cpu_base;
77 u32 percpu_offset;
78#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
79 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
80 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
81 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
82 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
83 u32 __percpu *saved_ppi_enable;
84 u32 __percpu *saved_ppi_active;
85 u32 __percpu *saved_ppi_conf;
86#endif
87 struct irq_domain *domain;
88 unsigned int gic_irqs;
89#ifdef CONFIG_GIC_NON_BANKED
90 void __iomem *(*get_base)(union gic_base *);
91#endif
92};
93
94#ifdef CONFIG_BL_SWITCHER
95
96static DEFINE_RAW_SPINLOCK(cpu_map_lock);
97
98#define gic_lock_irqsave(f) \
99 raw_spin_lock_irqsave(&cpu_map_lock, (f))
100#define gic_unlock_irqrestore(f) \
101 raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
102
103#define gic_lock() raw_spin_lock(&cpu_map_lock)
104#define gic_unlock() raw_spin_unlock(&cpu_map_lock)
105
106#else
107
108#define gic_lock_irqsave(f) do { (void)(f); } while(0)
109#define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
110
111#define gic_lock() do { } while(0)
112#define gic_unlock() do { } while(0)
113
114#endif
115
116/*
117 * The GIC mapping of CPU interfaces does not necessarily match
118 * the logical CPU numbering. Let's use a mapping as returned
119 * by the GIC itself.
120 */
121#define NR_GIC_CPU_IF 8
122static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
123
124static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
125
126static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
127
128static struct gic_kvm_info gic_v2_kvm_info;
129
130#ifdef CONFIG_GIC_NON_BANKED
131static void __iomem *gic_get_percpu_base(union gic_base *base)
132{
133 return raw_cpu_read(*base->percpu_base);
134}
135
136static void __iomem *gic_get_common_base(union gic_base *base)
137{
138 return base->common_base;
139}
140
141static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
142{
143 return data->get_base(&data->dist_base);
144}
145
146static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
147{
148 return data->get_base(&data->cpu_base);
149}
150
151static inline void gic_set_base_accessor(struct gic_chip_data *data,
152 void __iomem *(*f)(union gic_base *))
153{
154 data->get_base = f;
155}
156#else
157#define gic_data_dist_base(d) ((d)->dist_base.common_base)
158#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
159#define gic_set_base_accessor(d, f)
160#endif
161
162static inline void __iomem *gic_dist_base(struct irq_data *d)
163{
164 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
165 return gic_data_dist_base(gic_data);
166}
167
168static inline void __iomem *gic_cpu_base(struct irq_data *d)
169{
170 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
171 return gic_data_cpu_base(gic_data);
172}
173
174static inline unsigned int gic_irq(struct irq_data *d)
175{
176 return d->hwirq;
177}
178
179static inline bool cascading_gic_irq(struct irq_data *d)
180{
181 void *data = irq_data_get_irq_handler_data(d);
182
183 /*
184 * If handler_data is set, this is a cascading interrupt, and
185 * it cannot possibly be forwarded.
186 */
187 return data != NULL;
188}
189
190/*
191 * Routines to acknowledge, disable and enable interrupts
192 */
193static void gic_poke_irq(struct irq_data *d, u32 offset)
194{
195 u32 mask = 1 << (gic_irq(d) % 32);
196 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
197}
198
199static int gic_peek_irq(struct irq_data *d, u32 offset)
200{
201 u32 mask = 1 << (gic_irq(d) % 32);
202 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
203}
204
205static void gic_mask_irq(struct irq_data *d)
206{
207 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
208}
209
210static void gic_eoimode1_mask_irq(struct irq_data *d)
211{
212 gic_mask_irq(d);
213 /*
214 * When masking a forwarded interrupt, make sure it is
215 * deactivated as well.
216 *
217 * This ensures that an interrupt that is getting
218 * disabled/masked will not get "stuck", because there is
219 * noone to deactivate it (guest is being terminated).
220 */
221 if (irqd_is_forwarded_to_vcpu(d))
222 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
223}
224
225static void gic_unmask_irq(struct irq_data *d)
226{
227 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
228}
229
230static void gic_eoi_irq(struct irq_data *d)
231{
232 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
233}
234
235static void gic_eoimode1_eoi_irq(struct irq_data *d)
236{
237 /* Do not deactivate an IRQ forwarded to a vcpu. */
238 if (irqd_is_forwarded_to_vcpu(d))
239 return;
240
241 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
242}
243
244static int gic_irq_set_irqchip_state(struct irq_data *d,
245 enum irqchip_irq_state which, bool val)
246{
247 u32 reg;
248
249 switch (which) {
250 case IRQCHIP_STATE_PENDING:
251 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
252 break;
253
254 case IRQCHIP_STATE_ACTIVE:
255 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
256 break;
257
258 case IRQCHIP_STATE_MASKED:
259 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
260 break;
261
262 default:
263 return -EINVAL;
264 }
265
266 gic_poke_irq(d, reg);
267 return 0;
268}
269
270static int gic_irq_get_irqchip_state(struct irq_data *d,
271 enum irqchip_irq_state which, bool *val)
272{
273 switch (which) {
274 case IRQCHIP_STATE_PENDING:
275 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
276 break;
277
278 case IRQCHIP_STATE_ACTIVE:
279 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
280 break;
281
282 case IRQCHIP_STATE_MASKED:
283 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
284 break;
285
286 default:
287 return -EINVAL;
288 }
289
290 return 0;
291}
292
293static int gic_set_type(struct irq_data *d, unsigned int type)
294{
295 void __iomem *base = gic_dist_base(d);
296 unsigned int gicirq = gic_irq(d);
297
298 /* Interrupt configuration for SGIs can't be changed */
299 if (gicirq < 16)
300 return -EINVAL;
301
302 /* SPIs have restrictions on the supported types */
303 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
304 type != IRQ_TYPE_EDGE_RISING)
305 return -EINVAL;
306
307 return gic_configure_irq(gicirq, type, base, NULL);
308}
309
310static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
311{
312 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
313 if (cascading_gic_irq(d))
314 return -EINVAL;
315
316 if (vcpu)
317 irqd_set_forwarded_to_vcpu(d);
318 else
319 irqd_clr_forwarded_to_vcpu(d);
320 return 0;
321}
322
323#ifdef CONFIG_SMP
324static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
325 bool force)
326{
327 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
328 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
329 u32 val, mask, bit;
330 unsigned long flags;
331
332 gic_lock_irqsave(flags);
333 if (unlikely(d->common->state_use_accessors & IRQD_GIC_MULTI_TARGET)) {
334 struct cpumask temp_mask;
335
336 bit = 0;
337 if (!cpumask_and(&temp_mask, mask_val, cpu_online_mask))
338 goto err_out;
339#ifndef CONFIG_SCHED_HMP
340 if (!cpumask_and(&temp_mask, &temp_mask, cpu_coregroup_mask(0)))
341 goto err_out;
342#endif
343 for_each_cpu(cpu, &temp_mask) {
344 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
345 goto err_out;
346 bit |= gic_cpu_map[cpu];
347 }
348 bit <<= shift;
349 } else {
350 if (!force)
351 cpu = cpumask_any_and(mask_val, cpu_online_mask);
352 else
353 cpu = cpumask_first(mask_val);
354
355 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
356 goto err_out;
357
358 bit = gic_cpu_map[cpu] << shift;
359 }
360 mask = 0xff << shift;
361 val = readl_relaxed(reg) & ~mask;
362 writel_relaxed(val | bit, reg);
363 gic_unlock_irqrestore(flags);
364
365 irq_data_update_effective_affinity(d, cpumask_of(cpu));
366
367 return IRQ_SET_MASK_OK_DONE;
368err_out:
369 gic_unlock_irqrestore(flags);
370 return -EINVAL;
371}
372#endif
373
374static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
375{
376 u32 irqstat, irqnr;
377 struct gic_chip_data *gic = &gic_data[0];
378 void __iomem *cpu_base = gic_data_cpu_base(gic);
379
380 do {
381 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
382 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
383
384 dmb(ish);
385
386 if (likely(irqnr > 15 && irqnr < 1020)) {
387 if (static_key_true(&supports_deactivate))
388 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
389 isb();
390 handle_domain_irq(gic->domain, irqnr, regs);
391 continue;
392 }
393 if (irqnr < 16) {
394 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
395 if (static_key_true(&supports_deactivate))
396 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
397#ifdef CONFIG_SMP
398 /*
399 * Ensure any shared data written by the CPU sending
400 * the IPI is read after we've read the ACK register
401 * on the GIC.
402 *
403 * Pairs with the write barrier in gic_raise_softirq
404 */
405 smp_rmb();
406 handle_IPI(irqnr, regs);
407#endif
408 continue;
409 }
410 break;
411 } while (1);
412}
413
414static void gic_handle_cascade_irq(struct irq_desc *desc)
415{
416 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
417 struct irq_chip *chip = irq_desc_get_chip(desc);
418 unsigned int cascade_irq, gic_irq;
419 unsigned long status;
420
421 chained_irq_enter(chip, desc);
422
423 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
424
425 gic_irq = (status & GICC_IAR_INT_ID_MASK);
426 if (gic_irq == GICC_INT_SPURIOUS)
427 goto out;
428
429 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
430 if (unlikely(gic_irq < 32 || gic_irq > 1020)) {
431 handle_bad_irq(desc);
432 } else {
433 isb();
434 generic_handle_irq(cascade_irq);
435 }
436
437 out:
438 chained_irq_exit(chip, desc);
439}
440
441static const struct irq_chip gic_chip = {
442 .name = "GIC",
443 .irq_disable = gic_mask_irq,
444 .irq_enable = gic_unmask_irq,
445 .irq_mask = gic_mask_irq,
446 .irq_unmask = gic_unmask_irq,
447 .irq_eoi = gic_eoi_irq,
448 .irq_set_type = gic_set_type,
449 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
450 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
451 .flags = IRQCHIP_SET_TYPE_MASKED |
452 IRQCHIP_SKIP_SET_WAKE |
453 IRQCHIP_MASK_ON_SUSPEND,
454};
455
456void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
457{
458 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
459 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
460 &gic_data[gic_nr]);
461}
462
463static u8 gic_get_cpumask(struct gic_chip_data *gic)
464{
465 void __iomem *base = gic_data_dist_base(gic);
466 u32 mask, i;
467
468 for (i = mask = 0; i < 32; i += 4) {
469 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
470 mask |= mask >> 16;
471 mask |= mask >> 8;
472 if (mask)
473 break;
474 }
475
476 if (!mask && num_possible_cpus() > 1)
477 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
478
479 return mask;
480}
481
482static void gic_cpu_if_up(struct gic_chip_data *gic)
483{
484 void __iomem *cpu_base = gic_data_cpu_base(gic);
485 u32 bypass = 0;
486 u32 mode = 0;
487
488 if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
489 mode = GIC_CPU_CTRL_EOImodeNS;
490
491 /*
492 * Preserve bypass disable bits to be written back later
493 */
494 bypass = readl(cpu_base + GIC_CPU_CTRL);
495 bypass &= GICC_DIS_BYPASS_MASK;
496
497 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
498}
499
500
501static void gic_dist_init(struct gic_chip_data *gic)
502{
503 unsigned int i;
504 u32 cpumask;
505 unsigned int gic_irqs = gic->gic_irqs;
506 void __iomem *base = gic_data_dist_base(gic);
507
508 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
509
510 /*
511 * Set all global interrupts to this CPU only.
512 */
513 cpumask = gic_get_cpumask(gic);
514 cpumask |= cpumask << 8;
515 cpumask |= cpumask << 16;
516 for (i = 32; i < gic_irqs; i += 4)
517 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
518
519 gic_dist_config(base, gic_irqs, NULL);
520
521 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
522}
523
524static int gic_cpu_init(struct gic_chip_data *gic)
525{
526 void __iomem *dist_base = gic_data_dist_base(gic);
527 void __iomem *base = gic_data_cpu_base(gic);
528 unsigned int cpu_mask, cpu = smp_processor_id();
529 int i;
530
531 /*
532 * Setting up the CPU map is only relevant for the primary GIC
533 * because any nested/secondary GICs do not directly interface
534 * with the CPU(s).
535 */
536 if (gic == &gic_data[0]) {
537 /*
538 * Get what the GIC says our CPU mask is.
539 */
540 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
541 return -EINVAL;
542
543 gic_check_cpu_features();
544 cpu_mask = gic_get_cpumask(gic);
545 gic_cpu_map[cpu] = cpu_mask;
546
547 /*
548 * Clear our mask from the other map entries in case they're
549 * still undefined.
550 */
551 for (i = 0; i < NR_GIC_CPU_IF; i++)
552 if (i != cpu)
553 gic_cpu_map[i] &= ~cpu_mask;
554 }
555
556 gic_cpu_config(dist_base, NULL);
557
558 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
559 gic_cpu_if_up(gic);
560
561 return 0;
562}
563
564int gic_cpu_if_down(unsigned int gic_nr)
565{
566 void __iomem *cpu_base;
567 u32 val = 0;
568
569 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
570 return -EINVAL;
571
572 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
573 val = readl(cpu_base + GIC_CPU_CTRL);
574 val &= ~GICC_ENABLE;
575 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
576
577 return 0;
578}
579
580#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
581/*
582 * Saves the GIC distributor registers during suspend or idle. Must be called
583 * with interrupts disabled but before powering down the GIC. After calling
584 * this function, no interrupts will be delivered by the GIC, and another
585 * platform-specific wakeup source must be enabled.
586 */
587void gic_dist_save(struct gic_chip_data *gic)
588{
589 unsigned int gic_irqs;
590 void __iomem *dist_base;
591 int i;
592
593 if (WARN_ON(!gic))
594 return;
595
596 gic_irqs = gic->gic_irqs;
597 dist_base = gic_data_dist_base(gic);
598
599 if (!dist_base)
600 return;
601
602 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
603 gic->saved_spi_conf[i] =
604 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
605
606 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
607 gic->saved_spi_target[i] =
608 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
609
610 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
611 gic->saved_spi_enable[i] =
612 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
613
614 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
615 gic->saved_spi_active[i] =
616 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
617}
618
619/*
620 * Restores the GIC distributor registers during resume or when coming out of
621 * idle. Must be called before enabling interrupts. If a level interrupt
622 * that occured while the GIC was suspended is still present, it will be
623 * handled normally, but any edge interrupts that occured will not be seen by
624 * the GIC and need to be handled by the platform-specific wakeup source.
625 */
626void gic_dist_restore(struct gic_chip_data *gic)
627{
628 unsigned int gic_irqs;
629 unsigned int i;
630 void __iomem *dist_base;
631
632 if (WARN_ON(!gic))
633 return;
634
635 gic_irqs = gic->gic_irqs;
636 dist_base = gic_data_dist_base(gic);
637
638 if (!dist_base)
639 return;
640
641 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
642
643 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
644 writel_relaxed(gic->saved_spi_conf[i],
645 dist_base + GIC_DIST_CONFIG + i * 4);
646
647 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
648 writel_relaxed(GICD_INT_DEF_PRI_X4,
649 dist_base + GIC_DIST_PRI + i * 4);
650
651 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
652 writel_relaxed(gic->saved_spi_target[i],
653 dist_base + GIC_DIST_TARGET + i * 4);
654
655 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
656 writel_relaxed(GICD_INT_EN_CLR_X32,
657 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
658 writel_relaxed(gic->saved_spi_enable[i],
659 dist_base + GIC_DIST_ENABLE_SET + i * 4);
660 }
661
662 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
663 writel_relaxed(GICD_INT_EN_CLR_X32,
664 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
665 writel_relaxed(gic->saved_spi_active[i],
666 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
667 }
668
669 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
670}
671
672void gic_cpu_save(struct gic_chip_data *gic)
673{
674 int i;
675 u32 *ptr;
676 void __iomem *dist_base;
677 void __iomem *cpu_base;
678
679 if (WARN_ON(!gic))
680 return;
681
682 dist_base = gic_data_dist_base(gic);
683 cpu_base = gic_data_cpu_base(gic);
684
685 if (!dist_base || !cpu_base)
686 return;
687
688 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
689 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
690 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
691
692 ptr = raw_cpu_ptr(gic->saved_ppi_active);
693 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
694 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
695
696 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
697 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
698 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
699
700}
701
702void gic_cpu_restore(struct gic_chip_data *gic)
703{
704 int i;
705 u32 *ptr;
706 void __iomem *dist_base;
707 void __iomem *cpu_base;
708
709 if (WARN_ON(!gic))
710 return;
711
712 dist_base = gic_data_dist_base(gic);
713 cpu_base = gic_data_cpu_base(gic);
714
715 if (!dist_base || !cpu_base)
716 return;
717
718 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
719 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
720 writel_relaxed(GICD_INT_EN_CLR_X32,
721 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
722 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
723 }
724
725 ptr = raw_cpu_ptr(gic->saved_ppi_active);
726 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
727 writel_relaxed(GICD_INT_EN_CLR_X32,
728 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
729 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
730 }
731
732 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
733 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
734 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
735
736 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
737 writel_relaxed(GICD_INT_DEF_PRI_X4,
738 dist_base + GIC_DIST_PRI + i * 4);
739
740 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
741 gic_cpu_if_up(gic);
742}
743
744static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
745{
746 int i;
747
748 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
749#ifdef CONFIG_GIC_NON_BANKED
750 /* Skip over unused GICs */
751 if (!gic_data[i].get_base)
752 continue;
753#endif
754 switch (cmd) {
755 case CPU_PM_ENTER:
756 gic_cpu_save(&gic_data[i]);
757 break;
758 case CPU_PM_ENTER_FAILED:
759 case CPU_PM_EXIT:
760 gic_cpu_restore(&gic_data[i]);
761 break;
762 case CPU_CLUSTER_PM_ENTER:
763 gic_dist_save(&gic_data[i]);
764 break;
765 case CPU_CLUSTER_PM_ENTER_FAILED:
766 case CPU_CLUSTER_PM_EXIT:
767 gic_dist_restore(&gic_data[i]);
768 break;
769 }
770 }
771
772 return NOTIFY_OK;
773}
774
775static struct notifier_block gic_notifier_block = {
776 .notifier_call = gic_notifier,
777};
778
779static int gic_pm_init(struct gic_chip_data *gic)
780{
781 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
782 sizeof(u32));
783 if (WARN_ON(!gic->saved_ppi_enable))
784 return -ENOMEM;
785
786 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
787 sizeof(u32));
788 if (WARN_ON(!gic->saved_ppi_active))
789 goto free_ppi_enable;
790
791 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
792 sizeof(u32));
793 if (WARN_ON(!gic->saved_ppi_conf))
794 goto free_ppi_active;
795
796 if (gic == &gic_data[0])
797 cpu_pm_register_notifier(&gic_notifier_block);
798
799 return 0;
800
801free_ppi_active:
802 free_percpu(gic->saved_ppi_active);
803free_ppi_enable:
804 free_percpu(gic->saved_ppi_enable);
805
806 return -ENOMEM;
807}
808#else
809static int gic_pm_init(struct gic_chip_data *gic)
810{
811 return 0;
812}
813#endif
814
815#ifdef CONFIG_SMP
816static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
817{
818 int cpu;
819 unsigned long flags, map = 0;
820
821 if (unlikely(nr_cpu_ids == 1)) {
822 /* Only one CPU? let's do a self-IPI... */
823 writel_relaxed(2 << 24 | irq,
824 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
825 return;
826 }
827
828 gic_lock_irqsave(flags);
829
830 /* Convert our logical CPU mask into a physical one. */
831 for_each_cpu(cpu, mask)
832 map |= gic_cpu_map[cpu];
833
834 /*
835 * Ensure that stores to Normal memory are visible to the
836 * other CPUs before they observe us issuing the IPI.
837 */
838 dmb(ishst);
839
840 /* this always happens on GIC0 */
841 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
842
843 gic_unlock_irqrestore(flags);
844}
845#endif
846
847#ifdef CONFIG_BL_SWITCHER
848/*
849 * gic_send_sgi - send a SGI directly to given CPU interface number
850 *
851 * cpu_id: the ID for the destination CPU interface
852 * irq: the IPI number to send a SGI for
853 */
854void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
855{
856 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
857 cpu_id = 1 << cpu_id;
858 /* this always happens on GIC0 */
859 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
860}
861
862/*
863 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
864 *
865 * @cpu: the logical CPU number to get the GIC ID for.
866 *
867 * Return the CPU interface ID for the given logical CPU number,
868 * or -1 if the CPU number is too large or the interface ID is
869 * unknown (more than one bit set).
870 */
871int gic_get_cpu_id(unsigned int cpu)
872{
873 unsigned int cpu_bit;
874
875 if (cpu >= NR_GIC_CPU_IF)
876 return -1;
877 cpu_bit = gic_cpu_map[cpu];
878 if (cpu_bit & (cpu_bit - 1))
879 return -1;
880 return __ffs(cpu_bit);
881}
882
883/*
884 * gic_migrate_target - migrate IRQs to another CPU interface
885 *
886 * @new_cpu_id: the CPU target ID to migrate IRQs to
887 *
888 * Migrate all peripheral interrupts with a target matching the current CPU
889 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
890 * is also updated. Targets to other CPU interfaces are unchanged.
891 * This must be called with IRQs locally disabled.
892 */
893void gic_migrate_target(unsigned int new_cpu_id)
894{
895 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
896 void __iomem *dist_base;
897 int i, ror_val, cpu = smp_processor_id();
898 u32 val, cur_target_mask, active_mask;
899
900 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
901
902 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
903 if (!dist_base)
904 return;
905 gic_irqs = gic_data[gic_nr].gic_irqs;
906
907 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
908 cur_target_mask = 0x01010101 << cur_cpu_id;
909 ror_val = (cur_cpu_id - new_cpu_id) & 31;
910
911 gic_lock();
912
913 /* Update the target interface for this logical CPU */
914 gic_cpu_map[cpu] = 1 << new_cpu_id;
915
916 /*
917 * Find all the peripheral interrupts targetting the current
918 * CPU interface and migrate them to the new CPU interface.
919 * We skip DIST_TARGET 0 to 7 as they are read-only.
920 */
921 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
922 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
923 active_mask = val & cur_target_mask;
924 if (active_mask) {
925 val &= ~active_mask;
926 val |= ror32(active_mask, ror_val);
927 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
928 }
929 }
930
931 gic_unlock();
932
933 /*
934 * Now let's migrate and clear any potential SGIs that might be
935 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
936 * is a banked register, we can only forward the SGI using
937 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
938 * doesn't use that information anyway.
939 *
940 * For the same reason we do not adjust SGI source information
941 * for previously sent SGIs by us to other CPUs either.
942 */
943 for (i = 0; i < 16; i += 4) {
944 int j;
945 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
946 if (!val)
947 continue;
948 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
949 for (j = i; j < i + 4; j++) {
950 if (val & 0xff)
951 writel_relaxed((1 << (new_cpu_id + 16)) | j,
952 dist_base + GIC_DIST_SOFTINT);
953 val >>= 8;
954 }
955 }
956}
957
958/*
959 * gic_get_sgir_physaddr - get the physical address for the SGI register
960 *
961 * REturn the physical address of the SGI register to be used
962 * by some early assembly code when the kernel is not yet available.
963 */
964static unsigned long gic_dist_physaddr;
965
966unsigned long gic_get_sgir_physaddr(void)
967{
968 if (!gic_dist_physaddr)
969 return 0;
970 return gic_dist_physaddr + GIC_DIST_SOFTINT;
971}
972
973static void __init gic_init_physaddr(struct device_node *node)
974{
975 struct resource res;
976 if (of_address_to_resource(node, 0, &res) == 0) {
977 gic_dist_physaddr = res.start;
978 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
979 }
980}
981
982#else
983#define gic_init_physaddr(node) do { } while (0)
984#endif
985
986static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
987 irq_hw_number_t hw)
988{
989 struct gic_chip_data *gic = d->host_data;
990
991 if (hw < 32) {
992 irq_set_percpu_devid(irq);
993 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
994 handle_percpu_devid_irq, NULL, NULL);
995 irq_set_status_flags(irq, IRQ_NOAUTOEN);
996 } else {
997 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
998 handle_fasteoi_irq, NULL, NULL);
999 irq_set_probe(irq);
1000 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
1001 }
1002 return 0;
1003}
1004
1005static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
1006{
1007}
1008
1009static int gic_irq_domain_translate(struct irq_domain *d,
1010 struct irq_fwspec *fwspec,
1011 unsigned long *hwirq,
1012 unsigned int *type)
1013{
1014 if (is_of_node(fwspec->fwnode)) {
1015 if (fwspec->param_count < 3)
1016 return -EINVAL;
1017
1018 /* Get the interrupt number and add 16 to skip over SGIs */
1019 *hwirq = fwspec->param[1] + 16;
1020
1021 /*
1022 * For SPIs, we need to add 16 more to get the GIC irq
1023 * ID number
1024 */
1025 if (!fwspec->param[0])
1026 *hwirq += 16;
1027
1028 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1029 return 0;
1030 }
1031
1032 if (is_fwnode_irqchip(fwspec->fwnode)) {
1033 if(fwspec->param_count != 2)
1034 return -EINVAL;
1035
1036 *hwirq = fwspec->param[0];
1037 *type = fwspec->param[1];
1038 return 0;
1039 }
1040
1041 return -EINVAL;
1042}
1043
1044static int gic_starting_cpu(unsigned int cpu)
1045{
1046 gic_cpu_init(&gic_data[0]);
1047 return 0;
1048}
1049
1050static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1051 unsigned int nr_irqs, void *arg)
1052{
1053 int i, ret;
1054 irq_hw_number_t hwirq;
1055 unsigned int type = IRQ_TYPE_NONE;
1056 struct irq_fwspec *fwspec = arg;
1057
1058 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1059 if (ret)
1060 return ret;
1061
1062 for (i = 0; i < nr_irqs; i++) {
1063 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1064 if (ret)
1065 return ret;
1066 }
1067
1068 return 0;
1069}
1070
1071static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1072 .translate = gic_irq_domain_translate,
1073 .alloc = gic_irq_domain_alloc,
1074 .free = irq_domain_free_irqs_top,
1075};
1076
1077static const struct irq_domain_ops gic_irq_domain_ops = {
1078 .map = gic_irq_domain_map,
1079 .unmap = gic_irq_domain_unmap,
1080};
1081
1082static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1083 const char *name, bool use_eoimode1)
1084{
1085 /* Initialize irq_chip */
1086 gic->chip = gic_chip;
1087 gic->chip.name = name;
1088 gic->chip.parent_device = dev;
1089
1090 if (use_eoimode1) {
1091 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1092 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1093 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1094 }
1095
1096#ifdef CONFIG_SMP
1097 if (gic == &gic_data[0])
1098 gic->chip.irq_set_affinity = gic_set_affinity;
1099#endif
1100}
1101
1102static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1103 struct fwnode_handle *handle)
1104{
1105 irq_hw_number_t hwirq_base;
1106 int gic_irqs, irq_base, ret;
1107
1108 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1109 /* Frankein-GIC without banked registers... */
1110 unsigned int cpu;
1111
1112 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1113 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1114 if (WARN_ON(!gic->dist_base.percpu_base ||
1115 !gic->cpu_base.percpu_base)) {
1116 ret = -ENOMEM;
1117 goto error;
1118 }
1119
1120 for_each_possible_cpu(cpu) {
1121 u32 mpidr = cpu_logical_map(cpu);
1122 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1123 unsigned long offset = gic->percpu_offset * core_id;
1124 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1125 gic->raw_dist_base + offset;
1126 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1127 gic->raw_cpu_base + offset;
1128 }
1129
1130 gic_set_base_accessor(gic, gic_get_percpu_base);
1131 } else {
1132 /* Normal, sane GIC... */
1133 WARN(gic->percpu_offset,
1134 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1135 gic->percpu_offset);
1136 gic->dist_base.common_base = gic->raw_dist_base;
1137 gic->cpu_base.common_base = gic->raw_cpu_base;
1138 gic_set_base_accessor(gic, gic_get_common_base);
1139 }
1140
1141 /*
1142 * Find out how many interrupts are supported.
1143 * The GIC only supports up to 1020 interrupt sources.
1144 */
1145 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1146 gic_irqs = (gic_irqs + 1) * 32;
1147 if (gic_irqs > 1020)
1148 gic_irqs = 1020;
1149 gic->gic_irqs = gic_irqs;
1150
1151 if (handle) { /* DT/ACPI */
1152 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1153 &gic_irq_domain_hierarchy_ops,
1154 gic);
1155 } else { /* Legacy support */
1156 /*
1157 * For primary GICs, skip over SGIs.
1158 * For secondary GICs, skip over PPIs, too.
1159 */
1160 if (gic == &gic_data[0] && (irq_start & 31) > 0) {
1161 hwirq_base = 16;
1162 if (irq_start != -1)
1163 irq_start = (irq_start & ~31) + 16;
1164 } else {
1165 hwirq_base = 32;
1166 }
1167
1168 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1169
1170 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1171 numa_node_id());
1172 if (irq_base < 0) {
1173 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1174 irq_start);
1175 irq_base = irq_start;
1176 }
1177
1178 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1179 hwirq_base, &gic_irq_domain_ops, gic);
1180 }
1181
1182 if (WARN_ON(!gic->domain)) {
1183 ret = -ENODEV;
1184 goto error;
1185 }
1186
1187 gic_dist_init(gic);
1188 ret = gic_cpu_init(gic);
1189 if (ret)
1190 goto error;
1191
1192 ret = gic_pm_init(gic);
1193 if (ret)
1194 goto error;
1195
1196 return 0;
1197
1198error:
1199 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1200 free_percpu(gic->dist_base.percpu_base);
1201 free_percpu(gic->cpu_base.percpu_base);
1202 }
1203
1204 return ret;
1205}
1206
1207static int __init __gic_init_bases(struct gic_chip_data *gic,
1208 int irq_start,
1209 struct fwnode_handle *handle)
1210{
1211 char *name;
1212 int i, ret;
1213
1214 if (WARN_ON(!gic || gic->domain))
1215 return -EINVAL;
1216
1217 if (gic == &gic_data[0]) {
1218 /*
1219 * Initialize the CPU interface map to all CPUs.
1220 * It will be refined as each CPU probes its ID.
1221 * This is only necessary for the primary GIC.
1222 */
1223 for (i = 0; i < NR_GIC_CPU_IF; i++)
1224 gic_cpu_map[i] = 0xff;
1225#ifdef CONFIG_SMP
1226 set_smp_cross_call(gic_raise_softirq);
1227#endif
1228 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1229 "irqchip/arm/gic:starting",
1230 gic_starting_cpu, NULL);
1231 set_handle_irq(gic_handle_irq);
1232 if (static_key_true(&supports_deactivate))
1233 pr_info("GIC: Using split EOI/Deactivate mode\n");
1234 }
1235
1236 if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) {
1237 name = kasprintf(GFP_KERNEL, "GICv2");
1238 gic_init_chip(gic, NULL, name, true);
1239 } else {
1240 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1241 gic_init_chip(gic, NULL, name, false);
1242 }
1243
1244 ret = gic_init_bases(gic, irq_start, handle);
1245 if (ret)
1246 kfree(name);
1247
1248 return ret;
1249}
1250
1251void __init gic_init(unsigned int gic_nr, int irq_start,
1252 void __iomem *dist_base, void __iomem *cpu_base)
1253{
1254 struct gic_chip_data *gic;
1255
1256 if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
1257 return;
1258
1259 /*
1260 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1261 * bother with these...
1262 */
1263 static_key_slow_dec(&supports_deactivate);
1264
1265 gic = &gic_data[gic_nr];
1266 gic->raw_dist_base = dist_base;
1267 gic->raw_cpu_base = cpu_base;
1268
1269 __gic_init_bases(gic, irq_start, NULL);
1270}
1271
1272static void gic_teardown(struct gic_chip_data *gic)
1273{
1274 if (WARN_ON(!gic))
1275 return;
1276
1277 if (gic->raw_dist_base)
1278 iounmap(gic->raw_dist_base);
1279 if (gic->raw_cpu_base)
1280 iounmap(gic->raw_cpu_base);
1281}
1282
1283#ifdef CONFIG_OF
1284static int gic_cnt __initdata;
1285
1286static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1287{
1288 struct resource cpuif_res;
1289
1290 of_address_to_resource(node, 1, &cpuif_res);
1291
1292 if (!is_hyp_mode_available())
1293 return false;
1294 if (resource_size(&cpuif_res) < SZ_8K)
1295 return false;
1296 if (resource_size(&cpuif_res) == SZ_128K) {
1297 u32 val_low, val_high;
1298
1299 /*
1300 * Verify that we have the first 4kB of a GIC400
1301 * aliased over the first 64kB by checking the
1302 * GICC_IIDR register on both ends.
1303 */
1304 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1305 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1306 if ((val_low & 0xffff0fff) != 0x0202043B ||
1307 val_low != val_high)
1308 return false;
1309
1310 /*
1311 * Move the base up by 60kB, so that we have a 8kB
1312 * contiguous region, which allows us to use GICC_DIR
1313 * at its normal offset. Please pass me that bucket.
1314 */
1315 *base += 0xf000;
1316 cpuif_res.start += 0xf000;
1317 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1318 &cpuif_res.start);
1319 }
1320
1321 return true;
1322}
1323
1324static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1325{
1326 if (!gic || !node)
1327 return -EINVAL;
1328
1329 gic->raw_dist_base = of_iomap(node, 0);
1330 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1331 goto error;
1332
1333 gic->raw_cpu_base = of_iomap(node, 1);
1334 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1335 goto error;
1336
1337 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1338 gic->percpu_offset = 0;
1339
1340 return 0;
1341
1342error:
1343 gic_teardown(gic);
1344
1345 return -ENOMEM;
1346}
1347
1348int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1349{
1350 int ret;
1351
1352 if (!dev || !dev->of_node || !gic || !irq)
1353 return -EINVAL;
1354
1355 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1356 if (!*gic)
1357 return -ENOMEM;
1358
1359 gic_init_chip(*gic, dev, dev->of_node->name, false);
1360
1361 ret = gic_of_setup(*gic, dev->of_node);
1362 if (ret)
1363 return ret;
1364
1365 ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1366 if (ret) {
1367 gic_teardown(*gic);
1368 return ret;
1369 }
1370
1371 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1372
1373 return 0;
1374}
1375
1376static void __init gic_of_setup_kvm_info(struct device_node *node)
1377{
1378 int ret;
1379 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1380 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1381
1382 gic_v2_kvm_info.type = GIC_V2;
1383
1384 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1385 if (!gic_v2_kvm_info.maint_irq)
1386 return;
1387
1388 ret = of_address_to_resource(node, 2, vctrl_res);
1389 if (ret)
1390 return;
1391
1392 ret = of_address_to_resource(node, 3, vcpu_res);
1393 if (ret)
1394 return;
1395
1396 gic_set_kvm_info(&gic_v2_kvm_info);
1397}
1398
1399int __init
1400gic_of_init(struct device_node *node, struct device_node *parent)
1401{
1402 struct gic_chip_data *gic;
1403 int irq, ret;
1404
1405 if (WARN_ON(!node))
1406 return -ENODEV;
1407
1408 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1409 return -EINVAL;
1410
1411 gic = &gic_data[gic_cnt];
1412
1413 ret = gic_of_setup(gic, node);
1414 if (ret)
1415 return ret;
1416
1417 /*
1418 * Disable split EOI/Deactivate if either HYP is not available
1419 * or the CPU interface is too small.
1420 */
1421 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1422 static_key_slow_dec(&supports_deactivate);
1423
1424 ret = __gic_init_bases(gic, -1, &node->fwnode);
1425 if (ret) {
1426 gic_teardown(gic);
1427 return ret;
1428 }
1429
1430 if (!gic_cnt) {
1431 gic_init_physaddr(node);
1432 gic_of_setup_kvm_info(node);
1433 }
1434
1435 if (parent) {
1436 irq = irq_of_parse_and_map(node, 0);
1437 gic_cascade_irq(gic_cnt, irq);
1438 }
1439
1440 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1441 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1442
1443 gic_cnt++;
1444 return 0;
1445}
1446IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1447IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1448IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1449IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1450IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1451IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1452IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1453IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1454IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1455#else
1456int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1457{
1458 return -ENOTSUPP;
1459}
1460#endif
1461
1462#ifdef CONFIG_ACPI
1463static struct
1464{
1465 phys_addr_t cpu_phys_base;
1466 u32 maint_irq;
1467 int maint_irq_mode;
1468 phys_addr_t vctrl_base;
1469 phys_addr_t vcpu_base;
1470} acpi_data __initdata;
1471
1472static int __init
1473gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1474 const unsigned long end)
1475{
1476 struct acpi_madt_generic_interrupt *processor;
1477 phys_addr_t gic_cpu_base;
1478 static int cpu_base_assigned;
1479
1480 processor = (struct acpi_madt_generic_interrupt *)header;
1481
1482 if (BAD_MADT_GICC_ENTRY(processor, end))
1483 return -EINVAL;
1484
1485 /*
1486 * There is no support for non-banked GICv1/2 register in ACPI spec.
1487 * All CPU interface addresses have to be the same.
1488 */
1489 gic_cpu_base = processor->base_address;
1490 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1491 return -EINVAL;
1492
1493 acpi_data.cpu_phys_base = gic_cpu_base;
1494 acpi_data.maint_irq = processor->vgic_interrupt;
1495 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1496 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1497 acpi_data.vctrl_base = processor->gich_base_address;
1498 acpi_data.vcpu_base = processor->gicv_base_address;
1499
1500 cpu_base_assigned = 1;
1501 return 0;
1502}
1503
1504/* The things you have to do to just *count* something... */
1505static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1506 const unsigned long end)
1507{
1508 return 0;
1509}
1510
1511static bool __init acpi_gic_redist_is_present(void)
1512{
1513 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1514 acpi_dummy_func, 0) > 0;
1515}
1516
1517static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1518 struct acpi_probe_entry *ape)
1519{
1520 struct acpi_madt_generic_distributor *dist;
1521 dist = (struct acpi_madt_generic_distributor *)header;
1522
1523 return (dist->version == ape->driver_data &&
1524 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1525 !acpi_gic_redist_is_present()));
1526}
1527
1528#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1529#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1530#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1531#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1532
1533static void __init gic_acpi_setup_kvm_info(void)
1534{
1535 int irq;
1536 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1537 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1538
1539 gic_v2_kvm_info.type = GIC_V2;
1540
1541 if (!acpi_data.vctrl_base)
1542 return;
1543
1544 vctrl_res->flags = IORESOURCE_MEM;
1545 vctrl_res->start = acpi_data.vctrl_base;
1546 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1547
1548 if (!acpi_data.vcpu_base)
1549 return;
1550
1551 vcpu_res->flags = IORESOURCE_MEM;
1552 vcpu_res->start = acpi_data.vcpu_base;
1553 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1554
1555 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1556 acpi_data.maint_irq_mode,
1557 ACPI_ACTIVE_HIGH);
1558 if (irq <= 0)
1559 return;
1560
1561 gic_v2_kvm_info.maint_irq = irq;
1562
1563 gic_set_kvm_info(&gic_v2_kvm_info);
1564}
1565
1566static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1567 const unsigned long end)
1568{
1569 struct acpi_madt_generic_distributor *dist;
1570 struct fwnode_handle *domain_handle;
1571 struct gic_chip_data *gic = &gic_data[0];
1572 int count, ret;
1573
1574 /* Collect CPU base addresses */
1575 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1576 gic_acpi_parse_madt_cpu, 0);
1577 if (count <= 0) {
1578 pr_err("No valid GICC entries exist\n");
1579 return -EINVAL;
1580 }
1581
1582 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1583 if (!gic->raw_cpu_base) {
1584 pr_err("Unable to map GICC registers\n");
1585 return -ENOMEM;
1586 }
1587
1588 dist = (struct acpi_madt_generic_distributor *)header;
1589 gic->raw_dist_base = ioremap(dist->base_address,
1590 ACPI_GICV2_DIST_MEM_SIZE);
1591 if (!gic->raw_dist_base) {
1592 pr_err("Unable to map GICD registers\n");
1593 gic_teardown(gic);
1594 return -ENOMEM;
1595 }
1596
1597 /*
1598 * Disable split EOI/Deactivate if HYP is not available. ACPI
1599 * guarantees that we'll always have a GICv2, so the CPU
1600 * interface will always be the right size.
1601 */
1602 if (!is_hyp_mode_available())
1603 static_key_slow_dec(&supports_deactivate);
1604
1605 /*
1606 * Initialize GIC instance zero (no multi-GIC support).
1607 */
1608 domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base);
1609 if (!domain_handle) {
1610 pr_err("Unable to allocate domain handle\n");
1611 gic_teardown(gic);
1612 return -ENOMEM;
1613 }
1614
1615 ret = __gic_init_bases(gic, -1, domain_handle);
1616 if (ret) {
1617 pr_err("Failed to initialise GIC\n");
1618 irq_domain_free_fwnode(domain_handle);
1619 gic_teardown(gic);
1620 return ret;
1621 }
1622
1623 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1624
1625 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1626 gicv2m_init(NULL, gic_data[0].domain);
1627
1628 gic_acpi_setup_kvm_info();
1629
1630 return 0;
1631}
1632IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1633 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1634 gic_v2_acpi_init);
1635IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1636 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1637 gic_v2_acpi_init);
1638#endif