| 1 | /* |
| 2 | * Copyright (C) 2008 Maarten Maathuis. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining |
| 6 | * a copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sublicense, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the |
| 14 | * next paragraph) shall be included in all copies or substantial |
| 15 | * portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| 21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| 22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include <drm/drmP.h> |
| 28 | #include <drm/drm_crtc_helper.h> |
| 29 | |
| 30 | #include "nouveau_reg.h" |
| 31 | #include "nouveau_drm.h" |
| 32 | #include "nouveau_dma.h" |
| 33 | #include "nouveau_gem.h" |
| 34 | #include "nouveau_hw.h" |
| 35 | #include "nouveau_encoder.h" |
| 36 | #include "nouveau_crtc.h" |
| 37 | #include "nouveau_connector.h" |
| 38 | #include "nv50_display.h" |
| 39 | |
| 40 | #include <subdev/clock.h> |
| 41 | |
| 42 | static void |
| 43 | nv50_crtc_lut_load(struct drm_crtc *crtc) |
| 44 | { |
| 45 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
| 46 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 47 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); |
| 48 | int i; |
| 49 | |
| 50 | NV_DEBUG(drm, "\n"); |
| 51 | |
| 52 | for (i = 0; i < 256; i++) { |
| 53 | writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0); |
| 54 | writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2); |
| 55 | writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4); |
| 56 | } |
| 57 | |
| 58 | if (nv_crtc->lut.depth == 30) { |
| 59 | writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0); |
| 60 | writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2); |
| 61 | writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4); |
| 62 | } |
| 63 | } |
| 64 | |
| 65 | int |
| 66 | nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked) |
| 67 | { |
| 68 | struct drm_device *dev = nv_crtc->base.dev; |
| 69 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 70 | struct nouveau_channel *evo = nv50_display(dev)->master; |
| 71 | int index = nv_crtc->index, ret; |
| 72 | |
| 73 | NV_DEBUG(drm, "index %d\n", nv_crtc->index); |
| 74 | NV_DEBUG(drm, "%s\n", blanked ? "blanked" : "unblanked"); |
| 75 | |
| 76 | if (blanked) { |
| 77 | nv_crtc->cursor.hide(nv_crtc, false); |
| 78 | |
| 79 | ret = RING_SPACE(evo, nv_device(drm->device)->chipset != 0x50 ? 7 : 5); |
| 80 | if (ret) { |
| 81 | NV_ERROR(drm, "no space while blanking crtc\n"); |
| 82 | return ret; |
| 83 | } |
| 84 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); |
| 85 | OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK); |
| 86 | OUT_RING(evo, 0); |
| 87 | if (nv_device(drm->device)->chipset != 0x50) { |
| 88 | BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); |
| 89 | OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE); |
| 90 | } |
| 91 | |
| 92 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); |
| 93 | OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE); |
| 94 | } else { |
| 95 | if (nv_crtc->cursor.visible) |
| 96 | nv_crtc->cursor.show(nv_crtc, false); |
| 97 | else |
| 98 | nv_crtc->cursor.hide(nv_crtc, false); |
| 99 | |
| 100 | ret = RING_SPACE(evo, nv_device(drm->device)->chipset != 0x50 ? 10 : 8); |
| 101 | if (ret) { |
| 102 | NV_ERROR(drm, "no space while unblanking crtc\n"); |
| 103 | return ret; |
| 104 | } |
| 105 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); |
| 106 | OUT_RING(evo, nv_crtc->lut.depth == 8 ? |
| 107 | NV50_EVO_CRTC_CLUT_MODE_OFF : |
| 108 | NV50_EVO_CRTC_CLUT_MODE_ON); |
| 109 | OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8); |
| 110 | if (nv_device(drm->device)->chipset != 0x50) { |
| 111 | BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); |
| 112 | OUT_RING(evo, NvEvoVRAM); |
| 113 | } |
| 114 | |
| 115 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2); |
| 116 | OUT_RING(evo, nv_crtc->fb.offset >> 8); |
| 117 | OUT_RING(evo, 0); |
| 118 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); |
| 119 | if (nv_device(drm->device)->chipset != 0x50) |
| 120 | if (nv_crtc->fb.tile_flags == 0x7a00 || |
| 121 | nv_crtc->fb.tile_flags == 0xfe00) |
| 122 | OUT_RING(evo, NvEvoFB32); |
| 123 | else |
| 124 | if (nv_crtc->fb.tile_flags == 0x7000) |
| 125 | OUT_RING(evo, NvEvoFB16); |
| 126 | else |
| 127 | OUT_RING(evo, NvEvoVRAM_LP); |
| 128 | else |
| 129 | OUT_RING(evo, NvEvoVRAM_LP); |
| 130 | } |
| 131 | |
| 132 | nv_crtc->fb.blanked = blanked; |
| 133 | return 0; |
| 134 | } |
| 135 | |
| 136 | static int |
| 137 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
| 138 | { |
| 139 | struct nouveau_channel *evo = nv50_display(nv_crtc->base.dev)->master; |
| 140 | struct nouveau_connector *nv_connector; |
| 141 | struct drm_connector *connector; |
| 142 | int head = nv_crtc->index, ret; |
| 143 | u32 mode = 0x00; |
| 144 | |
| 145 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
| 146 | connector = &nv_connector->base; |
| 147 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { |
| 148 | if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3) |
| 149 | mode = DITHERING_MODE_DYNAMIC2X2; |
| 150 | } else { |
| 151 | mode = nv_connector->dithering_mode; |
| 152 | } |
| 153 | |
| 154 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { |
| 155 | if (connector->display_info.bpc >= 8) |
| 156 | mode |= DITHERING_DEPTH_8BPC; |
| 157 | } else { |
| 158 | mode |= nv_connector->dithering_depth; |
| 159 | } |
| 160 | |
| 161 | ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); |
| 162 | if (ret == 0) { |
| 163 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(head, DITHER_CTRL), 1); |
| 164 | OUT_RING (evo, mode); |
| 165 | if (update) { |
| 166 | BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); |
| 167 | OUT_RING (evo, 0); |
| 168 | FIRE_RING (evo); |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | return ret; |
| 173 | } |
| 174 | |
| 175 | static int |
| 176 | nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) |
| 177 | { |
| 178 | struct drm_device *dev = nv_crtc->base.dev; |
| 179 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 180 | struct nouveau_channel *evo = nv50_display(dev)->master; |
| 181 | int ret; |
| 182 | int adj; |
| 183 | u32 hue, vib; |
| 184 | |
| 185 | NV_DEBUG(drm, "vibrance = %i, hue = %i\n", |
| 186 | nv_crtc->color_vibrance, nv_crtc->vibrant_hue); |
| 187 | |
| 188 | ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); |
| 189 | if (ret) { |
| 190 | NV_ERROR(drm, "no space while setting color vibrance\n"); |
| 191 | return ret; |
| 192 | } |
| 193 | |
| 194 | adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; |
| 195 | vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; |
| 196 | |
| 197 | hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; |
| 198 | |
| 199 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1); |
| 200 | OUT_RING (evo, (hue << 20) | (vib << 8)); |
| 201 | |
| 202 | if (update) { |
| 203 | BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); |
| 204 | OUT_RING (evo, 0); |
| 205 | FIRE_RING (evo); |
| 206 | } |
| 207 | |
| 208 | return 0; |
| 209 | } |
| 210 | |
| 211 | struct nouveau_connector * |
| 212 | nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc) |
| 213 | { |
| 214 | struct drm_device *dev = nv_crtc->base.dev; |
| 215 | struct drm_connector *connector; |
| 216 | struct drm_crtc *crtc = to_drm_crtc(nv_crtc); |
| 217 | |
| 218 | /* The safest approach is to find an encoder with the right crtc, that |
| 219 | * is also linked to a connector. */ |
| 220 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 221 | if (connector->encoder) |
| 222 | if (connector->encoder->crtc == crtc) |
| 223 | return nouveau_connector(connector); |
| 224 | } |
| 225 | |
| 226 | return NULL; |
| 227 | } |
| 228 | |
| 229 | static int |
| 230 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
| 231 | { |
| 232 | struct nouveau_connector *nv_connector; |
| 233 | struct drm_crtc *crtc = &nv_crtc->base; |
| 234 | struct drm_device *dev = crtc->dev; |
| 235 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 236 | struct nouveau_channel *evo = nv50_display(dev)->master; |
| 237 | struct drm_display_mode *umode = &crtc->mode; |
| 238 | struct drm_display_mode *omode; |
| 239 | int scaling_mode, ret; |
| 240 | u32 ctrl = 0, oX, oY; |
| 241 | |
| 242 | NV_DEBUG(drm, "\n"); |
| 243 | |
| 244 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
| 245 | if (!nv_connector || !nv_connector->native_mode) { |
| 246 | NV_ERROR(drm, "no native mode, forcing panel scaling\n"); |
| 247 | scaling_mode = DRM_MODE_SCALE_NONE; |
| 248 | } else { |
| 249 | scaling_mode = nv_connector->scaling_mode; |
| 250 | } |
| 251 | |
| 252 | /* start off at the resolution we programmed the crtc for, this |
| 253 | * effectively handles NONE/FULL scaling |
| 254 | */ |
| 255 | if (scaling_mode != DRM_MODE_SCALE_NONE) |
| 256 | omode = nv_connector->native_mode; |
| 257 | else |
| 258 | omode = umode; |
| 259 | |
| 260 | oX = omode->hdisplay; |
| 261 | oY = omode->vdisplay; |
| 262 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 263 | oY *= 2; |
| 264 | |
| 265 | /* add overscan compensation if necessary, will keep the aspect |
| 266 | * ratio the same as the backend mode unless overridden by the |
| 267 | * user setting both hborder and vborder properties. |
| 268 | */ |
| 269 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || |
| 270 | (nv_connector->underscan == UNDERSCAN_AUTO && |
| 271 | nv_connector->edid && |
| 272 | drm_detect_hdmi_monitor(nv_connector->edid)))) { |
| 273 | u32 bX = nv_connector->underscan_hborder; |
| 274 | u32 bY = nv_connector->underscan_vborder; |
| 275 | u32 aspect = (oY << 19) / oX; |
| 276 | |
| 277 | if (bX) { |
| 278 | oX -= (bX * 2); |
| 279 | if (bY) oY -= (bY * 2); |
| 280 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; |
| 281 | } else { |
| 282 | oX -= (oX >> 4) + 32; |
| 283 | if (bY) oY -= (bY * 2); |
| 284 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | /* handle CENTER/ASPECT scaling, taking into account the areas |
| 289 | * removed already for overscan compensation |
| 290 | */ |
| 291 | switch (scaling_mode) { |
| 292 | case DRM_MODE_SCALE_CENTER: |
| 293 | oX = min((u32)umode->hdisplay, oX); |
| 294 | oY = min((u32)umode->vdisplay, oY); |
| 295 | /* fall-through */ |
| 296 | case DRM_MODE_SCALE_ASPECT: |
| 297 | if (oY < oX) { |
| 298 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; |
| 299 | oX = ((oY * aspect) + (aspect / 2)) >> 19; |
| 300 | } else { |
| 301 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; |
| 302 | oY = ((oX * aspect) + (aspect / 2)) >> 19; |
| 303 | } |
| 304 | break; |
| 305 | default: |
| 306 | break; |
| 307 | } |
| 308 | |
| 309 | if (umode->hdisplay != oX || umode->vdisplay != oY || |
| 310 | umode->flags & DRM_MODE_FLAG_INTERLACE || |
| 311 | umode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 312 | ctrl |= NV50_EVO_CRTC_SCALE_CTRL_ACTIVE; |
| 313 | |
| 314 | ret = RING_SPACE(evo, 5); |
| 315 | if (ret) |
| 316 | return ret; |
| 317 | |
| 318 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1); |
| 319 | OUT_RING (evo, ctrl); |
| 320 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2); |
| 321 | OUT_RING (evo, oY << 16 | oX); |
| 322 | OUT_RING (evo, oY << 16 | oX); |
| 323 | |
| 324 | if (update) { |
| 325 | nv50_display_flip_stop(crtc); |
| 326 | nv50_display_sync(dev); |
| 327 | nv50_display_flip_next(crtc, crtc->fb, NULL); |
| 328 | } |
| 329 | |
| 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | int |
| 334 | nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) |
| 335 | { |
| 336 | struct nouveau_device *device = nouveau_dev(dev); |
| 337 | struct nouveau_clock *clk = nouveau_clock(device); |
| 338 | |
| 339 | return clk->pll_set(clk, PLL_VPLL0 + head, pclk); |
| 340 | } |
| 341 | |
| 342 | static void |
| 343 | nv50_crtc_destroy(struct drm_crtc *crtc) |
| 344 | { |
| 345 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 346 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
| 347 | |
| 348 | NV_DEBUG(drm, "\n"); |
| 349 | |
| 350 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
| 351 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
| 352 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
| 353 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
| 354 | drm_crtc_cleanup(&nv_crtc->base); |
| 355 | kfree(nv_crtc); |
| 356 | } |
| 357 | |
| 358 | int |
| 359 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
| 360 | uint32_t buffer_handle, uint32_t width, uint32_t height) |
| 361 | { |
| 362 | struct drm_device *dev = crtc->dev; |
| 363 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 364 | struct nouveau_bo *cursor = NULL; |
| 365 | struct drm_gem_object *gem; |
| 366 | int ret = 0, i; |
| 367 | |
| 368 | if (!buffer_handle) { |
| 369 | nv_crtc->cursor.hide(nv_crtc, true); |
| 370 | return 0; |
| 371 | } |
| 372 | |
| 373 | if (width != 64 || height != 64) |
| 374 | return -EINVAL; |
| 375 | |
| 376 | gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); |
| 377 | if (!gem) |
| 378 | return -ENOENT; |
| 379 | cursor = nouveau_gem_object(gem); |
| 380 | |
| 381 | ret = nouveau_bo_map(cursor); |
| 382 | if (ret) |
| 383 | goto out; |
| 384 | |
| 385 | /* The simple will do for now. */ |
| 386 | for (i = 0; i < 64 * 64; i++) |
| 387 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i)); |
| 388 | |
| 389 | nouveau_bo_unmap(cursor); |
| 390 | |
| 391 | nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset); |
| 392 | nv_crtc->cursor.show(nv_crtc, true); |
| 393 | |
| 394 | out: |
| 395 | drm_gem_object_unreference_unlocked(gem); |
| 396 | return ret; |
| 397 | } |
| 398 | |
| 399 | int |
| 400 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 401 | { |
| 402 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 403 | |
| 404 | nv_crtc->cursor.set_pos(nv_crtc, x, y); |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | static void |
| 409 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
| 410 | uint32_t start, uint32_t size) |
| 411 | { |
| 412 | int end = (start + size > 256) ? 256 : start + size, i; |
| 413 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 414 | |
| 415 | for (i = start; i < end; i++) { |
| 416 | nv_crtc->lut.r[i] = r[i]; |
| 417 | nv_crtc->lut.g[i] = g[i]; |
| 418 | nv_crtc->lut.b[i] = b[i]; |
| 419 | } |
| 420 | |
| 421 | /* We need to know the depth before we upload, but it's possible to |
| 422 | * get called before a framebuffer is bound. If this is the case, |
| 423 | * mark the lut values as dirty by setting depth==0, and it'll be |
| 424 | * uploaded on the first mode_set_base() |
| 425 | */ |
| 426 | if (!nv_crtc->base.fb) { |
| 427 | nv_crtc->lut.depth = 0; |
| 428 | return; |
| 429 | } |
| 430 | |
| 431 | nv50_crtc_lut_load(crtc); |
| 432 | } |
| 433 | |
| 434 | static void |
| 435 | nv50_crtc_save(struct drm_crtc *crtc) |
| 436 | { |
| 437 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
| 438 | NV_ERROR(drm, "!!\n"); |
| 439 | } |
| 440 | |
| 441 | static void |
| 442 | nv50_crtc_restore(struct drm_crtc *crtc) |
| 443 | { |
| 444 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
| 445 | NV_ERROR(drm, "!!\n"); |
| 446 | } |
| 447 | |
| 448 | static const struct drm_crtc_funcs nv50_crtc_funcs = { |
| 449 | .save = nv50_crtc_save, |
| 450 | .restore = nv50_crtc_restore, |
| 451 | .cursor_set = nv50_crtc_cursor_set, |
| 452 | .cursor_move = nv50_crtc_cursor_move, |
| 453 | .gamma_set = nv50_crtc_gamma_set, |
| 454 | .set_config = drm_crtc_helper_set_config, |
| 455 | .page_flip = nouveau_crtc_page_flip, |
| 456 | .destroy = nv50_crtc_destroy, |
| 457 | }; |
| 458 | |
| 459 | static void |
| 460 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 461 | { |
| 462 | } |
| 463 | |
| 464 | static void |
| 465 | nv50_crtc_prepare(struct drm_crtc *crtc) |
| 466 | { |
| 467 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 468 | struct drm_device *dev = crtc->dev; |
| 469 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 470 | |
| 471 | NV_DEBUG(drm, "index %d\n", nv_crtc->index); |
| 472 | |
| 473 | nv50_display_flip_stop(crtc); |
| 474 | drm_vblank_pre_modeset(dev, nv_crtc->index); |
| 475 | nv50_crtc_blank(nv_crtc, true); |
| 476 | } |
| 477 | |
| 478 | static void |
| 479 | nv50_crtc_commit(struct drm_crtc *crtc) |
| 480 | { |
| 481 | struct drm_device *dev = crtc->dev; |
| 482 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 483 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 484 | |
| 485 | NV_DEBUG(drm, "index %d\n", nv_crtc->index); |
| 486 | |
| 487 | nv50_crtc_blank(nv_crtc, false); |
| 488 | drm_vblank_post_modeset(dev, nv_crtc->index); |
| 489 | nv50_display_sync(dev); |
| 490 | nv50_display_flip_next(crtc, crtc->fb, NULL); |
| 491 | } |
| 492 | |
| 493 | static bool |
| 494 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, |
| 495 | struct drm_display_mode *adjusted_mode) |
| 496 | { |
| 497 | return true; |
| 498 | } |
| 499 | |
| 500 | static int |
| 501 | nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, |
| 502 | struct drm_framebuffer *passed_fb, |
| 503 | int x, int y, bool atomic) |
| 504 | { |
| 505 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 506 | struct drm_device *dev = nv_crtc->base.dev; |
| 507 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 508 | struct nouveau_channel *evo = nv50_display(dev)->master; |
| 509 | struct drm_framebuffer *drm_fb; |
| 510 | struct nouveau_framebuffer *fb; |
| 511 | int ret; |
| 512 | |
| 513 | NV_DEBUG(drm, "index %d\n", nv_crtc->index); |
| 514 | |
| 515 | /* no fb bound */ |
| 516 | if (!atomic && !crtc->fb) { |
| 517 | NV_DEBUG(drm, "No FB bound\n"); |
| 518 | return 0; |
| 519 | } |
| 520 | |
| 521 | /* If atomic, we want to switch to the fb we were passed, so |
| 522 | * now we update pointers to do that. (We don't pin; just |
| 523 | * assume we're already pinned and update the base address.) |
| 524 | */ |
| 525 | if (atomic) { |
| 526 | drm_fb = passed_fb; |
| 527 | fb = nouveau_framebuffer(passed_fb); |
| 528 | } else { |
| 529 | drm_fb = crtc->fb; |
| 530 | fb = nouveau_framebuffer(crtc->fb); |
| 531 | /* If not atomic, we can go ahead and pin, and unpin the |
| 532 | * old fb we were passed. |
| 533 | */ |
| 534 | ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM); |
| 535 | if (ret) |
| 536 | return ret; |
| 537 | |
| 538 | if (passed_fb) { |
| 539 | struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb); |
| 540 | nouveau_bo_unpin(ofb->nvbo); |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | nv_crtc->fb.offset = fb->nvbo->bo.offset; |
| 545 | nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo); |
| 546 | nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8; |
| 547 | if (!nv_crtc->fb.blanked && nv_device(drm->device)->chipset != 0x50) { |
| 548 | ret = RING_SPACE(evo, 2); |
| 549 | if (ret) |
| 550 | return ret; |
| 551 | |
| 552 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1); |
| 553 | OUT_RING (evo, fb->r_dma); |
| 554 | } |
| 555 | |
| 556 | ret = RING_SPACE(evo, 12); |
| 557 | if (ret) |
| 558 | return ret; |
| 559 | |
| 560 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5); |
| 561 | OUT_RING (evo, nv_crtc->fb.offset >> 8); |
| 562 | OUT_RING (evo, 0); |
| 563 | OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width); |
| 564 | OUT_RING (evo, fb->r_pitch); |
| 565 | OUT_RING (evo, fb->r_format); |
| 566 | |
| 567 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1); |
| 568 | OUT_RING (evo, fb->base.depth == 8 ? |
| 569 | NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON); |
| 570 | |
| 571 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1); |
| 572 | OUT_RING (evo, (y << 16) | x); |
| 573 | |
| 574 | if (nv_crtc->lut.depth != fb->base.depth) { |
| 575 | nv_crtc->lut.depth = fb->base.depth; |
| 576 | nv50_crtc_lut_load(crtc); |
| 577 | } |
| 578 | |
| 579 | return 0; |
| 580 | } |
| 581 | |
| 582 | static int |
| 583 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, |
| 584 | struct drm_display_mode *mode, int x, int y, |
| 585 | struct drm_framebuffer *old_fb) |
| 586 | { |
| 587 | struct drm_device *dev = crtc->dev; |
| 588 | struct nouveau_channel *evo = nv50_display(dev)->master; |
| 589 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 590 | u32 head = nv_crtc->index * 0x400; |
| 591 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
| 592 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; |
| 593 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; |
| 594 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; |
| 595 | u32 vblan2e = 0, vblan2s = 1; |
| 596 | int ret; |
| 597 | |
| 598 | /* hw timing description looks like this: |
| 599 | * |
| 600 | * <sync> <back porch> <---------display---------> <front porch> |
| 601 | * ______ |
| 602 | * |____________|---------------------------|____________| |
| 603 | * |
| 604 | * ^ synce ^ blanke ^ blanks ^ active |
| 605 | * |
| 606 | * interlaced modes also have 2 additional values pointing at the end |
| 607 | * and start of the next field's blanking period. |
| 608 | */ |
| 609 | |
| 610 | hactive = mode->htotal; |
| 611 | hsynce = mode->hsync_end - mode->hsync_start - 1; |
| 612 | hbackp = mode->htotal - mode->hsync_end; |
| 613 | hblanke = hsynce + hbackp; |
| 614 | hfrontp = mode->hsync_start - mode->hdisplay; |
| 615 | hblanks = mode->htotal - hfrontp - 1; |
| 616 | |
| 617 | vactive = mode->vtotal * vscan / ilace; |
| 618 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; |
| 619 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; |
| 620 | vblanke = vsynce + vbackp; |
| 621 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; |
| 622 | vblanks = vactive - vfrontp - 1; |
| 623 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 624 | vblan2e = vactive + vsynce + vbackp; |
| 625 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); |
| 626 | vactive = (vactive * 2) + 1; |
| 627 | } |
| 628 | |
| 629 | ret = RING_SPACE(evo, 18); |
| 630 | if (ret == 0) { |
| 631 | BEGIN_NV04(evo, 0, 0x0804 + head, 2); |
| 632 | OUT_RING (evo, 0x00800000 | mode->clock); |
| 633 | OUT_RING (evo, (ilace == 2) ? 2 : 0); |
| 634 | BEGIN_NV04(evo, 0, 0x0810 + head, 6); |
| 635 | OUT_RING (evo, 0x00000000); /* border colour */ |
| 636 | OUT_RING (evo, (vactive << 16) | hactive); |
| 637 | OUT_RING (evo, ( vsynce << 16) | hsynce); |
| 638 | OUT_RING (evo, (vblanke << 16) | hblanke); |
| 639 | OUT_RING (evo, (vblanks << 16) | hblanks); |
| 640 | OUT_RING (evo, (vblan2e << 16) | vblan2s); |
| 641 | BEGIN_NV04(evo, 0, 0x082c + head, 1); |
| 642 | OUT_RING (evo, 0x00000000); |
| 643 | BEGIN_NV04(evo, 0, 0x0900 + head, 1); |
| 644 | OUT_RING (evo, 0x00000311); /* makes sync channel work */ |
| 645 | BEGIN_NV04(evo, 0, 0x08c8 + head, 1); |
| 646 | OUT_RING (evo, (umode->vdisplay << 16) | umode->hdisplay); |
| 647 | BEGIN_NV04(evo, 0, 0x08d4 + head, 1); |
| 648 | OUT_RING (evo, 0x00000000); /* screen position */ |
| 649 | } |
| 650 | |
| 651 | nv_crtc->set_dither(nv_crtc, false); |
| 652 | nv_crtc->set_scale(nv_crtc, false); |
| 653 | nv_crtc->set_color_vibrance(nv_crtc, false); |
| 654 | |
| 655 | return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false); |
| 656 | } |
| 657 | |
| 658 | static int |
| 659 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
| 660 | struct drm_framebuffer *old_fb) |
| 661 | { |
| 662 | int ret; |
| 663 | |
| 664 | nv50_display_flip_stop(crtc); |
| 665 | ret = nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false); |
| 666 | if (ret) |
| 667 | return ret; |
| 668 | |
| 669 | ret = nv50_display_sync(crtc->dev); |
| 670 | if (ret) |
| 671 | return ret; |
| 672 | |
| 673 | return nv50_display_flip_next(crtc, crtc->fb, NULL); |
| 674 | } |
| 675 | |
| 676 | static int |
| 677 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, |
| 678 | struct drm_framebuffer *fb, |
| 679 | int x, int y, enum mode_set_atomic state) |
| 680 | { |
| 681 | int ret; |
| 682 | |
| 683 | nv50_display_flip_stop(crtc); |
| 684 | ret = nv50_crtc_do_mode_set_base(crtc, fb, x, y, true); |
| 685 | if (ret) |
| 686 | return ret; |
| 687 | |
| 688 | return nv50_display_sync(crtc->dev); |
| 689 | } |
| 690 | |
| 691 | static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = { |
| 692 | .dpms = nv50_crtc_dpms, |
| 693 | .prepare = nv50_crtc_prepare, |
| 694 | .commit = nv50_crtc_commit, |
| 695 | .mode_fixup = nv50_crtc_mode_fixup, |
| 696 | .mode_set = nv50_crtc_mode_set, |
| 697 | .mode_set_base = nv50_crtc_mode_set_base, |
| 698 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, |
| 699 | .load_lut = nv50_crtc_lut_load, |
| 700 | }; |
| 701 | |
| 702 | int |
| 703 | nv50_crtc_create(struct drm_device *dev, int index) |
| 704 | { |
| 705 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 706 | struct nouveau_crtc *nv_crtc = NULL; |
| 707 | int ret, i; |
| 708 | |
| 709 | NV_DEBUG(drm, "\n"); |
| 710 | |
| 711 | nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); |
| 712 | if (!nv_crtc) |
| 713 | return -ENOMEM; |
| 714 | |
| 715 | nv_crtc->index = index; |
| 716 | nv_crtc->set_dither = nv50_crtc_set_dither; |
| 717 | nv_crtc->set_scale = nv50_crtc_set_scale; |
| 718 | nv_crtc->set_color_vibrance = nv50_crtc_set_color_vibrance; |
| 719 | nv_crtc->color_vibrance = 50; |
| 720 | nv_crtc->vibrant_hue = 0; |
| 721 | nv_crtc->lut.depth = 0; |
| 722 | for (i = 0; i < 256; i++) { |
| 723 | nv_crtc->lut.r[i] = i << 8; |
| 724 | nv_crtc->lut.g[i] = i << 8; |
| 725 | nv_crtc->lut.b[i] = i << 8; |
| 726 | } |
| 727 | |
| 728 | drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs); |
| 729 | drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs); |
| 730 | drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); |
| 731 | |
| 732 | ret = nouveau_bo_new(dev, 4096, 0x100, TTM_PL_FLAG_VRAM, |
| 733 | 0, 0x0000, NULL, &nv_crtc->lut.nvbo); |
| 734 | if (!ret) { |
| 735 | ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM); |
| 736 | if (!ret) |
| 737 | ret = nouveau_bo_map(nv_crtc->lut.nvbo); |
| 738 | if (ret) |
| 739 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
| 740 | } |
| 741 | |
| 742 | if (ret) |
| 743 | goto out; |
| 744 | |
| 745 | |
| 746 | ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, |
| 747 | 0, 0x0000, NULL, &nv_crtc->cursor.nvbo); |
| 748 | if (!ret) { |
| 749 | ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); |
| 750 | if (!ret) |
| 751 | ret = nouveau_bo_map(nv_crtc->cursor.nvbo); |
| 752 | if (ret) |
| 753 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
| 754 | } |
| 755 | |
| 756 | if (ret) |
| 757 | goto out; |
| 758 | |
| 759 | nv50_cursor_init(nv_crtc); |
| 760 | out: |
| 761 | if (ret) |
| 762 | nv50_crtc_destroy(&nv_crtc->base); |
| 763 | return ret; |
| 764 | } |