| 1 | #include "drmP.h" |
| 2 | #include "drm.h" |
| 3 | #include "nouveau_drv.h" |
| 4 | #include "nouveau_drm.h" |
| 5 | |
| 6 | int |
| 7 | nv1a_fb_vram_init(struct drm_device *dev) |
| 8 | { |
| 9 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 10 | struct pci_dev *bridge; |
| 11 | uint32_t mem, mib; |
| 12 | |
| 13 | bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); |
| 14 | if (!bridge) { |
| 15 | NV_ERROR(dev, "no bridge device\n"); |
| 16 | return 0; |
| 17 | } |
| 18 | |
| 19 | if (dev_priv->chipset == 0x1a) { |
| 20 | pci_read_config_dword(bridge, 0x7c, &mem); |
| 21 | mib = ((mem >> 6) & 31) + 1; |
| 22 | } else { |
| 23 | pci_read_config_dword(bridge, 0x84, &mem); |
| 24 | mib = ((mem >> 4) & 127) + 1; |
| 25 | } |
| 26 | |
| 27 | dev_priv->vram_size = mib * 1024 * 1024; |
| 28 | return 0; |
| 29 | } |
| 30 | |
| 31 | int |
| 32 | nv10_fb_vram_init(struct drm_device *dev) |
| 33 | { |
| 34 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 35 | u32 fifo_data = nv_rd32(dev, NV04_PFB_FIFO_DATA); |
| 36 | |
| 37 | dev_priv->vram_size = fifo_data & NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; |
| 38 | if (dev_priv->card_type < NV_20) { |
| 39 | u32 cfg0 = nv_rd32(dev, 0x100200); |
| 40 | if (cfg0 & 0x00000001) |
| 41 | dev_priv->vram_type = NV_MEM_TYPE_DDR1; |
| 42 | else |
| 43 | dev_priv->vram_type = NV_MEM_TYPE_SDRAM; |
| 44 | } |
| 45 | |
| 46 | return 0; |
| 47 | } |
| 48 | |
| 49 | static struct drm_mm_node * |
| 50 | nv20_fb_alloc_tag(struct drm_device *dev, uint32_t size) |
| 51 | { |
| 52 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 53 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; |
| 54 | struct drm_mm_node *mem; |
| 55 | int ret; |
| 56 | |
| 57 | ret = drm_mm_pre_get(&pfb->tag_heap); |
| 58 | if (ret) |
| 59 | return NULL; |
| 60 | |
| 61 | spin_lock(&dev_priv->tile.lock); |
| 62 | mem = drm_mm_search_free(&pfb->tag_heap, size, 0, 0); |
| 63 | if (mem) |
| 64 | mem = drm_mm_get_block_atomic(mem, size, 0); |
| 65 | spin_unlock(&dev_priv->tile.lock); |
| 66 | |
| 67 | return mem; |
| 68 | } |
| 69 | |
| 70 | static void |
| 71 | nv20_fb_free_tag(struct drm_device *dev, struct drm_mm_node *mem) |
| 72 | { |
| 73 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 74 | |
| 75 | spin_lock(&dev_priv->tile.lock); |
| 76 | drm_mm_put_block(mem); |
| 77 | spin_unlock(&dev_priv->tile.lock); |
| 78 | } |
| 79 | |
| 80 | void |
| 81 | nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr, |
| 82 | uint32_t size, uint32_t pitch, uint32_t flags) |
| 83 | { |
| 84 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 85 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; |
| 86 | int bpp = (flags & NOUVEAU_GEM_TILE_32BPP ? 32 : 16); |
| 87 | |
| 88 | tile->addr = addr; |
| 89 | tile->limit = max(1u, addr + size) - 1; |
| 90 | tile->pitch = pitch; |
| 91 | |
| 92 | if (dev_priv->card_type == NV_20) { |
| 93 | if (flags & NOUVEAU_GEM_TILE_ZETA) { |
| 94 | /* |
| 95 | * Allocate some of the on-die tag memory, |
| 96 | * used to store Z compression meta-data (most |
| 97 | * likely just a bitmap determining if a given |
| 98 | * tile is compressed or not). |
| 99 | */ |
| 100 | tile->tag_mem = nv20_fb_alloc_tag(dev, size / 256); |
| 101 | |
| 102 | if (tile->tag_mem) { |
| 103 | /* Enable Z compression */ |
| 104 | if (dev_priv->chipset >= 0x25) |
| 105 | tile->zcomp = tile->tag_mem->start | |
| 106 | (bpp == 16 ? |
| 107 | NV25_PFB_ZCOMP_MODE_16 : |
| 108 | NV25_PFB_ZCOMP_MODE_32); |
| 109 | else |
| 110 | tile->zcomp = tile->tag_mem->start | |
| 111 | NV20_PFB_ZCOMP_EN | |
| 112 | (bpp == 16 ? 0 : |
| 113 | NV20_PFB_ZCOMP_MODE_32); |
| 114 | } |
| 115 | |
| 116 | tile->addr |= 3; |
| 117 | } else { |
| 118 | tile->addr |= 1; |
| 119 | } |
| 120 | |
| 121 | } else { |
| 122 | tile->addr |= 1 << 31; |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | void |
| 127 | nv10_fb_free_tile_region(struct drm_device *dev, int i) |
| 128 | { |
| 129 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 130 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; |
| 131 | |
| 132 | if (tile->tag_mem) { |
| 133 | nv20_fb_free_tag(dev, tile->tag_mem); |
| 134 | tile->tag_mem = NULL; |
| 135 | } |
| 136 | |
| 137 | tile->addr = tile->limit = tile->pitch = tile->zcomp = 0; |
| 138 | } |
| 139 | |
| 140 | void |
| 141 | nv10_fb_set_tile_region(struct drm_device *dev, int i) |
| 142 | { |
| 143 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 144 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; |
| 145 | |
| 146 | nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit); |
| 147 | nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch); |
| 148 | nv_wr32(dev, NV10_PFB_TILE(i), tile->addr); |
| 149 | |
| 150 | if (dev_priv->card_type == NV_20) |
| 151 | nv_wr32(dev, NV20_PFB_ZCOMP(i), tile->zcomp); |
| 152 | } |
| 153 | |
| 154 | int |
| 155 | nv10_fb_init(struct drm_device *dev) |
| 156 | { |
| 157 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 158 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; |
| 159 | int i; |
| 160 | |
| 161 | pfb->num_tiles = NV10_PFB_TILE__SIZE; |
| 162 | |
| 163 | if (dev_priv->card_type == NV_20) |
| 164 | drm_mm_init(&pfb->tag_heap, 0, |
| 165 | (dev_priv->chipset >= 0x25 ? |
| 166 | 64 * 1024 : 32 * 1024)); |
| 167 | |
| 168 | /* Turn all the tiling regions off. */ |
| 169 | for (i = 0; i < pfb->num_tiles; i++) |
| 170 | pfb->set_tile_region(dev, i); |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | void |
| 176 | nv10_fb_takedown(struct drm_device *dev) |
| 177 | { |
| 178 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 179 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; |
| 180 | int i; |
| 181 | |
| 182 | for (i = 0; i < pfb->num_tiles; i++) |
| 183 | pfb->free_tile_region(dev, i); |
| 184 | |
| 185 | if (dev_priv->card_type == NV_20) |
| 186 | drm_mm_takedown(&pfb->tag_heap); |
| 187 | } |