| 1 | /* |
| 2 | * edac_mc kernel module |
| 3 | * (C) 2005, 2006 Linux Networx (http://lnxi.com) |
| 4 | * This file may be distributed under the terms of the |
| 5 | * GNU General Public License. |
| 6 | * |
| 7 | * Written by Thayne Harbaugh |
| 8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. |
| 9 | * http://www.anime.net/~goemon/linux-ecc/ |
| 10 | * |
| 11 | * Modified by Dave Peterson and Doug Thompson |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/proc_fs.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/smp.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/sysctl.h> |
| 22 | #include <linux/highmem.h> |
| 23 | #include <linux/timer.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/jiffies.h> |
| 26 | #include <linux/spinlock.h> |
| 27 | #include <linux/list.h> |
| 28 | #include <linux/ctype.h> |
| 29 | #include <linux/edac.h> |
| 30 | #include <linux/bitops.h> |
| 31 | #include <asm/uaccess.h> |
| 32 | #include <asm/page.h> |
| 33 | #include <asm/edac.h> |
| 34 | #include "edac_core.h" |
| 35 | #include "edac_module.h" |
| 36 | |
| 37 | #define CREATE_TRACE_POINTS |
| 38 | #define TRACE_INCLUDE_PATH ../../include/ras |
| 39 | #include <ras/ras_event.h> |
| 40 | |
| 41 | /* lock to memory controller's control array */ |
| 42 | static DEFINE_MUTEX(mem_ctls_mutex); |
| 43 | static LIST_HEAD(mc_devices); |
| 44 | |
| 45 | /* |
| 46 | * Used to lock EDAC MC to just one module, avoiding two drivers e. g. |
| 47 | * apei/ghes and i7core_edac to be used at the same time. |
| 48 | */ |
| 49 | static void const *edac_mc_owner; |
| 50 | |
| 51 | static struct bus_type mc_bus[EDAC_MAX_MCS]; |
| 52 | |
| 53 | unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf, |
| 54 | unsigned len) |
| 55 | { |
| 56 | struct mem_ctl_info *mci = dimm->mci; |
| 57 | int i, n, count = 0; |
| 58 | char *p = buf; |
| 59 | |
| 60 | for (i = 0; i < mci->n_layers; i++) { |
| 61 | n = snprintf(p, len, "%s %d ", |
| 62 | edac_layer_name[mci->layers[i].type], |
| 63 | dimm->location[i]); |
| 64 | p += n; |
| 65 | len -= n; |
| 66 | count += n; |
| 67 | if (!len) |
| 68 | break; |
| 69 | } |
| 70 | |
| 71 | return count; |
| 72 | } |
| 73 | |
| 74 | #ifdef CONFIG_EDAC_DEBUG |
| 75 | |
| 76 | static void edac_mc_dump_channel(struct rank_info *chan) |
| 77 | { |
| 78 | edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx); |
| 79 | edac_dbg(4, " channel = %p\n", chan); |
| 80 | edac_dbg(4, " channel->csrow = %p\n", chan->csrow); |
| 81 | edac_dbg(4, " channel->dimm = %p\n", chan->dimm); |
| 82 | } |
| 83 | |
| 84 | static void edac_mc_dump_dimm(struct dimm_info *dimm, int number) |
| 85 | { |
| 86 | char location[80]; |
| 87 | |
| 88 | edac_dimm_info_location(dimm, location, sizeof(location)); |
| 89 | |
| 90 | edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", |
| 91 | dimm->mci->csbased ? "rank" : "dimm", |
| 92 | number, location, dimm->csrow, dimm->cschannel); |
| 93 | edac_dbg(4, " dimm = %p\n", dimm); |
| 94 | edac_dbg(4, " dimm->label = '%s'\n", dimm->label); |
| 95 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); |
| 96 | edac_dbg(4, " dimm->grain = %d\n", dimm->grain); |
| 97 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); |
| 98 | } |
| 99 | |
| 100 | static void edac_mc_dump_csrow(struct csrow_info *csrow) |
| 101 | { |
| 102 | edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx); |
| 103 | edac_dbg(4, " csrow = %p\n", csrow); |
| 104 | edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page); |
| 105 | edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page); |
| 106 | edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask); |
| 107 | edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels); |
| 108 | edac_dbg(4, " csrow->channels = %p\n", csrow->channels); |
| 109 | edac_dbg(4, " csrow->mci = %p\n", csrow->mci); |
| 110 | } |
| 111 | |
| 112 | static void edac_mc_dump_mci(struct mem_ctl_info *mci) |
| 113 | { |
| 114 | edac_dbg(3, "\tmci = %p\n", mci); |
| 115 | edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap); |
| 116 | edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap); |
| 117 | edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap); |
| 118 | edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check); |
| 119 | edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n", |
| 120 | mci->nr_csrows, mci->csrows); |
| 121 | edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n", |
| 122 | mci->tot_dimms, mci->dimms); |
| 123 | edac_dbg(3, "\tdev = %p\n", mci->pdev); |
| 124 | edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n", |
| 125 | mci->mod_name, mci->ctl_name); |
| 126 | edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info); |
| 127 | } |
| 128 | |
| 129 | #endif /* CONFIG_EDAC_DEBUG */ |
| 130 | |
| 131 | /* |
| 132 | * keep those in sync with the enum mem_type |
| 133 | */ |
| 134 | const char *edac_mem_types[] = { |
| 135 | "Empty csrow", |
| 136 | "Reserved csrow type", |
| 137 | "Unknown csrow type", |
| 138 | "Fast page mode RAM", |
| 139 | "Extended data out RAM", |
| 140 | "Burst Extended data out RAM", |
| 141 | "Single data rate SDRAM", |
| 142 | "Registered single data rate SDRAM", |
| 143 | "Double data rate SDRAM", |
| 144 | "Registered Double data rate SDRAM", |
| 145 | "Rambus DRAM", |
| 146 | "Unbuffered DDR2 RAM", |
| 147 | "Fully buffered DDR2", |
| 148 | "Registered DDR2 RAM", |
| 149 | "Rambus XDR", |
| 150 | "Unbuffered DDR3 RAM", |
| 151 | "Registered DDR3 RAM", |
| 152 | }; |
| 153 | EXPORT_SYMBOL_GPL(edac_mem_types); |
| 154 | |
| 155 | /** |
| 156 | * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation |
| 157 | * @p: pointer to a pointer with the memory offset to be used. At |
| 158 | * return, this will be incremented to point to the next offset |
| 159 | * @size: Size of the data structure to be reserved |
| 160 | * @n_elems: Number of elements that should be reserved |
| 161 | * |
| 162 | * If 'size' is a constant, the compiler will optimize this whole function |
| 163 | * down to either a no-op or the addition of a constant to the value of '*p'. |
| 164 | * |
| 165 | * The 'p' pointer is absolutely needed to keep the proper advancing |
| 166 | * further in memory to the proper offsets when allocating the struct along |
| 167 | * with its embedded structs, as edac_device_alloc_ctl_info() does it |
| 168 | * above, for example. |
| 169 | * |
| 170 | * At return, the pointer 'p' will be incremented to be used on a next call |
| 171 | * to this function. |
| 172 | */ |
| 173 | void *edac_align_ptr(void **p, unsigned size, int n_elems) |
| 174 | { |
| 175 | unsigned align, r; |
| 176 | void *ptr = *p; |
| 177 | |
| 178 | *p += size * n_elems; |
| 179 | |
| 180 | /* |
| 181 | * 'p' can possibly be an unaligned item X such that sizeof(X) is |
| 182 | * 'size'. Adjust 'p' so that its alignment is at least as |
| 183 | * stringent as what the compiler would provide for X and return |
| 184 | * the aligned result. |
| 185 | * Here we assume that the alignment of a "long long" is the most |
| 186 | * stringent alignment that the compiler will ever provide by default. |
| 187 | * As far as I know, this is a reasonable assumption. |
| 188 | */ |
| 189 | if (size > sizeof(long)) |
| 190 | align = sizeof(long long); |
| 191 | else if (size > sizeof(int)) |
| 192 | align = sizeof(long); |
| 193 | else if (size > sizeof(short)) |
| 194 | align = sizeof(int); |
| 195 | else if (size > sizeof(char)) |
| 196 | align = sizeof(short); |
| 197 | else |
| 198 | return (char *)ptr; |
| 199 | |
| 200 | r = (unsigned long)p % align; |
| 201 | |
| 202 | if (r == 0) |
| 203 | return (char *)ptr; |
| 204 | |
| 205 | *p += align - r; |
| 206 | |
| 207 | return (void *)(((unsigned long)ptr) + align - r); |
| 208 | } |
| 209 | |
| 210 | static void _edac_mc_free(struct mem_ctl_info *mci) |
| 211 | { |
| 212 | int i, chn, row; |
| 213 | struct csrow_info *csr; |
| 214 | const unsigned int tot_dimms = mci->tot_dimms; |
| 215 | const unsigned int tot_channels = mci->num_cschannel; |
| 216 | const unsigned int tot_csrows = mci->nr_csrows; |
| 217 | |
| 218 | if (mci->dimms) { |
| 219 | for (i = 0; i < tot_dimms; i++) |
| 220 | kfree(mci->dimms[i]); |
| 221 | kfree(mci->dimms); |
| 222 | } |
| 223 | if (mci->csrows) { |
| 224 | for (row = 0; row < tot_csrows; row++) { |
| 225 | csr = mci->csrows[row]; |
| 226 | if (csr) { |
| 227 | if (csr->channels) { |
| 228 | for (chn = 0; chn < tot_channels; chn++) |
| 229 | kfree(csr->channels[chn]); |
| 230 | kfree(csr->channels); |
| 231 | } |
| 232 | kfree(csr); |
| 233 | } |
| 234 | } |
| 235 | kfree(mci->csrows); |
| 236 | } |
| 237 | kfree(mci); |
| 238 | } |
| 239 | |
| 240 | /** |
| 241 | * edac_mc_alloc: Allocate and partially fill a struct mem_ctl_info structure |
| 242 | * @mc_num: Memory controller number |
| 243 | * @n_layers: Number of MC hierarchy layers |
| 244 | * layers: Describes each layer as seen by the Memory Controller |
| 245 | * @size_pvt: size of private storage needed |
| 246 | * |
| 247 | * |
| 248 | * Everything is kmalloc'ed as one big chunk - more efficient. |
| 249 | * Only can be used if all structures have the same lifetime - otherwise |
| 250 | * you have to allocate and initialize your own structures. |
| 251 | * |
| 252 | * Use edac_mc_free() to free mc structures allocated by this function. |
| 253 | * |
| 254 | * NOTE: drivers handle multi-rank memories in different ways: in some |
| 255 | * drivers, one multi-rank memory stick is mapped as one entry, while, in |
| 256 | * others, a single multi-rank memory stick would be mapped into several |
| 257 | * entries. Currently, this function will allocate multiple struct dimm_info |
| 258 | * on such scenarios, as grouping the multiple ranks require drivers change. |
| 259 | * |
| 260 | * Returns: |
| 261 | * On failure: NULL |
| 262 | * On success: struct mem_ctl_info pointer |
| 263 | */ |
| 264 | struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, |
| 265 | unsigned n_layers, |
| 266 | struct edac_mc_layer *layers, |
| 267 | unsigned sz_pvt) |
| 268 | { |
| 269 | struct mem_ctl_info *mci; |
| 270 | struct edac_mc_layer *layer; |
| 271 | struct csrow_info *csr; |
| 272 | struct rank_info *chan; |
| 273 | struct dimm_info *dimm; |
| 274 | u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; |
| 275 | unsigned pos[EDAC_MAX_LAYERS]; |
| 276 | unsigned size, tot_dimms = 1, count = 1; |
| 277 | unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0; |
| 278 | void *pvt, *p, *ptr = NULL; |
| 279 | int i, j, row, chn, n, len, off; |
| 280 | bool per_rank = false; |
| 281 | |
| 282 | BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0); |
| 283 | /* |
| 284 | * Calculate the total amount of dimms and csrows/cschannels while |
| 285 | * in the old API emulation mode |
| 286 | */ |
| 287 | for (i = 0; i < n_layers; i++) { |
| 288 | tot_dimms *= layers[i].size; |
| 289 | if (layers[i].is_virt_csrow) |
| 290 | tot_csrows *= layers[i].size; |
| 291 | else |
| 292 | tot_channels *= layers[i].size; |
| 293 | |
| 294 | if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) |
| 295 | per_rank = true; |
| 296 | } |
| 297 | |
| 298 | /* Figure out the offsets of the various items from the start of an mc |
| 299 | * structure. We want the alignment of each item to be at least as |
| 300 | * stringent as what the compiler would provide if we could simply |
| 301 | * hardcode everything into a single struct. |
| 302 | */ |
| 303 | mci = edac_align_ptr(&ptr, sizeof(*mci), 1); |
| 304 | layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); |
| 305 | for (i = 0; i < n_layers; i++) { |
| 306 | count *= layers[i].size; |
| 307 | edac_dbg(4, "errcount layer %d size %d\n", i, count); |
| 308 | ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); |
| 309 | ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); |
| 310 | tot_errcount += 2 * count; |
| 311 | } |
| 312 | |
| 313 | edac_dbg(4, "allocating %d error counters\n", tot_errcount); |
| 314 | pvt = edac_align_ptr(&ptr, sz_pvt, 1); |
| 315 | size = ((unsigned long)pvt) + sz_pvt; |
| 316 | |
| 317 | edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", |
| 318 | size, |
| 319 | tot_dimms, |
| 320 | per_rank ? "ranks" : "dimms", |
| 321 | tot_csrows * tot_channels); |
| 322 | |
| 323 | mci = kzalloc(size, GFP_KERNEL); |
| 324 | if (mci == NULL) |
| 325 | return NULL; |
| 326 | |
| 327 | /* Adjust pointers so they point within the memory we just allocated |
| 328 | * rather than an imaginary chunk of memory located at address 0. |
| 329 | */ |
| 330 | layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); |
| 331 | for (i = 0; i < n_layers; i++) { |
| 332 | mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i])); |
| 333 | mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i])); |
| 334 | } |
| 335 | pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; |
| 336 | |
| 337 | /* setup index and various internal pointers */ |
| 338 | mci->mc_idx = mc_num; |
| 339 | mci->tot_dimms = tot_dimms; |
| 340 | mci->pvt_info = pvt; |
| 341 | mci->n_layers = n_layers; |
| 342 | mci->layers = layer; |
| 343 | memcpy(mci->layers, layers, sizeof(*layer) * n_layers); |
| 344 | mci->nr_csrows = tot_csrows; |
| 345 | mci->num_cschannel = tot_channels; |
| 346 | mci->csbased = per_rank; |
| 347 | |
| 348 | /* |
| 349 | * Alocate and fill the csrow/channels structs |
| 350 | */ |
| 351 | mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); |
| 352 | if (!mci->csrows) |
| 353 | goto error; |
| 354 | for (row = 0; row < tot_csrows; row++) { |
| 355 | csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); |
| 356 | if (!csr) |
| 357 | goto error; |
| 358 | mci->csrows[row] = csr; |
| 359 | csr->csrow_idx = row; |
| 360 | csr->mci = mci; |
| 361 | csr->nr_channels = tot_channels; |
| 362 | csr->channels = kcalloc(tot_channels, sizeof(*csr->channels), |
| 363 | GFP_KERNEL); |
| 364 | if (!csr->channels) |
| 365 | goto error; |
| 366 | |
| 367 | for (chn = 0; chn < tot_channels; chn++) { |
| 368 | chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL); |
| 369 | if (!chan) |
| 370 | goto error; |
| 371 | csr->channels[chn] = chan; |
| 372 | chan->chan_idx = chn; |
| 373 | chan->csrow = csr; |
| 374 | } |
| 375 | } |
| 376 | |
| 377 | /* |
| 378 | * Allocate and fill the dimm structs |
| 379 | */ |
| 380 | mci->dimms = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); |
| 381 | if (!mci->dimms) |
| 382 | goto error; |
| 383 | |
| 384 | memset(&pos, 0, sizeof(pos)); |
| 385 | row = 0; |
| 386 | chn = 0; |
| 387 | for (i = 0; i < tot_dimms; i++) { |
| 388 | chan = mci->csrows[row]->channels[chn]; |
| 389 | off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); |
| 390 | if (off < 0 || off >= tot_dimms) { |
| 391 | edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n"); |
| 392 | goto error; |
| 393 | } |
| 394 | |
| 395 | dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); |
| 396 | if (!dimm) |
| 397 | goto error; |
| 398 | mci->dimms[off] = dimm; |
| 399 | dimm->mci = mci; |
| 400 | |
| 401 | /* |
| 402 | * Copy DIMM location and initialize it. |
| 403 | */ |
| 404 | len = sizeof(dimm->label); |
| 405 | p = dimm->label; |
| 406 | n = snprintf(p, len, "mc#%u", mc_num); |
| 407 | p += n; |
| 408 | len -= n; |
| 409 | for (j = 0; j < n_layers; j++) { |
| 410 | n = snprintf(p, len, "%s#%u", |
| 411 | edac_layer_name[layers[j].type], |
| 412 | pos[j]); |
| 413 | p += n; |
| 414 | len -= n; |
| 415 | dimm->location[j] = pos[j]; |
| 416 | |
| 417 | if (len <= 0) |
| 418 | break; |
| 419 | } |
| 420 | |
| 421 | /* Link it to the csrows old API data */ |
| 422 | chan->dimm = dimm; |
| 423 | dimm->csrow = row; |
| 424 | dimm->cschannel = chn; |
| 425 | |
| 426 | /* Increment csrow location */ |
| 427 | if (layers[0].is_virt_csrow) { |
| 428 | chn++; |
| 429 | if (chn == tot_channels) { |
| 430 | chn = 0; |
| 431 | row++; |
| 432 | } |
| 433 | } else { |
| 434 | row++; |
| 435 | if (row == tot_csrows) { |
| 436 | row = 0; |
| 437 | chn++; |
| 438 | } |
| 439 | } |
| 440 | |
| 441 | /* Increment dimm location */ |
| 442 | for (j = n_layers - 1; j >= 0; j--) { |
| 443 | pos[j]++; |
| 444 | if (pos[j] < layers[j].size) |
| 445 | break; |
| 446 | pos[j] = 0; |
| 447 | } |
| 448 | } |
| 449 | |
| 450 | mci->op_state = OP_ALLOC; |
| 451 | |
| 452 | return mci; |
| 453 | |
| 454 | error: |
| 455 | _edac_mc_free(mci); |
| 456 | |
| 457 | return NULL; |
| 458 | } |
| 459 | EXPORT_SYMBOL_GPL(edac_mc_alloc); |
| 460 | |
| 461 | /** |
| 462 | * edac_mc_free |
| 463 | * 'Free' a previously allocated 'mci' structure |
| 464 | * @mci: pointer to a struct mem_ctl_info structure |
| 465 | */ |
| 466 | void edac_mc_free(struct mem_ctl_info *mci) |
| 467 | { |
| 468 | edac_dbg(1, "\n"); |
| 469 | |
| 470 | /* If we're not yet registered with sysfs free only what was allocated |
| 471 | * in edac_mc_alloc(). |
| 472 | */ |
| 473 | if (!device_is_registered(&mci->dev)) { |
| 474 | _edac_mc_free(mci); |
| 475 | return; |
| 476 | } |
| 477 | |
| 478 | /* the mci instance is freed here, when the sysfs object is dropped */ |
| 479 | edac_unregister_sysfs(mci); |
| 480 | } |
| 481 | EXPORT_SYMBOL_GPL(edac_mc_free); |
| 482 | |
| 483 | |
| 484 | /** |
| 485 | * find_mci_by_dev |
| 486 | * |
| 487 | * scan list of controllers looking for the one that manages |
| 488 | * the 'dev' device |
| 489 | * @dev: pointer to a struct device related with the MCI |
| 490 | */ |
| 491 | struct mem_ctl_info *find_mci_by_dev(struct device *dev) |
| 492 | { |
| 493 | struct mem_ctl_info *mci; |
| 494 | struct list_head *item; |
| 495 | |
| 496 | edac_dbg(3, "\n"); |
| 497 | |
| 498 | list_for_each(item, &mc_devices) { |
| 499 | mci = list_entry(item, struct mem_ctl_info, link); |
| 500 | |
| 501 | if (mci->pdev == dev) |
| 502 | return mci; |
| 503 | } |
| 504 | |
| 505 | return NULL; |
| 506 | } |
| 507 | EXPORT_SYMBOL_GPL(find_mci_by_dev); |
| 508 | |
| 509 | /* |
| 510 | * handler for EDAC to check if NMI type handler has asserted interrupt |
| 511 | */ |
| 512 | static int edac_mc_assert_error_check_and_clear(void) |
| 513 | { |
| 514 | int old_state; |
| 515 | |
| 516 | if (edac_op_state == EDAC_OPSTATE_POLL) |
| 517 | return 1; |
| 518 | |
| 519 | old_state = edac_err_assert; |
| 520 | edac_err_assert = 0; |
| 521 | |
| 522 | return old_state; |
| 523 | } |
| 524 | |
| 525 | /* |
| 526 | * edac_mc_workq_function |
| 527 | * performs the operation scheduled by a workq request |
| 528 | */ |
| 529 | static void edac_mc_workq_function(struct work_struct *work_req) |
| 530 | { |
| 531 | struct delayed_work *d_work = to_delayed_work(work_req); |
| 532 | struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work); |
| 533 | |
| 534 | mutex_lock(&mem_ctls_mutex); |
| 535 | |
| 536 | /* if this control struct has movd to offline state, we are done */ |
| 537 | if (mci->op_state == OP_OFFLINE) { |
| 538 | mutex_unlock(&mem_ctls_mutex); |
| 539 | return; |
| 540 | } |
| 541 | |
| 542 | /* Only poll controllers that are running polled and have a check */ |
| 543 | if (edac_mc_assert_error_check_and_clear() && (mci->edac_check != NULL)) |
| 544 | mci->edac_check(mci); |
| 545 | |
| 546 | mutex_unlock(&mem_ctls_mutex); |
| 547 | |
| 548 | /* Reschedule */ |
| 549 | queue_delayed_work(edac_workqueue, &mci->work, |
| 550 | msecs_to_jiffies(edac_mc_get_poll_msec())); |
| 551 | } |
| 552 | |
| 553 | /* |
| 554 | * edac_mc_workq_setup |
| 555 | * initialize a workq item for this mci |
| 556 | * passing in the new delay period in msec |
| 557 | * |
| 558 | * locking model: |
| 559 | * |
| 560 | * called with the mem_ctls_mutex held |
| 561 | */ |
| 562 | static void edac_mc_workq_setup(struct mem_ctl_info *mci, unsigned msec, |
| 563 | bool init) |
| 564 | { |
| 565 | edac_dbg(0, "\n"); |
| 566 | |
| 567 | /* if this instance is not in the POLL state, then simply return */ |
| 568 | if (mci->op_state != OP_RUNNING_POLL) |
| 569 | return; |
| 570 | |
| 571 | if (init) |
| 572 | INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function); |
| 573 | |
| 574 | mod_delayed_work(edac_workqueue, &mci->work, msecs_to_jiffies(msec)); |
| 575 | } |
| 576 | |
| 577 | /* |
| 578 | * edac_mc_workq_teardown |
| 579 | * stop the workq processing on this mci |
| 580 | * |
| 581 | * locking model: |
| 582 | * |
| 583 | * called WITHOUT lock held |
| 584 | */ |
| 585 | static void edac_mc_workq_teardown(struct mem_ctl_info *mci) |
| 586 | { |
| 587 | int status; |
| 588 | |
| 589 | if (mci->op_state != OP_RUNNING_POLL) |
| 590 | return; |
| 591 | |
| 592 | status = cancel_delayed_work(&mci->work); |
| 593 | if (status == 0) { |
| 594 | edac_dbg(0, "not canceled, flush the queue\n"); |
| 595 | |
| 596 | /* workq instance might be running, wait for it */ |
| 597 | flush_workqueue(edac_workqueue); |
| 598 | } |
| 599 | } |
| 600 | |
| 601 | /* |
| 602 | * edac_mc_reset_delay_period(unsigned long value) |
| 603 | * |
| 604 | * user space has updated our poll period value, need to |
| 605 | * reset our workq delays |
| 606 | */ |
| 607 | void edac_mc_reset_delay_period(unsigned long value) |
| 608 | { |
| 609 | struct mem_ctl_info *mci; |
| 610 | struct list_head *item; |
| 611 | |
| 612 | mutex_lock(&mem_ctls_mutex); |
| 613 | |
| 614 | list_for_each(item, &mc_devices) { |
| 615 | mci = list_entry(item, struct mem_ctl_info, link); |
| 616 | |
| 617 | edac_mc_workq_setup(mci, value, false); |
| 618 | } |
| 619 | |
| 620 | mutex_unlock(&mem_ctls_mutex); |
| 621 | } |
| 622 | |
| 623 | |
| 624 | |
| 625 | /* Return 0 on success, 1 on failure. |
| 626 | * Before calling this function, caller must |
| 627 | * assign a unique value to mci->mc_idx. |
| 628 | * |
| 629 | * locking model: |
| 630 | * |
| 631 | * called with the mem_ctls_mutex lock held |
| 632 | */ |
| 633 | static int add_mc_to_global_list(struct mem_ctl_info *mci) |
| 634 | { |
| 635 | struct list_head *item, *insert_before; |
| 636 | struct mem_ctl_info *p; |
| 637 | |
| 638 | insert_before = &mc_devices; |
| 639 | |
| 640 | p = find_mci_by_dev(mci->pdev); |
| 641 | if (unlikely(p != NULL)) |
| 642 | goto fail0; |
| 643 | |
| 644 | list_for_each(item, &mc_devices) { |
| 645 | p = list_entry(item, struct mem_ctl_info, link); |
| 646 | |
| 647 | if (p->mc_idx >= mci->mc_idx) { |
| 648 | if (unlikely(p->mc_idx == mci->mc_idx)) |
| 649 | goto fail1; |
| 650 | |
| 651 | insert_before = item; |
| 652 | break; |
| 653 | } |
| 654 | } |
| 655 | |
| 656 | list_add_tail_rcu(&mci->link, insert_before); |
| 657 | atomic_inc(&edac_handlers); |
| 658 | return 0; |
| 659 | |
| 660 | fail0: |
| 661 | edac_printk(KERN_WARNING, EDAC_MC, |
| 662 | "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev), |
| 663 | edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx); |
| 664 | return 1; |
| 665 | |
| 666 | fail1: |
| 667 | edac_printk(KERN_WARNING, EDAC_MC, |
| 668 | "bug in low-level driver: attempt to assign\n" |
| 669 | " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__); |
| 670 | return 1; |
| 671 | } |
| 672 | |
| 673 | static int del_mc_from_global_list(struct mem_ctl_info *mci) |
| 674 | { |
| 675 | int handlers = atomic_dec_return(&edac_handlers); |
| 676 | list_del_rcu(&mci->link); |
| 677 | |
| 678 | /* these are for safe removal of devices from global list while |
| 679 | * NMI handlers may be traversing list |
| 680 | */ |
| 681 | synchronize_rcu(); |
| 682 | INIT_LIST_HEAD(&mci->link); |
| 683 | |
| 684 | return handlers; |
| 685 | } |
| 686 | |
| 687 | /** |
| 688 | * edac_mc_find: Search for a mem_ctl_info structure whose index is 'idx'. |
| 689 | * |
| 690 | * If found, return a pointer to the structure. |
| 691 | * Else return NULL. |
| 692 | * |
| 693 | * Caller must hold mem_ctls_mutex. |
| 694 | */ |
| 695 | struct mem_ctl_info *edac_mc_find(int idx) |
| 696 | { |
| 697 | struct list_head *item; |
| 698 | struct mem_ctl_info *mci; |
| 699 | |
| 700 | list_for_each(item, &mc_devices) { |
| 701 | mci = list_entry(item, struct mem_ctl_info, link); |
| 702 | |
| 703 | if (mci->mc_idx >= idx) { |
| 704 | if (mci->mc_idx == idx) |
| 705 | return mci; |
| 706 | |
| 707 | break; |
| 708 | } |
| 709 | } |
| 710 | |
| 711 | return NULL; |
| 712 | } |
| 713 | EXPORT_SYMBOL(edac_mc_find); |
| 714 | |
| 715 | /** |
| 716 | * edac_mc_add_mc: Insert the 'mci' structure into the mci global list and |
| 717 | * create sysfs entries associated with mci structure |
| 718 | * @mci: pointer to the mci structure to be added to the list |
| 719 | * |
| 720 | * Return: |
| 721 | * 0 Success |
| 722 | * !0 Failure |
| 723 | */ |
| 724 | |
| 725 | /* FIXME - should a warning be printed if no error detection? correction? */ |
| 726 | int edac_mc_add_mc(struct mem_ctl_info *mci) |
| 727 | { |
| 728 | int ret = -EINVAL; |
| 729 | edac_dbg(0, "\n"); |
| 730 | |
| 731 | if (mci->mc_idx >= EDAC_MAX_MCS) { |
| 732 | pr_warn_once("Too many memory controllers: %d\n", mci->mc_idx); |
| 733 | return -ENODEV; |
| 734 | } |
| 735 | |
| 736 | #ifdef CONFIG_EDAC_DEBUG |
| 737 | if (edac_debug_level >= 3) |
| 738 | edac_mc_dump_mci(mci); |
| 739 | |
| 740 | if (edac_debug_level >= 4) { |
| 741 | int i; |
| 742 | |
| 743 | for (i = 0; i < mci->nr_csrows; i++) { |
| 744 | struct csrow_info *csrow = mci->csrows[i]; |
| 745 | u32 nr_pages = 0; |
| 746 | int j; |
| 747 | |
| 748 | for (j = 0; j < csrow->nr_channels; j++) |
| 749 | nr_pages += csrow->channels[j]->dimm->nr_pages; |
| 750 | if (!nr_pages) |
| 751 | continue; |
| 752 | edac_mc_dump_csrow(csrow); |
| 753 | for (j = 0; j < csrow->nr_channels; j++) |
| 754 | if (csrow->channels[j]->dimm->nr_pages) |
| 755 | edac_mc_dump_channel(csrow->channels[j]); |
| 756 | } |
| 757 | for (i = 0; i < mci->tot_dimms; i++) |
| 758 | if (mci->dimms[i]->nr_pages) |
| 759 | edac_mc_dump_dimm(mci->dimms[i], i); |
| 760 | } |
| 761 | #endif |
| 762 | mutex_lock(&mem_ctls_mutex); |
| 763 | |
| 764 | if (edac_mc_owner && edac_mc_owner != mci->mod_name) { |
| 765 | ret = -EPERM; |
| 766 | goto fail0; |
| 767 | } |
| 768 | |
| 769 | if (add_mc_to_global_list(mci)) |
| 770 | goto fail0; |
| 771 | |
| 772 | /* set load time so that error rate can be tracked */ |
| 773 | mci->start_time = jiffies; |
| 774 | |
| 775 | mci->bus = &mc_bus[mci->mc_idx]; |
| 776 | |
| 777 | if (edac_create_sysfs_mci_device(mci)) { |
| 778 | edac_mc_printk(mci, KERN_WARNING, |
| 779 | "failed to create sysfs device\n"); |
| 780 | goto fail1; |
| 781 | } |
| 782 | |
| 783 | /* If there IS a check routine, then we are running POLLED */ |
| 784 | if (mci->edac_check != NULL) { |
| 785 | /* This instance is NOW RUNNING */ |
| 786 | mci->op_state = OP_RUNNING_POLL; |
| 787 | |
| 788 | edac_mc_workq_setup(mci, edac_mc_get_poll_msec(), true); |
| 789 | } else { |
| 790 | mci->op_state = OP_RUNNING_INTERRUPT; |
| 791 | } |
| 792 | |
| 793 | /* Report action taken */ |
| 794 | edac_mc_printk(mci, KERN_INFO, "Giving out device to '%s' '%s':" |
| 795 | " DEV %s\n", mci->mod_name, mci->ctl_name, edac_dev_name(mci)); |
| 796 | |
| 797 | edac_mc_owner = mci->mod_name; |
| 798 | |
| 799 | mutex_unlock(&mem_ctls_mutex); |
| 800 | return 0; |
| 801 | |
| 802 | fail1: |
| 803 | del_mc_from_global_list(mci); |
| 804 | |
| 805 | fail0: |
| 806 | mutex_unlock(&mem_ctls_mutex); |
| 807 | return ret; |
| 808 | } |
| 809 | EXPORT_SYMBOL_GPL(edac_mc_add_mc); |
| 810 | |
| 811 | /** |
| 812 | * edac_mc_del_mc: Remove sysfs entries for specified mci structure and |
| 813 | * remove mci structure from global list |
| 814 | * @pdev: Pointer to 'struct device' representing mci structure to remove. |
| 815 | * |
| 816 | * Return pointer to removed mci structure, or NULL if device not found. |
| 817 | */ |
| 818 | struct mem_ctl_info *edac_mc_del_mc(struct device *dev) |
| 819 | { |
| 820 | struct mem_ctl_info *mci; |
| 821 | |
| 822 | edac_dbg(0, "\n"); |
| 823 | |
| 824 | mutex_lock(&mem_ctls_mutex); |
| 825 | |
| 826 | /* find the requested mci struct in the global list */ |
| 827 | mci = find_mci_by_dev(dev); |
| 828 | if (mci == NULL) { |
| 829 | mutex_unlock(&mem_ctls_mutex); |
| 830 | return NULL; |
| 831 | } |
| 832 | |
| 833 | if (!del_mc_from_global_list(mci)) |
| 834 | edac_mc_owner = NULL; |
| 835 | mutex_unlock(&mem_ctls_mutex); |
| 836 | |
| 837 | /* flush workq processes */ |
| 838 | edac_mc_workq_teardown(mci); |
| 839 | |
| 840 | /* marking MCI offline */ |
| 841 | mci->op_state = OP_OFFLINE; |
| 842 | |
| 843 | /* remove from sysfs */ |
| 844 | edac_remove_sysfs_mci_device(mci); |
| 845 | |
| 846 | edac_printk(KERN_INFO, EDAC_MC, |
| 847 | "Removed device %d for %s %s: DEV %s\n", mci->mc_idx, |
| 848 | mci->mod_name, mci->ctl_name, edac_dev_name(mci)); |
| 849 | |
| 850 | return mci; |
| 851 | } |
| 852 | EXPORT_SYMBOL_GPL(edac_mc_del_mc); |
| 853 | |
| 854 | static void edac_mc_scrub_block(unsigned long page, unsigned long offset, |
| 855 | u32 size) |
| 856 | { |
| 857 | struct page *pg; |
| 858 | void *virt_addr; |
| 859 | unsigned long flags = 0; |
| 860 | |
| 861 | edac_dbg(3, "\n"); |
| 862 | |
| 863 | /* ECC error page was not in our memory. Ignore it. */ |
| 864 | if (!pfn_valid(page)) |
| 865 | return; |
| 866 | |
| 867 | /* Find the actual page structure then map it and fix */ |
| 868 | pg = pfn_to_page(page); |
| 869 | |
| 870 | if (PageHighMem(pg)) |
| 871 | local_irq_save(flags); |
| 872 | |
| 873 | virt_addr = kmap_atomic(pg); |
| 874 | |
| 875 | /* Perform architecture specific atomic scrub operation */ |
| 876 | atomic_scrub(virt_addr + offset, size); |
| 877 | |
| 878 | /* Unmap and complete */ |
| 879 | kunmap_atomic(virt_addr); |
| 880 | |
| 881 | if (PageHighMem(pg)) |
| 882 | local_irq_restore(flags); |
| 883 | } |
| 884 | |
| 885 | /* FIXME - should return -1 */ |
| 886 | int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page) |
| 887 | { |
| 888 | struct csrow_info **csrows = mci->csrows; |
| 889 | int row, i, j, n; |
| 890 | |
| 891 | edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page); |
| 892 | row = -1; |
| 893 | |
| 894 | for (i = 0; i < mci->nr_csrows; i++) { |
| 895 | struct csrow_info *csrow = csrows[i]; |
| 896 | n = 0; |
| 897 | for (j = 0; j < csrow->nr_channels; j++) { |
| 898 | struct dimm_info *dimm = csrow->channels[j]->dimm; |
| 899 | n += dimm->nr_pages; |
| 900 | } |
| 901 | if (n == 0) |
| 902 | continue; |
| 903 | |
| 904 | edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n", |
| 905 | mci->mc_idx, |
| 906 | csrow->first_page, page, csrow->last_page, |
| 907 | csrow->page_mask); |
| 908 | |
| 909 | if ((page >= csrow->first_page) && |
| 910 | (page <= csrow->last_page) && |
| 911 | ((page & csrow->page_mask) == |
| 912 | (csrow->first_page & csrow->page_mask))) { |
| 913 | row = i; |
| 914 | break; |
| 915 | } |
| 916 | } |
| 917 | |
| 918 | if (row == -1) |
| 919 | edac_mc_printk(mci, KERN_ERR, |
| 920 | "could not look up page error address %lx\n", |
| 921 | (unsigned long)page); |
| 922 | |
| 923 | return row; |
| 924 | } |
| 925 | EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page); |
| 926 | |
| 927 | const char *edac_layer_name[] = { |
| 928 | [EDAC_MC_LAYER_BRANCH] = "branch", |
| 929 | [EDAC_MC_LAYER_CHANNEL] = "channel", |
| 930 | [EDAC_MC_LAYER_SLOT] = "slot", |
| 931 | [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", |
| 932 | [EDAC_MC_LAYER_ALL_MEM] = "memory", |
| 933 | }; |
| 934 | EXPORT_SYMBOL_GPL(edac_layer_name); |
| 935 | |
| 936 | static void edac_inc_ce_error(struct mem_ctl_info *mci, |
| 937 | bool enable_per_layer_report, |
| 938 | const int pos[EDAC_MAX_LAYERS], |
| 939 | const u16 count) |
| 940 | { |
| 941 | int i, index = 0; |
| 942 | |
| 943 | mci->ce_mc += count; |
| 944 | |
| 945 | if (!enable_per_layer_report) { |
| 946 | mci->ce_noinfo_count += count; |
| 947 | return; |
| 948 | } |
| 949 | |
| 950 | for (i = 0; i < mci->n_layers; i++) { |
| 951 | if (pos[i] < 0) |
| 952 | break; |
| 953 | index += pos[i]; |
| 954 | mci->ce_per_layer[i][index] += count; |
| 955 | |
| 956 | if (i < mci->n_layers - 1) |
| 957 | index *= mci->layers[i + 1].size; |
| 958 | } |
| 959 | } |
| 960 | |
| 961 | static void edac_inc_ue_error(struct mem_ctl_info *mci, |
| 962 | bool enable_per_layer_report, |
| 963 | const int pos[EDAC_MAX_LAYERS], |
| 964 | const u16 count) |
| 965 | { |
| 966 | int i, index = 0; |
| 967 | |
| 968 | mci->ue_mc += count; |
| 969 | |
| 970 | if (!enable_per_layer_report) { |
| 971 | mci->ue_noinfo_count += count; |
| 972 | return; |
| 973 | } |
| 974 | |
| 975 | for (i = 0; i < mci->n_layers; i++) { |
| 976 | if (pos[i] < 0) |
| 977 | break; |
| 978 | index += pos[i]; |
| 979 | mci->ue_per_layer[i][index] += count; |
| 980 | |
| 981 | if (i < mci->n_layers - 1) |
| 982 | index *= mci->layers[i + 1].size; |
| 983 | } |
| 984 | } |
| 985 | |
| 986 | static void edac_ce_error(struct mem_ctl_info *mci, |
| 987 | const u16 error_count, |
| 988 | const int pos[EDAC_MAX_LAYERS], |
| 989 | const char *msg, |
| 990 | const char *location, |
| 991 | const char *label, |
| 992 | const char *detail, |
| 993 | const char *other_detail, |
| 994 | const bool enable_per_layer_report, |
| 995 | const unsigned long page_frame_number, |
| 996 | const unsigned long offset_in_page, |
| 997 | long grain) |
| 998 | { |
| 999 | unsigned long remapped_page; |
| 1000 | char *msg_aux = ""; |
| 1001 | |
| 1002 | if (*msg) |
| 1003 | msg_aux = " "; |
| 1004 | |
| 1005 | if (edac_mc_get_log_ce()) { |
| 1006 | if (other_detail && *other_detail) |
| 1007 | edac_mc_printk(mci, KERN_WARNING, |
| 1008 | "%d CE %s%son %s (%s %s - %s)\n", |
| 1009 | error_count, msg, msg_aux, label, |
| 1010 | location, detail, other_detail); |
| 1011 | else |
| 1012 | edac_mc_printk(mci, KERN_WARNING, |
| 1013 | "%d CE %s%son %s (%s %s)\n", |
| 1014 | error_count, msg, msg_aux, label, |
| 1015 | location, detail); |
| 1016 | } |
| 1017 | edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count); |
| 1018 | |
| 1019 | if (mci->scrub_mode & SCRUB_SW_SRC) { |
| 1020 | /* |
| 1021 | * Some memory controllers (called MCs below) can remap |
| 1022 | * memory so that it is still available at a different |
| 1023 | * address when PCI devices map into memory. |
| 1024 | * MC's that can't do this, lose the memory where PCI |
| 1025 | * devices are mapped. This mapping is MC-dependent |
| 1026 | * and so we call back into the MC driver for it to |
| 1027 | * map the MC page to a physical (CPU) page which can |
| 1028 | * then be mapped to a virtual page - which can then |
| 1029 | * be scrubbed. |
| 1030 | */ |
| 1031 | remapped_page = mci->ctl_page_to_phys ? |
| 1032 | mci->ctl_page_to_phys(mci, page_frame_number) : |
| 1033 | page_frame_number; |
| 1034 | |
| 1035 | edac_mc_scrub_block(remapped_page, |
| 1036 | offset_in_page, grain); |
| 1037 | } |
| 1038 | } |
| 1039 | |
| 1040 | static void edac_ue_error(struct mem_ctl_info *mci, |
| 1041 | const u16 error_count, |
| 1042 | const int pos[EDAC_MAX_LAYERS], |
| 1043 | const char *msg, |
| 1044 | const char *location, |
| 1045 | const char *label, |
| 1046 | const char *detail, |
| 1047 | const char *other_detail, |
| 1048 | const bool enable_per_layer_report) |
| 1049 | { |
| 1050 | char *msg_aux = ""; |
| 1051 | |
| 1052 | if (*msg) |
| 1053 | msg_aux = " "; |
| 1054 | |
| 1055 | if (edac_mc_get_log_ue()) { |
| 1056 | if (other_detail && *other_detail) |
| 1057 | edac_mc_printk(mci, KERN_WARNING, |
| 1058 | "%d UE %s%son %s (%s %s - %s)\n", |
| 1059 | error_count, msg, msg_aux, label, |
| 1060 | location, detail, other_detail); |
| 1061 | else |
| 1062 | edac_mc_printk(mci, KERN_WARNING, |
| 1063 | "%d UE %s%son %s (%s %s)\n", |
| 1064 | error_count, msg, msg_aux, label, |
| 1065 | location, detail); |
| 1066 | } |
| 1067 | |
| 1068 | if (edac_mc_get_panic_on_ue()) { |
| 1069 | if (other_detail && *other_detail) |
| 1070 | panic("UE %s%son %s (%s%s - %s)\n", |
| 1071 | msg, msg_aux, label, location, detail, other_detail); |
| 1072 | else |
| 1073 | panic("UE %s%son %s (%s%s)\n", |
| 1074 | msg, msg_aux, label, location, detail); |
| 1075 | } |
| 1076 | |
| 1077 | edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count); |
| 1078 | } |
| 1079 | |
| 1080 | /** |
| 1081 | * edac_raw_mc_handle_error - reports a memory event to userspace without doing |
| 1082 | * anything to discover the error location |
| 1083 | * |
| 1084 | * @type: severity of the error (CE/UE/Fatal) |
| 1085 | * @mci: a struct mem_ctl_info pointer |
| 1086 | * @e: error description |
| 1087 | * |
| 1088 | * This raw function is used internally by edac_mc_handle_error(). It should |
| 1089 | * only be called directly when the hardware error come directly from BIOS, |
| 1090 | * like in the case of APEI GHES driver. |
| 1091 | */ |
| 1092 | void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, |
| 1093 | struct mem_ctl_info *mci, |
| 1094 | struct edac_raw_error_desc *e) |
| 1095 | { |
| 1096 | char detail[80]; |
| 1097 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; |
| 1098 | |
| 1099 | /* Memory type dependent details about the error */ |
| 1100 | if (type == HW_EVENT_ERR_CORRECTED) { |
| 1101 | snprintf(detail, sizeof(detail), |
| 1102 | "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", |
| 1103 | e->page_frame_number, e->offset_in_page, |
| 1104 | e->grain, e->syndrome); |
| 1105 | edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label, |
| 1106 | detail, e->other_detail, e->enable_per_layer_report, |
| 1107 | e->page_frame_number, e->offset_in_page, e->grain); |
| 1108 | } else { |
| 1109 | snprintf(detail, sizeof(detail), |
| 1110 | "page:0x%lx offset:0x%lx grain:%ld", |
| 1111 | e->page_frame_number, e->offset_in_page, e->grain); |
| 1112 | |
| 1113 | edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label, |
| 1114 | detail, e->other_detail, e->enable_per_layer_report); |
| 1115 | } |
| 1116 | |
| 1117 | |
| 1118 | } |
| 1119 | EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); |
| 1120 | |
| 1121 | /** |
| 1122 | * edac_mc_handle_error - reports a memory event to userspace |
| 1123 | * |
| 1124 | * @type: severity of the error (CE/UE/Fatal) |
| 1125 | * @mci: a struct mem_ctl_info pointer |
| 1126 | * @error_count: Number of errors of the same type |
| 1127 | * @page_frame_number: mem page where the error occurred |
| 1128 | * @offset_in_page: offset of the error inside the page |
| 1129 | * @syndrome: ECC syndrome |
| 1130 | * @top_layer: Memory layer[0] position |
| 1131 | * @mid_layer: Memory layer[1] position |
| 1132 | * @low_layer: Memory layer[2] position |
| 1133 | * @msg: Message meaningful to the end users that |
| 1134 | * explains the event |
| 1135 | * @other_detail: Technical details about the event that |
| 1136 | * may help hardware manufacturers and |
| 1137 | * EDAC developers to analyse the event |
| 1138 | */ |
| 1139 | void edac_mc_handle_error(const enum hw_event_mc_err_type type, |
| 1140 | struct mem_ctl_info *mci, |
| 1141 | const u16 error_count, |
| 1142 | const unsigned long page_frame_number, |
| 1143 | const unsigned long offset_in_page, |
| 1144 | const unsigned long syndrome, |
| 1145 | const int top_layer, |
| 1146 | const int mid_layer, |
| 1147 | const int low_layer, |
| 1148 | const char *msg, |
| 1149 | const char *other_detail) |
| 1150 | { |
| 1151 | char *p; |
| 1152 | int row = -1, chan = -1; |
| 1153 | int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; |
| 1154 | int i, n_labels = 0; |
| 1155 | u8 grain_bits; |
| 1156 | struct edac_raw_error_desc *e = &mci->error_desc; |
| 1157 | |
| 1158 | edac_dbg(3, "MC%d\n", mci->mc_idx); |
| 1159 | |
| 1160 | /* Fills the error report buffer */ |
| 1161 | memset(e, 0, sizeof (*e)); |
| 1162 | e->error_count = error_count; |
| 1163 | e->top_layer = top_layer; |
| 1164 | e->mid_layer = mid_layer; |
| 1165 | e->low_layer = low_layer; |
| 1166 | e->page_frame_number = page_frame_number; |
| 1167 | e->offset_in_page = offset_in_page; |
| 1168 | e->syndrome = syndrome; |
| 1169 | e->msg = msg; |
| 1170 | e->other_detail = other_detail; |
| 1171 | |
| 1172 | /* |
| 1173 | * Check if the event report is consistent and if the memory |
| 1174 | * location is known. If it is known, enable_per_layer_report will be |
| 1175 | * true, the DIMM(s) label info will be filled and the per-layer |
| 1176 | * error counters will be incremented. |
| 1177 | */ |
| 1178 | for (i = 0; i < mci->n_layers; i++) { |
| 1179 | if (pos[i] >= (int)mci->layers[i].size) { |
| 1180 | |
| 1181 | edac_mc_printk(mci, KERN_ERR, |
| 1182 | "INTERNAL ERROR: %s value is out of range (%d >= %d)\n", |
| 1183 | edac_layer_name[mci->layers[i].type], |
| 1184 | pos[i], mci->layers[i].size); |
| 1185 | /* |
| 1186 | * Instead of just returning it, let's use what's |
| 1187 | * known about the error. The increment routines and |
| 1188 | * the DIMM filter logic will do the right thing by |
| 1189 | * pointing the likely damaged DIMMs. |
| 1190 | */ |
| 1191 | pos[i] = -1; |
| 1192 | } |
| 1193 | if (pos[i] >= 0) |
| 1194 | e->enable_per_layer_report = true; |
| 1195 | } |
| 1196 | |
| 1197 | /* |
| 1198 | * Get the dimm label/grain that applies to the match criteria. |
| 1199 | * As the error algorithm may not be able to point to just one memory |
| 1200 | * stick, the logic here will get all possible labels that could |
| 1201 | * pottentially be affected by the error. |
| 1202 | * On FB-DIMM memory controllers, for uncorrected errors, it is common |
| 1203 | * to have only the MC channel and the MC dimm (also called "branch") |
| 1204 | * but the channel is not known, as the memory is arranged in pairs, |
| 1205 | * where each memory belongs to a separate channel within the same |
| 1206 | * branch. |
| 1207 | */ |
| 1208 | p = e->label; |
| 1209 | *p = '\0'; |
| 1210 | |
| 1211 | for (i = 0; i < mci->tot_dimms; i++) { |
| 1212 | struct dimm_info *dimm = mci->dimms[i]; |
| 1213 | |
| 1214 | if (top_layer >= 0 && top_layer != dimm->location[0]) |
| 1215 | continue; |
| 1216 | if (mid_layer >= 0 && mid_layer != dimm->location[1]) |
| 1217 | continue; |
| 1218 | if (low_layer >= 0 && low_layer != dimm->location[2]) |
| 1219 | continue; |
| 1220 | |
| 1221 | /* get the max grain, over the error match range */ |
| 1222 | if (dimm->grain > e->grain) |
| 1223 | e->grain = dimm->grain; |
| 1224 | |
| 1225 | /* |
| 1226 | * If the error is memory-controller wide, there's no need to |
| 1227 | * seek for the affected DIMMs because the whole |
| 1228 | * channel/memory controller/... may be affected. |
| 1229 | * Also, don't show errors for empty DIMM slots. |
| 1230 | */ |
| 1231 | if (e->enable_per_layer_report && dimm->nr_pages) { |
| 1232 | if (n_labels >= EDAC_MAX_LABELS) { |
| 1233 | e->enable_per_layer_report = false; |
| 1234 | break; |
| 1235 | } |
| 1236 | n_labels++; |
| 1237 | if (p != e->label) { |
| 1238 | strcpy(p, OTHER_LABEL); |
| 1239 | p += strlen(OTHER_LABEL); |
| 1240 | } |
| 1241 | strcpy(p, dimm->label); |
| 1242 | p += strlen(p); |
| 1243 | *p = '\0'; |
| 1244 | |
| 1245 | /* |
| 1246 | * get csrow/channel of the DIMM, in order to allow |
| 1247 | * incrementing the compat API counters |
| 1248 | */ |
| 1249 | edac_dbg(4, "%s csrows map: (%d,%d)\n", |
| 1250 | mci->csbased ? "rank" : "dimm", |
| 1251 | dimm->csrow, dimm->cschannel); |
| 1252 | if (row == -1) |
| 1253 | row = dimm->csrow; |
| 1254 | else if (row >= 0 && row != dimm->csrow) |
| 1255 | row = -2; |
| 1256 | |
| 1257 | if (chan == -1) |
| 1258 | chan = dimm->cschannel; |
| 1259 | else if (chan >= 0 && chan != dimm->cschannel) |
| 1260 | chan = -2; |
| 1261 | } |
| 1262 | } |
| 1263 | |
| 1264 | if (!e->enable_per_layer_report) { |
| 1265 | strcpy(e->label, "any memory"); |
| 1266 | } else { |
| 1267 | edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); |
| 1268 | if (p == e->label) |
| 1269 | strcpy(e->label, "unknown memory"); |
| 1270 | if (type == HW_EVENT_ERR_CORRECTED) { |
| 1271 | if (row >= 0) { |
| 1272 | mci->csrows[row]->ce_count += error_count; |
| 1273 | if (chan >= 0) |
| 1274 | mci->csrows[row]->channels[chan]->ce_count += error_count; |
| 1275 | } |
| 1276 | } else |
| 1277 | if (row >= 0) |
| 1278 | mci->csrows[row]->ue_count += error_count; |
| 1279 | } |
| 1280 | |
| 1281 | /* Fill the RAM location data */ |
| 1282 | p = e->location; |
| 1283 | |
| 1284 | for (i = 0; i < mci->n_layers; i++) { |
| 1285 | if (pos[i] < 0) |
| 1286 | continue; |
| 1287 | |
| 1288 | p += sprintf(p, "%s:%d ", |
| 1289 | edac_layer_name[mci->layers[i].type], |
| 1290 | pos[i]); |
| 1291 | } |
| 1292 | if (p > e->location) |
| 1293 | *(p - 1) = '\0'; |
| 1294 | |
| 1295 | /* Report the error via the trace interface */ |
| 1296 | grain_bits = fls_long(e->grain) + 1; |
| 1297 | trace_mc_event(type, e->msg, e->label, e->error_count, |
| 1298 | mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer, |
| 1299 | PAGES_TO_MiB(e->page_frame_number) | e->offset_in_page, |
| 1300 | grain_bits, e->syndrome, e->other_detail); |
| 1301 | |
| 1302 | edac_raw_mc_handle_error(type, mci, e); |
| 1303 | } |
| 1304 | EXPORT_SYMBOL_GPL(edac_mc_handle_error); |