| 1 | /* |
| 2 | * AMD CS5535/CS5536 GPIO driver. |
| 3 | * Allows a user space process to play with the GPIO pins. |
| 4 | * |
| 5 | * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the smems of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/fs.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/cdev.h> |
| 18 | #include <linux/ioport.h> |
| 19 | #include <linux/pci.h> |
| 20 | #include <linux/smp_lock.h> |
| 21 | #include <asm/uaccess.h> |
| 22 | #include <asm/io.h> |
| 23 | |
| 24 | |
| 25 | #define NAME "cs5535_gpio" |
| 26 | |
| 27 | MODULE_AUTHOR("Ben Gardner <bgardner@wabtec.com>"); |
| 28 | MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO Pin Driver"); |
| 29 | MODULE_LICENSE("GPL"); |
| 30 | |
| 31 | static int major; |
| 32 | module_param(major, int, 0); |
| 33 | MODULE_PARM_DESC(major, "Major device number"); |
| 34 | |
| 35 | static ulong mask; |
| 36 | module_param(mask, ulong, 0); |
| 37 | MODULE_PARM_DESC(mask, "GPIO channel mask"); |
| 38 | |
| 39 | #define MSR_LBAR_GPIO 0x5140000C |
| 40 | |
| 41 | static u32 gpio_base; |
| 42 | |
| 43 | static struct pci_device_id divil_pci[] = { |
| 44 | { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) }, |
| 45 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) }, |
| 46 | { } /* NULL entry */ |
| 47 | }; |
| 48 | MODULE_DEVICE_TABLE(pci, divil_pci); |
| 49 | |
| 50 | static struct cdev cs5535_gpio_cdev; |
| 51 | |
| 52 | /* reserve 32 entries even though some aren't usable */ |
| 53 | #define CS5535_GPIO_COUNT 32 |
| 54 | |
| 55 | /* IO block size */ |
| 56 | #define CS5535_GPIO_SIZE 256 |
| 57 | |
| 58 | struct gpio_regmap { |
| 59 | u32 rd_offset; |
| 60 | u32 wr_offset; |
| 61 | char on; |
| 62 | char off; |
| 63 | }; |
| 64 | static struct gpio_regmap rm[] = |
| 65 | { |
| 66 | { 0x30, 0x00, '1', '0' }, /* GPIOx_READ_BACK / GPIOx_OUT_VAL */ |
| 67 | { 0x20, 0x20, 'I', 'i' }, /* GPIOx_IN_EN */ |
| 68 | { 0x04, 0x04, 'O', 'o' }, /* GPIOx_OUT_EN */ |
| 69 | { 0x08, 0x08, 't', 'T' }, /* GPIOx_OUT_OD_EN */ |
| 70 | { 0x18, 0x18, 'P', 'p' }, /* GPIOx_OUT_PU_EN */ |
| 71 | { 0x1c, 0x1c, 'D', 'd' }, /* GPIOx_OUT_PD_EN */ |
| 72 | }; |
| 73 | |
| 74 | |
| 75 | /** |
| 76 | * Gets the register offset for the GPIO bank. |
| 77 | * Low (0-15) starts at 0x00, high (16-31) starts at 0x80 |
| 78 | */ |
| 79 | static inline u32 cs5535_lowhigh_base(int reg) |
| 80 | { |
| 81 | return (reg & 0x10) << 3; |
| 82 | } |
| 83 | |
| 84 | static ssize_t cs5535_gpio_write(struct file *file, const char __user *data, |
| 85 | size_t len, loff_t *ppos) |
| 86 | { |
| 87 | u32 m = iminor(file->f_path.dentry->d_inode); |
| 88 | int i, j; |
| 89 | u32 base = gpio_base + cs5535_lowhigh_base(m); |
| 90 | u32 m0, m1; |
| 91 | char c; |
| 92 | |
| 93 | /** |
| 94 | * Creates the mask for atomic bit programming. |
| 95 | * The high 16 bits and the low 16 bits are used to set the mask. |
| 96 | * For example, GPIO 15 maps to 31,15: 0,1 => On; 1,0=> Off |
| 97 | */ |
| 98 | m1 = 1 << (m & 0x0F); |
| 99 | m0 = m1 << 16; |
| 100 | |
| 101 | for (i = 0; i < len; ++i) { |
| 102 | if (get_user(c, data+i)) |
| 103 | return -EFAULT; |
| 104 | |
| 105 | for (j = 0; j < ARRAY_SIZE(rm); j++) { |
| 106 | if (c == rm[j].on) { |
| 107 | outl(m1, base + rm[j].wr_offset); |
| 108 | /* If enabling output, turn off AUX 1 and AUX 2 */ |
| 109 | if (c == 'O') { |
| 110 | outl(m0, base + 0x10); |
| 111 | outl(m0, base + 0x14); |
| 112 | } |
| 113 | break; |
| 114 | } else if (c == rm[j].off) { |
| 115 | outl(m0, base + rm[j].wr_offset); |
| 116 | break; |
| 117 | } |
| 118 | } |
| 119 | } |
| 120 | *ppos = 0; |
| 121 | return len; |
| 122 | } |
| 123 | |
| 124 | static ssize_t cs5535_gpio_read(struct file *file, char __user *buf, |
| 125 | size_t len, loff_t *ppos) |
| 126 | { |
| 127 | u32 m = iminor(file->f_path.dentry->d_inode); |
| 128 | u32 base = gpio_base + cs5535_lowhigh_base(m); |
| 129 | int rd_bit = 1 << (m & 0x0f); |
| 130 | int i; |
| 131 | char ch; |
| 132 | ssize_t count = 0; |
| 133 | |
| 134 | if (*ppos >= ARRAY_SIZE(rm)) |
| 135 | return 0; |
| 136 | |
| 137 | for (i = *ppos; (i < (*ppos + len)) && (i < ARRAY_SIZE(rm)); i++) { |
| 138 | ch = (inl(base + rm[i].rd_offset) & rd_bit) ? |
| 139 | rm[i].on : rm[i].off; |
| 140 | |
| 141 | if (put_user(ch, buf+count)) |
| 142 | return -EFAULT; |
| 143 | |
| 144 | count++; |
| 145 | } |
| 146 | |
| 147 | /* add a line-feed if there is room */ |
| 148 | if ((i == ARRAY_SIZE(rm)) && (count < len)) { |
| 149 | put_user('\n', buf + count); |
| 150 | count++; |
| 151 | } |
| 152 | |
| 153 | *ppos += count; |
| 154 | return count; |
| 155 | } |
| 156 | |
| 157 | static int cs5535_gpio_open(struct inode *inode, struct file *file) |
| 158 | { |
| 159 | u32 m = iminor(inode); |
| 160 | |
| 161 | cycle_kernel_lock(); |
| 162 | /* the mask says which pins are usable by this driver */ |
| 163 | if ((mask & (1 << m)) == 0) |
| 164 | return -EINVAL; |
| 165 | |
| 166 | return nonseekable_open(inode, file); |
| 167 | } |
| 168 | |
| 169 | static const struct file_operations cs5535_gpio_fops = { |
| 170 | .owner = THIS_MODULE, |
| 171 | .write = cs5535_gpio_write, |
| 172 | .read = cs5535_gpio_read, |
| 173 | .open = cs5535_gpio_open |
| 174 | }; |
| 175 | |
| 176 | static int __init cs5535_gpio_init(void) |
| 177 | { |
| 178 | dev_t dev_id; |
| 179 | u32 low, hi; |
| 180 | int retval; |
| 181 | |
| 182 | if (pci_dev_present(divil_pci) == 0) { |
| 183 | printk(KERN_WARNING NAME ": DIVIL not found\n"); |
| 184 | return -ENODEV; |
| 185 | } |
| 186 | |
| 187 | /* Grab the GPIO I/O range */ |
| 188 | rdmsr(MSR_LBAR_GPIO, low, hi); |
| 189 | |
| 190 | /* Check the mask and whether GPIO is enabled (sanity check) */ |
| 191 | if (hi != 0x0000f001) { |
| 192 | printk(KERN_WARNING NAME ": GPIO not enabled\n"); |
| 193 | return -ENODEV; |
| 194 | } |
| 195 | |
| 196 | /* Mask off the IO base address */ |
| 197 | gpio_base = low & 0x0000ff00; |
| 198 | |
| 199 | /** |
| 200 | * Some GPIO pins |
| 201 | * 31-29,23 : reserved (always mask out) |
| 202 | * 28 : Power Button |
| 203 | * 26 : PME# |
| 204 | * 22-16 : LPC |
| 205 | * 14,15 : SMBus |
| 206 | * 9,8 : UART1 |
| 207 | * 7 : PCI INTB |
| 208 | * 3,4 : UART2/DDC |
| 209 | * 2 : IDE_IRQ0 |
| 210 | * 0 : PCI INTA |
| 211 | * |
| 212 | * If a mask was not specified, be conservative and only allow: |
| 213 | * 1,2,5,6,10-13,24,25,27 |
| 214 | */ |
| 215 | if (mask != 0) |
| 216 | mask &= 0x1f7fffff; |
| 217 | else |
| 218 | mask = 0x0b003c66; |
| 219 | |
| 220 | if (!request_region(gpio_base, CS5535_GPIO_SIZE, NAME)) { |
| 221 | printk(KERN_ERR NAME ": can't allocate I/O for GPIO\n"); |
| 222 | return -ENODEV; |
| 223 | } |
| 224 | |
| 225 | if (major) { |
| 226 | dev_id = MKDEV(major, 0); |
| 227 | retval = register_chrdev_region(dev_id, CS5535_GPIO_COUNT, |
| 228 | NAME); |
| 229 | } else { |
| 230 | retval = alloc_chrdev_region(&dev_id, 0, CS5535_GPIO_COUNT, |
| 231 | NAME); |
| 232 | major = MAJOR(dev_id); |
| 233 | } |
| 234 | |
| 235 | if (retval) { |
| 236 | release_region(gpio_base, CS5535_GPIO_SIZE); |
| 237 | return -1; |
| 238 | } |
| 239 | |
| 240 | printk(KERN_DEBUG NAME ": base=%#x mask=%#lx major=%d\n", |
| 241 | gpio_base, mask, major); |
| 242 | |
| 243 | cdev_init(&cs5535_gpio_cdev, &cs5535_gpio_fops); |
| 244 | cdev_add(&cs5535_gpio_cdev, dev_id, CS5535_GPIO_COUNT); |
| 245 | |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | static void __exit cs5535_gpio_cleanup(void) |
| 250 | { |
| 251 | dev_t dev_id = MKDEV(major, 0); |
| 252 | |
| 253 | cdev_del(&cs5535_gpio_cdev); |
| 254 | unregister_chrdev_region(dev_id, CS5535_GPIO_COUNT); |
| 255 | release_region(gpio_base, CS5535_GPIO_SIZE); |
| 256 | } |
| 257 | |
| 258 | module_init(cs5535_gpio_init); |
| 259 | module_exit(cs5535_gpio_cleanup); |