| 1 | /* |
| 2 | * pata_optidma.c - Opti DMA PATA for new ATA layer |
| 3 | * (C) 2006 Red Hat Inc |
| 4 | * |
| 5 | * The Opti DMA controllers are related to the older PIO PCI controllers |
| 6 | * and indeed the VLB ones. The main differences are that the timing |
| 7 | * numbers are now based off PCI clocks not VLB and differ, and that |
| 8 | * MWDMA is supported. |
| 9 | * |
| 10 | * This driver should support Viper-N+, FireStar, FireStar Plus. |
| 11 | * |
| 12 | * These devices support virtual DMA for read (aka the CS5520). Later |
| 13 | * chips support UDMA33, but only if the rest of the board logic does, |
| 14 | * so you have to get this right. We don't support the virtual DMA |
| 15 | * but we do handle UDMA. |
| 16 | * |
| 17 | * Bits that are worth knowing |
| 18 | * Most control registers are shadowed into I/O registers |
| 19 | * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz |
| 20 | * Virtual DMA registers *move* between rev 0x02 and rev 0x10 |
| 21 | * UDMA requires a 66MHz FSB |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/pci.h> |
| 28 | #include <linux/blkdev.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <scsi/scsi_host.h> |
| 31 | #include <linux/libata.h> |
| 32 | |
| 33 | #define DRV_NAME "pata_optidma" |
| 34 | #define DRV_VERSION "0.3.2" |
| 35 | |
| 36 | enum { |
| 37 | READ_REG = 0, /* index of Read cycle timing register */ |
| 38 | WRITE_REG = 1, /* index of Write cycle timing register */ |
| 39 | CNTRL_REG = 3, /* index of Control register */ |
| 40 | STRAP_REG = 5, /* index of Strap register */ |
| 41 | MISC_REG = 6 /* index of Miscellaneous register */ |
| 42 | }; |
| 43 | |
| 44 | static int pci_clock; /* 0 = 33 1 = 25 */ |
| 45 | |
| 46 | /** |
| 47 | * optidma_pre_reset - probe begin |
| 48 | * @link: ATA link |
| 49 | * @deadline: deadline jiffies for the operation |
| 50 | * |
| 51 | * Set up cable type and use generic probe init |
| 52 | */ |
| 53 | |
| 54 | static int optidma_pre_reset(struct ata_link *link, unsigned long deadline) |
| 55 | { |
| 56 | struct ata_port *ap = link->ap; |
| 57 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 58 | static const struct pci_bits optidma_enable_bits = { |
| 59 | 0x40, 1, 0x08, 0x00 |
| 60 | }; |
| 61 | |
| 62 | if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) |
| 63 | return -ENOENT; |
| 64 | |
| 65 | return ata_sff_prereset(link, deadline); |
| 66 | } |
| 67 | |
| 68 | /** |
| 69 | * optidma_unlock - unlock control registers |
| 70 | * @ap: ATA port |
| 71 | * |
| 72 | * Unlock the control register block for this adapter. Registers must not |
| 73 | * be unlocked in a situation where libata might look at them. |
| 74 | */ |
| 75 | |
| 76 | static void optidma_unlock(struct ata_port *ap) |
| 77 | { |
| 78 | void __iomem *regio = ap->ioaddr.cmd_addr; |
| 79 | |
| 80 | /* These 3 unlock the control register access */ |
| 81 | ioread16(regio + 1); |
| 82 | ioread16(regio + 1); |
| 83 | iowrite8(3, regio + 2); |
| 84 | } |
| 85 | |
| 86 | /** |
| 87 | * optidma_lock - issue temporary relock |
| 88 | * @ap: ATA port |
| 89 | * |
| 90 | * Re-lock the configuration register settings. |
| 91 | */ |
| 92 | |
| 93 | static void optidma_lock(struct ata_port *ap) |
| 94 | { |
| 95 | void __iomem *regio = ap->ioaddr.cmd_addr; |
| 96 | |
| 97 | /* Relock */ |
| 98 | iowrite8(0x83, regio + 2); |
| 99 | } |
| 100 | |
| 101 | /** |
| 102 | * optidma_mode_setup - set mode data |
| 103 | * @ap: ATA interface |
| 104 | * @adev: ATA device |
| 105 | * @mode: Mode to set |
| 106 | * |
| 107 | * Called to do the DMA or PIO mode setup. Timing numbers are all |
| 108 | * pre computed to keep the code clean. There are two tables depending |
| 109 | * on the hardware clock speed. |
| 110 | * |
| 111 | * WARNING: While we do this the IDE registers vanish. If we take an |
| 112 | * IRQ here we depend on the host set locking to avoid catastrophe. |
| 113 | */ |
| 114 | |
| 115 | static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode) |
| 116 | { |
| 117 | struct ata_device *pair = ata_dev_pair(adev); |
| 118 | int pio = adev->pio_mode - XFER_PIO_0; |
| 119 | int dma = adev->dma_mode - XFER_MW_DMA_0; |
| 120 | void __iomem *regio = ap->ioaddr.cmd_addr; |
| 121 | u8 addr; |
| 122 | |
| 123 | /* Address table precomputed with a DCLK of 2 */ |
| 124 | static const u8 addr_timing[2][5] = { |
| 125 | { 0x30, 0x20, 0x20, 0x10, 0x10 }, |
| 126 | { 0x20, 0x20, 0x10, 0x10, 0x10 } |
| 127 | }; |
| 128 | static const u8 data_rec_timing[2][5] = { |
| 129 | { 0x59, 0x46, 0x30, 0x20, 0x20 }, |
| 130 | { 0x46, 0x32, 0x20, 0x20, 0x10 } |
| 131 | }; |
| 132 | static const u8 dma_data_rec_timing[2][3] = { |
| 133 | { 0x76, 0x20, 0x20 }, |
| 134 | { 0x54, 0x20, 0x10 } |
| 135 | }; |
| 136 | |
| 137 | /* Switch from IDE to control mode */ |
| 138 | optidma_unlock(ap); |
| 139 | |
| 140 | |
| 141 | /* |
| 142 | * As with many controllers the address setup time is shared |
| 143 | * and must suit both devices if present. FIXME: Check if we |
| 144 | * need to look at slowest of PIO/DMA mode of either device |
| 145 | */ |
| 146 | |
| 147 | if (mode >= XFER_MW_DMA_0) |
| 148 | addr = 0; |
| 149 | else |
| 150 | addr = addr_timing[pci_clock][pio]; |
| 151 | |
| 152 | if (pair) { |
| 153 | u8 pair_addr; |
| 154 | /* Hardware constraint */ |
| 155 | if (pair->dma_mode) |
| 156 | pair_addr = 0; |
| 157 | else |
| 158 | pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0]; |
| 159 | if (pair_addr > addr) |
| 160 | addr = pair_addr; |
| 161 | } |
| 162 | |
| 163 | /* Commence primary programming sequence */ |
| 164 | /* First we load the device number into the timing select */ |
| 165 | iowrite8(adev->devno, regio + MISC_REG); |
| 166 | /* Now we load the data timings into read data/write data */ |
| 167 | if (mode < XFER_MW_DMA_0) { |
| 168 | iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG); |
| 169 | iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); |
| 170 | } else if (mode < XFER_UDMA_0) { |
| 171 | iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG); |
| 172 | iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); |
| 173 | } |
| 174 | /* Finally we load the address setup into the misc register */ |
| 175 | iowrite8(addr | adev->devno, regio + MISC_REG); |
| 176 | |
| 177 | /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */ |
| 178 | iowrite8(0x85, regio + CNTRL_REG); |
| 179 | |
| 180 | /* Switch back to IDE mode */ |
| 181 | optidma_lock(ap); |
| 182 | |
| 183 | /* Note: at this point our programming is incomplete. We are |
| 184 | not supposed to program PCI 0x43 "things we hacked onto the chip" |
| 185 | until we've done both sets of PIO/DMA timings */ |
| 186 | } |
| 187 | |
| 188 | /** |
| 189 | * optiplus_mode_setup - DMA setup for Firestar Plus |
| 190 | * @ap: ATA port |
| 191 | * @adev: device |
| 192 | * @mode: desired mode |
| 193 | * |
| 194 | * The Firestar plus has additional UDMA functionality for UDMA0-2 and |
| 195 | * requires we do some additional work. Because the base work we must do |
| 196 | * is mostly shared we wrap the Firestar setup functionality in this |
| 197 | * one |
| 198 | */ |
| 199 | |
| 200 | static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode) |
| 201 | { |
| 202 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 203 | u8 udcfg; |
| 204 | u8 udslave; |
| 205 | int dev2 = 2 * adev->devno; |
| 206 | int unit = 2 * ap->port_no + adev->devno; |
| 207 | int udma = mode - XFER_UDMA_0; |
| 208 | |
| 209 | pci_read_config_byte(pdev, 0x44, &udcfg); |
| 210 | if (mode <= XFER_UDMA_0) { |
| 211 | udcfg &= ~(1 << unit); |
| 212 | optidma_mode_setup(ap, adev, adev->dma_mode); |
| 213 | } else { |
| 214 | udcfg |= (1 << unit); |
| 215 | if (ap->port_no) { |
| 216 | pci_read_config_byte(pdev, 0x45, &udslave); |
| 217 | udslave &= ~(0x03 << dev2); |
| 218 | udslave |= (udma << dev2); |
| 219 | pci_write_config_byte(pdev, 0x45, udslave); |
| 220 | } else { |
| 221 | udcfg &= ~(0x30 << dev2); |
| 222 | udcfg |= (udma << dev2); |
| 223 | } |
| 224 | } |
| 225 | pci_write_config_byte(pdev, 0x44, udcfg); |
| 226 | } |
| 227 | |
| 228 | /** |
| 229 | * optidma_set_pio_mode - PIO setup callback |
| 230 | * @ap: ATA port |
| 231 | * @adev: Device |
| 232 | * |
| 233 | * The libata core provides separate functions for handling PIO and |
| 234 | * DMA programming. The architecture of the Firestar makes it easier |
| 235 | * for us to have a common function so we provide wrappers |
| 236 | */ |
| 237 | |
| 238 | static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev) |
| 239 | { |
| 240 | optidma_mode_setup(ap, adev, adev->pio_mode); |
| 241 | } |
| 242 | |
| 243 | /** |
| 244 | * optidma_set_dma_mode - DMA setup callback |
| 245 | * @ap: ATA port |
| 246 | * @adev: Device |
| 247 | * |
| 248 | * The libata core provides separate functions for handling PIO and |
| 249 | * DMA programming. The architecture of the Firestar makes it easier |
| 250 | * for us to have a common function so we provide wrappers |
| 251 | */ |
| 252 | |
| 253 | static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev) |
| 254 | { |
| 255 | optidma_mode_setup(ap, adev, adev->dma_mode); |
| 256 | } |
| 257 | |
| 258 | /** |
| 259 | * optiplus_set_pio_mode - PIO setup callback |
| 260 | * @ap: ATA port |
| 261 | * @adev: Device |
| 262 | * |
| 263 | * The libata core provides separate functions for handling PIO and |
| 264 | * DMA programming. The architecture of the Firestar makes it easier |
| 265 | * for us to have a common function so we provide wrappers |
| 266 | */ |
| 267 | |
| 268 | static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev) |
| 269 | { |
| 270 | optiplus_mode_setup(ap, adev, adev->pio_mode); |
| 271 | } |
| 272 | |
| 273 | /** |
| 274 | * optiplus_set_dma_mode - DMA setup callback |
| 275 | * @ap: ATA port |
| 276 | * @adev: Device |
| 277 | * |
| 278 | * The libata core provides separate functions for handling PIO and |
| 279 | * DMA programming. The architecture of the Firestar makes it easier |
| 280 | * for us to have a common function so we provide wrappers |
| 281 | */ |
| 282 | |
| 283 | static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev) |
| 284 | { |
| 285 | optiplus_mode_setup(ap, adev, adev->dma_mode); |
| 286 | } |
| 287 | |
| 288 | /** |
| 289 | * optidma_make_bits - PCI setup helper |
| 290 | * @adev: ATA device |
| 291 | * |
| 292 | * Turn the ATA device setup into PCI configuration bits |
| 293 | * for register 0x43 and return the two bits needed. |
| 294 | */ |
| 295 | |
| 296 | static u8 optidma_make_bits43(struct ata_device *adev) |
| 297 | { |
| 298 | static const u8 bits43[5] = { |
| 299 | 0, 0, 0, 1, 2 |
| 300 | }; |
| 301 | if (!ata_dev_enabled(adev)) |
| 302 | return 0; |
| 303 | if (adev->dma_mode) |
| 304 | return adev->dma_mode - XFER_MW_DMA_0; |
| 305 | return bits43[adev->pio_mode - XFER_PIO_0]; |
| 306 | } |
| 307 | |
| 308 | /** |
| 309 | * optidma_set_mode - mode setup |
| 310 | * @link: link to set up |
| 311 | * |
| 312 | * Use the standard setup to tune the chipset and then finalise the |
| 313 | * configuration by writing the nibble of extra bits of data into |
| 314 | * the chip. |
| 315 | */ |
| 316 | |
| 317 | static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed) |
| 318 | { |
| 319 | struct ata_port *ap = link->ap; |
| 320 | u8 r; |
| 321 | int nybble = 4 * ap->port_no; |
| 322 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 323 | int rc = ata_do_set_mode(link, r_failed); |
| 324 | if (rc == 0) { |
| 325 | pci_read_config_byte(pdev, 0x43, &r); |
| 326 | |
| 327 | r &= (0x0F << nybble); |
| 328 | r |= (optidma_make_bits43(&link->device[0]) + |
| 329 | (optidma_make_bits43(&link->device[0]) << 2)) << nybble; |
| 330 | pci_write_config_byte(pdev, 0x43, r); |
| 331 | } |
| 332 | return rc; |
| 333 | } |
| 334 | |
| 335 | static struct scsi_host_template optidma_sht = { |
| 336 | ATA_BMDMA_SHT(DRV_NAME), |
| 337 | }; |
| 338 | |
| 339 | static struct ata_port_operations optidma_port_ops = { |
| 340 | .inherits = &ata_bmdma_port_ops, |
| 341 | .cable_detect = ata_cable_40wire, |
| 342 | .set_piomode = optidma_set_pio_mode, |
| 343 | .set_dmamode = optidma_set_dma_mode, |
| 344 | .set_mode = optidma_set_mode, |
| 345 | .prereset = optidma_pre_reset, |
| 346 | }; |
| 347 | |
| 348 | static struct ata_port_operations optiplus_port_ops = { |
| 349 | .inherits = &optidma_port_ops, |
| 350 | .set_piomode = optiplus_set_pio_mode, |
| 351 | .set_dmamode = optiplus_set_dma_mode, |
| 352 | }; |
| 353 | |
| 354 | /** |
| 355 | * optiplus_with_udma - Look for UDMA capable setup |
| 356 | * @pdev; ATA controller |
| 357 | */ |
| 358 | |
| 359 | static int optiplus_with_udma(struct pci_dev *pdev) |
| 360 | { |
| 361 | u8 r; |
| 362 | int ret = 0; |
| 363 | int ioport = 0x22; |
| 364 | struct pci_dev *dev1; |
| 365 | |
| 366 | /* Find function 1 */ |
| 367 | dev1 = pci_get_device(0x1045, 0xC701, NULL); |
| 368 | if (dev1 == NULL) |
| 369 | return 0; |
| 370 | |
| 371 | /* Rev must be >= 0x10 */ |
| 372 | pci_read_config_byte(dev1, 0x08, &r); |
| 373 | if (r < 0x10) |
| 374 | goto done_nomsg; |
| 375 | /* Read the chipset system configuration to check our mode */ |
| 376 | pci_read_config_byte(dev1, 0x5F, &r); |
| 377 | ioport |= (r << 8); |
| 378 | outb(0x10, ioport); |
| 379 | /* Must be 66Mhz sync */ |
| 380 | if ((inb(ioport + 2) & 1) == 0) |
| 381 | goto done; |
| 382 | |
| 383 | /* Check the ATA arbitration/timing is suitable */ |
| 384 | pci_read_config_byte(pdev, 0x42, &r); |
| 385 | if ((r & 0x36) != 0x36) |
| 386 | goto done; |
| 387 | pci_read_config_byte(dev1, 0x52, &r); |
| 388 | if (r & 0x80) /* IDEDIR disabled */ |
| 389 | ret = 1; |
| 390 | done: |
| 391 | printk(KERN_WARNING "UDMA not supported in this configuration.\n"); |
| 392 | done_nomsg: /* Wrong chip revision */ |
| 393 | pci_dev_put(dev1); |
| 394 | return ret; |
| 395 | } |
| 396 | |
| 397 | static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 398 | { |
| 399 | static const struct ata_port_info info_82c700 = { |
| 400 | .flags = ATA_FLAG_SLAVE_POSS, |
| 401 | .pio_mask = ATA_PIO4, |
| 402 | .mwdma_mask = ATA_MWDMA2, |
| 403 | .port_ops = &optidma_port_ops |
| 404 | }; |
| 405 | static const struct ata_port_info info_82c700_udma = { |
| 406 | .flags = ATA_FLAG_SLAVE_POSS, |
| 407 | .pio_mask = ATA_PIO4, |
| 408 | .mwdma_mask = ATA_MWDMA2, |
| 409 | .udma_mask = ATA_UDMA2, |
| 410 | .port_ops = &optiplus_port_ops |
| 411 | }; |
| 412 | const struct ata_port_info *ppi[] = { &info_82c700, NULL }; |
| 413 | int rc; |
| 414 | |
| 415 | ata_print_version_once(&dev->dev, DRV_VERSION); |
| 416 | |
| 417 | rc = pcim_enable_device(dev); |
| 418 | if (rc) |
| 419 | return rc; |
| 420 | |
| 421 | /* Fixed location chipset magic */ |
| 422 | inw(0x1F1); |
| 423 | inw(0x1F1); |
| 424 | pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */ |
| 425 | |
| 426 | if (optiplus_with_udma(dev)) |
| 427 | ppi[0] = &info_82c700_udma; |
| 428 | |
| 429 | return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0); |
| 430 | } |
| 431 | |
| 432 | static const struct pci_device_id optidma[] = { |
| 433 | { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */ |
| 434 | |
| 435 | { }, |
| 436 | }; |
| 437 | |
| 438 | static struct pci_driver optidma_pci_driver = { |
| 439 | .name = DRV_NAME, |
| 440 | .id_table = optidma, |
| 441 | .probe = optidma_init_one, |
| 442 | .remove = ata_pci_remove_one, |
| 443 | #ifdef CONFIG_PM_SLEEP |
| 444 | .suspend = ata_pci_device_suspend, |
| 445 | .resume = ata_pci_device_resume, |
| 446 | #endif |
| 447 | }; |
| 448 | |
| 449 | module_pci_driver(optidma_pci_driver); |
| 450 | |
| 451 | MODULE_AUTHOR("Alan Cox"); |
| 452 | MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus"); |
| 453 | MODULE_LICENSE("GPL"); |
| 454 | MODULE_DEVICE_TABLE(pci, optidma); |
| 455 | MODULE_VERSION(DRV_VERSION); |