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defconfig: exynos9610: Re-add dropped Wi-Fi AP options lost
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ata / ahci.c
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1/*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <linux/dmi.h>
44#include <linux/gfp.h>
45#include <linux/msi.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_cmnd.h>
48#include <linux/libata.h>
49#include <linux/ahci-remap.h>
50#include <linux/io-64-nonatomic-lo-hi.h>
51#include "ahci.h"
52
53#define DRV_NAME "ahci"
54#define DRV_VERSION "3.0"
55
56enum {
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_STANDARD = 5,
61};
62
63enum board_ids {
64 /* board IDs by feature in alphabetical order */
65 board_ahci,
66 board_ahci_ign_iferr,
67 board_ahci_nomsi,
68 board_ahci_noncq,
69 board_ahci_nosntf,
70 board_ahci_yes_fbs,
71
72 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_avn,
74 board_ahci_mcp65,
75 board_ahci_mcp77,
76 board_ahci_mcp89,
77 board_ahci_mv,
78 board_ahci_sb600,
79 board_ahci_sb700, /* for SB700 and SB800 */
80 board_ahci_vt8251,
81
82 /* aliases */
83 board_ahci_mcp_linux = board_ahci_mcp65,
84 board_ahci_mcp67 = board_ahci_mcp65,
85 board_ahci_mcp73 = board_ahci_mcp65,
86 board_ahci_mcp79 = board_ahci_mcp77,
87};
88
89static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
90static void ahci_remove_one(struct pci_dev *dev);
91static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
93static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
95static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
96static bool is_mcp89_apple(struct pci_dev *pdev);
97static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
98 unsigned long deadline);
99#ifdef CONFIG_PM
100static int ahci_pci_device_runtime_suspend(struct device *dev);
101static int ahci_pci_device_runtime_resume(struct device *dev);
102#ifdef CONFIG_PM_SLEEP
103static int ahci_pci_device_suspend(struct device *dev);
104static int ahci_pci_device_resume(struct device *dev);
105#endif
106#endif /* CONFIG_PM */
107
108static struct scsi_host_template ahci_sht = {
109 AHCI_SHT("ahci"),
110};
111
112static struct ata_port_operations ahci_vt8251_ops = {
113 .inherits = &ahci_ops,
114 .hardreset = ahci_vt8251_hardreset,
115};
116
117static struct ata_port_operations ahci_p5wdh_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_p5wdh_hardreset,
120};
121
122static struct ata_port_operations ahci_avn_ops = {
123 .inherits = &ahci_ops,
124 .hardreset = ahci_avn_hardreset,
125};
126
127static const struct ata_port_info ahci_port_info[] = {
128 /* by features */
129 [board_ahci] = {
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
135 [board_ahci_ign_iferr] = {
136 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
141 },
142 [board_ahci_nomsi] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_noncq] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
156 [board_ahci_nosntf] = {
157 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
162 },
163 [board_ahci_yes_fbs] = {
164 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_ops,
169 },
170 /* by chipsets */
171 [board_ahci_avn] = {
172 .flags = AHCI_FLAG_COMMON,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_avn_ops,
176 },
177 [board_ahci_mcp65] = {
178 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
179 AHCI_HFLAG_YES_NCQ),
180 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 [board_ahci_mcp77] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
192 [board_ahci_mcp89] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_ops,
198 },
199 [board_ahci_mv] = {
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
201 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
202 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
206 },
207 [board_ahci_sb600] = {
208 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
209 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
210 AHCI_HFLAG_32BIT_ONLY),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
215 },
216 [board_ahci_sb700] = { /* for SB700 and SB800 */
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_pmp_retry_srst_ops,
222 },
223 [board_ahci_vt8251] = {
224 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
225 .flags = AHCI_FLAG_COMMON,
226 .pio_mask = ATA_PIO4,
227 .udma_mask = ATA_UDMA6,
228 .port_ops = &ahci_vt8251_ops,
229 },
230};
231
232static const struct pci_device_id ahci_pci_tbl[] = {
233 /* Intel */
234 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
235 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
236 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
237 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
238 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
239 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
240 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
241 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
242 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
243 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
244 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
245 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
246 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
247 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
248 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
249 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
250 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
255 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
260 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
261 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
262 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
263 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
264 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
265 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
266 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
268 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
269 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
270 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
271 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
272 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
273 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
295 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
296 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
297 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
298 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
299 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
300 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
301 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
302 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
303 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
304 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
305 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */
307 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
308 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
309 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
310 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */
311 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
312 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
313 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */
314 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
315 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */
316 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
317 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */
318 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
319 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */
320 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
321 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
322 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
323 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
329 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
331 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
337 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
338 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
347 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
350 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
351 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
352 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
355 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
356 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
359 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
360 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
361 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
362 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
363 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
364 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
365 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
366 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
367 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
368 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
369 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
370 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
371 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */
372 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
373 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
374 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */
375 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
376 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
377 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
378 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
379 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
381 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
382 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
385 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
386 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
389 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
390 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
391 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Trail AHCI */
392 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* Apollo Lake AHCI */
393
394 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
395 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
396 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
397 /* JMicron 362B and 362C have an AHCI function with IDE class code */
398 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
399 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
400 /* May need to update quirk_jmicron_async_suspend() for additions */
401
402 /* ATI */
403 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
404 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
405 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
406 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
407 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
408 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
409 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
410
411 /* AMD */
412 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
413 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
414 /* AMD is using RAID class only for ahci controllers */
415 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
416 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
417
418 /* VIA */
419 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
420 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
421
422 /* NVIDIA */
423 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
502 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
503 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
504 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
507
508 /* SiS */
509 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
510 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
511 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
512
513 /* ST Microelectronics */
514 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
515
516 /* Marvell */
517 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
518 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
519 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
520 .class = PCI_CLASS_STORAGE_SATA_AHCI,
521 .class_mask = 0xffffff,
522 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
523 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
524 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
525 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
526 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
527 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
529 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
530 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
531 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
532 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
533 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
534 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
535 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
536 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
537 .driver_data = board_ahci_yes_fbs },
538 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
539 .driver_data = board_ahci_yes_fbs },
540 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
541 .driver_data = board_ahci_yes_fbs },
542 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
543 .driver_data = board_ahci_yes_fbs },
544 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
545 .driver_data = board_ahci_yes_fbs },
546 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
547 .driver_data = board_ahci_yes_fbs },
548
549 /* Promise */
550 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
551 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
552
553 /* Asmedia */
554 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
555 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
556 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
557 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
558 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
559 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
560
561 /*
562 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
563 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
564 */
565 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
566 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
567
568 /* Enmotus */
569 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
570
571 /* Generic, PCI class code for AHCI */
572 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
573 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
574
575 { } /* terminate list */
576};
577
578static const struct dev_pm_ops ahci_pci_pm_ops = {
579 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
580 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
581 ahci_pci_device_runtime_resume, NULL)
582};
583
584static struct pci_driver ahci_pci_driver = {
585 .name = DRV_NAME,
586 .id_table = ahci_pci_tbl,
587 .probe = ahci_init_one,
588 .remove = ahci_remove_one,
589 .driver = {
590 .pm = &ahci_pci_pm_ops,
591 },
592};
593
594#if IS_ENABLED(CONFIG_PATA_MARVELL)
595static int marvell_enable;
596#else
597static int marvell_enable = 1;
598#endif
599module_param(marvell_enable, int, 0644);
600MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
601
602
603static void ahci_pci_save_initial_config(struct pci_dev *pdev,
604 struct ahci_host_priv *hpriv)
605{
606 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
607 dev_info(&pdev->dev, "JMB361 has only one port\n");
608 hpriv->force_port_map = 1;
609 }
610
611 /*
612 * Temporary Marvell 6145 hack: PATA port presence
613 * is asserted through the standard AHCI port
614 * presence register, as bit 4 (counting from 0)
615 */
616 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
617 if (pdev->device == 0x6121)
618 hpriv->mask_port_map = 0x3;
619 else
620 hpriv->mask_port_map = 0xf;
621 dev_info(&pdev->dev,
622 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
623 }
624
625 ahci_save_initial_config(&pdev->dev, hpriv);
626}
627
628static int ahci_pci_reset_controller(struct ata_host *host)
629{
630 struct pci_dev *pdev = to_pci_dev(host->dev);
631 int rc;
632
633 rc = ahci_reset_controller(host);
634 if (rc)
635 return rc;
636
637 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
638 struct ahci_host_priv *hpriv = host->private_data;
639 u16 tmp16;
640
641 /* configure PCS */
642 pci_read_config_word(pdev, 0x92, &tmp16);
643 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
644 tmp16 |= hpriv->port_map;
645 pci_write_config_word(pdev, 0x92, tmp16);
646 }
647 }
648
649 return 0;
650}
651
652static void ahci_pci_init_controller(struct ata_host *host)
653{
654 struct ahci_host_priv *hpriv = host->private_data;
655 struct pci_dev *pdev = to_pci_dev(host->dev);
656 void __iomem *port_mmio;
657 u32 tmp;
658 int mv;
659
660 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
661 if (pdev->device == 0x6121)
662 mv = 2;
663 else
664 mv = 4;
665 port_mmio = __ahci_port_base(host, mv);
666
667 writel(0, port_mmio + PORT_IRQ_MASK);
668
669 /* clear port IRQ */
670 tmp = readl(port_mmio + PORT_IRQ_STAT);
671 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
672 if (tmp)
673 writel(tmp, port_mmio + PORT_IRQ_STAT);
674 }
675
676 ahci_init_controller(host);
677}
678
679static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
680 unsigned long deadline)
681{
682 struct ata_port *ap = link->ap;
683 struct ahci_host_priv *hpriv = ap->host->private_data;
684 bool online;
685 int rc;
686
687 DPRINTK("ENTER\n");
688
689 hpriv->stop_engine(ap);
690
691 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
692 deadline, &online, NULL);
693
694 hpriv->start_engine(ap);
695
696 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
697
698 /* vt8251 doesn't clear BSY on signature FIS reception,
699 * request follow-up softreset.
700 */
701 return online ? -EAGAIN : rc;
702}
703
704static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
705 unsigned long deadline)
706{
707 struct ata_port *ap = link->ap;
708 struct ahci_port_priv *pp = ap->private_data;
709 struct ahci_host_priv *hpriv = ap->host->private_data;
710 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
711 struct ata_taskfile tf;
712 bool online;
713 int rc;
714
715 hpriv->stop_engine(ap);
716
717 /* clear D2H reception area to properly wait for D2H FIS */
718 ata_tf_init(link->device, &tf);
719 tf.command = ATA_BUSY;
720 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
721
722 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
723 deadline, &online, NULL);
724
725 hpriv->start_engine(ap);
726
727 /* The pseudo configuration device on SIMG4726 attached to
728 * ASUS P5W-DH Deluxe doesn't send signature FIS after
729 * hardreset if no device is attached to the first downstream
730 * port && the pseudo device locks up on SRST w/ PMP==0. To
731 * work around this, wait for !BSY only briefly. If BSY isn't
732 * cleared, perform CLO and proceed to IDENTIFY (achieved by
733 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
734 *
735 * Wait for two seconds. Devices attached to downstream port
736 * which can't process the following IDENTIFY after this will
737 * have to be reset again. For most cases, this should
738 * suffice while making probing snappish enough.
739 */
740 if (online) {
741 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
742 ahci_check_ready);
743 if (rc)
744 ahci_kick_engine(ap);
745 }
746 return rc;
747}
748
749/*
750 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
751 *
752 * It has been observed with some SSDs that the timing of events in the
753 * link synchronization phase can leave the port in a state that can not
754 * be recovered by a SATA-hard-reset alone. The failing signature is
755 * SStatus.DET stuck at 1 ("Device presence detected but Phy
756 * communication not established"). It was found that unloading and
757 * reloading the driver when this problem occurs allows the drive
758 * connection to be recovered (DET advanced to 0x3). The critical
759 * component of reloading the driver is that the port state machines are
760 * reset by bouncing "port enable" in the AHCI PCS configuration
761 * register. So, reproduce that effect by bouncing a port whenever we
762 * see DET==1 after a reset.
763 */
764static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
765 unsigned long deadline)
766{
767 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
768 struct ata_port *ap = link->ap;
769 struct ahci_port_priv *pp = ap->private_data;
770 struct ahci_host_priv *hpriv = ap->host->private_data;
771 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
772 unsigned long tmo = deadline - jiffies;
773 struct ata_taskfile tf;
774 bool online;
775 int rc, i;
776
777 DPRINTK("ENTER\n");
778
779 hpriv->stop_engine(ap);
780
781 for (i = 0; i < 2; i++) {
782 u16 val;
783 u32 sstatus;
784 int port = ap->port_no;
785 struct ata_host *host = ap->host;
786 struct pci_dev *pdev = to_pci_dev(host->dev);
787
788 /* clear D2H reception area to properly wait for D2H FIS */
789 ata_tf_init(link->device, &tf);
790 tf.command = ATA_BUSY;
791 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
792
793 rc = sata_link_hardreset(link, timing, deadline, &online,
794 ahci_check_ready);
795
796 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
797 (sstatus & 0xf) != 1)
798 break;
799
800 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
801 port);
802
803 pci_read_config_word(pdev, 0x92, &val);
804 val &= ~(1 << port);
805 pci_write_config_word(pdev, 0x92, val);
806 ata_msleep(ap, 1000);
807 val |= 1 << port;
808 pci_write_config_word(pdev, 0x92, val);
809 deadline += tmo;
810 }
811
812 hpriv->start_engine(ap);
813
814 if (online)
815 *class = ahci_dev_classify(ap);
816
817 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
818 return rc;
819}
820
821
822#ifdef CONFIG_PM
823static void ahci_pci_disable_interrupts(struct ata_host *host)
824{
825 struct ahci_host_priv *hpriv = host->private_data;
826 void __iomem *mmio = hpriv->mmio;
827 u32 ctl;
828
829 /* AHCI spec rev1.1 section 8.3.3:
830 * Software must disable interrupts prior to requesting a
831 * transition of the HBA to D3 state.
832 */
833 ctl = readl(mmio + HOST_CTL);
834 ctl &= ~HOST_IRQ_EN;
835 writel(ctl, mmio + HOST_CTL);
836 readl(mmio + HOST_CTL); /* flush */
837}
838
839static int ahci_pci_device_runtime_suspend(struct device *dev)
840{
841 struct pci_dev *pdev = to_pci_dev(dev);
842 struct ata_host *host = pci_get_drvdata(pdev);
843
844 ahci_pci_disable_interrupts(host);
845 return 0;
846}
847
848static int ahci_pci_device_runtime_resume(struct device *dev)
849{
850 struct pci_dev *pdev = to_pci_dev(dev);
851 struct ata_host *host = pci_get_drvdata(pdev);
852 int rc;
853
854 rc = ahci_pci_reset_controller(host);
855 if (rc)
856 return rc;
857 ahci_pci_init_controller(host);
858 return 0;
859}
860
861#ifdef CONFIG_PM_SLEEP
862static int ahci_pci_device_suspend(struct device *dev)
863{
864 struct pci_dev *pdev = to_pci_dev(dev);
865 struct ata_host *host = pci_get_drvdata(pdev);
866 struct ahci_host_priv *hpriv = host->private_data;
867
868 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
869 dev_err(&pdev->dev,
870 "BIOS update required for suspend/resume\n");
871 return -EIO;
872 }
873
874 ahci_pci_disable_interrupts(host);
875 return ata_host_suspend(host, PMSG_SUSPEND);
876}
877
878static int ahci_pci_device_resume(struct device *dev)
879{
880 struct pci_dev *pdev = to_pci_dev(dev);
881 struct ata_host *host = pci_get_drvdata(pdev);
882 int rc;
883
884 /* Apple BIOS helpfully mangles the registers on resume */
885 if (is_mcp89_apple(pdev))
886 ahci_mcp89_apple_enable(pdev);
887
888 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
889 rc = ahci_pci_reset_controller(host);
890 if (rc)
891 return rc;
892
893 ahci_pci_init_controller(host);
894 }
895
896 ata_host_resume(host);
897
898 return 0;
899}
900#endif
901
902#endif /* CONFIG_PM */
903
904static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
905{
906 int rc;
907
908 /*
909 * If the device fixup already set the dma_mask to some non-standard
910 * value, don't extend it here. This happens on STA2X11, for example.
911 */
912 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
913 return 0;
914
915 if (using_dac &&
916 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
917 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
918 if (rc) {
919 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
920 if (rc) {
921 dev_err(&pdev->dev,
922 "64-bit DMA enable failed\n");
923 return rc;
924 }
925 }
926 } else {
927 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
928 if (rc) {
929 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
930 return rc;
931 }
932 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
933 if (rc) {
934 dev_err(&pdev->dev,
935 "32-bit consistent DMA enable failed\n");
936 return rc;
937 }
938 }
939 return 0;
940}
941
942static void ahci_pci_print_info(struct ata_host *host)
943{
944 struct pci_dev *pdev = to_pci_dev(host->dev);
945 u16 cc;
946 const char *scc_s;
947
948 pci_read_config_word(pdev, 0x0a, &cc);
949 if (cc == PCI_CLASS_STORAGE_IDE)
950 scc_s = "IDE";
951 else if (cc == PCI_CLASS_STORAGE_SATA)
952 scc_s = "SATA";
953 else if (cc == PCI_CLASS_STORAGE_RAID)
954 scc_s = "RAID";
955 else
956 scc_s = "unknown";
957
958 ahci_print_info(host, scc_s);
959}
960
961/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
962 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
963 * support PMP and the 4726 either directly exports the device
964 * attached to the first downstream port or acts as a hardware storage
965 * controller and emulate a single ATA device (can be RAID 0/1 or some
966 * other configuration).
967 *
968 * When there's no device attached to the first downstream port of the
969 * 4726, "Config Disk" appears, which is a pseudo ATA device to
970 * configure the 4726. However, ATA emulation of the device is very
971 * lame. It doesn't send signature D2H Reg FIS after the initial
972 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
973 *
974 * The following function works around the problem by always using
975 * hardreset on the port and not depending on receiving signature FIS
976 * afterward. If signature FIS isn't received soon, ATA class is
977 * assumed without follow-up softreset.
978 */
979static void ahci_p5wdh_workaround(struct ata_host *host)
980{
981 static const struct dmi_system_id sysids[] = {
982 {
983 .ident = "P5W DH Deluxe",
984 .matches = {
985 DMI_MATCH(DMI_SYS_VENDOR,
986 "ASUSTEK COMPUTER INC"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
988 },
989 },
990 { }
991 };
992 struct pci_dev *pdev = to_pci_dev(host->dev);
993
994 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
995 dmi_check_system(sysids)) {
996 struct ata_port *ap = host->ports[1];
997
998 dev_info(&pdev->dev,
999 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1000
1001 ap->ops = &ahci_p5wdh_ops;
1002 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1003 }
1004}
1005
1006/*
1007 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1008 * booting in BIOS compatibility mode. We restore the registers but not ID.
1009 */
1010static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1011{
1012 u32 val;
1013
1014 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1015
1016 pci_read_config_dword(pdev, 0xf8, &val);
1017 val |= 1 << 0x1b;
1018 /* the following changes the device ID, but appears not to affect function */
1019 /* val = (val & ~0xf0000000) | 0x80000000; */
1020 pci_write_config_dword(pdev, 0xf8, val);
1021
1022 pci_read_config_dword(pdev, 0x54c, &val);
1023 val |= 1 << 0xc;
1024 pci_write_config_dword(pdev, 0x54c, val);
1025
1026 pci_read_config_dword(pdev, 0x4a4, &val);
1027 val &= 0xff;
1028 val |= 0x01060100;
1029 pci_write_config_dword(pdev, 0x4a4, val);
1030
1031 pci_read_config_dword(pdev, 0x54c, &val);
1032 val &= ~(1 << 0xc);
1033 pci_write_config_dword(pdev, 0x54c, val);
1034
1035 pci_read_config_dword(pdev, 0xf8, &val);
1036 val &= ~(1 << 0x1b);
1037 pci_write_config_dword(pdev, 0xf8, val);
1038}
1039
1040static bool is_mcp89_apple(struct pci_dev *pdev)
1041{
1042 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1043 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1044 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1045 pdev->subsystem_device == 0xcb89;
1046}
1047
1048/* only some SB600 ahci controllers can do 64bit DMA */
1049static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1050{
1051 static const struct dmi_system_id sysids[] = {
1052 /*
1053 * The oldest version known to be broken is 0901 and
1054 * working is 1501 which was released on 2007-10-26.
1055 * Enable 64bit DMA on 1501 and anything newer.
1056 *
1057 * Please read bko#9412 for more info.
1058 */
1059 {
1060 .ident = "ASUS M2A-VM",
1061 .matches = {
1062 DMI_MATCH(DMI_BOARD_VENDOR,
1063 "ASUSTeK Computer INC."),
1064 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1065 },
1066 .driver_data = "20071026", /* yyyymmdd */
1067 },
1068 /*
1069 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1070 * support 64bit DMA.
1071 *
1072 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1073 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1074 * This spelling mistake was fixed in BIOS version 1.5, so
1075 * 1.5 and later have the Manufacturer as
1076 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1077 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1078 *
1079 * BIOS versions earlier than 1.9 had a Board Product Name
1080 * DMI field of "MS-7376". This was changed to be
1081 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1082 * match on DMI_BOARD_NAME of "MS-7376".
1083 */
1084 {
1085 .ident = "MSI K9A2 Platinum",
1086 .matches = {
1087 DMI_MATCH(DMI_BOARD_VENDOR,
1088 "MICRO-STAR INTER"),
1089 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1090 },
1091 },
1092 /*
1093 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1094 * 64bit DMA.
1095 *
1096 * This board also had the typo mentioned above in the
1097 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1098 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1099 */
1100 {
1101 .ident = "MSI K9AGM2",
1102 .matches = {
1103 DMI_MATCH(DMI_BOARD_VENDOR,
1104 "MICRO-STAR INTER"),
1105 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1106 },
1107 },
1108 /*
1109 * All BIOS versions for the Asus M3A support 64bit DMA.
1110 * (all release versions from 0301 to 1206 were tested)
1111 */
1112 {
1113 .ident = "ASUS M3A",
1114 .matches = {
1115 DMI_MATCH(DMI_BOARD_VENDOR,
1116 "ASUSTeK Computer INC."),
1117 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1118 },
1119 },
1120 { }
1121 };
1122 const struct dmi_system_id *match;
1123 int year, month, date;
1124 char buf[9];
1125
1126 match = dmi_first_match(sysids);
1127 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1128 !match)
1129 return false;
1130
1131 if (!match->driver_data)
1132 goto enable_64bit;
1133
1134 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1135 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1136
1137 if (strcmp(buf, match->driver_data) >= 0)
1138 goto enable_64bit;
1139 else {
1140 dev_warn(&pdev->dev,
1141 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1142 match->ident);
1143 return false;
1144 }
1145
1146enable_64bit:
1147 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1148 return true;
1149}
1150
1151static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1152{
1153 static const struct dmi_system_id broken_systems[] = {
1154 {
1155 .ident = "HP Compaq nx6310",
1156 .matches = {
1157 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1158 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1159 },
1160 /* PCI slot number of the controller */
1161 .driver_data = (void *)0x1FUL,
1162 },
1163 {
1164 .ident = "HP Compaq 6720s",
1165 .matches = {
1166 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1167 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1168 },
1169 /* PCI slot number of the controller */
1170 .driver_data = (void *)0x1FUL,
1171 },
1172
1173 { } /* terminate list */
1174 };
1175 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1176
1177 if (dmi) {
1178 unsigned long slot = (unsigned long)dmi->driver_data;
1179 /* apply the quirk only to on-board controllers */
1180 return slot == PCI_SLOT(pdev->devfn);
1181 }
1182
1183 return false;
1184}
1185
1186static bool ahci_broken_suspend(struct pci_dev *pdev)
1187{
1188 static const struct dmi_system_id sysids[] = {
1189 /*
1190 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1191 * to the harddisk doesn't become online after
1192 * resuming from STR. Warn and fail suspend.
1193 *
1194 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1195 *
1196 * Use dates instead of versions to match as HP is
1197 * apparently recycling both product and version
1198 * strings.
1199 *
1200 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1201 */
1202 {
1203 .ident = "dv4",
1204 .matches = {
1205 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1206 DMI_MATCH(DMI_PRODUCT_NAME,
1207 "HP Pavilion dv4 Notebook PC"),
1208 },
1209 .driver_data = "20090105", /* F.30 */
1210 },
1211 {
1212 .ident = "dv5",
1213 .matches = {
1214 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1215 DMI_MATCH(DMI_PRODUCT_NAME,
1216 "HP Pavilion dv5 Notebook PC"),
1217 },
1218 .driver_data = "20090506", /* F.16 */
1219 },
1220 {
1221 .ident = "dv6",
1222 .matches = {
1223 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1224 DMI_MATCH(DMI_PRODUCT_NAME,
1225 "HP Pavilion dv6 Notebook PC"),
1226 },
1227 .driver_data = "20090423", /* F.21 */
1228 },
1229 {
1230 .ident = "HDX18",
1231 .matches = {
1232 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1233 DMI_MATCH(DMI_PRODUCT_NAME,
1234 "HP HDX18 Notebook PC"),
1235 },
1236 .driver_data = "20090430", /* F.23 */
1237 },
1238 /*
1239 * Acer eMachines G725 has the same problem. BIOS
1240 * V1.03 is known to be broken. V3.04 is known to
1241 * work. Between, there are V1.06, V2.06 and V3.03
1242 * that we don't have much idea about. For now,
1243 * blacklist anything older than V3.04.
1244 *
1245 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1246 */
1247 {
1248 .ident = "G725",
1249 .matches = {
1250 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1251 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1252 },
1253 .driver_data = "20091216", /* V3.04 */
1254 },
1255 { } /* terminate list */
1256 };
1257 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1258 int year, month, date;
1259 char buf[9];
1260
1261 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1262 return false;
1263
1264 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1265 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1266
1267 return strcmp(buf, dmi->driver_data) < 0;
1268}
1269
1270static bool ahci_broken_lpm(struct pci_dev *pdev)
1271{
1272 static const struct dmi_system_id sysids[] = {
1273 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1274 {
1275 .matches = {
1276 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1277 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1278 },
1279 .driver_data = "20180406", /* 1.31 */
1280 },
1281 {
1282 .matches = {
1283 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1284 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1285 },
1286 .driver_data = "20180420", /* 1.28 */
1287 },
1288 {
1289 .matches = {
1290 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1291 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1292 },
1293 .driver_data = "20180315", /* 1.33 */
1294 },
1295 {
1296 .matches = {
1297 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1298 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1299 },
1300 /*
1301 * Note date based on release notes, 2.35 has been
1302 * reported to be good, but I've been unable to get
1303 * a hold of the reporter to get the DMI BIOS date.
1304 * TODO: fix this.
1305 */
1306 .driver_data = "20180310", /* 2.35 */
1307 },
1308 { } /* terminate list */
1309 };
1310 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1311 int year, month, date;
1312 char buf[9];
1313
1314 if (!dmi)
1315 return false;
1316
1317 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1318 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1319
1320 return strcmp(buf, dmi->driver_data) < 0;
1321}
1322
1323static bool ahci_broken_online(struct pci_dev *pdev)
1324{
1325#define ENCODE_BUSDEVFN(bus, slot, func) \
1326 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1327 static const struct dmi_system_id sysids[] = {
1328 /*
1329 * There are several gigabyte boards which use
1330 * SIMG5723s configured as hardware RAID. Certain
1331 * 5723 firmware revisions shipped there keep the link
1332 * online but fail to answer properly to SRST or
1333 * IDENTIFY when no device is attached downstream
1334 * causing libata to retry quite a few times leading
1335 * to excessive detection delay.
1336 *
1337 * As these firmwares respond to the second reset try
1338 * with invalid device signature, considering unknown
1339 * sig as offline works around the problem acceptably.
1340 */
1341 {
1342 .ident = "EP45-DQ6",
1343 .matches = {
1344 DMI_MATCH(DMI_BOARD_VENDOR,
1345 "Gigabyte Technology Co., Ltd."),
1346 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1347 },
1348 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1349 },
1350 {
1351 .ident = "EP45-DS5",
1352 .matches = {
1353 DMI_MATCH(DMI_BOARD_VENDOR,
1354 "Gigabyte Technology Co., Ltd."),
1355 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1356 },
1357 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1358 },
1359 { } /* terminate list */
1360 };
1361#undef ENCODE_BUSDEVFN
1362 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1363 unsigned int val;
1364
1365 if (!dmi)
1366 return false;
1367
1368 val = (unsigned long)dmi->driver_data;
1369
1370 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1371}
1372
1373static bool ahci_broken_devslp(struct pci_dev *pdev)
1374{
1375 /* device with broken DEVSLP but still showing SDS capability */
1376 static const struct pci_device_id ids[] = {
1377 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1378 {}
1379 };
1380
1381 return pci_match_id(ids, pdev);
1382}
1383
1384#ifdef CONFIG_ATA_ACPI
1385static void ahci_gtf_filter_workaround(struct ata_host *host)
1386{
1387 static const struct dmi_system_id sysids[] = {
1388 /*
1389 * Aspire 3810T issues a bunch of SATA enable commands
1390 * via _GTF including an invalid one and one which is
1391 * rejected by the device. Among the successful ones
1392 * is FPDMA non-zero offset enable which when enabled
1393 * only on the drive side leads to NCQ command
1394 * failures. Filter it out.
1395 */
1396 {
1397 .ident = "Aspire 3810T",
1398 .matches = {
1399 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1400 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1401 },
1402 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1403 },
1404 { }
1405 };
1406 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1407 unsigned int filter;
1408 int i;
1409
1410 if (!dmi)
1411 return;
1412
1413 filter = (unsigned long)dmi->driver_data;
1414 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1415 filter, dmi->ident);
1416
1417 for (i = 0; i < host->n_ports; i++) {
1418 struct ata_port *ap = host->ports[i];
1419 struct ata_link *link;
1420 struct ata_device *dev;
1421
1422 ata_for_each_link(link, ap, EDGE)
1423 ata_for_each_dev(dev, link, ALL)
1424 dev->gtf_filter |= filter;
1425 }
1426}
1427#else
1428static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1429{}
1430#endif
1431
1432/*
1433 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1434 * as DUMMY, or detected but eventually get a "link down" and never get up
1435 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1436 * port_map may hold a value of 0x00.
1437 *
1438 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1439 * and can significantly reduce the occurrence of the problem.
1440 *
1441 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1442 */
1443static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1444 struct pci_dev *pdev)
1445{
1446 static const struct dmi_system_id sysids[] = {
1447 {
1448 .ident = "Acer Switch Alpha 12",
1449 .matches = {
1450 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1451 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1452 },
1453 },
1454 { }
1455 };
1456
1457 if (dmi_check_system(sysids)) {
1458 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1459 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1460 hpriv->port_map = 0x7;
1461 hpriv->cap = 0xC734FF02;
1462 }
1463 }
1464}
1465
1466#ifdef CONFIG_ARM64
1467/*
1468 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1469 * Workaround is to make sure all pending IRQs are served before leaving
1470 * handler.
1471 */
1472static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1473{
1474 struct ata_host *host = dev_instance;
1475 struct ahci_host_priv *hpriv;
1476 unsigned int rc = 0;
1477 void __iomem *mmio;
1478 u32 irq_stat, irq_masked;
1479 unsigned int handled = 1;
1480
1481 VPRINTK("ENTER\n");
1482 hpriv = host->private_data;
1483 mmio = hpriv->mmio;
1484 irq_stat = readl(mmio + HOST_IRQ_STAT);
1485 if (!irq_stat)
1486 return IRQ_NONE;
1487
1488 do {
1489 irq_masked = irq_stat & hpriv->port_map;
1490 spin_lock(&host->lock);
1491 rc = ahci_handle_port_intr(host, irq_masked);
1492 if (!rc)
1493 handled = 0;
1494 writel(irq_stat, mmio + HOST_IRQ_STAT);
1495 irq_stat = readl(mmio + HOST_IRQ_STAT);
1496 spin_unlock(&host->lock);
1497 } while (irq_stat);
1498 VPRINTK("EXIT\n");
1499
1500 return IRQ_RETVAL(handled);
1501}
1502#endif
1503
1504static void ahci_remap_check(struct pci_dev *pdev, int bar,
1505 struct ahci_host_priv *hpriv)
1506{
1507 int i, count = 0;
1508 u32 cap;
1509
1510 /*
1511 * Check if this device might have remapped nvme devices.
1512 */
1513 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1514 pci_resource_len(pdev, bar) < SZ_512K ||
1515 bar != AHCI_PCI_BAR_STANDARD ||
1516 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1517 return;
1518
1519 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1520 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1521 if ((cap & (1 << i)) == 0)
1522 continue;
1523 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1524 != PCI_CLASS_STORAGE_EXPRESS)
1525 continue;
1526
1527 /* We've found a remapped device */
1528 count++;
1529 }
1530
1531 if (!count)
1532 return;
1533
1534 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1535 dev_warn(&pdev->dev,
1536 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1537
1538 /*
1539 * Don't rely on the msi-x capability in the remap case,
1540 * share the legacy interrupt across ahci and remapped devices.
1541 */
1542 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1543}
1544
1545static int ahci_get_irq_vector(struct ata_host *host, int port)
1546{
1547 return pci_irq_vector(to_pci_dev(host->dev), port);
1548}
1549
1550static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1551 struct ahci_host_priv *hpriv)
1552{
1553 int nvec;
1554
1555 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1556 return -ENODEV;
1557
1558 /*
1559 * If number of MSIs is less than number of ports then Sharing Last
1560 * Message mode could be enforced. In this case assume that advantage
1561 * of multipe MSIs is negated and use single MSI mode instead.
1562 */
1563 if (n_ports > 1) {
1564 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1565 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1566 if (nvec > 0) {
1567 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1568 hpriv->get_irq_vector = ahci_get_irq_vector;
1569 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1570 return nvec;
1571 }
1572
1573 /*
1574 * Fallback to single MSI mode if the controller
1575 * enforced MRSM mode.
1576 */
1577 printk(KERN_INFO
1578 "ahci: MRSM is on, fallback to single MSI\n");
1579 pci_free_irq_vectors(pdev);
1580 }
1581 }
1582
1583 /*
1584 * If the host is not capable of supporting per-port vectors, fall
1585 * back to single MSI before finally attempting single MSI-X.
1586 */
1587 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1588 if (nvec == 1)
1589 return nvec;
1590 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1591}
1592
1593static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1594{
1595 unsigned int board_id = ent->driver_data;
1596 struct ata_port_info pi = ahci_port_info[board_id];
1597 const struct ata_port_info *ppi[] = { &pi, NULL };
1598 struct device *dev = &pdev->dev;
1599 struct ahci_host_priv *hpriv;
1600 struct ata_host *host;
1601 int n_ports, i, rc;
1602 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1603
1604 VPRINTK("ENTER\n");
1605
1606 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1607
1608 ata_print_version_once(&pdev->dev, DRV_VERSION);
1609
1610 /* The AHCI driver can only drive the SATA ports, the PATA driver
1611 can drive them all so if both drivers are selected make sure
1612 AHCI stays out of the way */
1613 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1614 return -ENODEV;
1615
1616 /* Apple BIOS on MCP89 prevents us using AHCI */
1617 if (is_mcp89_apple(pdev))
1618 ahci_mcp89_apple_enable(pdev);
1619
1620 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1621 * At the moment, we can only use the AHCI mode. Let the users know
1622 * that for SAS drives they're out of luck.
1623 */
1624 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1625 dev_info(&pdev->dev,
1626 "PDC42819 can only drive SATA devices with this driver\n");
1627
1628 /* Some devices use non-standard BARs */
1629 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1630 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1631 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1632 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1633 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1634 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1635
1636 /* acquire resources */
1637 rc = pcim_enable_device(pdev);
1638 if (rc)
1639 return rc;
1640
1641 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1642 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1643 u8 map;
1644
1645 /* ICH6s share the same PCI ID for both piix and ahci
1646 * modes. Enabling ahci mode while MAP indicates
1647 * combined mode is a bad idea. Yield to ata_piix.
1648 */
1649 pci_read_config_byte(pdev, ICH_MAP, &map);
1650 if (map & 0x3) {
1651 dev_info(&pdev->dev,
1652 "controller is in combined mode, can't enable AHCI mode\n");
1653 return -ENODEV;
1654 }
1655 }
1656
1657 /* AHCI controllers often implement SFF compatible interface.
1658 * Grab all PCI BARs just in case.
1659 */
1660 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1661 if (rc == -EBUSY)
1662 pcim_pin_device(pdev);
1663 if (rc)
1664 return rc;
1665
1666 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1667 if (!hpriv)
1668 return -ENOMEM;
1669 hpriv->flags |= (unsigned long)pi.private_data;
1670
1671 /* MCP65 revision A1 and A2 can't do MSI */
1672 if (board_id == board_ahci_mcp65 &&
1673 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1674 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1675
1676 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1677 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1678 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1679
1680 /* only some SB600s can do 64bit DMA */
1681 if (ahci_sb600_enable_64bit(pdev))
1682 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1683
1684 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1685
1686 /* detect remapped nvme devices */
1687 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1688
1689 /* must set flag prior to save config in order to take effect */
1690 if (ahci_broken_devslp(pdev))
1691 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1692
1693#ifdef CONFIG_ARM64
1694 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1695 hpriv->irq_handler = ahci_thunderx_irq_handler;
1696#endif
1697
1698 /* save initial config */
1699 ahci_pci_save_initial_config(pdev, hpriv);
1700
1701 /* prepare host */
1702 if (hpriv->cap & HOST_CAP_NCQ) {
1703 pi.flags |= ATA_FLAG_NCQ;
1704 /*
1705 * Auto-activate optimization is supposed to be
1706 * supported on all AHCI controllers indicating NCQ
1707 * capability, but it seems to be broken on some
1708 * chipsets including NVIDIAs.
1709 */
1710 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1711 pi.flags |= ATA_FLAG_FPDMA_AA;
1712
1713 /*
1714 * All AHCI controllers should be forward-compatible
1715 * with the new auxiliary field. This code should be
1716 * conditionalized if any buggy AHCI controllers are
1717 * encountered.
1718 */
1719 pi.flags |= ATA_FLAG_FPDMA_AUX;
1720 }
1721
1722 if (hpriv->cap & HOST_CAP_PMP)
1723 pi.flags |= ATA_FLAG_PMP;
1724
1725 ahci_set_em_messages(hpriv, &pi);
1726
1727 if (ahci_broken_system_poweroff(pdev)) {
1728 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1729 dev_info(&pdev->dev,
1730 "quirky BIOS, skipping spindown on poweroff\n");
1731 }
1732
1733 if (ahci_broken_lpm(pdev)) {
1734 pi.flags |= ATA_FLAG_NO_LPM;
1735 dev_warn(&pdev->dev,
1736 "BIOS update required for Link Power Management support\n");
1737 }
1738
1739 if (ahci_broken_suspend(pdev)) {
1740 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1741 dev_warn(&pdev->dev,
1742 "BIOS update required for suspend/resume\n");
1743 }
1744
1745 if (ahci_broken_online(pdev)) {
1746 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1747 dev_info(&pdev->dev,
1748 "online status unreliable, applying workaround\n");
1749 }
1750
1751
1752 /* Acer SA5-271 workaround modifies private_data */
1753 acer_sa5_271_workaround(hpriv, pdev);
1754
1755 /* CAP.NP sometimes indicate the index of the last enabled
1756 * port, at other times, that of the last possible port, so
1757 * determining the maximum port number requires looking at
1758 * both CAP.NP and port_map.
1759 */
1760 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1761
1762 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1763 if (!host)
1764 return -ENOMEM;
1765 host->private_data = hpriv;
1766
1767 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1768 /* legacy intx interrupts */
1769 pci_intx(pdev, 1);
1770 }
1771 hpriv->irq = pci_irq_vector(pdev, 0);
1772
1773 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1774 host->flags |= ATA_HOST_PARALLEL_SCAN;
1775 else
1776 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1777
1778 if (pi.flags & ATA_FLAG_EM)
1779 ahci_reset_em(host);
1780
1781 for (i = 0; i < host->n_ports; i++) {
1782 struct ata_port *ap = host->ports[i];
1783
1784 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1785 ata_port_pbar_desc(ap, ahci_pci_bar,
1786 0x100 + ap->port_no * 0x80, "port");
1787
1788 /* set enclosure management message type */
1789 if (ap->flags & ATA_FLAG_EM)
1790 ap->em_message_type = hpriv->em_msg_type;
1791
1792
1793 /* disabled/not-implemented port */
1794 if (!(hpriv->port_map & (1 << i)))
1795 ap->ops = &ata_dummy_port_ops;
1796 }
1797
1798 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1799 ahci_p5wdh_workaround(host);
1800
1801 /* apply gtf filter quirk */
1802 ahci_gtf_filter_workaround(host);
1803
1804 /* initialize adapter */
1805 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1806 if (rc)
1807 return rc;
1808
1809 rc = ahci_pci_reset_controller(host);
1810 if (rc)
1811 return rc;
1812
1813 ahci_pci_init_controller(host);
1814 ahci_pci_print_info(host);
1815
1816 pci_set_master(pdev);
1817
1818 rc = ahci_host_activate(host, &ahci_sht);
1819 if (rc)
1820 return rc;
1821
1822 pm_runtime_put_noidle(&pdev->dev);
1823 return 0;
1824}
1825
1826static void ahci_remove_one(struct pci_dev *pdev)
1827{
1828 pm_runtime_get_noresume(&pdev->dev);
1829 ata_pci_remove_one(pdev);
1830}
1831
1832module_pci_driver(ahci_pci_driver);
1833
1834MODULE_AUTHOR("Jeff Garzik");
1835MODULE_DESCRIPTION("AHCI SATA low-level driver");
1836MODULE_LICENSE("GPL");
1837MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1838MODULE_VERSION(DRV_VERSION);