| 1 | /* |
| 2 | * mmconfig-shared.c - Low-level direct PCI config space access via |
| 3 | * MMCONFIG - common code between i386 and x86-64. |
| 4 | * |
| 5 | * This code does: |
| 6 | * - known chipset handling |
| 7 | * - ACPI decoding and validation |
| 8 | * |
| 9 | * Per-architecture code takes care of the mappings and accesses |
| 10 | * themselves. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/pci.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/acpi.h> |
| 16 | #include <linux/bitmap.h> |
| 17 | #include <asm/e820.h> |
| 18 | |
| 19 | #include "pci.h" |
| 20 | |
| 21 | /* aperture is up to 256MB but BIOS may reserve less */ |
| 22 | #define MMCONFIG_APER_MIN (2 * 1024*1024) |
| 23 | #define MMCONFIG_APER_MAX (256 * 1024*1024) |
| 24 | |
| 25 | /* Indicate if the mmcfg resources have been placed into the resource table. */ |
| 26 | static int __initdata pci_mmcfg_resources_inserted; |
| 27 | |
| 28 | static const char __init *pci_mmcfg_e7520(void) |
| 29 | { |
| 30 | u32 win; |
| 31 | pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win); |
| 32 | |
| 33 | win = win & 0xf000; |
| 34 | if(win == 0x0000 || win == 0xf000) |
| 35 | pci_mmcfg_config_num = 0; |
| 36 | else { |
| 37 | pci_mmcfg_config_num = 1; |
| 38 | pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL); |
| 39 | if (!pci_mmcfg_config) |
| 40 | return NULL; |
| 41 | pci_mmcfg_config[0].address = win << 16; |
| 42 | pci_mmcfg_config[0].pci_segment = 0; |
| 43 | pci_mmcfg_config[0].start_bus_number = 0; |
| 44 | pci_mmcfg_config[0].end_bus_number = 255; |
| 45 | } |
| 46 | |
| 47 | return "Intel Corporation E7520 Memory Controller Hub"; |
| 48 | } |
| 49 | |
| 50 | static const char __init *pci_mmcfg_intel_945(void) |
| 51 | { |
| 52 | u32 pciexbar, mask = 0, len = 0; |
| 53 | |
| 54 | pci_mmcfg_config_num = 1; |
| 55 | |
| 56 | pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar); |
| 57 | |
| 58 | /* Enable bit */ |
| 59 | if (!(pciexbar & 1)) |
| 60 | pci_mmcfg_config_num = 0; |
| 61 | |
| 62 | /* Size bits */ |
| 63 | switch ((pciexbar >> 1) & 3) { |
| 64 | case 0: |
| 65 | mask = 0xf0000000U; |
| 66 | len = 0x10000000U; |
| 67 | break; |
| 68 | case 1: |
| 69 | mask = 0xf8000000U; |
| 70 | len = 0x08000000U; |
| 71 | break; |
| 72 | case 2: |
| 73 | mask = 0xfc000000U; |
| 74 | len = 0x04000000U; |
| 75 | break; |
| 76 | default: |
| 77 | pci_mmcfg_config_num = 0; |
| 78 | } |
| 79 | |
| 80 | /* Errata #2, things break when not aligned on a 256Mb boundary */ |
| 81 | /* Can only happen in 64M/128M mode */ |
| 82 | |
| 83 | if ((pciexbar & mask) & 0x0fffffffU) |
| 84 | pci_mmcfg_config_num = 0; |
| 85 | |
| 86 | /* Don't hit the APIC registers and their friends */ |
| 87 | if ((pciexbar & mask) >= 0xf0000000U) |
| 88 | pci_mmcfg_config_num = 0; |
| 89 | |
| 90 | if (pci_mmcfg_config_num) { |
| 91 | pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL); |
| 92 | if (!pci_mmcfg_config) |
| 93 | return NULL; |
| 94 | pci_mmcfg_config[0].address = pciexbar & mask; |
| 95 | pci_mmcfg_config[0].pci_segment = 0; |
| 96 | pci_mmcfg_config[0].start_bus_number = 0; |
| 97 | pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1; |
| 98 | } |
| 99 | |
| 100 | return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; |
| 101 | } |
| 102 | |
| 103 | struct pci_mmcfg_hostbridge_probe { |
| 104 | u32 vendor; |
| 105 | u32 device; |
| 106 | const char *(*probe)(void); |
| 107 | }; |
| 108 | |
| 109 | static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { |
| 110 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, |
| 111 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, |
| 112 | }; |
| 113 | |
| 114 | static int __init pci_mmcfg_check_hostbridge(void) |
| 115 | { |
| 116 | u32 l; |
| 117 | u16 vendor, device; |
| 118 | int i; |
| 119 | const char *name; |
| 120 | |
| 121 | pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0, 4, &l); |
| 122 | vendor = l & 0xffff; |
| 123 | device = (l >> 16) & 0xffff; |
| 124 | |
| 125 | pci_mmcfg_config_num = 0; |
| 126 | pci_mmcfg_config = NULL; |
| 127 | name = NULL; |
| 128 | |
| 129 | for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) { |
| 130 | if (pci_mmcfg_probes[i].vendor == vendor && |
| 131 | pci_mmcfg_probes[i].device == device) |
| 132 | name = pci_mmcfg_probes[i].probe(); |
| 133 | } |
| 134 | |
| 135 | if (name) { |
| 136 | printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n", |
| 137 | name, pci_mmcfg_config_num ? "with" : "without"); |
| 138 | } |
| 139 | |
| 140 | return name != NULL; |
| 141 | } |
| 142 | |
| 143 | static void __init pci_mmcfg_insert_resources(unsigned long resource_flags) |
| 144 | { |
| 145 | #define PCI_MMCFG_RESOURCE_NAME_LEN 19 |
| 146 | int i; |
| 147 | struct resource *res; |
| 148 | char *names; |
| 149 | unsigned num_buses; |
| 150 | |
| 151 | res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res), |
| 152 | pci_mmcfg_config_num, GFP_KERNEL); |
| 153 | if (!res) { |
| 154 | printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n"); |
| 155 | return; |
| 156 | } |
| 157 | |
| 158 | names = (void *)&res[pci_mmcfg_config_num]; |
| 159 | for (i = 0; i < pci_mmcfg_config_num; i++, res++) { |
| 160 | struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i]; |
| 161 | num_buses = cfg->end_bus_number - cfg->start_bus_number + 1; |
| 162 | res->name = names; |
| 163 | snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u", |
| 164 | cfg->pci_segment); |
| 165 | res->start = cfg->address; |
| 166 | res->end = res->start + (num_buses << 20) - 1; |
| 167 | res->flags = IORESOURCE_MEM | resource_flags; |
| 168 | insert_resource(&iomem_resource, res); |
| 169 | names += PCI_MMCFG_RESOURCE_NAME_LEN; |
| 170 | } |
| 171 | |
| 172 | /* Mark that the resources have been inserted. */ |
| 173 | pci_mmcfg_resources_inserted = 1; |
| 174 | } |
| 175 | |
| 176 | static acpi_status __init check_mcfg_resource(struct acpi_resource *res, |
| 177 | void *data) |
| 178 | { |
| 179 | struct resource *mcfg_res = data; |
| 180 | struct acpi_resource_address64 address; |
| 181 | acpi_status status; |
| 182 | |
| 183 | if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { |
| 184 | struct acpi_resource_fixed_memory32 *fixmem32 = |
| 185 | &res->data.fixed_memory32; |
| 186 | if (!fixmem32) |
| 187 | return AE_OK; |
| 188 | if ((mcfg_res->start >= fixmem32->address) && |
| 189 | (mcfg_res->end < (fixmem32->address + |
| 190 | fixmem32->address_length))) { |
| 191 | mcfg_res->flags = 1; |
| 192 | return AE_CTRL_TERMINATE; |
| 193 | } |
| 194 | } |
| 195 | if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && |
| 196 | (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) |
| 197 | return AE_OK; |
| 198 | |
| 199 | status = acpi_resource_to_address64(res, &address); |
| 200 | if (ACPI_FAILURE(status) || |
| 201 | (address.address_length <= 0) || |
| 202 | (address.resource_type != ACPI_MEMORY_RANGE)) |
| 203 | return AE_OK; |
| 204 | |
| 205 | if ((mcfg_res->start >= address.minimum) && |
| 206 | (mcfg_res->end < (address.minimum + address.address_length))) { |
| 207 | mcfg_res->flags = 1; |
| 208 | return AE_CTRL_TERMINATE; |
| 209 | } |
| 210 | return AE_OK; |
| 211 | } |
| 212 | |
| 213 | static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, |
| 214 | void *context, void **rv) |
| 215 | { |
| 216 | struct resource *mcfg_res = context; |
| 217 | |
| 218 | acpi_walk_resources(handle, METHOD_NAME__CRS, |
| 219 | check_mcfg_resource, context); |
| 220 | |
| 221 | if (mcfg_res->flags) |
| 222 | return AE_CTRL_TERMINATE; |
| 223 | |
| 224 | return AE_OK; |
| 225 | } |
| 226 | |
| 227 | static int __init is_acpi_reserved(unsigned long start, unsigned long end) |
| 228 | { |
| 229 | struct resource mcfg_res; |
| 230 | |
| 231 | mcfg_res.start = start; |
| 232 | mcfg_res.end = end; |
| 233 | mcfg_res.flags = 0; |
| 234 | |
| 235 | acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); |
| 236 | |
| 237 | if (!mcfg_res.flags) |
| 238 | acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, |
| 239 | NULL); |
| 240 | |
| 241 | return mcfg_res.flags; |
| 242 | } |
| 243 | |
| 244 | static void __init pci_mmcfg_reject_broken(void) |
| 245 | { |
| 246 | typeof(pci_mmcfg_config[0]) *cfg; |
| 247 | int i; |
| 248 | |
| 249 | if ((pci_mmcfg_config_num == 0) || |
| 250 | (pci_mmcfg_config == NULL) || |
| 251 | (pci_mmcfg_config[0].address == 0)) |
| 252 | return; |
| 253 | |
| 254 | cfg = &pci_mmcfg_config[0]; |
| 255 | |
| 256 | /* |
| 257 | * Handle more broken MCFG tables on Asus etc. |
| 258 | * They only contain a single entry for bus 0-0. |
| 259 | */ |
| 260 | if (pci_mmcfg_config_num == 1 && |
| 261 | cfg->pci_segment == 0 && |
| 262 | (cfg->start_bus_number | cfg->end_bus_number) == 0) { |
| 263 | printk(KERN_ERR "PCI: start and end of bus number is 0. " |
| 264 | "Rejected as broken MCFG.\n"); |
| 265 | goto reject; |
| 266 | } |
| 267 | |
| 268 | for (i = 0; i < pci_mmcfg_config_num; i++) { |
| 269 | u32 size = (cfg->end_bus_number + 1) << 20; |
| 270 | cfg = &pci_mmcfg_config[i]; |
| 271 | printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lu " |
| 272 | "segment %hu buses %u - %u\n", |
| 273 | i, (unsigned long)cfg->address, cfg->pci_segment, |
| 274 | (unsigned int)cfg->start_bus_number, |
| 275 | (unsigned int)cfg->end_bus_number); |
| 276 | if (is_acpi_reserved(cfg->address, cfg->address + size - 1)) { |
| 277 | printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved " |
| 278 | "in ACPI motherboard resources\n", |
| 279 | cfg->address); |
| 280 | } else { |
| 281 | printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not" |
| 282 | " reserved in ACPI motherboard resources\n", |
| 283 | cfg->address); |
| 284 | /* Don't try to do this check unless configuration |
| 285 | type 1 is available. */ |
| 286 | if ((pci_probe & PCI_PROBE_CONF1) && |
| 287 | e820_all_mapped(cfg->address, |
| 288 | cfg->address + size - 1, |
| 289 | E820_RESERVED)) |
| 290 | printk(KERN_NOTICE |
| 291 | "PCI: MCFG area at %Lx reserved in " |
| 292 | "E820\n", |
| 293 | cfg->address); |
| 294 | else |
| 295 | goto reject; |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | return; |
| 300 | |
| 301 | reject: |
| 302 | printk(KERN_ERR "PCI: Not using MMCONFIG.\n"); |
| 303 | pci_mmcfg_arch_free(); |
| 304 | kfree(pci_mmcfg_config); |
| 305 | pci_mmcfg_config = NULL; |
| 306 | pci_mmcfg_config_num = 0; |
| 307 | } |
| 308 | |
| 309 | void __init pci_mmcfg_early_init(int type) |
| 310 | { |
| 311 | if ((pci_probe & PCI_PROBE_MMCONF) == 0) |
| 312 | return; |
| 313 | |
| 314 | /* If type 1 access is available, no need to enable MMCONFIG yet, we can |
| 315 | defer until later when the ACPI interpreter is available to better |
| 316 | validate things. */ |
| 317 | if (type == 1) |
| 318 | return; |
| 319 | |
| 320 | acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg); |
| 321 | |
| 322 | if ((pci_mmcfg_config_num == 0) || |
| 323 | (pci_mmcfg_config == NULL) || |
| 324 | (pci_mmcfg_config[0].address == 0)) |
| 325 | return; |
| 326 | |
| 327 | if (pci_mmcfg_arch_init()) |
| 328 | pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; |
| 329 | } |
| 330 | |
| 331 | void __init pci_mmcfg_late_init(void) |
| 332 | { |
| 333 | int known_bridge = 0; |
| 334 | |
| 335 | /* MMCONFIG disabled */ |
| 336 | if ((pci_probe & PCI_PROBE_MMCONF) == 0) |
| 337 | return; |
| 338 | |
| 339 | /* MMCONFIG already enabled */ |
| 340 | if (!(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) |
| 341 | return; |
| 342 | |
| 343 | if ((pci_probe & PCI_PROBE_CONF1) && pci_mmcfg_check_hostbridge()) |
| 344 | known_bridge = 1; |
| 345 | else |
| 346 | acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg); |
| 347 | |
| 348 | pci_mmcfg_reject_broken(); |
| 349 | |
| 350 | if ((pci_mmcfg_config_num == 0) || |
| 351 | (pci_mmcfg_config == NULL) || |
| 352 | (pci_mmcfg_config[0].address == 0)) |
| 353 | return; |
| 354 | |
| 355 | if (pci_mmcfg_arch_init()) { |
| 356 | if (known_bridge) |
| 357 | pci_mmcfg_insert_resources(IORESOURCE_BUSY); |
| 358 | pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; |
| 359 | } else { |
| 360 | /* |
| 361 | * Signal not to attempt to insert mmcfg resources because |
| 362 | * the architecture mmcfg setup could not initialize. |
| 363 | */ |
| 364 | pci_mmcfg_resources_inserted = 1; |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | static int __init pci_mmcfg_late_insert_resources(void) |
| 369 | { |
| 370 | /* |
| 371 | * If resources are already inserted or we are not using MMCONFIG, |
| 372 | * don't insert the resources. |
| 373 | */ |
| 374 | if ((pci_mmcfg_resources_inserted == 1) || |
| 375 | (pci_probe & PCI_PROBE_MMCONF) == 0 || |
| 376 | (pci_mmcfg_config_num == 0) || |
| 377 | (pci_mmcfg_config == NULL) || |
| 378 | (pci_mmcfg_config[0].address == 0)) |
| 379 | return 1; |
| 380 | |
| 381 | /* |
| 382 | * Attempt to insert the mmcfg resources but not with the busy flag |
| 383 | * marked so it won't cause request errors when __request_region is |
| 384 | * called. |
| 385 | */ |
| 386 | pci_mmcfg_insert_resources(0); |
| 387 | |
| 388 | return 0; |
| 389 | } |
| 390 | |
| 391 | /* |
| 392 | * Perform MMCONFIG resource insertion after PCI initialization to allow for |
| 393 | * misprogrammed MCFG tables that state larger sizes but actually conflict |
| 394 | * with other system resources. |
| 395 | */ |
| 396 | late_initcall(pci_mmcfg_late_insert_resources); |