| 1 | /* |
| 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
| 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version |
| 8 | * 2 of the License, or (at your option) any later version. |
| 9 | * |
| 10 | * Modified by Cort Dougan (cort@cs.nmt.edu) |
| 11 | * and Paul Mackerras (paulus@samba.org) |
| 12 | */ |
| 13 | |
| 14 | /* |
| 15 | * This file handles the architecture-dependent parts of hardware exceptions |
| 16 | */ |
| 17 | |
| 18 | #include <linux/errno.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/mm.h> |
| 22 | #include <linux/stddef.h> |
| 23 | #include <linux/unistd.h> |
| 24 | #include <linux/ptrace.h> |
| 25 | #include <linux/user.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/init.h> |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/prctl.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/kprobes.h> |
| 32 | #include <linux/kexec.h> |
| 33 | #include <linux/backlight.h> |
| 34 | #include <linux/bug.h> |
| 35 | #include <linux/kdebug.h> |
| 36 | #include <linux/debugfs.h> |
| 37 | #include <linux/ratelimit.h> |
| 38 | #include <linux/context_tracking.h> |
| 39 | |
| 40 | #include <asm/emulated_ops.h> |
| 41 | #include <asm/pgtable.h> |
| 42 | #include <asm/uaccess.h> |
| 43 | #include <asm/io.h> |
| 44 | #include <asm/machdep.h> |
| 45 | #include <asm/rtas.h> |
| 46 | #include <asm/pmc.h> |
| 47 | #include <asm/reg.h> |
| 48 | #ifdef CONFIG_PMAC_BACKLIGHT |
| 49 | #include <asm/backlight.h> |
| 50 | #endif |
| 51 | #ifdef CONFIG_PPC64 |
| 52 | #include <asm/firmware.h> |
| 53 | #include <asm/processor.h> |
| 54 | #include <asm/tm.h> |
| 55 | #endif |
| 56 | #include <asm/kexec.h> |
| 57 | #include <asm/ppc-opcode.h> |
| 58 | #include <asm/rio.h> |
| 59 | #include <asm/fadump.h> |
| 60 | #include <asm/switch_to.h> |
| 61 | #include <asm/tm.h> |
| 62 | #include <asm/debug.h> |
| 63 | |
| 64 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
| 65 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
| 66 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; |
| 67 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; |
| 68 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; |
| 69 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; |
| 70 | int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; |
| 71 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; |
| 72 | |
| 73 | EXPORT_SYMBOL(__debugger); |
| 74 | EXPORT_SYMBOL(__debugger_ipi); |
| 75 | EXPORT_SYMBOL(__debugger_bpt); |
| 76 | EXPORT_SYMBOL(__debugger_sstep); |
| 77 | EXPORT_SYMBOL(__debugger_iabr_match); |
| 78 | EXPORT_SYMBOL(__debugger_break_match); |
| 79 | EXPORT_SYMBOL(__debugger_fault_handler); |
| 80 | #endif |
| 81 | |
| 82 | /* Transactional Memory trap debug */ |
| 83 | #ifdef TM_DEBUG_SW |
| 84 | #define TM_DEBUG(x...) printk(KERN_INFO x) |
| 85 | #else |
| 86 | #define TM_DEBUG(x...) do { } while(0) |
| 87 | #endif |
| 88 | |
| 89 | /* |
| 90 | * Trap & Exception support |
| 91 | */ |
| 92 | |
| 93 | #ifdef CONFIG_PMAC_BACKLIGHT |
| 94 | static void pmac_backlight_unblank(void) |
| 95 | { |
| 96 | mutex_lock(&pmac_backlight_mutex); |
| 97 | if (pmac_backlight) { |
| 98 | struct backlight_properties *props; |
| 99 | |
| 100 | props = &pmac_backlight->props; |
| 101 | props->brightness = props->max_brightness; |
| 102 | props->power = FB_BLANK_UNBLANK; |
| 103 | backlight_update_status(pmac_backlight); |
| 104 | } |
| 105 | mutex_unlock(&pmac_backlight_mutex); |
| 106 | } |
| 107 | #else |
| 108 | static inline void pmac_backlight_unblank(void) { } |
| 109 | #endif |
| 110 | |
| 111 | static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
| 112 | static int die_owner = -1; |
| 113 | static unsigned int die_nest_count; |
| 114 | static int die_counter; |
| 115 | |
| 116 | static unsigned __kprobes long oops_begin(struct pt_regs *regs) |
| 117 | { |
| 118 | int cpu; |
| 119 | unsigned long flags; |
| 120 | |
| 121 | if (debugger(regs)) |
| 122 | return 1; |
| 123 | |
| 124 | oops_enter(); |
| 125 | |
| 126 | /* racy, but better than risking deadlock. */ |
| 127 | raw_local_irq_save(flags); |
| 128 | cpu = smp_processor_id(); |
| 129 | if (!arch_spin_trylock(&die_lock)) { |
| 130 | if (cpu == die_owner) |
| 131 | /* nested oops. should stop eventually */; |
| 132 | else |
| 133 | arch_spin_lock(&die_lock); |
| 134 | } |
| 135 | die_nest_count++; |
| 136 | die_owner = cpu; |
| 137 | console_verbose(); |
| 138 | bust_spinlocks(1); |
| 139 | if (machine_is(powermac)) |
| 140 | pmac_backlight_unblank(); |
| 141 | return flags; |
| 142 | } |
| 143 | |
| 144 | static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, |
| 145 | int signr) |
| 146 | { |
| 147 | bust_spinlocks(0); |
| 148 | die_owner = -1; |
| 149 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
| 150 | die_nest_count--; |
| 151 | oops_exit(); |
| 152 | printk("\n"); |
| 153 | if (!die_nest_count) |
| 154 | /* Nest count reaches zero, release the lock. */ |
| 155 | arch_spin_unlock(&die_lock); |
| 156 | raw_local_irq_restore(flags); |
| 157 | |
| 158 | crash_fadump(regs, "die oops"); |
| 159 | |
| 160 | /* |
| 161 | * A system reset (0x100) is a request to dump, so we always send |
| 162 | * it through the crashdump code. |
| 163 | */ |
| 164 | if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { |
| 165 | crash_kexec(regs); |
| 166 | |
| 167 | /* |
| 168 | * We aren't the primary crash CPU. We need to send it |
| 169 | * to a holding pattern to avoid it ending up in the panic |
| 170 | * code. |
| 171 | */ |
| 172 | crash_kexec_secondary(regs); |
| 173 | } |
| 174 | |
| 175 | if (!signr) |
| 176 | return; |
| 177 | |
| 178 | /* |
| 179 | * While our oops output is serialised by a spinlock, output |
| 180 | * from panic() called below can race and corrupt it. If we |
| 181 | * know we are going to panic, delay for 1 second so we have a |
| 182 | * chance to get clean backtraces from all CPUs that are oopsing. |
| 183 | */ |
| 184 | if (in_interrupt() || panic_on_oops || !current->pid || |
| 185 | is_global_init(current)) { |
| 186 | mdelay(MSEC_PER_SEC); |
| 187 | } |
| 188 | |
| 189 | if (in_interrupt()) |
| 190 | panic("Fatal exception in interrupt"); |
| 191 | if (panic_on_oops) |
| 192 | panic("Fatal exception"); |
| 193 | do_exit(signr); |
| 194 | } |
| 195 | |
| 196 | static int __kprobes __die(const char *str, struct pt_regs *regs, long err) |
| 197 | { |
| 198 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); |
| 199 | #ifdef CONFIG_PREEMPT |
| 200 | printk("PREEMPT "); |
| 201 | #endif |
| 202 | #ifdef CONFIG_SMP |
| 203 | printk("SMP NR_CPUS=%d ", NR_CPUS); |
| 204 | #endif |
| 205 | #ifdef CONFIG_DEBUG_PAGEALLOC |
| 206 | printk("DEBUG_PAGEALLOC "); |
| 207 | #endif |
| 208 | #ifdef CONFIG_NUMA |
| 209 | printk("NUMA "); |
| 210 | #endif |
| 211 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); |
| 212 | |
| 213 | if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) |
| 214 | return 1; |
| 215 | |
| 216 | print_modules(); |
| 217 | show_regs(regs); |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | |
| 222 | void die(const char *str, struct pt_regs *regs, long err) |
| 223 | { |
| 224 | unsigned long flags = oops_begin(regs); |
| 225 | |
| 226 | if (__die(str, regs, err)) |
| 227 | err = 0; |
| 228 | oops_end(flags, regs, err); |
| 229 | } |
| 230 | |
| 231 | void user_single_step_siginfo(struct task_struct *tsk, |
| 232 | struct pt_regs *regs, siginfo_t *info) |
| 233 | { |
| 234 | memset(info, 0, sizeof(*info)); |
| 235 | info->si_signo = SIGTRAP; |
| 236 | info->si_code = TRAP_TRACE; |
| 237 | info->si_addr = (void __user *)regs->nip; |
| 238 | } |
| 239 | |
| 240 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
| 241 | { |
| 242 | siginfo_t info; |
| 243 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
| 244 | "at %08lx nip %08lx lr %08lx code %x\n"; |
| 245 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
| 246 | "at %016lx nip %016lx lr %016lx code %x\n"; |
| 247 | |
| 248 | if (!user_mode(regs)) { |
| 249 | die("Exception in kernel mode", regs, signr); |
| 250 | return; |
| 251 | } |
| 252 | |
| 253 | if (show_unhandled_signals && unhandled_signal(current, signr)) { |
| 254 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
| 255 | current->comm, current->pid, signr, |
| 256 | addr, regs->nip, regs->link, code); |
| 257 | } |
| 258 | |
| 259 | if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) |
| 260 | local_irq_enable(); |
| 261 | |
| 262 | current->thread.trap_nr = code; |
| 263 | memset(&info, 0, sizeof(info)); |
| 264 | info.si_signo = signr; |
| 265 | info.si_code = code; |
| 266 | info.si_addr = (void __user *) addr; |
| 267 | force_sig_info(signr, &info, current); |
| 268 | } |
| 269 | |
| 270 | #ifdef CONFIG_PPC64 |
| 271 | void system_reset_exception(struct pt_regs *regs) |
| 272 | { |
| 273 | /* See if any machine dependent calls */ |
| 274 | if (ppc_md.system_reset_exception) { |
| 275 | if (ppc_md.system_reset_exception(regs)) |
| 276 | return; |
| 277 | } |
| 278 | |
| 279 | die("System Reset", regs, SIGABRT); |
| 280 | |
| 281 | /* Must die if the interrupt is not recoverable */ |
| 282 | if (!(regs->msr & MSR_RI)) |
| 283 | panic("Unrecoverable System Reset"); |
| 284 | |
| 285 | /* What should we do here? We could issue a shutdown or hard reset. */ |
| 286 | } |
| 287 | #endif |
| 288 | |
| 289 | /* |
| 290 | * I/O accesses can cause machine checks on powermacs. |
| 291 | * Check if the NIP corresponds to the address of a sync |
| 292 | * instruction for which there is an entry in the exception |
| 293 | * table. |
| 294 | * Note that the 601 only takes a machine check on TEA |
| 295 | * (transfer error ack) signal assertion, and does not |
| 296 | * set any of the top 16 bits of SRR1. |
| 297 | * -- paulus. |
| 298 | */ |
| 299 | static inline int check_io_access(struct pt_regs *regs) |
| 300 | { |
| 301 | #ifdef CONFIG_PPC32 |
| 302 | unsigned long msr = regs->msr; |
| 303 | const struct exception_table_entry *entry; |
| 304 | unsigned int *nip = (unsigned int *)regs->nip; |
| 305 | |
| 306 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) |
| 307 | && (entry = search_exception_tables(regs->nip)) != NULL) { |
| 308 | /* |
| 309 | * Check that it's a sync instruction, or somewhere |
| 310 | * in the twi; isync; nop sequence that inb/inw/inl uses. |
| 311 | * As the address is in the exception table |
| 312 | * we should be able to read the instr there. |
| 313 | * For the debug message, we look at the preceding |
| 314 | * load or store. |
| 315 | */ |
| 316 | if (*nip == 0x60000000) /* nop */ |
| 317 | nip -= 2; |
| 318 | else if (*nip == 0x4c00012c) /* isync */ |
| 319 | --nip; |
| 320 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { |
| 321 | /* sync or twi */ |
| 322 | unsigned int rb; |
| 323 | |
| 324 | --nip; |
| 325 | rb = (*nip >> 11) & 0x1f; |
| 326 | printk(KERN_DEBUG "%s bad port %lx at %p\n", |
| 327 | (*nip & 0x100)? "OUT to": "IN from", |
| 328 | regs->gpr[rb] - _IO_BASE, nip); |
| 329 | regs->msr |= MSR_RI; |
| 330 | regs->nip = entry->fixup; |
| 331 | return 1; |
| 332 | } |
| 333 | } |
| 334 | #endif /* CONFIG_PPC32 */ |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
| 339 | /* On 4xx, the reason for the machine check or program exception |
| 340 | is in the ESR. */ |
| 341 | #define get_reason(regs) ((regs)->dsisr) |
| 342 | #ifndef CONFIG_FSL_BOOKE |
| 343 | #define get_mc_reason(regs) ((regs)->dsisr) |
| 344 | #else |
| 345 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) |
| 346 | #endif |
| 347 | #define REASON_FP ESR_FP |
| 348 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) |
| 349 | #define REASON_PRIVILEGED ESR_PPR |
| 350 | #define REASON_TRAP ESR_PTR |
| 351 | |
| 352 | /* single-step stuff */ |
| 353 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) |
| 354 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) |
| 355 | |
| 356 | #else |
| 357 | /* On non-4xx, the reason for the machine check or program |
| 358 | exception is in the MSR. */ |
| 359 | #define get_reason(regs) ((regs)->msr) |
| 360 | #define get_mc_reason(regs) ((regs)->msr) |
| 361 | #define REASON_TM 0x200000 |
| 362 | #define REASON_FP 0x100000 |
| 363 | #define REASON_ILLEGAL 0x80000 |
| 364 | #define REASON_PRIVILEGED 0x40000 |
| 365 | #define REASON_TRAP 0x20000 |
| 366 | |
| 367 | #define single_stepping(regs) ((regs)->msr & MSR_SE) |
| 368 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) |
| 369 | #endif |
| 370 | |
| 371 | #if defined(CONFIG_4xx) |
| 372 | int machine_check_4xx(struct pt_regs *regs) |
| 373 | { |
| 374 | unsigned long reason = get_mc_reason(regs); |
| 375 | |
| 376 | if (reason & ESR_IMCP) { |
| 377 | printk("Instruction"); |
| 378 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); |
| 379 | } else |
| 380 | printk("Data"); |
| 381 | printk(" machine check in kernel mode.\n"); |
| 382 | |
| 383 | return 0; |
| 384 | } |
| 385 | |
| 386 | int machine_check_440A(struct pt_regs *regs) |
| 387 | { |
| 388 | unsigned long reason = get_mc_reason(regs); |
| 389 | |
| 390 | printk("Machine check in kernel mode.\n"); |
| 391 | if (reason & ESR_IMCP){ |
| 392 | printk("Instruction Synchronous Machine Check exception\n"); |
| 393 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); |
| 394 | } |
| 395 | else { |
| 396 | u32 mcsr = mfspr(SPRN_MCSR); |
| 397 | if (mcsr & MCSR_IB) |
| 398 | printk("Instruction Read PLB Error\n"); |
| 399 | if (mcsr & MCSR_DRB) |
| 400 | printk("Data Read PLB Error\n"); |
| 401 | if (mcsr & MCSR_DWB) |
| 402 | printk("Data Write PLB Error\n"); |
| 403 | if (mcsr & MCSR_TLBP) |
| 404 | printk("TLB Parity Error\n"); |
| 405 | if (mcsr & MCSR_ICP){ |
| 406 | flush_instruction_cache(); |
| 407 | printk("I-Cache Parity Error\n"); |
| 408 | } |
| 409 | if (mcsr & MCSR_DCSP) |
| 410 | printk("D-Cache Search Parity Error\n"); |
| 411 | if (mcsr & MCSR_DCFP) |
| 412 | printk("D-Cache Flush Parity Error\n"); |
| 413 | if (mcsr & MCSR_IMPE) |
| 414 | printk("Machine Check exception is imprecise\n"); |
| 415 | |
| 416 | /* Clear MCSR */ |
| 417 | mtspr(SPRN_MCSR, mcsr); |
| 418 | } |
| 419 | return 0; |
| 420 | } |
| 421 | |
| 422 | int machine_check_47x(struct pt_regs *regs) |
| 423 | { |
| 424 | unsigned long reason = get_mc_reason(regs); |
| 425 | u32 mcsr; |
| 426 | |
| 427 | printk(KERN_ERR "Machine check in kernel mode.\n"); |
| 428 | if (reason & ESR_IMCP) { |
| 429 | printk(KERN_ERR |
| 430 | "Instruction Synchronous Machine Check exception\n"); |
| 431 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); |
| 432 | return 0; |
| 433 | } |
| 434 | mcsr = mfspr(SPRN_MCSR); |
| 435 | if (mcsr & MCSR_IB) |
| 436 | printk(KERN_ERR "Instruction Read PLB Error\n"); |
| 437 | if (mcsr & MCSR_DRB) |
| 438 | printk(KERN_ERR "Data Read PLB Error\n"); |
| 439 | if (mcsr & MCSR_DWB) |
| 440 | printk(KERN_ERR "Data Write PLB Error\n"); |
| 441 | if (mcsr & MCSR_TLBP) |
| 442 | printk(KERN_ERR "TLB Parity Error\n"); |
| 443 | if (mcsr & MCSR_ICP) { |
| 444 | flush_instruction_cache(); |
| 445 | printk(KERN_ERR "I-Cache Parity Error\n"); |
| 446 | } |
| 447 | if (mcsr & MCSR_DCSP) |
| 448 | printk(KERN_ERR "D-Cache Search Parity Error\n"); |
| 449 | if (mcsr & PPC47x_MCSR_GPR) |
| 450 | printk(KERN_ERR "GPR Parity Error\n"); |
| 451 | if (mcsr & PPC47x_MCSR_FPR) |
| 452 | printk(KERN_ERR "FPR Parity Error\n"); |
| 453 | if (mcsr & PPC47x_MCSR_IPR) |
| 454 | printk(KERN_ERR "Machine Check exception is imprecise\n"); |
| 455 | |
| 456 | /* Clear MCSR */ |
| 457 | mtspr(SPRN_MCSR, mcsr); |
| 458 | |
| 459 | return 0; |
| 460 | } |
| 461 | #elif defined(CONFIG_E500) |
| 462 | int machine_check_e500mc(struct pt_regs *regs) |
| 463 | { |
| 464 | unsigned long mcsr = mfspr(SPRN_MCSR); |
| 465 | unsigned long reason = mcsr; |
| 466 | int recoverable = 1; |
| 467 | |
| 468 | if (reason & MCSR_LD) { |
| 469 | recoverable = fsl_rio_mcheck_exception(regs); |
| 470 | if (recoverable == 1) |
| 471 | goto silent_out; |
| 472 | } |
| 473 | |
| 474 | printk("Machine check in kernel mode.\n"); |
| 475 | printk("Caused by (from MCSR=%lx): ", reason); |
| 476 | |
| 477 | if (reason & MCSR_MCP) |
| 478 | printk("Machine Check Signal\n"); |
| 479 | |
| 480 | if (reason & MCSR_ICPERR) { |
| 481 | printk("Instruction Cache Parity Error\n"); |
| 482 | |
| 483 | /* |
| 484 | * This is recoverable by invalidating the i-cache. |
| 485 | */ |
| 486 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); |
| 487 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) |
| 488 | ; |
| 489 | |
| 490 | /* |
| 491 | * This will generally be accompanied by an instruction |
| 492 | * fetch error report -- only treat MCSR_IF as fatal |
| 493 | * if it wasn't due to an L1 parity error. |
| 494 | */ |
| 495 | reason &= ~MCSR_IF; |
| 496 | } |
| 497 | |
| 498 | if (reason & MCSR_DCPERR_MC) { |
| 499 | printk("Data Cache Parity Error\n"); |
| 500 | |
| 501 | /* |
| 502 | * In write shadow mode we auto-recover from the error, but it |
| 503 | * may still get logged and cause a machine check. We should |
| 504 | * only treat the non-write shadow case as non-recoverable. |
| 505 | */ |
| 506 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) |
| 507 | recoverable = 0; |
| 508 | } |
| 509 | |
| 510 | if (reason & MCSR_L2MMU_MHIT) { |
| 511 | printk("Hit on multiple TLB entries\n"); |
| 512 | recoverable = 0; |
| 513 | } |
| 514 | |
| 515 | if (reason & MCSR_NMI) |
| 516 | printk("Non-maskable interrupt\n"); |
| 517 | |
| 518 | if (reason & MCSR_IF) { |
| 519 | printk("Instruction Fetch Error Report\n"); |
| 520 | recoverable = 0; |
| 521 | } |
| 522 | |
| 523 | if (reason & MCSR_LD) { |
| 524 | printk("Load Error Report\n"); |
| 525 | recoverable = 0; |
| 526 | } |
| 527 | |
| 528 | if (reason & MCSR_ST) { |
| 529 | printk("Store Error Report\n"); |
| 530 | recoverable = 0; |
| 531 | } |
| 532 | |
| 533 | if (reason & MCSR_LDG) { |
| 534 | printk("Guarded Load Error Report\n"); |
| 535 | recoverable = 0; |
| 536 | } |
| 537 | |
| 538 | if (reason & MCSR_TLBSYNC) |
| 539 | printk("Simultaneous tlbsync operations\n"); |
| 540 | |
| 541 | if (reason & MCSR_BSL2_ERR) { |
| 542 | printk("Level 2 Cache Error\n"); |
| 543 | recoverable = 0; |
| 544 | } |
| 545 | |
| 546 | if (reason & MCSR_MAV) { |
| 547 | u64 addr; |
| 548 | |
| 549 | addr = mfspr(SPRN_MCAR); |
| 550 | addr |= (u64)mfspr(SPRN_MCARU) << 32; |
| 551 | |
| 552 | printk("Machine Check %s Address: %#llx\n", |
| 553 | reason & MCSR_MEA ? "Effective" : "Physical", addr); |
| 554 | } |
| 555 | |
| 556 | silent_out: |
| 557 | mtspr(SPRN_MCSR, mcsr); |
| 558 | return mfspr(SPRN_MCSR) == 0 && recoverable; |
| 559 | } |
| 560 | |
| 561 | int machine_check_e500(struct pt_regs *regs) |
| 562 | { |
| 563 | unsigned long reason = get_mc_reason(regs); |
| 564 | |
| 565 | if (reason & MCSR_BUS_RBERR) { |
| 566 | if (fsl_rio_mcheck_exception(regs)) |
| 567 | return 1; |
| 568 | } |
| 569 | |
| 570 | printk("Machine check in kernel mode.\n"); |
| 571 | printk("Caused by (from MCSR=%lx): ", reason); |
| 572 | |
| 573 | if (reason & MCSR_MCP) |
| 574 | printk("Machine Check Signal\n"); |
| 575 | if (reason & MCSR_ICPERR) |
| 576 | printk("Instruction Cache Parity Error\n"); |
| 577 | if (reason & MCSR_DCP_PERR) |
| 578 | printk("Data Cache Push Parity Error\n"); |
| 579 | if (reason & MCSR_DCPERR) |
| 580 | printk("Data Cache Parity Error\n"); |
| 581 | if (reason & MCSR_BUS_IAERR) |
| 582 | printk("Bus - Instruction Address Error\n"); |
| 583 | if (reason & MCSR_BUS_RAERR) |
| 584 | printk("Bus - Read Address Error\n"); |
| 585 | if (reason & MCSR_BUS_WAERR) |
| 586 | printk("Bus - Write Address Error\n"); |
| 587 | if (reason & MCSR_BUS_IBERR) |
| 588 | printk("Bus - Instruction Data Error\n"); |
| 589 | if (reason & MCSR_BUS_RBERR) |
| 590 | printk("Bus - Read Data Bus Error\n"); |
| 591 | if (reason & MCSR_BUS_WBERR) |
| 592 | printk("Bus - Read Data Bus Error\n"); |
| 593 | if (reason & MCSR_BUS_IPERR) |
| 594 | printk("Bus - Instruction Parity Error\n"); |
| 595 | if (reason & MCSR_BUS_RPERR) |
| 596 | printk("Bus - Read Parity Error\n"); |
| 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | int machine_check_generic(struct pt_regs *regs) |
| 602 | { |
| 603 | return 0; |
| 604 | } |
| 605 | #elif defined(CONFIG_E200) |
| 606 | int machine_check_e200(struct pt_regs *regs) |
| 607 | { |
| 608 | unsigned long reason = get_mc_reason(regs); |
| 609 | |
| 610 | printk("Machine check in kernel mode.\n"); |
| 611 | printk("Caused by (from MCSR=%lx): ", reason); |
| 612 | |
| 613 | if (reason & MCSR_MCP) |
| 614 | printk("Machine Check Signal\n"); |
| 615 | if (reason & MCSR_CP_PERR) |
| 616 | printk("Cache Push Parity Error\n"); |
| 617 | if (reason & MCSR_CPERR) |
| 618 | printk("Cache Parity Error\n"); |
| 619 | if (reason & MCSR_EXCP_ERR) |
| 620 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); |
| 621 | if (reason & MCSR_BUS_IRERR) |
| 622 | printk("Bus - Read Bus Error on instruction fetch\n"); |
| 623 | if (reason & MCSR_BUS_DRERR) |
| 624 | printk("Bus - Read Bus Error on data load\n"); |
| 625 | if (reason & MCSR_BUS_WRERR) |
| 626 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); |
| 627 | |
| 628 | return 0; |
| 629 | } |
| 630 | #else |
| 631 | int machine_check_generic(struct pt_regs *regs) |
| 632 | { |
| 633 | unsigned long reason = get_mc_reason(regs); |
| 634 | |
| 635 | printk("Machine check in kernel mode.\n"); |
| 636 | printk("Caused by (from SRR1=%lx): ", reason); |
| 637 | switch (reason & 0x601F0000) { |
| 638 | case 0x80000: |
| 639 | printk("Machine check signal\n"); |
| 640 | break; |
| 641 | case 0: /* for 601 */ |
| 642 | case 0x40000: |
| 643 | case 0x140000: /* 7450 MSS error and TEA */ |
| 644 | printk("Transfer error ack signal\n"); |
| 645 | break; |
| 646 | case 0x20000: |
| 647 | printk("Data parity error signal\n"); |
| 648 | break; |
| 649 | case 0x10000: |
| 650 | printk("Address parity error signal\n"); |
| 651 | break; |
| 652 | case 0x20000000: |
| 653 | printk("L1 Data Cache error\n"); |
| 654 | break; |
| 655 | case 0x40000000: |
| 656 | printk("L1 Instruction Cache error\n"); |
| 657 | break; |
| 658 | case 0x00100000: |
| 659 | printk("L2 data cache parity error\n"); |
| 660 | break; |
| 661 | default: |
| 662 | printk("Unknown values in msr\n"); |
| 663 | } |
| 664 | return 0; |
| 665 | } |
| 666 | #endif /* everything else */ |
| 667 | |
| 668 | void machine_check_exception(struct pt_regs *regs) |
| 669 | { |
| 670 | enum ctx_state prev_state = exception_enter(); |
| 671 | int recover = 0; |
| 672 | |
| 673 | __get_cpu_var(irq_stat).mce_exceptions++; |
| 674 | |
| 675 | /* See if any machine dependent calls. In theory, we would want |
| 676 | * to call the CPU first, and call the ppc_md. one if the CPU |
| 677 | * one returns a positive number. However there is existing code |
| 678 | * that assumes the board gets a first chance, so let's keep it |
| 679 | * that way for now and fix things later. --BenH. |
| 680 | */ |
| 681 | if (ppc_md.machine_check_exception) |
| 682 | recover = ppc_md.machine_check_exception(regs); |
| 683 | else if (cur_cpu_spec->machine_check) |
| 684 | recover = cur_cpu_spec->machine_check(regs); |
| 685 | |
| 686 | if (recover > 0) |
| 687 | goto bail; |
| 688 | |
| 689 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) |
| 690 | /* the qspan pci read routines can cause machine checks -- Cort |
| 691 | * |
| 692 | * yuck !!! that totally needs to go away ! There are better ways |
| 693 | * to deal with that than having a wart in the mcheck handler. |
| 694 | * -- BenH |
| 695 | */ |
| 696 | bad_page_fault(regs, regs->dar, SIGBUS); |
| 697 | goto bail; |
| 698 | #endif |
| 699 | |
| 700 | if (debugger_fault_handler(regs)) |
| 701 | goto bail; |
| 702 | |
| 703 | if (check_io_access(regs)) |
| 704 | goto bail; |
| 705 | |
| 706 | die("Machine check", regs, SIGBUS); |
| 707 | |
| 708 | /* Must die if the interrupt is not recoverable */ |
| 709 | if (!(regs->msr & MSR_RI)) |
| 710 | panic("Unrecoverable Machine check"); |
| 711 | |
| 712 | bail: |
| 713 | exception_exit(prev_state); |
| 714 | } |
| 715 | |
| 716 | void SMIException(struct pt_regs *regs) |
| 717 | { |
| 718 | die("System Management Interrupt", regs, SIGABRT); |
| 719 | } |
| 720 | |
| 721 | void unknown_exception(struct pt_regs *regs) |
| 722 | { |
| 723 | enum ctx_state prev_state = exception_enter(); |
| 724 | |
| 725 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
| 726 | regs->nip, regs->msr, regs->trap); |
| 727 | |
| 728 | _exception(SIGTRAP, regs, 0, 0); |
| 729 | |
| 730 | exception_exit(prev_state); |
| 731 | } |
| 732 | |
| 733 | void instruction_breakpoint_exception(struct pt_regs *regs) |
| 734 | { |
| 735 | enum ctx_state prev_state = exception_enter(); |
| 736 | |
| 737 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, |
| 738 | 5, SIGTRAP) == NOTIFY_STOP) |
| 739 | goto bail; |
| 740 | if (debugger_iabr_match(regs)) |
| 741 | goto bail; |
| 742 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
| 743 | |
| 744 | bail: |
| 745 | exception_exit(prev_state); |
| 746 | } |
| 747 | |
| 748 | void RunModeException(struct pt_regs *regs) |
| 749 | { |
| 750 | _exception(SIGTRAP, regs, 0, 0); |
| 751 | } |
| 752 | |
| 753 | void __kprobes single_step_exception(struct pt_regs *regs) |
| 754 | { |
| 755 | enum ctx_state prev_state = exception_enter(); |
| 756 | |
| 757 | clear_single_step(regs); |
| 758 | |
| 759 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
| 760 | 5, SIGTRAP) == NOTIFY_STOP) |
| 761 | goto bail; |
| 762 | if (debugger_sstep(regs)) |
| 763 | goto bail; |
| 764 | |
| 765 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); |
| 766 | |
| 767 | bail: |
| 768 | exception_exit(prev_state); |
| 769 | } |
| 770 | |
| 771 | /* |
| 772 | * After we have successfully emulated an instruction, we have to |
| 773 | * check if the instruction was being single-stepped, and if so, |
| 774 | * pretend we got a single-step exception. This was pointed out |
| 775 | * by Kumar Gala. -- paulus |
| 776 | */ |
| 777 | static void emulate_single_step(struct pt_regs *regs) |
| 778 | { |
| 779 | if (single_stepping(regs)) |
| 780 | single_step_exception(regs); |
| 781 | } |
| 782 | |
| 783 | static inline int __parse_fpscr(unsigned long fpscr) |
| 784 | { |
| 785 | int ret = 0; |
| 786 | |
| 787 | /* Invalid operation */ |
| 788 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) |
| 789 | ret = FPE_FLTINV; |
| 790 | |
| 791 | /* Overflow */ |
| 792 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) |
| 793 | ret = FPE_FLTOVF; |
| 794 | |
| 795 | /* Underflow */ |
| 796 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) |
| 797 | ret = FPE_FLTUND; |
| 798 | |
| 799 | /* Divide by zero */ |
| 800 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) |
| 801 | ret = FPE_FLTDIV; |
| 802 | |
| 803 | /* Inexact result */ |
| 804 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) |
| 805 | ret = FPE_FLTRES; |
| 806 | |
| 807 | return ret; |
| 808 | } |
| 809 | |
| 810 | static void parse_fpe(struct pt_regs *regs) |
| 811 | { |
| 812 | int code = 0; |
| 813 | |
| 814 | flush_fp_to_thread(current); |
| 815 | |
| 816 | code = __parse_fpscr(current->thread.fpscr.val); |
| 817 | |
| 818 | _exception(SIGFPE, regs, code, regs->nip); |
| 819 | } |
| 820 | |
| 821 | /* |
| 822 | * Illegal instruction emulation support. Originally written to |
| 823 | * provide the PVR to user applications using the mfspr rd, PVR. |
| 824 | * Return non-zero if we can't emulate, or -EFAULT if the associated |
| 825 | * memory access caused an access fault. Return zero on success. |
| 826 | * |
| 827 | * There are a couple of ways to do this, either "decode" the instruction |
| 828 | * or directly match lots of bits. In this case, matching lots of |
| 829 | * bits is faster and easier. |
| 830 | * |
| 831 | */ |
| 832 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
| 833 | { |
| 834 | u8 rT = (instword >> 21) & 0x1f; |
| 835 | u8 rA = (instword >> 16) & 0x1f; |
| 836 | u8 NB_RB = (instword >> 11) & 0x1f; |
| 837 | u32 num_bytes; |
| 838 | unsigned long EA; |
| 839 | int pos = 0; |
| 840 | |
| 841 | /* Early out if we are an invalid form of lswx */ |
| 842 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
| 843 | if ((rT == rA) || (rT == NB_RB)) |
| 844 | return -EINVAL; |
| 845 | |
| 846 | EA = (rA == 0) ? 0 : regs->gpr[rA]; |
| 847 | |
| 848 | switch (instword & PPC_INST_STRING_MASK) { |
| 849 | case PPC_INST_LSWX: |
| 850 | case PPC_INST_STSWX: |
| 851 | EA += NB_RB; |
| 852 | num_bytes = regs->xer & 0x7f; |
| 853 | break; |
| 854 | case PPC_INST_LSWI: |
| 855 | case PPC_INST_STSWI: |
| 856 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
| 857 | break; |
| 858 | default: |
| 859 | return -EINVAL; |
| 860 | } |
| 861 | |
| 862 | while (num_bytes != 0) |
| 863 | { |
| 864 | u8 val; |
| 865 | u32 shift = 8 * (3 - (pos & 0x3)); |
| 866 | |
| 867 | switch ((instword & PPC_INST_STRING_MASK)) { |
| 868 | case PPC_INST_LSWX: |
| 869 | case PPC_INST_LSWI: |
| 870 | if (get_user(val, (u8 __user *)EA)) |
| 871 | return -EFAULT; |
| 872 | /* first time updating this reg, |
| 873 | * zero it out */ |
| 874 | if (pos == 0) |
| 875 | regs->gpr[rT] = 0; |
| 876 | regs->gpr[rT] |= val << shift; |
| 877 | break; |
| 878 | case PPC_INST_STSWI: |
| 879 | case PPC_INST_STSWX: |
| 880 | val = regs->gpr[rT] >> shift; |
| 881 | if (put_user(val, (u8 __user *)EA)) |
| 882 | return -EFAULT; |
| 883 | break; |
| 884 | } |
| 885 | /* move EA to next address */ |
| 886 | EA += 1; |
| 887 | num_bytes--; |
| 888 | |
| 889 | /* manage our position within the register */ |
| 890 | if (++pos == 4) { |
| 891 | pos = 0; |
| 892 | if (++rT == 32) |
| 893 | rT = 0; |
| 894 | } |
| 895 | } |
| 896 | |
| 897 | return 0; |
| 898 | } |
| 899 | |
| 900 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
| 901 | { |
| 902 | u32 ra,rs; |
| 903 | unsigned long tmp; |
| 904 | |
| 905 | ra = (instword >> 16) & 0x1f; |
| 906 | rs = (instword >> 21) & 0x1f; |
| 907 | |
| 908 | tmp = regs->gpr[rs]; |
| 909 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); |
| 910 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); |
| 911 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; |
| 912 | regs->gpr[ra] = tmp; |
| 913 | |
| 914 | return 0; |
| 915 | } |
| 916 | |
| 917 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
| 918 | { |
| 919 | u8 rT = (instword >> 21) & 0x1f; |
| 920 | u8 rA = (instword >> 16) & 0x1f; |
| 921 | u8 rB = (instword >> 11) & 0x1f; |
| 922 | u8 BC = (instword >> 6) & 0x1f; |
| 923 | u8 bit; |
| 924 | unsigned long tmp; |
| 925 | |
| 926 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; |
| 927 | bit = (regs->ccr >> (31 - BC)) & 0x1; |
| 928 | |
| 929 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; |
| 930 | |
| 931 | return 0; |
| 932 | } |
| 933 | |
| 934 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 935 | static inline bool tm_abort_check(struct pt_regs *regs, int cause) |
| 936 | { |
| 937 | /* If we're emulating a load/store in an active transaction, we cannot |
| 938 | * emulate it as the kernel operates in transaction suspended context. |
| 939 | * We need to abort the transaction. This creates a persistent TM |
| 940 | * abort so tell the user what caused it with a new code. |
| 941 | */ |
| 942 | if (MSR_TM_TRANSACTIONAL(regs->msr)) { |
| 943 | tm_enable(); |
| 944 | tm_abort(cause); |
| 945 | return true; |
| 946 | } |
| 947 | return false; |
| 948 | } |
| 949 | #else |
| 950 | static inline bool tm_abort_check(struct pt_regs *regs, int reason) |
| 951 | { |
| 952 | return false; |
| 953 | } |
| 954 | #endif |
| 955 | |
| 956 | static int emulate_instruction(struct pt_regs *regs) |
| 957 | { |
| 958 | u32 instword; |
| 959 | u32 rd; |
| 960 | |
| 961 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
| 962 | return -EINVAL; |
| 963 | CHECK_FULL_REGS(regs); |
| 964 | |
| 965 | if (get_user(instword, (u32 __user *)(regs->nip))) |
| 966 | return -EFAULT; |
| 967 | |
| 968 | /* Emulate the mfspr rD, PVR. */ |
| 969 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
| 970 | PPC_WARN_EMULATED(mfpvr, regs); |
| 971 | rd = (instword >> 21) & 0x1f; |
| 972 | regs->gpr[rd] = mfspr(SPRN_PVR); |
| 973 | return 0; |
| 974 | } |
| 975 | |
| 976 | /* Emulating the dcba insn is just a no-op. */ |
| 977 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
| 978 | PPC_WARN_EMULATED(dcba, regs); |
| 979 | return 0; |
| 980 | } |
| 981 | |
| 982 | /* Emulate the mcrxr insn. */ |
| 983 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
| 984 | int shift = (instword >> 21) & 0x1c; |
| 985 | unsigned long msk = 0xf0000000UL >> shift; |
| 986 | |
| 987 | PPC_WARN_EMULATED(mcrxr, regs); |
| 988 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
| 989 | regs->xer &= ~0xf0000000UL; |
| 990 | return 0; |
| 991 | } |
| 992 | |
| 993 | /* Emulate load/store string insn. */ |
| 994 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
| 995 | if (tm_abort_check(regs, |
| 996 | TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) |
| 997 | return -EINVAL; |
| 998 | PPC_WARN_EMULATED(string, regs); |
| 999 | return emulate_string_inst(regs, instword); |
| 1000 | } |
| 1001 | |
| 1002 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
| 1003 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
| 1004 | PPC_WARN_EMULATED(popcntb, regs); |
| 1005 | return emulate_popcntb_inst(regs, instword); |
| 1006 | } |
| 1007 | |
| 1008 | /* Emulate isel (Integer Select) instruction */ |
| 1009 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
| 1010 | PPC_WARN_EMULATED(isel, regs); |
| 1011 | return emulate_isel(regs, instword); |
| 1012 | } |
| 1013 | |
| 1014 | #ifdef CONFIG_PPC64 |
| 1015 | /* Emulate the mfspr rD, DSCR. */ |
| 1016 | if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == |
| 1017 | PPC_INST_MFSPR_DSCR_USER) || |
| 1018 | ((instword & PPC_INST_MFSPR_DSCR_MASK) == |
| 1019 | PPC_INST_MFSPR_DSCR)) && |
| 1020 | cpu_has_feature(CPU_FTR_DSCR)) { |
| 1021 | PPC_WARN_EMULATED(mfdscr, regs); |
| 1022 | rd = (instword >> 21) & 0x1f; |
| 1023 | regs->gpr[rd] = mfspr(SPRN_DSCR); |
| 1024 | return 0; |
| 1025 | } |
| 1026 | /* Emulate the mtspr DSCR, rD. */ |
| 1027 | if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == |
| 1028 | PPC_INST_MTSPR_DSCR_USER) || |
| 1029 | ((instword & PPC_INST_MTSPR_DSCR_MASK) == |
| 1030 | PPC_INST_MTSPR_DSCR)) && |
| 1031 | cpu_has_feature(CPU_FTR_DSCR)) { |
| 1032 | PPC_WARN_EMULATED(mtdscr, regs); |
| 1033 | rd = (instword >> 21) & 0x1f; |
| 1034 | current->thread.dscr = regs->gpr[rd]; |
| 1035 | current->thread.dscr_inherit = 1; |
| 1036 | mtspr(SPRN_DSCR, current->thread.dscr); |
| 1037 | return 0; |
| 1038 | } |
| 1039 | #endif |
| 1040 | |
| 1041 | return -EINVAL; |
| 1042 | } |
| 1043 | |
| 1044 | int is_valid_bugaddr(unsigned long addr) |
| 1045 | { |
| 1046 | return is_kernel_addr(addr); |
| 1047 | } |
| 1048 | |
| 1049 | void __kprobes program_check_exception(struct pt_regs *regs) |
| 1050 | { |
| 1051 | enum ctx_state prev_state = exception_enter(); |
| 1052 | unsigned int reason = get_reason(regs); |
| 1053 | extern int do_mathemu(struct pt_regs *regs); |
| 1054 | |
| 1055 | /* We can now get here via a FP Unavailable exception if the core |
| 1056 | * has no FPU, in that case the reason flags will be 0 */ |
| 1057 | |
| 1058 | if (reason & REASON_FP) { |
| 1059 | /* IEEE FP exception */ |
| 1060 | parse_fpe(regs); |
| 1061 | goto bail; |
| 1062 | } |
| 1063 | if (reason & REASON_TRAP) { |
| 1064 | /* Debugger is first in line to stop recursive faults in |
| 1065 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ |
| 1066 | if (debugger_bpt(regs)) |
| 1067 | goto bail; |
| 1068 | |
| 1069 | /* trap exception */ |
| 1070 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
| 1071 | == NOTIFY_STOP) |
| 1072 | goto bail; |
| 1073 | |
| 1074 | if (!(regs->msr & MSR_PR) && /* not user-mode */ |
| 1075 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
| 1076 | regs->nip += 4; |
| 1077 | goto bail; |
| 1078 | } |
| 1079 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
| 1080 | goto bail; |
| 1081 | } |
| 1082 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1083 | if (reason & REASON_TM) { |
| 1084 | /* This is a TM "Bad Thing Exception" program check. |
| 1085 | * This occurs when: |
| 1086 | * - An rfid/hrfid/mtmsrd attempts to cause an illegal |
| 1087 | * transition in TM states. |
| 1088 | * - A trechkpt is attempted when transactional. |
| 1089 | * - A treclaim is attempted when non transactional. |
| 1090 | * - A tend is illegally attempted. |
| 1091 | * - writing a TM SPR when transactional. |
| 1092 | */ |
| 1093 | if (!user_mode(regs) && |
| 1094 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
| 1095 | regs->nip += 4; |
| 1096 | goto bail; |
| 1097 | } |
| 1098 | /* If usermode caused this, it's done something illegal and |
| 1099 | * gets a SIGILL slap on the wrist. We call it an illegal |
| 1100 | * operand to distinguish from the instruction just being bad |
| 1101 | * (e.g. executing a 'tend' on a CPU without TM!); it's an |
| 1102 | * illegal /placement/ of a valid instruction. |
| 1103 | */ |
| 1104 | if (user_mode(regs)) { |
| 1105 | _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); |
| 1106 | goto bail; |
| 1107 | } else { |
| 1108 | printk(KERN_EMERG "Unexpected TM Bad Thing exception " |
| 1109 | "at %lx (msr 0x%x)\n", regs->nip, reason); |
| 1110 | die("Unrecoverable exception", regs, SIGABRT); |
| 1111 | } |
| 1112 | } |
| 1113 | #endif |
| 1114 | |
| 1115 | /* We restore the interrupt state now */ |
| 1116 | if (!arch_irq_disabled_regs(regs)) |
| 1117 | local_irq_enable(); |
| 1118 | |
| 1119 | #ifdef CONFIG_MATH_EMULATION |
| 1120 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, |
| 1121 | * but there seems to be a hardware bug on the 405GP (RevD) |
| 1122 | * that means ESR is sometimes set incorrectly - either to |
| 1123 | * ESR_DST (!?) or 0. In the process of chasing this with the |
| 1124 | * hardware people - not sure if it can happen on any illegal |
| 1125 | * instruction or only on FP instructions, whether there is a |
| 1126 | * pattern to occurrences etc. -dgibson 31/Mar/2003 */ |
| 1127 | switch (do_mathemu(regs)) { |
| 1128 | case 0: |
| 1129 | emulate_single_step(regs); |
| 1130 | goto bail; |
| 1131 | case 1: { |
| 1132 | int code = 0; |
| 1133 | code = __parse_fpscr(current->thread.fpscr.val); |
| 1134 | _exception(SIGFPE, regs, code, regs->nip); |
| 1135 | goto bail; |
| 1136 | } |
| 1137 | case -EFAULT: |
| 1138 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); |
| 1139 | goto bail; |
| 1140 | } |
| 1141 | /* fall through on any other errors */ |
| 1142 | #endif /* CONFIG_MATH_EMULATION */ |
| 1143 | |
| 1144 | /* Try to emulate it if we should. */ |
| 1145 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { |
| 1146 | switch (emulate_instruction(regs)) { |
| 1147 | case 0: |
| 1148 | regs->nip += 4; |
| 1149 | emulate_single_step(regs); |
| 1150 | goto bail; |
| 1151 | case -EFAULT: |
| 1152 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); |
| 1153 | goto bail; |
| 1154 | } |
| 1155 | } |
| 1156 | |
| 1157 | if (reason & REASON_PRIVILEGED) |
| 1158 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); |
| 1159 | else |
| 1160 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1161 | |
| 1162 | bail: |
| 1163 | exception_exit(prev_state); |
| 1164 | } |
| 1165 | |
| 1166 | /* |
| 1167 | * This occurs when running in hypervisor mode on POWER6 or later |
| 1168 | * and an illegal instruction is encountered. |
| 1169 | */ |
| 1170 | void __kprobes emulation_assist_interrupt(struct pt_regs *regs) |
| 1171 | { |
| 1172 | regs->msr |= REASON_ILLEGAL; |
| 1173 | program_check_exception(regs); |
| 1174 | } |
| 1175 | |
| 1176 | void alignment_exception(struct pt_regs *regs) |
| 1177 | { |
| 1178 | enum ctx_state prev_state = exception_enter(); |
| 1179 | int sig, code, fixed = 0; |
| 1180 | |
| 1181 | /* We restore the interrupt state now */ |
| 1182 | if (!arch_irq_disabled_regs(regs)) |
| 1183 | local_irq_enable(); |
| 1184 | |
| 1185 | if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) |
| 1186 | goto bail; |
| 1187 | |
| 1188 | /* we don't implement logging of alignment exceptions */ |
| 1189 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) |
| 1190 | fixed = fix_alignment(regs); |
| 1191 | |
| 1192 | if (fixed == 1) { |
| 1193 | regs->nip += 4; /* skip over emulated instruction */ |
| 1194 | emulate_single_step(regs); |
| 1195 | goto bail; |
| 1196 | } |
| 1197 | |
| 1198 | /* Operand address was bad */ |
| 1199 | if (fixed == -EFAULT) { |
| 1200 | sig = SIGSEGV; |
| 1201 | code = SEGV_ACCERR; |
| 1202 | } else { |
| 1203 | sig = SIGBUS; |
| 1204 | code = BUS_ADRALN; |
| 1205 | } |
| 1206 | if (user_mode(regs)) |
| 1207 | _exception(sig, regs, code, regs->dar); |
| 1208 | else |
| 1209 | bad_page_fault(regs, regs->dar, sig); |
| 1210 | |
| 1211 | bail: |
| 1212 | exception_exit(prev_state); |
| 1213 | } |
| 1214 | |
| 1215 | void StackOverflow(struct pt_regs *regs) |
| 1216 | { |
| 1217 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", |
| 1218 | current, regs->gpr[1]); |
| 1219 | debugger(regs); |
| 1220 | show_regs(regs); |
| 1221 | panic("kernel stack overflow"); |
| 1222 | } |
| 1223 | |
| 1224 | void nonrecoverable_exception(struct pt_regs *regs) |
| 1225 | { |
| 1226 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", |
| 1227 | regs->nip, regs->msr); |
| 1228 | debugger(regs); |
| 1229 | die("nonrecoverable exception", regs, SIGKILL); |
| 1230 | } |
| 1231 | |
| 1232 | void trace_syscall(struct pt_regs *regs) |
| 1233 | { |
| 1234 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", |
| 1235 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
| 1236 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
| 1237 | } |
| 1238 | |
| 1239 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
| 1240 | { |
| 1241 | enum ctx_state prev_state = exception_enter(); |
| 1242 | |
| 1243 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " |
| 1244 | "%lx at %lx\n", regs->trap, regs->nip); |
| 1245 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); |
| 1246 | |
| 1247 | exception_exit(prev_state); |
| 1248 | } |
| 1249 | |
| 1250 | void altivec_unavailable_exception(struct pt_regs *regs) |
| 1251 | { |
| 1252 | enum ctx_state prev_state = exception_enter(); |
| 1253 | |
| 1254 | if (user_mode(regs)) { |
| 1255 | /* A user program has executed an altivec instruction, |
| 1256 | but this kernel doesn't support altivec. */ |
| 1257 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1258 | goto bail; |
| 1259 | } |
| 1260 | |
| 1261 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
| 1262 | "%lx at %lx\n", regs->trap, regs->nip); |
| 1263 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); |
| 1264 | |
| 1265 | bail: |
| 1266 | exception_exit(prev_state); |
| 1267 | } |
| 1268 | |
| 1269 | void vsx_unavailable_exception(struct pt_regs *regs) |
| 1270 | { |
| 1271 | if (user_mode(regs)) { |
| 1272 | /* A user program has executed an vsx instruction, |
| 1273 | but this kernel doesn't support vsx. */ |
| 1274 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1275 | return; |
| 1276 | } |
| 1277 | |
| 1278 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " |
| 1279 | "%lx at %lx\n", regs->trap, regs->nip); |
| 1280 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); |
| 1281 | } |
| 1282 | |
| 1283 | #ifdef CONFIG_PPC64 |
| 1284 | void facility_unavailable_exception(struct pt_regs *regs) |
| 1285 | { |
| 1286 | static char *facility_strings[] = { |
| 1287 | [FSCR_FP_LG] = "FPU", |
| 1288 | [FSCR_VECVSX_LG] = "VMX/VSX", |
| 1289 | [FSCR_DSCR_LG] = "DSCR", |
| 1290 | [FSCR_PM_LG] = "PMU SPRs", |
| 1291 | [FSCR_BHRB_LG] = "BHRB", |
| 1292 | [FSCR_TM_LG] = "TM", |
| 1293 | [FSCR_EBB_LG] = "EBB", |
| 1294 | [FSCR_TAR_LG] = "TAR", |
| 1295 | }; |
| 1296 | char *facility = "unknown"; |
| 1297 | u64 value; |
| 1298 | u8 status; |
| 1299 | bool hv; |
| 1300 | |
| 1301 | hv = (regs->trap == 0xf80); |
| 1302 | if (hv) |
| 1303 | value = mfspr(SPRN_HFSCR); |
| 1304 | else |
| 1305 | value = mfspr(SPRN_FSCR); |
| 1306 | |
| 1307 | status = value >> 56; |
| 1308 | if (status == FSCR_DSCR_LG) { |
| 1309 | /* User is acessing the DSCR. Set the inherit bit and allow |
| 1310 | * the user to set it directly in future by setting via the |
| 1311 | * H/FSCR DSCR bit. |
| 1312 | */ |
| 1313 | current->thread.dscr_inherit = 1; |
| 1314 | if (hv) |
| 1315 | mtspr(SPRN_HFSCR, value | HFSCR_DSCR); |
| 1316 | else |
| 1317 | mtspr(SPRN_FSCR, value | FSCR_DSCR); |
| 1318 | return; |
| 1319 | } |
| 1320 | |
| 1321 | if ((status < ARRAY_SIZE(facility_strings)) && |
| 1322 | facility_strings[status]) |
| 1323 | facility = facility_strings[status]; |
| 1324 | |
| 1325 | /* We restore the interrupt state now */ |
| 1326 | if (!arch_irq_disabled_regs(regs)) |
| 1327 | local_irq_enable(); |
| 1328 | |
| 1329 | pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n", |
| 1330 | hv ? "Hypervisor " : "", facility, regs->nip, regs->msr); |
| 1331 | |
| 1332 | if (user_mode(regs)) { |
| 1333 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1334 | return; |
| 1335 | } |
| 1336 | |
| 1337 | die("Unexpected facility unavailable exception", regs, SIGABRT); |
| 1338 | } |
| 1339 | #endif |
| 1340 | |
| 1341 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1342 | |
| 1343 | extern void do_load_up_fpu(struct pt_regs *regs); |
| 1344 | |
| 1345 | void fp_unavailable_tm(struct pt_regs *regs) |
| 1346 | { |
| 1347 | /* Note: This does not handle any kind of FP laziness. */ |
| 1348 | |
| 1349 | TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", |
| 1350 | regs->nip, regs->msr); |
| 1351 | tm_enable(); |
| 1352 | |
| 1353 | /* We can only have got here if the task started using FP after |
| 1354 | * beginning the transaction. So, the transactional regs are just a |
| 1355 | * copy of the checkpointed ones. But, we still need to recheckpoint |
| 1356 | * as we're enabling FP for the process; it will return, abort the |
| 1357 | * transaction, and probably retry but now with FP enabled. So the |
| 1358 | * checkpointed FP registers need to be loaded. |
| 1359 | */ |
| 1360 | tm_reclaim(¤t->thread, current->thread.regs->msr, |
| 1361 | TM_CAUSE_FAC_UNAV); |
| 1362 | /* Reclaim didn't save out any FPRs to transact_fprs. */ |
| 1363 | |
| 1364 | /* Enable FP for the task: */ |
| 1365 | regs->msr |= (MSR_FP | current->thread.fpexc_mode); |
| 1366 | |
| 1367 | /* This loads and recheckpoints the FP registers from |
| 1368 | * thread.fpr[]. They will remain in registers after the |
| 1369 | * checkpoint so we don't need to reload them after. |
| 1370 | */ |
| 1371 | tm_recheckpoint(¤t->thread, regs->msr); |
| 1372 | } |
| 1373 | |
| 1374 | #ifdef CONFIG_ALTIVEC |
| 1375 | extern void do_load_up_altivec(struct pt_regs *regs); |
| 1376 | |
| 1377 | void altivec_unavailable_tm(struct pt_regs *regs) |
| 1378 | { |
| 1379 | /* See the comments in fp_unavailable_tm(). This function operates |
| 1380 | * the same way. |
| 1381 | */ |
| 1382 | |
| 1383 | TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," |
| 1384 | "MSR=%lx\n", |
| 1385 | regs->nip, regs->msr); |
| 1386 | tm_enable(); |
| 1387 | tm_reclaim(¤t->thread, current->thread.regs->msr, |
| 1388 | TM_CAUSE_FAC_UNAV); |
| 1389 | regs->msr |= MSR_VEC; |
| 1390 | tm_recheckpoint(¤t->thread, regs->msr); |
| 1391 | current->thread.used_vr = 1; |
| 1392 | } |
| 1393 | #endif |
| 1394 | |
| 1395 | #ifdef CONFIG_VSX |
| 1396 | void vsx_unavailable_tm(struct pt_regs *regs) |
| 1397 | { |
| 1398 | /* See the comments in fp_unavailable_tm(). This works similarly, |
| 1399 | * though we're loading both FP and VEC registers in here. |
| 1400 | * |
| 1401 | * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC |
| 1402 | * regs. Either way, set MSR_VSX. |
| 1403 | */ |
| 1404 | |
| 1405 | TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," |
| 1406 | "MSR=%lx\n", |
| 1407 | regs->nip, regs->msr); |
| 1408 | |
| 1409 | tm_enable(); |
| 1410 | /* This reclaims FP and/or VR regs if they're already enabled */ |
| 1411 | tm_reclaim(¤t->thread, current->thread.regs->msr, |
| 1412 | TM_CAUSE_FAC_UNAV); |
| 1413 | |
| 1414 | regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | |
| 1415 | MSR_VSX; |
| 1416 | /* This loads & recheckpoints FP and VRs. */ |
| 1417 | tm_recheckpoint(¤t->thread, regs->msr); |
| 1418 | current->thread.used_vsr = 1; |
| 1419 | } |
| 1420 | #endif |
| 1421 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
| 1422 | |
| 1423 | void performance_monitor_exception(struct pt_regs *regs) |
| 1424 | { |
| 1425 | __get_cpu_var(irq_stat).pmu_irqs++; |
| 1426 | |
| 1427 | perf_irq(regs); |
| 1428 | } |
| 1429 | |
| 1430 | #ifdef CONFIG_8xx |
| 1431 | void SoftwareEmulation(struct pt_regs *regs) |
| 1432 | { |
| 1433 | extern int do_mathemu(struct pt_regs *); |
| 1434 | extern int Soft_emulate_8xx(struct pt_regs *); |
| 1435 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
| 1436 | int errcode; |
| 1437 | #endif |
| 1438 | |
| 1439 | CHECK_FULL_REGS(regs); |
| 1440 | |
| 1441 | if (!user_mode(regs)) { |
| 1442 | debugger(regs); |
| 1443 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); |
| 1444 | } |
| 1445 | |
| 1446 | #ifdef CONFIG_MATH_EMULATION |
| 1447 | errcode = do_mathemu(regs); |
| 1448 | if (errcode >= 0) |
| 1449 | PPC_WARN_EMULATED(math, regs); |
| 1450 | |
| 1451 | switch (errcode) { |
| 1452 | case 0: |
| 1453 | emulate_single_step(regs); |
| 1454 | return; |
| 1455 | case 1: { |
| 1456 | int code = 0; |
| 1457 | code = __parse_fpscr(current->thread.fpscr.val); |
| 1458 | _exception(SIGFPE, regs, code, regs->nip); |
| 1459 | return; |
| 1460 | } |
| 1461 | case -EFAULT: |
| 1462 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); |
| 1463 | return; |
| 1464 | default: |
| 1465 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1466 | return; |
| 1467 | } |
| 1468 | |
| 1469 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
| 1470 | errcode = Soft_emulate_8xx(regs); |
| 1471 | if (errcode >= 0) |
| 1472 | PPC_WARN_EMULATED(8xx, regs); |
| 1473 | |
| 1474 | switch (errcode) { |
| 1475 | case 0: |
| 1476 | emulate_single_step(regs); |
| 1477 | return; |
| 1478 | case 1: |
| 1479 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1480 | return; |
| 1481 | case -EFAULT: |
| 1482 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); |
| 1483 | return; |
| 1484 | } |
| 1485 | #else |
| 1486 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1487 | #endif |
| 1488 | } |
| 1489 | #endif /* CONFIG_8xx */ |
| 1490 | |
| 1491 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
| 1492 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
| 1493 | { |
| 1494 | int changed = 0; |
| 1495 | /* |
| 1496 | * Determine the cause of the debug event, clear the |
| 1497 | * event flags and send a trap to the handler. Torez |
| 1498 | */ |
| 1499 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { |
| 1500 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
| 1501 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
| 1502 | current->thread.dbcr2 &= ~DBCR2_DAC12MODE; |
| 1503 | #endif |
| 1504 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, |
| 1505 | 5); |
| 1506 | changed |= 0x01; |
| 1507 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { |
| 1508 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
| 1509 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, |
| 1510 | 6); |
| 1511 | changed |= 0x01; |
| 1512 | } else if (debug_status & DBSR_IAC1) { |
| 1513 | current->thread.dbcr0 &= ~DBCR0_IAC1; |
| 1514 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; |
| 1515 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, |
| 1516 | 1); |
| 1517 | changed |= 0x01; |
| 1518 | } else if (debug_status & DBSR_IAC2) { |
| 1519 | current->thread.dbcr0 &= ~DBCR0_IAC2; |
| 1520 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, |
| 1521 | 2); |
| 1522 | changed |= 0x01; |
| 1523 | } else if (debug_status & DBSR_IAC3) { |
| 1524 | current->thread.dbcr0 &= ~DBCR0_IAC3; |
| 1525 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; |
| 1526 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, |
| 1527 | 3); |
| 1528 | changed |= 0x01; |
| 1529 | } else if (debug_status & DBSR_IAC4) { |
| 1530 | current->thread.dbcr0 &= ~DBCR0_IAC4; |
| 1531 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, |
| 1532 | 4); |
| 1533 | changed |= 0x01; |
| 1534 | } |
| 1535 | /* |
| 1536 | * At the point this routine was called, the MSR(DE) was turned off. |
| 1537 | * Check all other debug flags and see if that bit needs to be turned |
| 1538 | * back on or not. |
| 1539 | */ |
| 1540 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) |
| 1541 | regs->msr |= MSR_DE; |
| 1542 | else |
| 1543 | /* Make sure the IDM flag is off */ |
| 1544 | current->thread.dbcr0 &= ~DBCR0_IDM; |
| 1545 | |
| 1546 | if (changed & 0x01) |
| 1547 | mtspr(SPRN_DBCR0, current->thread.dbcr0); |
| 1548 | } |
| 1549 | |
| 1550 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
| 1551 | { |
| 1552 | current->thread.dbsr = debug_status; |
| 1553 | |
| 1554 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
| 1555 | * on server, it stops on the target of the branch. In order to simulate |
| 1556 | * the server behaviour, we thus restart right away with a single step |
| 1557 | * instead of stopping here when hitting a BT |
| 1558 | */ |
| 1559 | if (debug_status & DBSR_BT) { |
| 1560 | regs->msr &= ~MSR_DE; |
| 1561 | |
| 1562 | /* Disable BT */ |
| 1563 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); |
| 1564 | /* Clear the BT event */ |
| 1565 | mtspr(SPRN_DBSR, DBSR_BT); |
| 1566 | |
| 1567 | /* Do the single step trick only when coming from userspace */ |
| 1568 | if (user_mode(regs)) { |
| 1569 | current->thread.dbcr0 &= ~DBCR0_BT; |
| 1570 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; |
| 1571 | regs->msr |= MSR_DE; |
| 1572 | return; |
| 1573 | } |
| 1574 | |
| 1575 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, |
| 1576 | 5, SIGTRAP) == NOTIFY_STOP) { |
| 1577 | return; |
| 1578 | } |
| 1579 | if (debugger_sstep(regs)) |
| 1580 | return; |
| 1581 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ |
| 1582 | regs->msr &= ~MSR_DE; |
| 1583 | |
| 1584 | /* Disable instruction completion */ |
| 1585 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); |
| 1586 | /* Clear the instruction completion event */ |
| 1587 | mtspr(SPRN_DBSR, DBSR_IC); |
| 1588 | |
| 1589 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
| 1590 | 5, SIGTRAP) == NOTIFY_STOP) { |
| 1591 | return; |
| 1592 | } |
| 1593 | |
| 1594 | if (debugger_sstep(regs)) |
| 1595 | return; |
| 1596 | |
| 1597 | if (user_mode(regs)) { |
| 1598 | current->thread.dbcr0 &= ~DBCR0_IC; |
| 1599 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, |
| 1600 | current->thread.dbcr1)) |
| 1601 | regs->msr |= MSR_DE; |
| 1602 | else |
| 1603 | /* Make sure the IDM bit is off */ |
| 1604 | current->thread.dbcr0 &= ~DBCR0_IDM; |
| 1605 | } |
| 1606 | |
| 1607 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); |
| 1608 | } else |
| 1609 | handle_debug(regs, debug_status); |
| 1610 | } |
| 1611 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
| 1612 | |
| 1613 | #if !defined(CONFIG_TAU_INT) |
| 1614 | void TAUException(struct pt_regs *regs) |
| 1615 | { |
| 1616 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", |
| 1617 | regs->nip, regs->msr, regs->trap, print_tainted()); |
| 1618 | } |
| 1619 | #endif /* CONFIG_INT_TAU */ |
| 1620 | |
| 1621 | #ifdef CONFIG_ALTIVEC |
| 1622 | void altivec_assist_exception(struct pt_regs *regs) |
| 1623 | { |
| 1624 | int err; |
| 1625 | |
| 1626 | if (!user_mode(regs)) { |
| 1627 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" |
| 1628 | " at %lx\n", regs->nip); |
| 1629 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
| 1630 | } |
| 1631 | |
| 1632 | flush_altivec_to_thread(current); |
| 1633 | |
| 1634 | PPC_WARN_EMULATED(altivec, regs); |
| 1635 | err = emulate_altivec(regs); |
| 1636 | if (err == 0) { |
| 1637 | regs->nip += 4; /* skip emulated instruction */ |
| 1638 | emulate_single_step(regs); |
| 1639 | return; |
| 1640 | } |
| 1641 | |
| 1642 | if (err == -EFAULT) { |
| 1643 | /* got an error reading the instruction */ |
| 1644 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); |
| 1645 | } else { |
| 1646 | /* didn't recognize the instruction */ |
| 1647 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ |
| 1648 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
| 1649 | "in %s at %lx\n", current->comm, regs->nip); |
| 1650 | current->thread.vscr.u[3] |= 0x10000; |
| 1651 | } |
| 1652 | } |
| 1653 | #endif /* CONFIG_ALTIVEC */ |
| 1654 | |
| 1655 | #ifdef CONFIG_VSX |
| 1656 | void vsx_assist_exception(struct pt_regs *regs) |
| 1657 | { |
| 1658 | if (!user_mode(regs)) { |
| 1659 | printk(KERN_EMERG "VSX assist exception in kernel mode" |
| 1660 | " at %lx\n", regs->nip); |
| 1661 | die("Kernel VSX assist exception", regs, SIGILL); |
| 1662 | } |
| 1663 | |
| 1664 | flush_vsx_to_thread(current); |
| 1665 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); |
| 1666 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1667 | } |
| 1668 | #endif /* CONFIG_VSX */ |
| 1669 | |
| 1670 | #ifdef CONFIG_FSL_BOOKE |
| 1671 | void CacheLockingException(struct pt_regs *regs, unsigned long address, |
| 1672 | unsigned long error_code) |
| 1673 | { |
| 1674 | /* We treat cache locking instructions from the user |
| 1675 | * as priv ops, in the future we could try to do |
| 1676 | * something smarter |
| 1677 | */ |
| 1678 | if (error_code & (ESR_DLK|ESR_ILK)) |
| 1679 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); |
| 1680 | return; |
| 1681 | } |
| 1682 | #endif /* CONFIG_FSL_BOOKE */ |
| 1683 | |
| 1684 | #ifdef CONFIG_SPE |
| 1685 | void SPEFloatingPointException(struct pt_regs *regs) |
| 1686 | { |
| 1687 | extern int do_spe_mathemu(struct pt_regs *regs); |
| 1688 | unsigned long spefscr; |
| 1689 | int fpexc_mode; |
| 1690 | int code = 0; |
| 1691 | int err; |
| 1692 | |
| 1693 | flush_spe_to_thread(current); |
| 1694 | |
| 1695 | spefscr = current->thread.spefscr; |
| 1696 | fpexc_mode = current->thread.fpexc_mode; |
| 1697 | |
| 1698 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
| 1699 | code = FPE_FLTOVF; |
| 1700 | } |
| 1701 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { |
| 1702 | code = FPE_FLTUND; |
| 1703 | } |
| 1704 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) |
| 1705 | code = FPE_FLTDIV; |
| 1706 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { |
| 1707 | code = FPE_FLTINV; |
| 1708 | } |
| 1709 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) |
| 1710 | code = FPE_FLTRES; |
| 1711 | |
| 1712 | err = do_spe_mathemu(regs); |
| 1713 | if (err == 0) { |
| 1714 | regs->nip += 4; /* skip emulated instruction */ |
| 1715 | emulate_single_step(regs); |
| 1716 | return; |
| 1717 | } |
| 1718 | |
| 1719 | if (err == -EFAULT) { |
| 1720 | /* got an error reading the instruction */ |
| 1721 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); |
| 1722 | } else if (err == -EINVAL) { |
| 1723 | /* didn't recognize the instruction */ |
| 1724 | printk(KERN_ERR "unrecognized spe instruction " |
| 1725 | "in %s at %lx\n", current->comm, regs->nip); |
| 1726 | } else { |
| 1727 | _exception(SIGFPE, regs, code, regs->nip); |
| 1728 | } |
| 1729 | |
| 1730 | return; |
| 1731 | } |
| 1732 | |
| 1733 | void SPEFloatingPointRoundException(struct pt_regs *regs) |
| 1734 | { |
| 1735 | extern int speround_handler(struct pt_regs *regs); |
| 1736 | int err; |
| 1737 | |
| 1738 | preempt_disable(); |
| 1739 | if (regs->msr & MSR_SPE) |
| 1740 | giveup_spe(current); |
| 1741 | preempt_enable(); |
| 1742 | |
| 1743 | regs->nip -= 4; |
| 1744 | err = speround_handler(regs); |
| 1745 | if (err == 0) { |
| 1746 | regs->nip += 4; /* skip emulated instruction */ |
| 1747 | emulate_single_step(regs); |
| 1748 | return; |
| 1749 | } |
| 1750 | |
| 1751 | if (err == -EFAULT) { |
| 1752 | /* got an error reading the instruction */ |
| 1753 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); |
| 1754 | } else if (err == -EINVAL) { |
| 1755 | /* didn't recognize the instruction */ |
| 1756 | printk(KERN_ERR "unrecognized spe instruction " |
| 1757 | "in %s at %lx\n", current->comm, regs->nip); |
| 1758 | } else { |
| 1759 | _exception(SIGFPE, regs, 0, regs->nip); |
| 1760 | return; |
| 1761 | } |
| 1762 | } |
| 1763 | #endif |
| 1764 | |
| 1765 | /* |
| 1766 | * We enter here if we get an unrecoverable exception, that is, one |
| 1767 | * that happened at a point where the RI (recoverable interrupt) bit |
| 1768 | * in the MSR is 0. This indicates that SRR0/1 are live, and that |
| 1769 | * we therefore lost state by taking this exception. |
| 1770 | */ |
| 1771 | void unrecoverable_exception(struct pt_regs *regs) |
| 1772 | { |
| 1773 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", |
| 1774 | regs->trap, regs->nip); |
| 1775 | die("Unrecoverable exception", regs, SIGABRT); |
| 1776 | } |
| 1777 | |
| 1778 | #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) |
| 1779 | /* |
| 1780 | * Default handler for a Watchdog exception, |
| 1781 | * spins until a reboot occurs |
| 1782 | */ |
| 1783 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) |
| 1784 | { |
| 1785 | /* Generic WatchdogHandler, implement your own */ |
| 1786 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); |
| 1787 | return; |
| 1788 | } |
| 1789 | |
| 1790 | void WatchdogException(struct pt_regs *regs) |
| 1791 | { |
| 1792 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); |
| 1793 | WatchdogHandler(regs); |
| 1794 | } |
| 1795 | #endif |
| 1796 | |
| 1797 | /* |
| 1798 | * We enter here if we discover during exception entry that we are |
| 1799 | * running in supervisor mode with a userspace value in the stack pointer. |
| 1800 | */ |
| 1801 | void kernel_bad_stack(struct pt_regs *regs) |
| 1802 | { |
| 1803 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", |
| 1804 | regs->gpr[1], regs->nip); |
| 1805 | die("Bad kernel stack pointer", regs, SIGABRT); |
| 1806 | } |
| 1807 | |
| 1808 | void __init trap_init(void) |
| 1809 | { |
| 1810 | } |
| 1811 | |
| 1812 | |
| 1813 | #ifdef CONFIG_PPC_EMULATED_STATS |
| 1814 | |
| 1815 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } |
| 1816 | |
| 1817 | struct ppc_emulated ppc_emulated = { |
| 1818 | #ifdef CONFIG_ALTIVEC |
| 1819 | WARN_EMULATED_SETUP(altivec), |
| 1820 | #endif |
| 1821 | WARN_EMULATED_SETUP(dcba), |
| 1822 | WARN_EMULATED_SETUP(dcbz), |
| 1823 | WARN_EMULATED_SETUP(fp_pair), |
| 1824 | WARN_EMULATED_SETUP(isel), |
| 1825 | WARN_EMULATED_SETUP(mcrxr), |
| 1826 | WARN_EMULATED_SETUP(mfpvr), |
| 1827 | WARN_EMULATED_SETUP(multiple), |
| 1828 | WARN_EMULATED_SETUP(popcntb), |
| 1829 | WARN_EMULATED_SETUP(spe), |
| 1830 | WARN_EMULATED_SETUP(string), |
| 1831 | WARN_EMULATED_SETUP(unaligned), |
| 1832 | #ifdef CONFIG_MATH_EMULATION |
| 1833 | WARN_EMULATED_SETUP(math), |
| 1834 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
| 1835 | WARN_EMULATED_SETUP(8xx), |
| 1836 | #endif |
| 1837 | #ifdef CONFIG_VSX |
| 1838 | WARN_EMULATED_SETUP(vsx), |
| 1839 | #endif |
| 1840 | #ifdef CONFIG_PPC64 |
| 1841 | WARN_EMULATED_SETUP(mfdscr), |
| 1842 | WARN_EMULATED_SETUP(mtdscr), |
| 1843 | #endif |
| 1844 | }; |
| 1845 | |
| 1846 | u32 ppc_warn_emulated; |
| 1847 | |
| 1848 | void ppc_warn_emulated_print(const char *type) |
| 1849 | { |
| 1850 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
| 1851 | type); |
| 1852 | } |
| 1853 | |
| 1854 | static int __init ppc_warn_emulated_init(void) |
| 1855 | { |
| 1856 | struct dentry *dir, *d; |
| 1857 | unsigned int i; |
| 1858 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; |
| 1859 | |
| 1860 | if (!powerpc_debugfs_root) |
| 1861 | return -ENODEV; |
| 1862 | |
| 1863 | dir = debugfs_create_dir("emulated_instructions", |
| 1864 | powerpc_debugfs_root); |
| 1865 | if (!dir) |
| 1866 | return -ENOMEM; |
| 1867 | |
| 1868 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, |
| 1869 | &ppc_warn_emulated); |
| 1870 | if (!d) |
| 1871 | goto fail; |
| 1872 | |
| 1873 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { |
| 1874 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, |
| 1875 | (u32 *)&entries[i].val.counter); |
| 1876 | if (!d) |
| 1877 | goto fail; |
| 1878 | } |
| 1879 | |
| 1880 | return 0; |
| 1881 | |
| 1882 | fail: |
| 1883 | debugfs_remove_recursive(dir); |
| 1884 | return -ENOMEM; |
| 1885 | } |
| 1886 | |
| 1887 | device_initcall(ppc_warn_emulated_init); |
| 1888 | |
| 1889 | #endif /* CONFIG_PPC_EMULATED_STATS */ |