| 1 | /* |
| 2 | * Common pmac/prep/chrp pci routines. -- Cort |
| 3 | */ |
| 4 | |
| 5 | #include <linux/kernel.h> |
| 6 | #include <linux/pci.h> |
| 7 | #include <linux/delay.h> |
| 8 | #include <linux/string.h> |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/capability.h> |
| 11 | #include <linux/sched.h> |
| 12 | #include <linux/errno.h> |
| 13 | #include <linux/bootmem.h> |
| 14 | #include <linux/irq.h> |
| 15 | #include <linux/list.h> |
| 16 | |
| 17 | #include <asm/processor.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <asm/prom.h> |
| 20 | #include <asm/sections.h> |
| 21 | #include <asm/pci-bridge.h> |
| 22 | #include <asm/byteorder.h> |
| 23 | #include <asm/uaccess.h> |
| 24 | #include <asm/machdep.h> |
| 25 | |
| 26 | #undef DEBUG |
| 27 | |
| 28 | #ifdef DEBUG |
| 29 | #define DBG(x...) printk(x) |
| 30 | #else |
| 31 | #define DBG(x...) |
| 32 | #endif |
| 33 | |
| 34 | unsigned long isa_io_base = 0; |
| 35 | unsigned long isa_mem_base = 0; |
| 36 | unsigned long pci_dram_offset = 0; |
| 37 | int pcibios_assign_bus_offset = 1; |
| 38 | |
| 39 | void pcibios_make_OF_bus_map(void); |
| 40 | |
| 41 | static int pci_relocate_bridge_resource(struct pci_bus *bus, int i); |
| 42 | static int probe_resource(struct pci_bus *parent, struct resource *pr, |
| 43 | struct resource *res, struct resource **conflict); |
| 44 | static void update_bridge_base(struct pci_bus *bus, int i); |
| 45 | static void pcibios_fixup_resources(struct pci_dev* dev); |
| 46 | static void fixup_broken_pcnet32(struct pci_dev* dev); |
| 47 | static int reparent_resources(struct resource *parent, struct resource *res); |
| 48 | static void fixup_cpc710_pci64(struct pci_dev* dev); |
| 49 | #ifdef CONFIG_PPC_OF |
| 50 | static u8* pci_to_OF_bus_map; |
| 51 | #endif |
| 52 | |
| 53 | /* By default, we don't re-assign bus numbers. We do this only on |
| 54 | * some pmacs |
| 55 | */ |
| 56 | int pci_assign_all_buses; |
| 57 | |
| 58 | struct pci_controller* hose_head; |
| 59 | struct pci_controller** hose_tail = &hose_head; |
| 60 | |
| 61 | static int pci_bus_count; |
| 62 | |
| 63 | static void |
| 64 | fixup_broken_pcnet32(struct pci_dev* dev) |
| 65 | { |
| 66 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { |
| 67 | dev->vendor = PCI_VENDOR_ID_AMD; |
| 68 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); |
| 69 | } |
| 70 | } |
| 71 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); |
| 72 | |
| 73 | static void |
| 74 | fixup_cpc710_pci64(struct pci_dev* dev) |
| 75 | { |
| 76 | /* Hide the PCI64 BARs from the kernel as their content doesn't |
| 77 | * fit well in the resource management |
| 78 | */ |
| 79 | dev->resource[0].start = dev->resource[0].end = 0; |
| 80 | dev->resource[0].flags = 0; |
| 81 | dev->resource[1].start = dev->resource[1].end = 0; |
| 82 | dev->resource[1].flags = 0; |
| 83 | } |
| 84 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64); |
| 85 | |
| 86 | static void |
| 87 | pcibios_fixup_resources(struct pci_dev *dev) |
| 88 | { |
| 89 | struct pci_controller* hose = (struct pci_controller *)dev->sysdata; |
| 90 | int i; |
| 91 | unsigned long offset; |
| 92 | |
| 93 | if (!hose) { |
| 94 | printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev)); |
| 95 | return; |
| 96 | } |
| 97 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 98 | struct resource *res = dev->resource + i; |
| 99 | if (!res->flags) |
| 100 | continue; |
| 101 | if (res->end == 0xffffffff) { |
| 102 | DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n", |
| 103 | pci_name(dev), i, res->start, res->end); |
| 104 | res->end -= res->start; |
| 105 | res->start = 0; |
| 106 | res->flags |= IORESOURCE_UNSET; |
| 107 | continue; |
| 108 | } |
| 109 | offset = 0; |
| 110 | if (res->flags & IORESOURCE_MEM) { |
| 111 | offset = hose->pci_mem_offset; |
| 112 | } else if (res->flags & IORESOURCE_IO) { |
| 113 | offset = (unsigned long) hose->io_base_virt |
| 114 | - isa_io_base; |
| 115 | } |
| 116 | if (offset != 0) { |
| 117 | res->start += offset; |
| 118 | res->end += offset; |
| 119 | #ifdef DEBUG |
| 120 | printk("Fixup res %d (%lx) of dev %s: %llx -> %llx\n", |
| 121 | i, res->flags, pci_name(dev), |
| 122 | res->start - offset, res->start); |
| 123 | #endif |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | /* Call machine specific resource fixup */ |
| 128 | if (ppc_md.pcibios_fixup_resources) |
| 129 | ppc_md.pcibios_fixup_resources(dev); |
| 130 | } |
| 131 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); |
| 132 | |
| 133 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
| 134 | struct resource *res) |
| 135 | { |
| 136 | unsigned long offset = 0; |
| 137 | struct pci_controller *hose = dev->sysdata; |
| 138 | |
| 139 | if (hose && res->flags & IORESOURCE_IO) |
| 140 | offset = (unsigned long)hose->io_base_virt - isa_io_base; |
| 141 | else if (hose && res->flags & IORESOURCE_MEM) |
| 142 | offset = hose->pci_mem_offset; |
| 143 | region->start = res->start - offset; |
| 144 | region->end = res->end - offset; |
| 145 | } |
| 146 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
| 147 | |
| 148 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
| 149 | struct pci_bus_region *region) |
| 150 | { |
| 151 | unsigned long offset = 0; |
| 152 | struct pci_controller *hose = dev->sysdata; |
| 153 | |
| 154 | if (hose && res->flags & IORESOURCE_IO) |
| 155 | offset = (unsigned long)hose->io_base_virt - isa_io_base; |
| 156 | else if (hose && res->flags & IORESOURCE_MEM) |
| 157 | offset = hose->pci_mem_offset; |
| 158 | res->start = region->start + offset; |
| 159 | res->end = region->end + offset; |
| 160 | } |
| 161 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
| 162 | |
| 163 | /* |
| 164 | * We need to avoid collisions with `mirrored' VGA ports |
| 165 | * and other strange ISA hardware, so we always want the |
| 166 | * addresses to be allocated in the 0x000-0x0ff region |
| 167 | * modulo 0x400. |
| 168 | * |
| 169 | * Why? Because some silly external IO cards only decode |
| 170 | * the low 10 bits of the IO address. The 0x00-0xff region |
| 171 | * is reserved for motherboard devices that decode all 16 |
| 172 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, |
| 173 | * but we want to try to avoid allocating at 0x2900-0x2bff |
| 174 | * which might have be mirrored at 0x0100-0x03ff.. |
| 175 | */ |
| 176 | void pcibios_align_resource(void *data, struct resource *res, |
| 177 | resource_size_t size, resource_size_t align) |
| 178 | { |
| 179 | struct pci_dev *dev = data; |
| 180 | |
| 181 | if (res->flags & IORESOURCE_IO) { |
| 182 | resource_size_t start = res->start; |
| 183 | |
| 184 | if (size > 0x100) { |
| 185 | printk(KERN_ERR "PCI: I/O Region %s/%d too large" |
| 186 | " (%lld bytes)\n", pci_name(dev), |
| 187 | dev->resource - res, (unsigned long long)size); |
| 188 | } |
| 189 | |
| 190 | if (start & 0x300) { |
| 191 | start = (start + 0x3ff) & ~0x3ff; |
| 192 | res->start = start; |
| 193 | } |
| 194 | } |
| 195 | } |
| 196 | EXPORT_SYMBOL(pcibios_align_resource); |
| 197 | |
| 198 | /* |
| 199 | * Handle resources of PCI devices. If the world were perfect, we could |
| 200 | * just allocate all the resource regions and do nothing more. It isn't. |
| 201 | * On the other hand, we cannot just re-allocate all devices, as it would |
| 202 | * require us to know lots of host bridge internals. So we attempt to |
| 203 | * keep as much of the original configuration as possible, but tweak it |
| 204 | * when it's found to be wrong. |
| 205 | * |
| 206 | * Known BIOS problems we have to work around: |
| 207 | * - I/O or memory regions not configured |
| 208 | * - regions configured, but not enabled in the command register |
| 209 | * - bogus I/O addresses above 64K used |
| 210 | * - expansion ROMs left enabled (this may sound harmless, but given |
| 211 | * the fact the PCI specs explicitly allow address decoders to be |
| 212 | * shared between expansion ROMs and other resource regions, it's |
| 213 | * at least dangerous) |
| 214 | * |
| 215 | * Our solution: |
| 216 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. |
| 217 | * This gives us fixed barriers on where we can allocate. |
| 218 | * (2) Allocate resources for all enabled devices. If there is |
| 219 | * a collision, just mark the resource as unallocated. Also |
| 220 | * disable expansion ROMs during this step. |
| 221 | * (3) Try to allocate resources for disabled devices. If the |
| 222 | * resources were assigned correctly, everything goes well, |
| 223 | * if they weren't, they won't disturb allocation of other |
| 224 | * resources. |
| 225 | * (4) Assign new addresses to resources which were either |
| 226 | * not configured at all or misconfigured. If explicitly |
| 227 | * requested by the user, configure expansion ROM address |
| 228 | * as well. |
| 229 | */ |
| 230 | |
| 231 | static void __init |
| 232 | pcibios_allocate_bus_resources(struct list_head *bus_list) |
| 233 | { |
| 234 | struct pci_bus *bus; |
| 235 | int i; |
| 236 | struct resource *res, *pr; |
| 237 | |
| 238 | /* Depth-First Search on bus tree */ |
| 239 | list_for_each_entry(bus, bus_list, node) { |
| 240 | for (i = 0; i < 4; ++i) { |
| 241 | if ((res = bus->resource[i]) == NULL || !res->flags |
| 242 | || res->start > res->end) |
| 243 | continue; |
| 244 | if (bus->parent == NULL) |
| 245 | pr = (res->flags & IORESOURCE_IO)? |
| 246 | &ioport_resource: &iomem_resource; |
| 247 | else { |
| 248 | pr = pci_find_parent_resource(bus->self, res); |
| 249 | if (pr == res) { |
| 250 | /* this happens when the generic PCI |
| 251 | * code (wrongly) decides that this |
| 252 | * bridge is transparent -- paulus |
| 253 | */ |
| 254 | continue; |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n", |
| 259 | res->start, res->end, res->flags, pr); |
| 260 | if (pr) { |
| 261 | if (request_resource(pr, res) == 0) |
| 262 | continue; |
| 263 | /* |
| 264 | * Must be a conflict with an existing entry. |
| 265 | * Move that entry (or entries) under the |
| 266 | * bridge resource and try again. |
| 267 | */ |
| 268 | if (reparent_resources(pr, res) == 0) |
| 269 | continue; |
| 270 | } |
| 271 | printk(KERN_ERR "PCI: Cannot allocate resource region " |
| 272 | "%d of PCI bridge %d\n", i, bus->number); |
| 273 | if (pci_relocate_bridge_resource(bus, i)) |
| 274 | bus->resource[i] = NULL; |
| 275 | } |
| 276 | pcibios_allocate_bus_resources(&bus->children); |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | /* |
| 281 | * Reparent resource children of pr that conflict with res |
| 282 | * under res, and make res replace those children. |
| 283 | */ |
| 284 | static int __init |
| 285 | reparent_resources(struct resource *parent, struct resource *res) |
| 286 | { |
| 287 | struct resource *p, **pp; |
| 288 | struct resource **firstpp = NULL; |
| 289 | |
| 290 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { |
| 291 | if (p->end < res->start) |
| 292 | continue; |
| 293 | if (res->end < p->start) |
| 294 | break; |
| 295 | if (p->start < res->start || p->end > res->end) |
| 296 | return -1; /* not completely contained */ |
| 297 | if (firstpp == NULL) |
| 298 | firstpp = pp; |
| 299 | } |
| 300 | if (firstpp == NULL) |
| 301 | return -1; /* didn't find any conflicting entries? */ |
| 302 | res->parent = parent; |
| 303 | res->child = *firstpp; |
| 304 | res->sibling = *pp; |
| 305 | *firstpp = res; |
| 306 | *pp = NULL; |
| 307 | for (p = res->child; p != NULL; p = p->sibling) { |
| 308 | p->parent = res; |
| 309 | DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n", |
| 310 | p->name, p->start, p->end, res->name); |
| 311 | } |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | /* |
| 316 | * A bridge has been allocated a range which is outside the range |
| 317 | * of its parent bridge, so it needs to be moved. |
| 318 | */ |
| 319 | static int __init |
| 320 | pci_relocate_bridge_resource(struct pci_bus *bus, int i) |
| 321 | { |
| 322 | struct resource *res, *pr, *conflict; |
| 323 | unsigned long try, size; |
| 324 | int j; |
| 325 | struct pci_bus *parent = bus->parent; |
| 326 | |
| 327 | if (parent == NULL) { |
| 328 | /* shouldn't ever happen */ |
| 329 | printk(KERN_ERR "PCI: can't move host bridge resource\n"); |
| 330 | return -1; |
| 331 | } |
| 332 | res = bus->resource[i]; |
| 333 | if (res == NULL) |
| 334 | return -1; |
| 335 | pr = NULL; |
| 336 | for (j = 0; j < 4; j++) { |
| 337 | struct resource *r = parent->resource[j]; |
| 338 | if (!r) |
| 339 | continue; |
| 340 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) |
| 341 | continue; |
| 342 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) { |
| 343 | pr = r; |
| 344 | break; |
| 345 | } |
| 346 | if (res->flags & IORESOURCE_PREFETCH) |
| 347 | pr = r; |
| 348 | } |
| 349 | if (pr == NULL) |
| 350 | return -1; |
| 351 | size = res->end - res->start; |
| 352 | if (pr->start > pr->end || size > pr->end - pr->start) |
| 353 | return -1; |
| 354 | try = pr->end; |
| 355 | for (;;) { |
| 356 | res->start = try - size; |
| 357 | res->end = try; |
| 358 | if (probe_resource(bus->parent, pr, res, &conflict) == 0) |
| 359 | break; |
| 360 | if (conflict->start <= pr->start + size) |
| 361 | return -1; |
| 362 | try = conflict->start - 1; |
| 363 | } |
| 364 | if (request_resource(pr, res)) { |
| 365 | DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n", |
| 366 | res->start, res->end); |
| 367 | return -1; /* "can't happen" */ |
| 368 | } |
| 369 | update_bridge_base(bus, i); |
| 370 | printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n", |
| 371 | bus->number, i, (unsigned long long)res->start, |
| 372 | (unsigned long long)res->end); |
| 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | static int __init |
| 377 | probe_resource(struct pci_bus *parent, struct resource *pr, |
| 378 | struct resource *res, struct resource **conflict) |
| 379 | { |
| 380 | struct pci_bus *bus; |
| 381 | struct pci_dev *dev; |
| 382 | struct resource *r; |
| 383 | int i; |
| 384 | |
| 385 | for (r = pr->child; r != NULL; r = r->sibling) { |
| 386 | if (r->end >= res->start && res->end >= r->start) { |
| 387 | *conflict = r; |
| 388 | return 1; |
| 389 | } |
| 390 | } |
| 391 | list_for_each_entry(bus, &parent->children, node) { |
| 392 | for (i = 0; i < 4; ++i) { |
| 393 | if ((r = bus->resource[i]) == NULL) |
| 394 | continue; |
| 395 | if (!r->flags || r->start > r->end || r == res) |
| 396 | continue; |
| 397 | if (pci_find_parent_resource(bus->self, r) != pr) |
| 398 | continue; |
| 399 | if (r->end >= res->start && res->end >= r->start) { |
| 400 | *conflict = r; |
| 401 | return 1; |
| 402 | } |
| 403 | } |
| 404 | } |
| 405 | list_for_each_entry(dev, &parent->devices, bus_list) { |
| 406 | for (i = 0; i < 6; ++i) { |
| 407 | r = &dev->resource[i]; |
| 408 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) |
| 409 | continue; |
| 410 | if (pci_find_parent_resource(dev, r) != pr) |
| 411 | continue; |
| 412 | if (r->end >= res->start && res->end >= r->start) { |
| 413 | *conflict = r; |
| 414 | return 1; |
| 415 | } |
| 416 | } |
| 417 | } |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | static void __init |
| 422 | update_bridge_base(struct pci_bus *bus, int i) |
| 423 | { |
| 424 | struct resource *res = bus->resource[i]; |
| 425 | u8 io_base_lo, io_limit_lo; |
| 426 | u16 mem_base, mem_limit; |
| 427 | u16 cmd; |
| 428 | unsigned long start, end, off; |
| 429 | struct pci_dev *dev = bus->self; |
| 430 | struct pci_controller *hose = dev->sysdata; |
| 431 | |
| 432 | if (!hose) { |
| 433 | printk("update_bridge_base: no hose?\n"); |
| 434 | return; |
| 435 | } |
| 436 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 437 | pci_write_config_word(dev, PCI_COMMAND, |
| 438 | cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); |
| 439 | if (res->flags & IORESOURCE_IO) { |
| 440 | off = (unsigned long) hose->io_base_virt - isa_io_base; |
| 441 | start = res->start - off; |
| 442 | end = res->end - off; |
| 443 | io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK; |
| 444 | io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK; |
| 445 | if (end > 0xffff) |
| 446 | io_base_lo |= PCI_IO_RANGE_TYPE_32; |
| 447 | else |
| 448 | io_base_lo |= PCI_IO_RANGE_TYPE_16; |
| 449 | pci_write_config_word(dev, PCI_IO_BASE_UPPER16, |
| 450 | start >> 16); |
| 451 | pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, |
| 452 | end >> 16); |
| 453 | pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo); |
| 454 | pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo); |
| 455 | |
| 456 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) |
| 457 | == IORESOURCE_MEM) { |
| 458 | off = hose->pci_mem_offset; |
| 459 | mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK; |
| 460 | mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK; |
| 461 | pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base); |
| 462 | pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit); |
| 463 | |
| 464 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) |
| 465 | == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) { |
| 466 | off = hose->pci_mem_offset; |
| 467 | mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK; |
| 468 | mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK; |
| 469 | pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base); |
| 470 | pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); |
| 471 | |
| 472 | } else { |
| 473 | DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n", |
| 474 | pci_name(dev), i, res->flags); |
| 475 | } |
| 476 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 477 | } |
| 478 | |
| 479 | static inline void alloc_resource(struct pci_dev *dev, int idx) |
| 480 | { |
| 481 | struct resource *pr, *r = &dev->resource[idx]; |
| 482 | |
| 483 | DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n", |
| 484 | pci_name(dev), idx, r->start, r->end, r->flags); |
| 485 | pr = pci_find_parent_resource(dev, r); |
| 486 | if (!pr || request_resource(pr, r) < 0) { |
| 487 | printk(KERN_ERR "PCI: Cannot allocate resource region %d" |
| 488 | " of device %s\n", idx, pci_name(dev)); |
| 489 | if (pr) |
| 490 | DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n", |
| 491 | pr, pr->start, pr->end, pr->flags); |
| 492 | /* We'll assign a new address later */ |
| 493 | r->flags |= IORESOURCE_UNSET; |
| 494 | r->end -= r->start; |
| 495 | r->start = 0; |
| 496 | } |
| 497 | } |
| 498 | |
| 499 | static void __init |
| 500 | pcibios_allocate_resources(int pass) |
| 501 | { |
| 502 | struct pci_dev *dev = NULL; |
| 503 | int idx, disabled; |
| 504 | u16 command; |
| 505 | struct resource *r; |
| 506 | |
| 507 | for_each_pci_dev(dev) { |
| 508 | pci_read_config_word(dev, PCI_COMMAND, &command); |
| 509 | for (idx = 0; idx < 6; idx++) { |
| 510 | r = &dev->resource[idx]; |
| 511 | if (r->parent) /* Already allocated */ |
| 512 | continue; |
| 513 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) |
| 514 | continue; /* Not assigned at all */ |
| 515 | if (r->flags & IORESOURCE_IO) |
| 516 | disabled = !(command & PCI_COMMAND_IO); |
| 517 | else |
| 518 | disabled = !(command & PCI_COMMAND_MEMORY); |
| 519 | if (pass == disabled) |
| 520 | alloc_resource(dev, idx); |
| 521 | } |
| 522 | if (pass) |
| 523 | continue; |
| 524 | r = &dev->resource[PCI_ROM_RESOURCE]; |
| 525 | if (r->flags & IORESOURCE_ROM_ENABLE) { |
| 526 | /* Turn the ROM off, leave the resource region, but keep it unregistered. */ |
| 527 | u32 reg; |
| 528 | DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); |
| 529 | r->flags &= ~IORESOURCE_ROM_ENABLE; |
| 530 | pci_read_config_dword(dev, dev->rom_base_reg, ®); |
| 531 | pci_write_config_dword(dev, dev->rom_base_reg, |
| 532 | reg & ~PCI_ROM_ADDRESS_ENABLE); |
| 533 | } |
| 534 | } |
| 535 | } |
| 536 | |
| 537 | static void __init |
| 538 | pcibios_assign_resources(void) |
| 539 | { |
| 540 | struct pci_dev *dev = NULL; |
| 541 | int idx; |
| 542 | struct resource *r; |
| 543 | |
| 544 | for_each_pci_dev(dev) { |
| 545 | int class = dev->class >> 8; |
| 546 | |
| 547 | /* Don't touch classless devices and host bridges */ |
| 548 | if (!class || class == PCI_CLASS_BRIDGE_HOST) |
| 549 | continue; |
| 550 | |
| 551 | for (idx = 0; idx < 6; idx++) { |
| 552 | r = &dev->resource[idx]; |
| 553 | |
| 554 | /* |
| 555 | * We shall assign a new address to this resource, |
| 556 | * either because the BIOS (sic) forgot to do so |
| 557 | * or because we have decided the old address was |
| 558 | * unusable for some reason. |
| 559 | */ |
| 560 | if ((r->flags & IORESOURCE_UNSET) && r->end && |
| 561 | (!ppc_md.pcibios_enable_device_hook || |
| 562 | !ppc_md.pcibios_enable_device_hook(dev, 1))) { |
| 563 | r->flags &= ~IORESOURCE_UNSET; |
| 564 | pci_assign_resource(dev, idx); |
| 565 | } |
| 566 | } |
| 567 | |
| 568 | #if 0 /* don't assign ROMs */ |
| 569 | r = &dev->resource[PCI_ROM_RESOURCE]; |
| 570 | r->end -= r->start; |
| 571 | r->start = 0; |
| 572 | if (r->end) |
| 573 | pci_assign_resource(dev, PCI_ROM_RESOURCE); |
| 574 | #endif |
| 575 | } |
| 576 | } |
| 577 | |
| 578 | |
| 579 | int |
| 580 | pcibios_enable_resources(struct pci_dev *dev, int mask) |
| 581 | { |
| 582 | u16 cmd, old_cmd; |
| 583 | int idx; |
| 584 | struct resource *r; |
| 585 | |
| 586 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 587 | old_cmd = cmd; |
| 588 | for (idx=0; idx<6; idx++) { |
| 589 | /* Only set up the requested stuff */ |
| 590 | if (!(mask & (1<<idx))) |
| 591 | continue; |
| 592 | |
| 593 | r = &dev->resource[idx]; |
| 594 | if (r->flags & IORESOURCE_UNSET) { |
| 595 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); |
| 596 | return -EINVAL; |
| 597 | } |
| 598 | if (r->flags & IORESOURCE_IO) |
| 599 | cmd |= PCI_COMMAND_IO; |
| 600 | if (r->flags & IORESOURCE_MEM) |
| 601 | cmd |= PCI_COMMAND_MEMORY; |
| 602 | } |
| 603 | if (dev->resource[PCI_ROM_RESOURCE].start) |
| 604 | cmd |= PCI_COMMAND_MEMORY; |
| 605 | if (cmd != old_cmd) { |
| 606 | printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); |
| 607 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 608 | } |
| 609 | return 0; |
| 610 | } |
| 611 | |
| 612 | static int next_controller_index; |
| 613 | |
| 614 | struct pci_controller * __init |
| 615 | pcibios_alloc_controller(void) |
| 616 | { |
| 617 | struct pci_controller *hose; |
| 618 | |
| 619 | hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose)); |
| 620 | memset(hose, 0, sizeof(struct pci_controller)); |
| 621 | |
| 622 | *hose_tail = hose; |
| 623 | hose_tail = &hose->next; |
| 624 | |
| 625 | hose->index = next_controller_index++; |
| 626 | |
| 627 | return hose; |
| 628 | } |
| 629 | |
| 630 | #ifdef CONFIG_PPC_OF |
| 631 | /* |
| 632 | * Functions below are used on OpenFirmware machines. |
| 633 | */ |
| 634 | static void |
| 635 | make_one_node_map(struct device_node* node, u8 pci_bus) |
| 636 | { |
| 637 | const int *bus_range; |
| 638 | int len; |
| 639 | |
| 640 | if (pci_bus >= pci_bus_count) |
| 641 | return; |
| 642 | bus_range = get_property(node, "bus-range", &len); |
| 643 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
| 644 | printk(KERN_WARNING "Can't get bus-range for %s, " |
| 645 | "assuming it starts at 0\n", node->full_name); |
| 646 | pci_to_OF_bus_map[pci_bus] = 0; |
| 647 | } else |
| 648 | pci_to_OF_bus_map[pci_bus] = bus_range[0]; |
| 649 | |
| 650 | for (node=node->child; node != 0;node = node->sibling) { |
| 651 | struct pci_dev* dev; |
| 652 | const unsigned int *class_code, *reg; |
| 653 | |
| 654 | class_code = get_property(node, "class-code", NULL); |
| 655 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
| 656 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) |
| 657 | continue; |
| 658 | reg = get_property(node, "reg", NULL); |
| 659 | if (!reg) |
| 660 | continue; |
| 661 | dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff)); |
| 662 | if (!dev || !dev->subordinate) |
| 663 | continue; |
| 664 | make_one_node_map(node, dev->subordinate->number); |
| 665 | } |
| 666 | } |
| 667 | |
| 668 | void |
| 669 | pcibios_make_OF_bus_map(void) |
| 670 | { |
| 671 | int i; |
| 672 | struct pci_controller* hose; |
| 673 | struct property *map_prop; |
| 674 | |
| 675 | pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL); |
| 676 | if (!pci_to_OF_bus_map) { |
| 677 | printk(KERN_ERR "Can't allocate OF bus map !\n"); |
| 678 | return; |
| 679 | } |
| 680 | |
| 681 | /* We fill the bus map with invalid values, that helps |
| 682 | * debugging. |
| 683 | */ |
| 684 | for (i=0; i<pci_bus_count; i++) |
| 685 | pci_to_OF_bus_map[i] = 0xff; |
| 686 | |
| 687 | /* For each hose, we begin searching bridges */ |
| 688 | for(hose=hose_head; hose; hose=hose->next) { |
| 689 | struct device_node* node; |
| 690 | node = (struct device_node *)hose->arch_data; |
| 691 | if (!node) |
| 692 | continue; |
| 693 | make_one_node_map(node, hose->first_busno); |
| 694 | } |
| 695 | map_prop = of_find_property(find_path_device("/"), |
| 696 | "pci-OF-bus-map", NULL); |
| 697 | if (map_prop) { |
| 698 | BUG_ON(pci_bus_count > map_prop->length); |
| 699 | memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count); |
| 700 | } |
| 701 | #ifdef DEBUG |
| 702 | printk("PCI->OF bus map:\n"); |
| 703 | for (i=0; i<pci_bus_count; i++) { |
| 704 | if (pci_to_OF_bus_map[i] == 0xff) |
| 705 | continue; |
| 706 | printk("%d -> %d\n", i, pci_to_OF_bus_map[i]); |
| 707 | } |
| 708 | #endif |
| 709 | } |
| 710 | |
| 711 | typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data); |
| 712 | |
| 713 | static struct device_node* |
| 714 | scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data) |
| 715 | { |
| 716 | struct device_node* sub_node; |
| 717 | |
| 718 | for (; node != 0;node = node->sibling) { |
| 719 | const unsigned int *class_code; |
| 720 | |
| 721 | if (filter(node, data)) |
| 722 | return node; |
| 723 | |
| 724 | /* For PCI<->PCI bridges or CardBus bridges, we go down |
| 725 | * Note: some OFs create a parent node "multifunc-device" as |
| 726 | * a fake root for all functions of a multi-function device, |
| 727 | * we go down them as well. |
| 728 | */ |
| 729 | class_code = get_property(node, "class-code", NULL); |
| 730 | if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
| 731 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) && |
| 732 | strcmp(node->name, "multifunc-device")) |
| 733 | continue; |
| 734 | sub_node = scan_OF_pci_childs(node->child, filter, data); |
| 735 | if (sub_node) |
| 736 | return sub_node; |
| 737 | } |
| 738 | return NULL; |
| 739 | } |
| 740 | |
| 741 | static int |
| 742 | scan_OF_pci_childs_iterator(struct device_node* node, void* data) |
| 743 | { |
| 744 | const unsigned int *reg; |
| 745 | u8* fdata = (u8*)data; |
| 746 | |
| 747 | reg = get_property(node, "reg", NULL); |
| 748 | if (reg && ((reg[0] >> 8) & 0xff) == fdata[1] |
| 749 | && ((reg[0] >> 16) & 0xff) == fdata[0]) |
| 750 | return 1; |
| 751 | return 0; |
| 752 | } |
| 753 | |
| 754 | static struct device_node* |
| 755 | scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn) |
| 756 | { |
| 757 | u8 filter_data[2] = {bus, dev_fn}; |
| 758 | |
| 759 | return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data); |
| 760 | } |
| 761 | |
| 762 | /* |
| 763 | * Scans the OF tree for a device node matching a PCI device |
| 764 | */ |
| 765 | struct device_node * |
| 766 | pci_busdev_to_OF_node(struct pci_bus *bus, int devfn) |
| 767 | { |
| 768 | struct pci_controller *hose; |
| 769 | struct device_node *node; |
| 770 | int busnr; |
| 771 | |
| 772 | if (!have_of) |
| 773 | return NULL; |
| 774 | |
| 775 | /* Lookup the hose */ |
| 776 | busnr = bus->number; |
| 777 | hose = pci_bus_to_hose(busnr); |
| 778 | if (!hose) |
| 779 | return NULL; |
| 780 | |
| 781 | /* Check it has an OF node associated */ |
| 782 | node = (struct device_node *) hose->arch_data; |
| 783 | if (!node) |
| 784 | return NULL; |
| 785 | |
| 786 | /* Fixup bus number according to what OF think it is. */ |
| 787 | #ifdef CONFIG_PPC_PMAC |
| 788 | /* The G5 need a special case here. Basically, we don't remap all |
| 789 | * busses on it so we don't create the pci-OF-map. However, we do |
| 790 | * remap the AGP bus and so have to deal with it. A future better |
| 791 | * fix has to be done by making the remapping per-host and always |
| 792 | * filling the pci_to_OF map. --BenH |
| 793 | */ |
| 794 | if (machine_is(powermac) && busnr >= 0xf0) |
| 795 | busnr -= 0xf0; |
| 796 | else |
| 797 | #endif |
| 798 | if (pci_to_OF_bus_map) |
| 799 | busnr = pci_to_OF_bus_map[busnr]; |
| 800 | if (busnr == 0xff) |
| 801 | return NULL; |
| 802 | |
| 803 | /* Now, lookup childs of the hose */ |
| 804 | return scan_OF_childs_for_device(node->child, busnr, devfn); |
| 805 | } |
| 806 | EXPORT_SYMBOL(pci_busdev_to_OF_node); |
| 807 | |
| 808 | struct device_node* |
| 809 | pci_device_to_OF_node(struct pci_dev *dev) |
| 810 | { |
| 811 | return pci_busdev_to_OF_node(dev->bus, dev->devfn); |
| 812 | } |
| 813 | EXPORT_SYMBOL(pci_device_to_OF_node); |
| 814 | |
| 815 | /* This routine is meant to be used early during boot, when the |
| 816 | * PCI bus numbers have not yet been assigned, and you need to |
| 817 | * issue PCI config cycles to an OF device. |
| 818 | * It could also be used to "fix" RTAS config cycles if you want |
| 819 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI |
| 820 | * config cycles. |
| 821 | */ |
| 822 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) |
| 823 | { |
| 824 | if (!have_of) |
| 825 | return NULL; |
| 826 | while(node) { |
| 827 | struct pci_controller* hose; |
| 828 | for (hose=hose_head;hose;hose=hose->next) |
| 829 | if (hose->arch_data == node) |
| 830 | return hose; |
| 831 | node=node->parent; |
| 832 | } |
| 833 | return NULL; |
| 834 | } |
| 835 | |
| 836 | static int |
| 837 | find_OF_pci_device_filter(struct device_node* node, void* data) |
| 838 | { |
| 839 | return ((void *)node == data); |
| 840 | } |
| 841 | |
| 842 | /* |
| 843 | * Returns the PCI device matching a given OF node |
| 844 | */ |
| 845 | int |
| 846 | pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn) |
| 847 | { |
| 848 | const unsigned int *reg; |
| 849 | struct pci_controller* hose; |
| 850 | struct pci_dev* dev = NULL; |
| 851 | |
| 852 | if (!have_of) |
| 853 | return -ENODEV; |
| 854 | /* Make sure it's really a PCI device */ |
| 855 | hose = pci_find_hose_for_OF_device(node); |
| 856 | if (!hose || !hose->arch_data) |
| 857 | return -ENODEV; |
| 858 | if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child, |
| 859 | find_OF_pci_device_filter, (void *)node)) |
| 860 | return -ENODEV; |
| 861 | reg = get_property(node, "reg", NULL); |
| 862 | if (!reg) |
| 863 | return -ENODEV; |
| 864 | *bus = (reg[0] >> 16) & 0xff; |
| 865 | *devfn = ((reg[0] >> 8) & 0xff); |
| 866 | |
| 867 | /* Ok, here we need some tweak. If we have already renumbered |
| 868 | * all busses, we can't rely on the OF bus number any more. |
| 869 | * the pci_to_OF_bus_map is not enough as several PCI busses |
| 870 | * may match the same OF bus number. |
| 871 | */ |
| 872 | if (!pci_to_OF_bus_map) |
| 873 | return 0; |
| 874 | |
| 875 | for_each_pci_dev(dev) |
| 876 | if (pci_to_OF_bus_map[dev->bus->number] == *bus && |
| 877 | dev->devfn == *devfn) { |
| 878 | *bus = dev->bus->number; |
| 879 | pci_dev_put(dev); |
| 880 | return 0; |
| 881 | } |
| 882 | |
| 883 | return -ENODEV; |
| 884 | } |
| 885 | EXPORT_SYMBOL(pci_device_from_OF_node); |
| 886 | |
| 887 | void __init |
| 888 | pci_process_bridge_OF_ranges(struct pci_controller *hose, |
| 889 | struct device_node *dev, int primary) |
| 890 | { |
| 891 | static unsigned int static_lc_ranges[256] __initdata; |
| 892 | const unsigned int *dt_ranges; |
| 893 | unsigned int *lc_ranges, *ranges, *prev, size; |
| 894 | int rlen = 0, orig_rlen; |
| 895 | int memno = 0; |
| 896 | struct resource *res; |
| 897 | int np, na = prom_n_addr_cells(dev); |
| 898 | np = na + 5; |
| 899 | |
| 900 | /* First we try to merge ranges to fix a problem with some pmacs |
| 901 | * that can have more than 3 ranges, fortunately using contiguous |
| 902 | * addresses -- BenH |
| 903 | */ |
| 904 | dt_ranges = get_property(dev, "ranges", &rlen); |
| 905 | if (!dt_ranges) |
| 906 | return; |
| 907 | /* Sanity check, though hopefully that never happens */ |
| 908 | if (rlen > sizeof(static_lc_ranges)) { |
| 909 | printk(KERN_WARNING "OF ranges property too large !\n"); |
| 910 | rlen = sizeof(static_lc_ranges); |
| 911 | } |
| 912 | lc_ranges = static_lc_ranges; |
| 913 | memcpy(lc_ranges, dt_ranges, rlen); |
| 914 | orig_rlen = rlen; |
| 915 | |
| 916 | /* Let's work on a copy of the "ranges" property instead of damaging |
| 917 | * the device-tree image in memory |
| 918 | */ |
| 919 | ranges = lc_ranges; |
| 920 | prev = NULL; |
| 921 | while ((rlen -= np * sizeof(unsigned int)) >= 0) { |
| 922 | if (prev) { |
| 923 | if (prev[0] == ranges[0] && prev[1] == ranges[1] && |
| 924 | (prev[2] + prev[na+4]) == ranges[2] && |
| 925 | (prev[na+2] + prev[na+4]) == ranges[na+2]) { |
| 926 | prev[na+4] += ranges[na+4]; |
| 927 | ranges[0] = 0; |
| 928 | ranges += np; |
| 929 | continue; |
| 930 | } |
| 931 | } |
| 932 | prev = ranges; |
| 933 | ranges += np; |
| 934 | } |
| 935 | |
| 936 | /* |
| 937 | * The ranges property is laid out as an array of elements, |
| 938 | * each of which comprises: |
| 939 | * cells 0 - 2: a PCI address |
| 940 | * cells 3 or 3+4: a CPU physical address |
| 941 | * (size depending on dev->n_addr_cells) |
| 942 | * cells 4+5 or 5+6: the size of the range |
| 943 | */ |
| 944 | ranges = lc_ranges; |
| 945 | rlen = orig_rlen; |
| 946 | while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) { |
| 947 | res = NULL; |
| 948 | size = ranges[na+4]; |
| 949 | switch ((ranges[0] >> 24) & 0x3) { |
| 950 | case 1: /* I/O space */ |
| 951 | if (ranges[2] != 0) |
| 952 | break; |
| 953 | hose->io_base_phys = ranges[na+2]; |
| 954 | /* limit I/O space to 16MB */ |
| 955 | if (size > 0x01000000) |
| 956 | size = 0x01000000; |
| 957 | hose->io_base_virt = ioremap(ranges[na+2], size); |
| 958 | if (primary) |
| 959 | isa_io_base = (unsigned long) hose->io_base_virt; |
| 960 | res = &hose->io_resource; |
| 961 | res->flags = IORESOURCE_IO; |
| 962 | res->start = ranges[2]; |
| 963 | DBG("PCI: IO 0x%llx -> 0x%llx\n", |
| 964 | res->start, res->start + size - 1); |
| 965 | break; |
| 966 | case 2: /* memory space */ |
| 967 | memno = 0; |
| 968 | if (ranges[1] == 0 && ranges[2] == 0 |
| 969 | && ranges[na+4] <= (16 << 20)) { |
| 970 | /* 1st 16MB, i.e. ISA memory area */ |
| 971 | if (primary) |
| 972 | isa_mem_base = ranges[na+2]; |
| 973 | memno = 1; |
| 974 | } |
| 975 | while (memno < 3 && hose->mem_resources[memno].flags) |
| 976 | ++memno; |
| 977 | if (memno == 0) |
| 978 | hose->pci_mem_offset = ranges[na+2] - ranges[2]; |
| 979 | if (memno < 3) { |
| 980 | res = &hose->mem_resources[memno]; |
| 981 | res->flags = IORESOURCE_MEM; |
| 982 | if(ranges[0] & 0x40000000) |
| 983 | res->flags |= IORESOURCE_PREFETCH; |
| 984 | res->start = ranges[na+2]; |
| 985 | DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno, |
| 986 | res->start, res->start + size - 1); |
| 987 | } |
| 988 | break; |
| 989 | } |
| 990 | if (res != NULL) { |
| 991 | res->name = dev->full_name; |
| 992 | res->end = res->start + size - 1; |
| 993 | res->parent = NULL; |
| 994 | res->sibling = NULL; |
| 995 | res->child = NULL; |
| 996 | } |
| 997 | ranges += np; |
| 998 | } |
| 999 | } |
| 1000 | |
| 1001 | /* We create the "pci-OF-bus-map" property now so it appears in the |
| 1002 | * /proc device tree |
| 1003 | */ |
| 1004 | void __init |
| 1005 | pci_create_OF_bus_map(void) |
| 1006 | { |
| 1007 | struct property* of_prop; |
| 1008 | |
| 1009 | of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256); |
| 1010 | if (of_prop && find_path_device("/")) { |
| 1011 | memset(of_prop, -1, sizeof(struct property) + 256); |
| 1012 | of_prop->name = "pci-OF-bus-map"; |
| 1013 | of_prop->length = 256; |
| 1014 | of_prop->value = (unsigned char *)&of_prop[1]; |
| 1015 | prom_add_property(find_path_device("/"), of_prop); |
| 1016 | } |
| 1017 | } |
| 1018 | |
| 1019 | static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf) |
| 1020 | { |
| 1021 | struct pci_dev *pdev; |
| 1022 | struct device_node *np; |
| 1023 | |
| 1024 | pdev = to_pci_dev (dev); |
| 1025 | np = pci_device_to_OF_node(pdev); |
| 1026 | if (np == NULL || np->full_name == NULL) |
| 1027 | return 0; |
| 1028 | return sprintf(buf, "%s", np->full_name); |
| 1029 | } |
| 1030 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); |
| 1031 | |
| 1032 | #else /* CONFIG_PPC_OF */ |
| 1033 | void pcibios_make_OF_bus_map(void) |
| 1034 | { |
| 1035 | } |
| 1036 | #endif /* CONFIG_PPC_OF */ |
| 1037 | |
| 1038 | /* Add sysfs properties */ |
| 1039 | void pcibios_add_platform_entries(struct pci_dev *pdev) |
| 1040 | { |
| 1041 | #ifdef CONFIG_PPC_OF |
| 1042 | device_create_file(&pdev->dev, &dev_attr_devspec); |
| 1043 | #endif /* CONFIG_PPC_OF */ |
| 1044 | } |
| 1045 | |
| 1046 | |
| 1047 | #ifdef CONFIG_PPC_PMAC |
| 1048 | /* |
| 1049 | * This set of routines checks for PCI<->PCI bridges that have closed |
| 1050 | * IO resources and have child devices. It tries to re-open an IO |
| 1051 | * window on them. |
| 1052 | * |
| 1053 | * This is a _temporary_ fix to workaround a problem with Apple's OF |
| 1054 | * closing IO windows on P2P bridges when the OF drivers of cards |
| 1055 | * below this bridge don't claim any IO range (typically ATI or |
| 1056 | * Adaptec). |
| 1057 | * |
| 1058 | * A more complete fix would be to use drivers/pci/setup-bus.c, which |
| 1059 | * involves a working pcibios_fixup_pbus_ranges(), some more care about |
| 1060 | * ordering when creating the host bus resources, and maybe a few more |
| 1061 | * minor tweaks |
| 1062 | */ |
| 1063 | |
| 1064 | /* Initialize bridges with base/limit values we have collected */ |
| 1065 | static void __init |
| 1066 | do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga) |
| 1067 | { |
| 1068 | struct pci_dev *bridge = bus->self; |
| 1069 | struct pci_controller* hose = (struct pci_controller *)bridge->sysdata; |
| 1070 | u32 l; |
| 1071 | u16 w; |
| 1072 | struct resource res; |
| 1073 | |
| 1074 | if (bus->resource[0] == NULL) |
| 1075 | return; |
| 1076 | res = *(bus->resource[0]); |
| 1077 | |
| 1078 | DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge)); |
| 1079 | res.start -= ((unsigned long) hose->io_base_virt - isa_io_base); |
| 1080 | res.end -= ((unsigned long) hose->io_base_virt - isa_io_base); |
| 1081 | DBG(" IO window: %016llx-%016llx\n", res.start, res.end); |
| 1082 | |
| 1083 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
| 1084 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
| 1085 | l &= 0xffff000f; |
| 1086 | l |= (res.start >> 8) & 0x00f0; |
| 1087 | l |= res.end & 0xf000; |
| 1088 | pci_write_config_dword(bridge, PCI_IO_BASE, l); |
| 1089 | |
| 1090 | if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { |
| 1091 | l = (res.start >> 16) | (res.end & 0xffff0000); |
| 1092 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l); |
| 1093 | } |
| 1094 | |
| 1095 | pci_read_config_word(bridge, PCI_COMMAND, &w); |
| 1096 | w |= PCI_COMMAND_IO; |
| 1097 | pci_write_config_word(bridge, PCI_COMMAND, w); |
| 1098 | |
| 1099 | #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */ |
| 1100 | if (enable_vga) { |
| 1101 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w); |
| 1102 | w |= PCI_BRIDGE_CTL_VGA; |
| 1103 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w); |
| 1104 | } |
| 1105 | #endif |
| 1106 | } |
| 1107 | |
| 1108 | /* This function is pretty basic and actually quite broken for the |
| 1109 | * general case, it's enough for us right now though. It's supposed |
| 1110 | * to tell us if we need to open an IO range at all or not and what |
| 1111 | * size. |
| 1112 | */ |
| 1113 | static int __init |
| 1114 | check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga) |
| 1115 | { |
| 1116 | struct pci_dev *dev; |
| 1117 | int i; |
| 1118 | int rc = 0; |
| 1119 | |
| 1120 | #define push_end(res, mask) do { \ |
| 1121 | BUG_ON((mask+1) & mask); \ |
| 1122 | res->end = (res->end + mask) | mask; \ |
| 1123 | } while (0) |
| 1124 | |
| 1125 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 1126 | u16 class = dev->class >> 8; |
| 1127 | |
| 1128 | if (class == PCI_CLASS_DISPLAY_VGA || |
| 1129 | class == PCI_CLASS_NOT_DEFINED_VGA) |
| 1130 | *found_vga = 1; |
| 1131 | if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate) |
| 1132 | rc |= check_for_io_childs(dev->subordinate, res, found_vga); |
| 1133 | if (class == PCI_CLASS_BRIDGE_CARDBUS) |
| 1134 | push_end(res, 0xfff); |
| 1135 | |
| 1136 | for (i=0; i<PCI_NUM_RESOURCES; i++) { |
| 1137 | struct resource *r; |
| 1138 | unsigned long r_size; |
| 1139 | |
| 1140 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI |
| 1141 | && i >= PCI_BRIDGE_RESOURCES) |
| 1142 | continue; |
| 1143 | r = &dev->resource[i]; |
| 1144 | r_size = r->end - r->start; |
| 1145 | if (r_size < 0xfff) |
| 1146 | r_size = 0xfff; |
| 1147 | if (r->flags & IORESOURCE_IO && (r_size) != 0) { |
| 1148 | rc = 1; |
| 1149 | push_end(res, r_size); |
| 1150 | } |
| 1151 | } |
| 1152 | } |
| 1153 | |
| 1154 | return rc; |
| 1155 | } |
| 1156 | |
| 1157 | /* Here we scan all P2P bridges of a given level that have a closed |
| 1158 | * IO window. Note that the test for the presence of a VGA card should |
| 1159 | * be improved to take into account already configured P2P bridges, |
| 1160 | * currently, we don't see them and might end up configuring 2 bridges |
| 1161 | * with VGA pass through enabled |
| 1162 | */ |
| 1163 | static void __init |
| 1164 | do_fixup_p2p_level(struct pci_bus *bus) |
| 1165 | { |
| 1166 | struct pci_bus *b; |
| 1167 | int i, parent_io; |
| 1168 | int has_vga = 0; |
| 1169 | |
| 1170 | for (parent_io=0; parent_io<4; parent_io++) |
| 1171 | if (bus->resource[parent_io] |
| 1172 | && bus->resource[parent_io]->flags & IORESOURCE_IO) |
| 1173 | break; |
| 1174 | if (parent_io >= 4) |
| 1175 | return; |
| 1176 | |
| 1177 | list_for_each_entry(b, &bus->children, node) { |
| 1178 | struct pci_dev *d = b->self; |
| 1179 | struct pci_controller* hose = (struct pci_controller *)d->sysdata; |
| 1180 | struct resource *res = b->resource[0]; |
| 1181 | struct resource tmp_res; |
| 1182 | unsigned long max; |
| 1183 | int found_vga = 0; |
| 1184 | |
| 1185 | memset(&tmp_res, 0, sizeof(tmp_res)); |
| 1186 | tmp_res.start = bus->resource[parent_io]->start; |
| 1187 | |
| 1188 | /* We don't let low addresses go through that closed P2P bridge, well, |
| 1189 | * that may not be necessary but I feel safer that way |
| 1190 | */ |
| 1191 | if (tmp_res.start == 0) |
| 1192 | tmp_res.start = 0x1000; |
| 1193 | |
| 1194 | if (!list_empty(&b->devices) && res && res->flags == 0 && |
| 1195 | res != bus->resource[parent_io] && |
| 1196 | (d->class >> 8) == PCI_CLASS_BRIDGE_PCI && |
| 1197 | check_for_io_childs(b, &tmp_res, &found_vga)) { |
| 1198 | u8 io_base_lo; |
| 1199 | |
| 1200 | printk(KERN_INFO "Fixing up IO bus %s\n", b->name); |
| 1201 | |
| 1202 | if (found_vga) { |
| 1203 | if (has_vga) { |
| 1204 | printk(KERN_WARNING "Skipping VGA, already active" |
| 1205 | " on bus segment\n"); |
| 1206 | found_vga = 0; |
| 1207 | } else |
| 1208 | has_vga = 1; |
| 1209 | } |
| 1210 | pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo); |
| 1211 | |
| 1212 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) |
| 1213 | max = ((unsigned long) hose->io_base_virt |
| 1214 | - isa_io_base) + 0xffffffff; |
| 1215 | else |
| 1216 | max = ((unsigned long) hose->io_base_virt |
| 1217 | - isa_io_base) + 0xffff; |
| 1218 | |
| 1219 | *res = tmp_res; |
| 1220 | res->flags = IORESOURCE_IO; |
| 1221 | res->name = b->name; |
| 1222 | |
| 1223 | /* Find a resource in the parent where we can allocate */ |
| 1224 | for (i = 0 ; i < 4; i++) { |
| 1225 | struct resource *r = bus->resource[i]; |
| 1226 | if (!r) |
| 1227 | continue; |
| 1228 | if ((r->flags & IORESOURCE_IO) == 0) |
| 1229 | continue; |
| 1230 | DBG("Trying to allocate from %016llx, size %016llx from parent" |
| 1231 | " res %d: %016llx -> %016llx\n", |
| 1232 | res->start, res->end, i, r->start, r->end); |
| 1233 | |
| 1234 | if (allocate_resource(r, res, res->end + 1, res->start, max, |
| 1235 | res->end + 1, NULL, NULL) < 0) { |
| 1236 | DBG("Failed !\n"); |
| 1237 | continue; |
| 1238 | } |
| 1239 | do_update_p2p_io_resource(b, found_vga); |
| 1240 | break; |
| 1241 | } |
| 1242 | } |
| 1243 | do_fixup_p2p_level(b); |
| 1244 | } |
| 1245 | } |
| 1246 | |
| 1247 | static void |
| 1248 | pcibios_fixup_p2p_bridges(void) |
| 1249 | { |
| 1250 | struct pci_bus *b; |
| 1251 | |
| 1252 | list_for_each_entry(b, &pci_root_buses, node) |
| 1253 | do_fixup_p2p_level(b); |
| 1254 | } |
| 1255 | |
| 1256 | #endif /* CONFIG_PPC_PMAC */ |
| 1257 | |
| 1258 | static int __init |
| 1259 | pcibios_init(void) |
| 1260 | { |
| 1261 | struct pci_controller *hose; |
| 1262 | struct pci_bus *bus; |
| 1263 | int next_busno; |
| 1264 | |
| 1265 | printk(KERN_INFO "PCI: Probing PCI hardware\n"); |
| 1266 | |
| 1267 | /* Scan all of the recorded PCI controllers. */ |
| 1268 | for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { |
| 1269 | if (pci_assign_all_buses) |
| 1270 | hose->first_busno = next_busno; |
| 1271 | hose->last_busno = 0xff; |
| 1272 | bus = pci_scan_bus_parented(hose->parent, hose->first_busno, |
| 1273 | hose->ops, hose); |
| 1274 | if (bus) |
| 1275 | pci_bus_add_devices(bus); |
| 1276 | hose->last_busno = bus->subordinate; |
| 1277 | if (pci_assign_all_buses || next_busno <= hose->last_busno) |
| 1278 | next_busno = hose->last_busno + pcibios_assign_bus_offset; |
| 1279 | } |
| 1280 | pci_bus_count = next_busno; |
| 1281 | |
| 1282 | /* OpenFirmware based machines need a map of OF bus |
| 1283 | * numbers vs. kernel bus numbers since we may have to |
| 1284 | * remap them. |
| 1285 | */ |
| 1286 | if (pci_assign_all_buses && have_of) |
| 1287 | pcibios_make_OF_bus_map(); |
| 1288 | |
| 1289 | /* Call machine dependent fixup */ |
| 1290 | if (ppc_md.pcibios_fixup) |
| 1291 | ppc_md.pcibios_fixup(); |
| 1292 | |
| 1293 | /* Allocate and assign resources */ |
| 1294 | pcibios_allocate_bus_resources(&pci_root_buses); |
| 1295 | pcibios_allocate_resources(0); |
| 1296 | pcibios_allocate_resources(1); |
| 1297 | #ifdef CONFIG_PPC_PMAC |
| 1298 | pcibios_fixup_p2p_bridges(); |
| 1299 | #endif /* CONFIG_PPC_PMAC */ |
| 1300 | pcibios_assign_resources(); |
| 1301 | |
| 1302 | /* Call machine dependent post-init code */ |
| 1303 | if (ppc_md.pcibios_after_init) |
| 1304 | ppc_md.pcibios_after_init(); |
| 1305 | |
| 1306 | return 0; |
| 1307 | } |
| 1308 | |
| 1309 | subsys_initcall(pcibios_init); |
| 1310 | |
| 1311 | unsigned long resource_fixup(struct pci_dev * dev, struct resource * res, |
| 1312 | unsigned long start, unsigned long size) |
| 1313 | { |
| 1314 | return start; |
| 1315 | } |
| 1316 | |
| 1317 | void __init pcibios_fixup_bus(struct pci_bus *bus) |
| 1318 | { |
| 1319 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; |
| 1320 | unsigned long io_offset; |
| 1321 | struct resource *res; |
| 1322 | struct pci_dev *dev; |
| 1323 | int i; |
| 1324 | |
| 1325 | io_offset = (unsigned long)hose->io_base_virt - isa_io_base; |
| 1326 | if (bus->parent == NULL) { |
| 1327 | /* This is a host bridge - fill in its resources */ |
| 1328 | hose->bus = bus; |
| 1329 | |
| 1330 | bus->resource[0] = res = &hose->io_resource; |
| 1331 | if (!res->flags) { |
| 1332 | if (io_offset) |
| 1333 | printk(KERN_ERR "I/O resource not set for host" |
| 1334 | " bridge %d\n", hose->index); |
| 1335 | res->start = 0; |
| 1336 | res->end = IO_SPACE_LIMIT; |
| 1337 | res->flags = IORESOURCE_IO; |
| 1338 | } |
| 1339 | res->start += io_offset; |
| 1340 | res->end += io_offset; |
| 1341 | |
| 1342 | for (i = 0; i < 3; ++i) { |
| 1343 | res = &hose->mem_resources[i]; |
| 1344 | if (!res->flags) { |
| 1345 | if (i > 0) |
| 1346 | continue; |
| 1347 | printk(KERN_ERR "Memory resource not set for " |
| 1348 | "host bridge %d\n", hose->index); |
| 1349 | res->start = hose->pci_mem_offset; |
| 1350 | res->end = ~0U; |
| 1351 | res->flags = IORESOURCE_MEM; |
| 1352 | } |
| 1353 | bus->resource[i+1] = res; |
| 1354 | } |
| 1355 | } else { |
| 1356 | /* This is a subordinate bridge */ |
| 1357 | pci_read_bridge_bases(bus); |
| 1358 | |
| 1359 | for (i = 0; i < 4; ++i) { |
| 1360 | if ((res = bus->resource[i]) == NULL) |
| 1361 | continue; |
| 1362 | if (!res->flags) |
| 1363 | continue; |
| 1364 | if (io_offset && (res->flags & IORESOURCE_IO)) { |
| 1365 | res->start += io_offset; |
| 1366 | res->end += io_offset; |
| 1367 | } else if (hose->pci_mem_offset |
| 1368 | && (res->flags & IORESOURCE_MEM)) { |
| 1369 | res->start += hose->pci_mem_offset; |
| 1370 | res->end += hose->pci_mem_offset; |
| 1371 | } |
| 1372 | } |
| 1373 | } |
| 1374 | |
| 1375 | /* Platform specific bus fixups */ |
| 1376 | if (ppc_md.pcibios_fixup_bus) |
| 1377 | ppc_md.pcibios_fixup_bus(bus); |
| 1378 | |
| 1379 | /* Read default IRQs and fixup if necessary */ |
| 1380 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 1381 | pci_read_irq_line(dev); |
| 1382 | if (ppc_md.pci_irq_fixup) |
| 1383 | ppc_md.pci_irq_fixup(dev); |
| 1384 | } |
| 1385 | } |
| 1386 | |
| 1387 | char __init *pcibios_setup(char *str) |
| 1388 | { |
| 1389 | return str; |
| 1390 | } |
| 1391 | |
| 1392 | /* the next one is stolen from the alpha port... */ |
| 1393 | void __init |
| 1394 | pcibios_update_irq(struct pci_dev *dev, int irq) |
| 1395 | { |
| 1396 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); |
| 1397 | /* XXX FIXME - update OF device tree node interrupt property */ |
| 1398 | } |
| 1399 | |
| 1400 | #ifdef CONFIG_PPC_MERGE |
| 1401 | /* XXX This is a copy of the ppc64 version. This is temporary until we start |
| 1402 | * merging the 2 PCI layers |
| 1403 | */ |
| 1404 | /* |
| 1405 | * Reads the interrupt pin to determine if interrupt is use by card. |
| 1406 | * If the interrupt is used, then gets the interrupt line from the |
| 1407 | * openfirmware and sets it in the pci_dev and pci_config line. |
| 1408 | */ |
| 1409 | int pci_read_irq_line(struct pci_dev *pci_dev) |
| 1410 | { |
| 1411 | struct of_irq oirq; |
| 1412 | unsigned int virq; |
| 1413 | |
| 1414 | DBG("Try to map irq for %s...\n", pci_name(pci_dev)); |
| 1415 | |
| 1416 | /* Try to get a mapping from the device-tree */ |
| 1417 | if (of_irq_map_pci(pci_dev, &oirq)) { |
| 1418 | u8 line, pin; |
| 1419 | |
| 1420 | /* If that fails, lets fallback to what is in the config |
| 1421 | * space and map that through the default controller. We |
| 1422 | * also set the type to level low since that's what PCI |
| 1423 | * interrupts are. If your platform does differently, then |
| 1424 | * either provide a proper interrupt tree or don't use this |
| 1425 | * function. |
| 1426 | */ |
| 1427 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) |
| 1428 | return -1; |
| 1429 | if (pin == 0) |
| 1430 | return -1; |
| 1431 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || |
| 1432 | line == 0xff) { |
| 1433 | return -1; |
| 1434 | } |
| 1435 | DBG(" -> no map ! Using irq line %d from PCI config\n", line); |
| 1436 | |
| 1437 | virq = irq_create_mapping(NULL, line); |
| 1438 | if (virq != NO_IRQ) |
| 1439 | set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
| 1440 | } else { |
| 1441 | DBG(" -> got one, spec %d cells (0x%08x...) on %s\n", |
| 1442 | oirq.size, oirq.specifier[0], oirq.controller->full_name); |
| 1443 | |
| 1444 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, |
| 1445 | oirq.size); |
| 1446 | } |
| 1447 | if(virq == NO_IRQ) { |
| 1448 | DBG(" -> failed to map !\n"); |
| 1449 | return -1; |
| 1450 | } |
| 1451 | pci_dev->irq = virq; |
| 1452 | pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq); |
| 1453 | |
| 1454 | return 0; |
| 1455 | } |
| 1456 | EXPORT_SYMBOL(pci_read_irq_line); |
| 1457 | #endif /* CONFIG_PPC_MERGE */ |
| 1458 | |
| 1459 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
| 1460 | { |
| 1461 | u16 cmd, old_cmd; |
| 1462 | int idx; |
| 1463 | struct resource *r; |
| 1464 | |
| 1465 | if (ppc_md.pcibios_enable_device_hook) |
| 1466 | if (ppc_md.pcibios_enable_device_hook(dev, 0)) |
| 1467 | return -EINVAL; |
| 1468 | |
| 1469 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 1470 | old_cmd = cmd; |
| 1471 | for (idx=0; idx<6; idx++) { |
| 1472 | r = &dev->resource[idx]; |
| 1473 | if (r->flags & IORESOURCE_UNSET) { |
| 1474 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); |
| 1475 | return -EINVAL; |
| 1476 | } |
| 1477 | if (r->flags & IORESOURCE_IO) |
| 1478 | cmd |= PCI_COMMAND_IO; |
| 1479 | if (r->flags & IORESOURCE_MEM) |
| 1480 | cmd |= PCI_COMMAND_MEMORY; |
| 1481 | } |
| 1482 | if (cmd != old_cmd) { |
| 1483 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
| 1484 | pci_name(dev), old_cmd, cmd); |
| 1485 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 1486 | } |
| 1487 | return 0; |
| 1488 | } |
| 1489 | |
| 1490 | struct pci_controller* |
| 1491 | pci_bus_to_hose(int bus) |
| 1492 | { |
| 1493 | struct pci_controller* hose = hose_head; |
| 1494 | |
| 1495 | for (; hose; hose = hose->next) |
| 1496 | if (bus >= hose->first_busno && bus <= hose->last_busno) |
| 1497 | return hose; |
| 1498 | return NULL; |
| 1499 | } |
| 1500 | |
| 1501 | void __iomem * |
| 1502 | pci_bus_io_base(unsigned int bus) |
| 1503 | { |
| 1504 | struct pci_controller *hose; |
| 1505 | |
| 1506 | hose = pci_bus_to_hose(bus); |
| 1507 | if (!hose) |
| 1508 | return NULL; |
| 1509 | return hose->io_base_virt; |
| 1510 | } |
| 1511 | |
| 1512 | unsigned long |
| 1513 | pci_bus_io_base_phys(unsigned int bus) |
| 1514 | { |
| 1515 | struct pci_controller *hose; |
| 1516 | |
| 1517 | hose = pci_bus_to_hose(bus); |
| 1518 | if (!hose) |
| 1519 | return 0; |
| 1520 | return hose->io_base_phys; |
| 1521 | } |
| 1522 | |
| 1523 | unsigned long |
| 1524 | pci_bus_mem_base_phys(unsigned int bus) |
| 1525 | { |
| 1526 | struct pci_controller *hose; |
| 1527 | |
| 1528 | hose = pci_bus_to_hose(bus); |
| 1529 | if (!hose) |
| 1530 | return 0; |
| 1531 | return hose->pci_mem_offset; |
| 1532 | } |
| 1533 | |
| 1534 | unsigned long |
| 1535 | pci_resource_to_bus(struct pci_dev *pdev, struct resource *res) |
| 1536 | { |
| 1537 | /* Hack alert again ! See comments in chrp_pci.c |
| 1538 | */ |
| 1539 | struct pci_controller* hose = |
| 1540 | (struct pci_controller *)pdev->sysdata; |
| 1541 | if (hose && res->flags & IORESOURCE_MEM) |
| 1542 | return res->start - hose->pci_mem_offset; |
| 1543 | /* We may want to do something with IOs here... */ |
| 1544 | return res->start; |
| 1545 | } |
| 1546 | |
| 1547 | |
| 1548 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, |
| 1549 | unsigned long *offset, |
| 1550 | enum pci_mmap_state mmap_state) |
| 1551 | { |
| 1552 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); |
| 1553 | unsigned long io_offset = 0; |
| 1554 | int i, res_bit; |
| 1555 | |
| 1556 | if (hose == 0) |
| 1557 | return NULL; /* should never happen */ |
| 1558 | |
| 1559 | /* If memory, add on the PCI bridge address offset */ |
| 1560 | if (mmap_state == pci_mmap_mem) { |
| 1561 | *offset += hose->pci_mem_offset; |
| 1562 | res_bit = IORESOURCE_MEM; |
| 1563 | } else { |
| 1564 | io_offset = hose->io_base_virt - ___IO_BASE; |
| 1565 | *offset += io_offset; |
| 1566 | res_bit = IORESOURCE_IO; |
| 1567 | } |
| 1568 | |
| 1569 | /* |
| 1570 | * Check that the offset requested corresponds to one of the |
| 1571 | * resources of the device. |
| 1572 | */ |
| 1573 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
| 1574 | struct resource *rp = &dev->resource[i]; |
| 1575 | int flags = rp->flags; |
| 1576 | |
| 1577 | /* treat ROM as memory (should be already) */ |
| 1578 | if (i == PCI_ROM_RESOURCE) |
| 1579 | flags |= IORESOURCE_MEM; |
| 1580 | |
| 1581 | /* Active and same type? */ |
| 1582 | if ((flags & res_bit) == 0) |
| 1583 | continue; |
| 1584 | |
| 1585 | /* In the range of this resource? */ |
| 1586 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) |
| 1587 | continue; |
| 1588 | |
| 1589 | /* found it! construct the final physical address */ |
| 1590 | if (mmap_state == pci_mmap_io) |
| 1591 | *offset += hose->io_base_phys - io_offset; |
| 1592 | return rp; |
| 1593 | } |
| 1594 | |
| 1595 | return NULL; |
| 1596 | } |
| 1597 | |
| 1598 | /* |
| 1599 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci |
| 1600 | * device mapping. |
| 1601 | */ |
| 1602 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, |
| 1603 | pgprot_t protection, |
| 1604 | enum pci_mmap_state mmap_state, |
| 1605 | int write_combine) |
| 1606 | { |
| 1607 | unsigned long prot = pgprot_val(protection); |
| 1608 | |
| 1609 | /* Write combine is always 0 on non-memory space mappings. On |
| 1610 | * memory space, if the user didn't pass 1, we check for a |
| 1611 | * "prefetchable" resource. This is a bit hackish, but we use |
| 1612 | * this to workaround the inability of /sysfs to provide a write |
| 1613 | * combine bit |
| 1614 | */ |
| 1615 | if (mmap_state != pci_mmap_mem) |
| 1616 | write_combine = 0; |
| 1617 | else if (write_combine == 0) { |
| 1618 | if (rp->flags & IORESOURCE_PREFETCH) |
| 1619 | write_combine = 1; |
| 1620 | } |
| 1621 | |
| 1622 | /* XXX would be nice to have a way to ask for write-through */ |
| 1623 | prot |= _PAGE_NO_CACHE; |
| 1624 | if (write_combine) |
| 1625 | prot &= ~_PAGE_GUARDED; |
| 1626 | else |
| 1627 | prot |= _PAGE_GUARDED; |
| 1628 | |
| 1629 | printk("PCI map for %s:%llx, prot: %lx\n", pci_name(dev), |
| 1630 | (unsigned long long)rp->start, prot); |
| 1631 | |
| 1632 | return __pgprot(prot); |
| 1633 | } |
| 1634 | |
| 1635 | /* |
| 1636 | * This one is used by /dev/mem and fbdev who have no clue about the |
| 1637 | * PCI device, it tries to find the PCI device first and calls the |
| 1638 | * above routine |
| 1639 | */ |
| 1640 | pgprot_t pci_phys_mem_access_prot(struct file *file, |
| 1641 | unsigned long pfn, |
| 1642 | unsigned long size, |
| 1643 | pgprot_t protection) |
| 1644 | { |
| 1645 | struct pci_dev *pdev = NULL; |
| 1646 | struct resource *found = NULL; |
| 1647 | unsigned long prot = pgprot_val(protection); |
| 1648 | unsigned long offset = pfn << PAGE_SHIFT; |
| 1649 | int i; |
| 1650 | |
| 1651 | if (page_is_ram(pfn)) |
| 1652 | return prot; |
| 1653 | |
| 1654 | prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; |
| 1655 | |
| 1656 | for_each_pci_dev(pdev) { |
| 1657 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
| 1658 | struct resource *rp = &pdev->resource[i]; |
| 1659 | int flags = rp->flags; |
| 1660 | |
| 1661 | /* Active and same type? */ |
| 1662 | if ((flags & IORESOURCE_MEM) == 0) |
| 1663 | continue; |
| 1664 | /* In the range of this resource? */ |
| 1665 | if (offset < (rp->start & PAGE_MASK) || |
| 1666 | offset > rp->end) |
| 1667 | continue; |
| 1668 | found = rp; |
| 1669 | break; |
| 1670 | } |
| 1671 | if (found) |
| 1672 | break; |
| 1673 | } |
| 1674 | if (found) { |
| 1675 | if (found->flags & IORESOURCE_PREFETCH) |
| 1676 | prot &= ~_PAGE_GUARDED; |
| 1677 | pci_dev_put(pdev); |
| 1678 | } |
| 1679 | |
| 1680 | DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); |
| 1681 | |
| 1682 | return __pgprot(prot); |
| 1683 | } |
| 1684 | |
| 1685 | |
| 1686 | /* |
| 1687 | * Perform the actual remap of the pages for a PCI device mapping, as |
| 1688 | * appropriate for this architecture. The region in the process to map |
| 1689 | * is described by vm_start and vm_end members of VMA, the base physical |
| 1690 | * address is found in vm_pgoff. |
| 1691 | * The pci device structure is provided so that architectures may make mapping |
| 1692 | * decisions on a per-device or per-bus basis. |
| 1693 | * |
| 1694 | * Returns a negative error code on failure, zero on success. |
| 1695 | */ |
| 1696 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, |
| 1697 | enum pci_mmap_state mmap_state, |
| 1698 | int write_combine) |
| 1699 | { |
| 1700 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; |
| 1701 | struct resource *rp; |
| 1702 | int ret; |
| 1703 | |
| 1704 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); |
| 1705 | if (rp == NULL) |
| 1706 | return -EINVAL; |
| 1707 | |
| 1708 | vma->vm_pgoff = offset >> PAGE_SHIFT; |
| 1709 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, |
| 1710 | vma->vm_page_prot, |
| 1711 | mmap_state, write_combine); |
| 1712 | |
| 1713 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
| 1714 | vma->vm_end - vma->vm_start, vma->vm_page_prot); |
| 1715 | |
| 1716 | return ret; |
| 1717 | } |
| 1718 | |
| 1719 | /* Obsolete functions. Should be removed once the symbios driver |
| 1720 | * is fixed |
| 1721 | */ |
| 1722 | unsigned long |
| 1723 | phys_to_bus(unsigned long pa) |
| 1724 | { |
| 1725 | struct pci_controller *hose; |
| 1726 | int i; |
| 1727 | |
| 1728 | for (hose = hose_head; hose; hose = hose->next) { |
| 1729 | for (i = 0; i < 3; ++i) { |
| 1730 | if (pa >= hose->mem_resources[i].start |
| 1731 | && pa <= hose->mem_resources[i].end) { |
| 1732 | /* |
| 1733 | * XXX the hose->pci_mem_offset really |
| 1734 | * only applies to mem_resources[0]. |
| 1735 | * We need a way to store an offset for |
| 1736 | * the others. -- paulus |
| 1737 | */ |
| 1738 | if (i == 0) |
| 1739 | pa -= hose->pci_mem_offset; |
| 1740 | return pa; |
| 1741 | } |
| 1742 | } |
| 1743 | } |
| 1744 | /* hmmm, didn't find it */ |
| 1745 | return 0; |
| 1746 | } |
| 1747 | |
| 1748 | unsigned long |
| 1749 | pci_phys_to_bus(unsigned long pa, int busnr) |
| 1750 | { |
| 1751 | struct pci_controller* hose = pci_bus_to_hose(busnr); |
| 1752 | if (!hose) |
| 1753 | return pa; |
| 1754 | return pa - hose->pci_mem_offset; |
| 1755 | } |
| 1756 | |
| 1757 | unsigned long |
| 1758 | pci_bus_to_phys(unsigned int ba, int busnr) |
| 1759 | { |
| 1760 | struct pci_controller* hose = pci_bus_to_hose(busnr); |
| 1761 | if (!hose) |
| 1762 | return ba; |
| 1763 | return ba + hose->pci_mem_offset; |
| 1764 | } |
| 1765 | |
| 1766 | /* Provide information on locations of various I/O regions in physical |
| 1767 | * memory. Do this on a per-card basis so that we choose the right |
| 1768 | * root bridge. |
| 1769 | * Note that the returned IO or memory base is a physical address |
| 1770 | */ |
| 1771 | |
| 1772 | long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) |
| 1773 | { |
| 1774 | struct pci_controller* hose; |
| 1775 | long result = -EOPNOTSUPP; |
| 1776 | |
| 1777 | /* Argh ! Please forgive me for that hack, but that's the |
| 1778 | * simplest way to get existing XFree to not lockup on some |
| 1779 | * G5 machines... So when something asks for bus 0 io base |
| 1780 | * (bus 0 is HT root), we return the AGP one instead. |
| 1781 | */ |
| 1782 | #ifdef CONFIG_PPC_PMAC |
| 1783 | if (machine_is(powermac) && machine_is_compatible("MacRISC4")) |
| 1784 | if (bus == 0) |
| 1785 | bus = 0xf0; |
| 1786 | #endif /* CONFIG_PPC_PMAC */ |
| 1787 | |
| 1788 | hose = pci_bus_to_hose(bus); |
| 1789 | if (!hose) |
| 1790 | return -ENODEV; |
| 1791 | |
| 1792 | switch (which) { |
| 1793 | case IOBASE_BRIDGE_NUMBER: |
| 1794 | return (long)hose->first_busno; |
| 1795 | case IOBASE_MEMORY: |
| 1796 | return (long)hose->pci_mem_offset; |
| 1797 | case IOBASE_IO: |
| 1798 | return (long)hose->io_base_phys; |
| 1799 | case IOBASE_ISA_IO: |
| 1800 | return (long)isa_io_base; |
| 1801 | case IOBASE_ISA_MEM: |
| 1802 | return (long)isa_mem_base; |
| 1803 | } |
| 1804 | |
| 1805 | return result; |
| 1806 | } |
| 1807 | |
| 1808 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
| 1809 | const struct resource *rsrc, |
| 1810 | resource_size_t *start, resource_size_t *end) |
| 1811 | { |
| 1812 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); |
| 1813 | unsigned long offset = 0; |
| 1814 | |
| 1815 | if (hose == NULL) |
| 1816 | return; |
| 1817 | |
| 1818 | if (rsrc->flags & IORESOURCE_IO) |
| 1819 | offset = ___IO_BASE - hose->io_base_virt + hose->io_base_phys; |
| 1820 | |
| 1821 | *start = rsrc->start + offset; |
| 1822 | *end = rsrc->end + offset; |
| 1823 | } |
| 1824 | |
| 1825 | void __init |
| 1826 | pci_init_resource(struct resource *res, unsigned long start, unsigned long end, |
| 1827 | int flags, char *name) |
| 1828 | { |
| 1829 | res->start = start; |
| 1830 | res->end = end; |
| 1831 | res->flags = flags; |
| 1832 | res->name = name; |
| 1833 | res->parent = NULL; |
| 1834 | res->sibling = NULL; |
| 1835 | res->child = NULL; |
| 1836 | } |
| 1837 | |
| 1838 | void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) |
| 1839 | { |
| 1840 | unsigned long start = pci_resource_start(dev, bar); |
| 1841 | unsigned long len = pci_resource_len(dev, bar); |
| 1842 | unsigned long flags = pci_resource_flags(dev, bar); |
| 1843 | |
| 1844 | if (!len) |
| 1845 | return NULL; |
| 1846 | if (max && len > max) |
| 1847 | len = max; |
| 1848 | if (flags & IORESOURCE_IO) |
| 1849 | return ioport_map(start, len); |
| 1850 | if (flags & IORESOURCE_MEM) |
| 1851 | /* Not checking IORESOURCE_CACHEABLE because PPC does |
| 1852 | * not currently distinguish between ioremap and |
| 1853 | * ioremap_nocache. |
| 1854 | */ |
| 1855 | return ioremap(start, len); |
| 1856 | /* What? */ |
| 1857 | return NULL; |
| 1858 | } |
| 1859 | |
| 1860 | void pci_iounmap(struct pci_dev *dev, void __iomem *addr) |
| 1861 | { |
| 1862 | /* Nothing to do */ |
| 1863 | } |
| 1864 | EXPORT_SYMBOL(pci_iomap); |
| 1865 | EXPORT_SYMBOL(pci_iounmap); |
| 1866 | |
| 1867 | unsigned long pci_address_to_pio(phys_addr_t address) |
| 1868 | { |
| 1869 | struct pci_controller* hose = hose_head; |
| 1870 | |
| 1871 | for (; hose; hose = hose->next) { |
| 1872 | unsigned int size = hose->io_resource.end - |
| 1873 | hose->io_resource.start + 1; |
| 1874 | if (address >= hose->io_base_phys && |
| 1875 | address < (hose->io_base_phys + size)) { |
| 1876 | unsigned long base = |
| 1877 | (unsigned long)hose->io_base_virt - _IO_BASE; |
| 1878 | return base + (address - hose->io_base_phys); |
| 1879 | } |
| 1880 | } |
| 1881 | return (unsigned int)-1; |
| 1882 | } |
| 1883 | EXPORT_SYMBOL(pci_address_to_pio); |
| 1884 | |
| 1885 | /* |
| 1886 | * Null PCI config access functions, for the case when we can't |
| 1887 | * find a hose. |
| 1888 | */ |
| 1889 | #define NULL_PCI_OP(rw, size, type) \ |
| 1890 | static int \ |
| 1891 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ |
| 1892 | { \ |
| 1893 | return PCIBIOS_DEVICE_NOT_FOUND; \ |
| 1894 | } |
| 1895 | |
| 1896 | static int |
| 1897 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 1898 | int len, u32 *val) |
| 1899 | { |
| 1900 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 1901 | } |
| 1902 | |
| 1903 | static int |
| 1904 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 1905 | int len, u32 val) |
| 1906 | { |
| 1907 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 1908 | } |
| 1909 | |
| 1910 | static struct pci_ops null_pci_ops = |
| 1911 | { |
| 1912 | null_read_config, |
| 1913 | null_write_config |
| 1914 | }; |
| 1915 | |
| 1916 | /* |
| 1917 | * These functions are used early on before PCI scanning is done |
| 1918 | * and all of the pci_dev and pci_bus structures have been created. |
| 1919 | */ |
| 1920 | static struct pci_bus * |
| 1921 | fake_pci_bus(struct pci_controller *hose, int busnr) |
| 1922 | { |
| 1923 | static struct pci_bus bus; |
| 1924 | |
| 1925 | if (hose == 0) { |
| 1926 | hose = pci_bus_to_hose(busnr); |
| 1927 | if (hose == 0) |
| 1928 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); |
| 1929 | } |
| 1930 | bus.number = busnr; |
| 1931 | bus.sysdata = hose; |
| 1932 | bus.ops = hose? hose->ops: &null_pci_ops; |
| 1933 | return &bus; |
| 1934 | } |
| 1935 | |
| 1936 | #define EARLY_PCI_OP(rw, size, type) \ |
| 1937 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ |
| 1938 | int devfn, int offset, type value) \ |
| 1939 | { \ |
| 1940 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ |
| 1941 | devfn, offset, value); \ |
| 1942 | } |
| 1943 | |
| 1944 | EARLY_PCI_OP(read, byte, u8 *) |
| 1945 | EARLY_PCI_OP(read, word, u16 *) |
| 1946 | EARLY_PCI_OP(read, dword, u32 *) |
| 1947 | EARLY_PCI_OP(write, byte, u8) |
| 1948 | EARLY_PCI_OP(write, word, u16) |
| 1949 | EARLY_PCI_OP(write, dword, u32) |