| | 1 | /* |
| | 2 | * Lite5200B board Device Tree Source |
| | 3 | * |
| | 4 | * Copyright 2006-2007 Secret Lab Technologies Ltd. |
| | 5 | * Grant Likely <grant.likely@secretlab.ca> |
| | 6 | * |
| | 7 | * This program is free software; you can redistribute it and/or modify it |
| | 8 | * under the terms of the GNU General Public License as published by the |
| | 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| | 10 | * option) any later version. |
| | 11 | */ |
| | 12 | |
| | 13 | /* |
| | 14 | * WARNING: Do not depend on this tree layout remaining static just yet. |
| | 15 | * The MPC5200 device tree conventions are still in flux |
| | 16 | * Keep an eye on the linuxppc-dev mailing list for more details |
| | 17 | */ |
| | 18 | |
| | 19 | / { |
| | 20 | model = "fsl,lite5200b"; |
| | 21 | // revision = "1.0"; |
| | 22 | compatible = "fsl,lite5200b","generic-mpc5200"; |
| | 23 | #address-cells = <1>; |
| | 24 | #size-cells = <1>; |
| | 25 | |
| | 26 | cpus { |
| | 27 | #address-cells = <1>; |
| | 28 | #size-cells = <0>; |
| | 29 | |
| | 30 | PowerPC,5200@0 { |
| | 31 | device_type = "cpu"; |
| | 32 | reg = <0>; |
| | 33 | d-cache-line-size = <20>; |
| | 34 | i-cache-line-size = <20>; |
| | 35 | d-cache-size = <4000>; // L1, 16K |
| | 36 | i-cache-size = <4000>; // L1, 16K |
| | 37 | timebase-frequency = <0>; // from bootloader |
| | 38 | bus-frequency = <0>; // from bootloader |
| | 39 | clock-frequency = <0>; // from bootloader |
| | 40 | }; |
| | 41 | }; |
| | 42 | |
| | 43 | memory { |
| | 44 | device_type = "memory"; |
| | 45 | reg = <00000000 10000000>; // 256MB |
| | 46 | }; |
| | 47 | |
| | 48 | soc5200@f0000000 { |
| | 49 | model = "fsl,mpc5200b"; |
| | 50 | compatible = "mpc5200"; |
| | 51 | revision = ""; // from bootloader |
| | 52 | device_type = "soc"; |
| | 53 | ranges = <0 f0000000 0000c000>; |
| | 54 | reg = <f0000000 00000100>; |
| | 55 | bus-frequency = <0>; // from bootloader |
| | 56 | system-frequency = <0>; // from bootloader |
| | 57 | |
| | 58 | cdm@200 { |
| | 59 | compatible = "mpc5200b-cdm","mpc5200-cdm"; |
| | 60 | reg = <200 38>; |
| | 61 | }; |
| | 62 | |
| | 63 | mpc5200_pic: pic@500 { |
| | 64 | // 5200 interrupts are encoded into two levels; |
| | 65 | interrupt-controller; |
| | 66 | #interrupt-cells = <3>; |
| | 67 | device_type = "interrupt-controller"; |
| | 68 | compatible = "mpc5200b-pic","mpc5200-pic"; |
| | 69 | reg = <500 80>; |
| | 70 | }; |
| | 71 | |
| | 72 | gpt@600 { // General Purpose Timer |
| | 73 | compatible = "mpc5200b-gpt","mpc5200-gpt"; |
| | 74 | device_type = "gpt"; |
| | 75 | cell-index = <0>; |
| | 76 | reg = <600 10>; |
| | 77 | interrupts = <1 9 0>; |
| | 78 | interrupt-parent = <&mpc5200_pic>; |
| | 79 | has-wdt; |
| | 80 | }; |
| | 81 | |
| | 82 | gpt@610 { // General Purpose Timer |
| | 83 | compatible = "mpc5200b-gpt","mpc5200-gpt"; |
| | 84 | device_type = "gpt"; |
| | 85 | cell-index = <1>; |
| | 86 | reg = <610 10>; |
| | 87 | interrupts = <1 a 0>; |
| | 88 | interrupt-parent = <&mpc5200_pic>; |
| | 89 | }; |
| | 90 | |
| | 91 | gpt@620 { // General Purpose Timer |
| | 92 | compatible = "mpc5200b-gpt","mpc5200-gpt"; |
| | 93 | device_type = "gpt"; |
| | 94 | cell-index = <2>; |
| | 95 | reg = <620 10>; |
| | 96 | interrupts = <1 b 0>; |
| | 97 | interrupt-parent = <&mpc5200_pic>; |
| | 98 | }; |
| | 99 | |
| | 100 | gpt@630 { // General Purpose Timer |
| | 101 | compatible = "mpc5200b-gpt","mpc5200-gpt"; |
| | 102 | device_type = "gpt"; |
| | 103 | cell-index = <3>; |
| | 104 | reg = <630 10>; |
| | 105 | interrupts = <1 c 0>; |
| | 106 | interrupt-parent = <&mpc5200_pic>; |
| | 107 | }; |
| | 108 | |
| | 109 | gpt@640 { // General Purpose Timer |
| | 110 | compatible = "mpc5200b-gpt","mpc5200-gpt"; |
| | 111 | device_type = "gpt"; |
| | 112 | cell-index = <4>; |
| | 113 | reg = <640 10>; |
| | 114 | interrupts = <1 d 0>; |
| | 115 | interrupt-parent = <&mpc5200_pic>; |
| | 116 | }; |
| | 117 | |
| | 118 | gpt@650 { // General Purpose Timer |
| | 119 | compatible = "mpc5200b-gpt","mpc5200-gpt"; |
| | 120 | device_type = "gpt"; |
| | 121 | cell-index = <5>; |
| | 122 | reg = <650 10>; |
| | 123 | interrupts = <1 e 0>; |
| | 124 | interrupt-parent = <&mpc5200_pic>; |
| | 125 | }; |
| | 126 | |
| | 127 | gpt@660 { // General Purpose Timer |
| | 128 | compatible = "mpc5200b-gpt","mpc5200-gpt"; |
| | 129 | device_type = "gpt"; |
| | 130 | cell-index = <6>; |
| | 131 | reg = <660 10>; |
| | 132 | interrupts = <1 f 0>; |
| | 133 | interrupt-parent = <&mpc5200_pic>; |
| | 134 | }; |
| | 135 | |
| | 136 | gpt@670 { // General Purpose Timer |
| | 137 | compatible = "mpc5200b-gpt","mpc5200-gpt"; |
| | 138 | device_type = "gpt"; |
| | 139 | cell-index = <7>; |
| | 140 | reg = <670 10>; |
| | 141 | interrupts = <1 10 0>; |
| | 142 | interrupt-parent = <&mpc5200_pic>; |
| | 143 | }; |
| | 144 | |
| | 145 | rtc@800 { // Real time clock |
| | 146 | compatible = "mpc5200b-rtc","mpc5200-rtc"; |
| | 147 | device_type = "rtc"; |
| | 148 | reg = <800 100>; |
| | 149 | interrupts = <1 5 0 1 6 0>; |
| | 150 | interrupt-parent = <&mpc5200_pic>; |
| | 151 | }; |
| | 152 | |
| | 153 | mscan@900 { |
| | 154 | device_type = "mscan"; |
| | 155 | compatible = "mpc5200b-mscan","mpc5200-mscan"; |
| | 156 | cell-index = <0>; |
| | 157 | interrupts = <2 11 0>; |
| | 158 | interrupt-parent = <&mpc5200_pic>; |
| | 159 | reg = <900 80>; |
| | 160 | }; |
| | 161 | |
| | 162 | mscan@980 { |
| | 163 | device_type = "mscan"; |
| | 164 | compatible = "mpc5200b-mscan","mpc5200-mscan"; |
| | 165 | cell-index = <1>; |
| | 166 | interrupts = <2 12 0>; |
| | 167 | interrupt-parent = <&mpc5200_pic>; |
| | 168 | reg = <980 80>; |
| | 169 | }; |
| | 170 | |
| | 171 | gpio@b00 { |
| | 172 | compatible = "mpc5200b-gpio","mpc5200-gpio"; |
| | 173 | reg = <b00 40>; |
| | 174 | interrupts = <1 7 0>; |
| | 175 | interrupt-parent = <&mpc5200_pic>; |
| | 176 | }; |
| | 177 | |
| | 178 | gpio-wkup@c00 { |
| | 179 | compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup"; |
| | 180 | reg = <c00 40>; |
| | 181 | interrupts = <1 8 0 0 3 0>; |
| | 182 | interrupt-parent = <&mpc5200_pic>; |
| | 183 | }; |
| | 184 | |
| | 185 | spi@f00 { |
| | 186 | device_type = "spi"; |
| | 187 | compatible = "mpc5200b-spi","mpc5200-spi"; |
| | 188 | reg = <f00 20>; |
| | 189 | interrupts = <2 d 0 2 e 0>; |
| | 190 | interrupt-parent = <&mpc5200_pic>; |
| | 191 | }; |
| | 192 | |
| | 193 | usb@1000 { |
| | 194 | device_type = "usb-ohci-be"; |
| | 195 | compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be"; |
| | 196 | reg = <1000 ff>; |
| | 197 | interrupts = <2 6 0>; |
| | 198 | interrupt-parent = <&mpc5200_pic>; |
| | 199 | }; |
| | 200 | |
| | 201 | bestcomm@1200 { |
| | 202 | device_type = "dma-controller"; |
| | 203 | compatible = "mpc5200b-bestcomm","mpc5200-bestcomm"; |
| | 204 | reg = <1200 80>; |
| | 205 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
| | 206 | 3 4 0 3 5 0 3 6 0 3 7 0 |
| | 207 | 3 8 0 3 9 0 3 a 0 3 b 0 |
| | 208 | 3 c 0 3 d 0 3 e 0 3 f 0>; |
| | 209 | interrupt-parent = <&mpc5200_pic>; |
| | 210 | }; |
| | 211 | |
| | 212 | xlb@1f00 { |
| | 213 | compatible = "mpc5200b-xlb","mpc5200-xlb"; |
| | 214 | reg = <1f00 100>; |
| | 215 | }; |
| | 216 | |
| | 217 | serial@2000 { // PSC1 |
| | 218 | device_type = "serial"; |
| | 219 | compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; |
| | 220 | port-number = <0>; // Logical port assignment |
| | 221 | cell-index = <0>; |
| | 222 | reg = <2000 100>; |
| | 223 | interrupts = <2 1 0>; |
| | 224 | interrupt-parent = <&mpc5200_pic>; |
| | 225 | }; |
| | 226 | |
| | 227 | // PSC2 in ac97 mode example |
| | 228 | //ac97@2200 { // PSC2 |
| | 229 | // device_type = "sound"; |
| | 230 | // compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97"; |
| | 231 | // cell-index = <1>; |
| | 232 | // reg = <2200 100>; |
| | 233 | // interrupts = <2 2 0>; |
| | 234 | // interrupt-parent = <&mpc5200_pic>; |
| | 235 | //}; |
| | 236 | |
| | 237 | // PSC3 in CODEC mode example |
| | 238 | //i2s@2400 { // PSC3 |
| | 239 | // device_type = "sound"; |
| | 240 | // compatible = "mpc5200b-psc-i2s"; //not 5200 compatible |
| | 241 | // cell-index = <2>; |
| | 242 | // reg = <2400 100>; |
| | 243 | // interrupts = <2 3 0>; |
| | 244 | // interrupt-parent = <&mpc5200_pic>; |
| | 245 | //}; |
| | 246 | |
| | 247 | // PSC4 in uart mode example |
| | 248 | //serial@2600 { // PSC4 |
| | 249 | // device_type = "serial"; |
| | 250 | // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; |
| | 251 | // cell-index = <3>; |
| | 252 | // reg = <2600 100>; |
| | 253 | // interrupts = <2 b 0>; |
| | 254 | // interrupt-parent = <&mpc5200_pic>; |
| | 255 | //}; |
| | 256 | |
| | 257 | // PSC5 in uart mode example |
| | 258 | //serial@2800 { // PSC5 |
| | 259 | // device_type = "serial"; |
| | 260 | // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; |
| | 261 | // cell-index = <4>; |
| | 262 | // reg = <2800 100>; |
| | 263 | // interrupts = <2 c 0>; |
| | 264 | // interrupt-parent = <&mpc5200_pic>; |
| | 265 | //}; |
| | 266 | |
| | 267 | // PSC6 in spi mode example |
| | 268 | //spi@2c00 { // PSC6 |
| | 269 | // device_type = "spi"; |
| | 270 | // compatible = "mpc5200b-psc-spi","mpc5200-psc-spi"; |
| | 271 | // cell-index = <5>; |
| | 272 | // reg = <2c00 100>; |
| | 273 | // interrupts = <2 4 0>; |
| | 274 | // interrupt-parent = <&mpc5200_pic>; |
| | 275 | //}; |
| | 276 | |
| | 277 | ethernet@3000 { |
| | 278 | device_type = "network"; |
| | 279 | compatible = "mpc5200b-fec","mpc5200-fec"; |
| | 280 | reg = <3000 800>; |
| | 281 | mac-address = [ 02 03 04 05 06 07 ]; // Bad! |
| | 282 | interrupts = <2 5 0>; |
| | 283 | interrupt-parent = <&mpc5200_pic>; |
| | 284 | }; |
| | 285 | |
| | 286 | ata@3a00 { |
| | 287 | device_type = "ata"; |
| | 288 | compatible = "mpc5200b-ata","mpc5200-ata"; |
| | 289 | reg = <3a00 100>; |
| | 290 | interrupts = <2 7 0>; |
| | 291 | interrupt-parent = <&mpc5200_pic>; |
| | 292 | }; |
| | 293 | |
| | 294 | i2c@3d00 { |
| | 295 | device_type = "i2c"; |
| | 296 | compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; |
| | 297 | cell-index = <0>; |
| | 298 | reg = <3d00 40>; |
| | 299 | interrupts = <2 f 0>; |
| | 300 | interrupt-parent = <&mpc5200_pic>; |
| | 301 | fsl5200-clocking; |
| | 302 | }; |
| | 303 | |
| | 304 | i2c@3d40 { |
| | 305 | device_type = "i2c"; |
| | 306 | compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; |
| | 307 | cell-index = <1>; |
| | 308 | reg = <3d40 40>; |
| | 309 | interrupts = <2 10 0>; |
| | 310 | interrupt-parent = <&mpc5200_pic>; |
| | 311 | fsl5200-clocking; |
| | 312 | }; |
| | 313 | sram@8000 { |
| | 314 | device_type = "sram"; |
| | 315 | compatible = "mpc5200b-sram","mpc5200-sram","sram"; |
| | 316 | reg = <8000 4000>; |
| | 317 | }; |
| | 318 | }; |
| | 319 | |
| | 320 | pci@f0000d00 { |
| | 321 | #interrupt-cells = <1>; |
| | 322 | #size-cells = <2>; |
| | 323 | #address-cells = <3>; |
| | 324 | device_type = "pci"; |
| | 325 | compatible = "mpc5200b-pci","mpc5200-pci"; |
| | 326 | reg = <f0000d00 100>; |
| | 327 | interrupt-map-mask = <f800 0 0 7>; |
| | 328 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot |
| | 329 | c000 0 0 2 &mpc5200_pic 1 1 3 |
| | 330 | c000 0 0 3 &mpc5200_pic 1 2 3 |
| | 331 | c000 0 0 4 &mpc5200_pic 1 3 3 |
| | 332 | |
| | 333 | c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot |
| | 334 | c800 0 0 2 &mpc5200_pic 1 2 3 |
| | 335 | c800 0 0 3 &mpc5200_pic 1 3 3 |
| | 336 | c800 0 0 4 &mpc5200_pic 0 0 3>; |
| | 337 | clock-frequency = <0>; // From boot loader |
| | 338 | interrupts = <2 8 0 2 9 0 2 a 0>; |
| | 339 | interrupt-parent = <&mpc5200_pic>; |
| | 340 | bus-range = <0 0>; |
| | 341 | ranges = <42000000 0 80000000 80000000 0 20000000 |
| | 342 | 02000000 0 a0000000 a0000000 0 10000000 |
| | 343 | 01000000 0 00000000 b0000000 0 01000000>; |
| | 344 | }; |
| | 345 | }; |
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