[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / cache-l2x0.c

/*
 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
 *
 * Copyright (C) 2007 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>

#define CACHE_LINE_SIZE		32

static void __iomem *l2x0_base;
static DEFINE_SPINLOCK(l2x0_lock);
static uint32_t l2x0_way_mask;	/* Bitmask of active ways */
static uint32_t l2x0_size;

static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
{
	/* wait for cache operation by line or way to complete */
	while (readl_relaxed(reg) & mask)
		;
}

#ifdef CONFIG_CACHE_PL310
static inline void cache_wait(void __iomem *reg, unsigned long mask)
{
	/* cache operations by line are atomic on PL310 */
}
#else
#define cache_wait	cache_wait_way
#endif

static inline void cache_sync(void)
{
	void __iomem *base = l2x0_base;

#ifdef CONFIG_ARM_ERRATA_753970
	/* write to an unmmapped register */
	writel_relaxed(0, base + L2X0_DUMMY_REG);
#else
	writel_relaxed(0, base + L2X0_CACHE_SYNC);
#endif
	cache_wait(base + L2X0_CACHE_SYNC, 1);
}

static inline void l2x0_clean_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
}

static inline void l2x0_inv_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}

#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)

#define debug_writel(val)	outer_cache.set_debug(val)

static void l2x0_set_debug(unsigned long val)
{
	writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
}
#else
/* Optimised out for non-errata case */
static inline void debug_writel(unsigned long val)
{
}

#define l2x0_set_debug	NULL
#endif

#ifdef CONFIG_PL310_ERRATA_588369
static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;

	/* Clean by PA followed by Invalidate by PA */
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
}
#else

static inline void l2x0_flush_line(unsigned long addr)
{
	void __iomem *base = l2x0_base;
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
}
#endif

static void l2x0_cache_sync(void)
{
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void __l2x0_flush_all(void)
{
	debug_writel(0x03);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
	cache_sync();
	debug_writel(0x00);
}

static void l2x0_flush_all(void)
{
	unsigned long flags;

	/* clean all ways */
	spin_lock_irqsave(&l2x0_lock, flags);
	__l2x0_flush_all();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_clean_all(void)
{
	unsigned long flags;

	/* clean all ways */
	spin_lock_irqsave(&l2x0_lock, flags);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
	cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_inv_all(void)
{
	unsigned long flags;

	/* invalidate all ways */
	spin_lock_irqsave(&l2x0_lock, flags);
	/* Invalidating when L2 is enabled is a nono */
	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_inv_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	if (start & (CACHE_LINE_SIZE - 1)) {
		start &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(start);
		debug_writel(0x00);
		start += CACHE_LINE_SIZE;
	}

	if (end & (CACHE_LINE_SIZE - 1)) {
		end &= ~(CACHE_LINE_SIZE - 1);
		debug_writel(0x03);
		l2x0_flush_line(end);
		debug_writel(0x00);
	}

	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_inv_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			spin_unlock_irqrestore(&l2x0_lock, flags);
			spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_INV_LINE_PA, 1);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_clean_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	if ((end - start) >= l2x0_size) {
		l2x0_clean_all();
		return;
	}

	spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		while (start < blk_end) {
			l2x0_clean_line(start);
			start += CACHE_LINE_SIZE;
		}

		if (blk_end < end) {
			spin_unlock_irqrestore(&l2x0_lock, flags);
			spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_flush_range(unsigned long start, unsigned long end)
{
	void __iomem *base = l2x0_base;
	unsigned long flags;

	if ((end - start) >= l2x0_size) {
		l2x0_flush_all();
		return;
	}

	spin_lock_irqsave(&l2x0_lock, flags);
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		unsigned long blk_end = start + min(end - start, 4096UL);

		debug_writel(0x03);
		while (start < blk_end) {
			l2x0_flush_line(start);
			start += CACHE_LINE_SIZE;
		}
		debug_writel(0x00);

		if (blk_end < end) {
			spin_unlock_irqrestore(&l2x0_lock, flags);
			spin_lock_irqsave(&l2x0_lock, flags);
		}
	}
	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	cache_sync();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void l2x0_disable(void)
{
	unsigned long flags;

	spin_lock_irqsave(&l2x0_lock, flags);
	__l2x0_flush_all();
	writel_relaxed(0, l2x0_base + L2X0_CTRL);
	dsb();
	spin_unlock_irqrestore(&l2x0_lock, flags);
}

static void __init l2x0_unlock(__u32 cache_id)
{
	int lockregs;
	int i;

	if (cache_id == L2X0_CACHE_ID_PART_L310)
		lockregs = 8;
	else
		/* L210 and unknown types */
		lockregs = 1;

	for (i = 0; i < lockregs; i++) {
		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
			       i * L2X0_LOCKDOWN_STRIDE);
		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
			       i * L2X0_LOCKDOWN_STRIDE);
	}
}

void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
	__u32 aux;
	__u32 cache_id;
	__u32 way_size = 0;
	int ways;
	const char *type;

	l2x0_base = base;

	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);

	aux &= aux_mask;
	aux |= aux_val;

	/* Determine the number of ways */
	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	case L2X0_CACHE_ID_PART_L310:
		if (aux & (1 << 16))
			ways = 16;
		else
			ways = 8;
		type = "L310";
		break;
	case L2X0_CACHE_ID_PART_L210:
		ways = (aux >> 13) & 0xf;
		type = "L210";
		break;
	default:
		/* Assume unknown chips have 8 ways */
		ways = 8;
		type = "L2x0 series";
		break;
	}

	l2x0_way_mask = (1 << ways) - 1;

	/*
	 * L2 cache Size =  Way size * Number of ways
	 */
	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
	way_size = 1 << (way_size + 3);
	l2x0_size = ways * way_size * SZ_1K;

	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
		/* Make sure that I&D is not locked down when starting */
		l2x0_unlock(cache_id);

		/* l2x0 controller is disabled */
		writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);

		l2x0_inv_all();

		/* enable L2X0 */
		writel_relaxed(1, l2x0_base + L2X0_CTRL);
	}

	outer_cache.inv_range = l2x0_inv_range;
	outer_cache.clean_range = l2x0_clean_range;
	outer_cache.flush_range = l2x0_flush_range;
	outer_cache.sync = l2x0_cache_sync;
	outer_cache.flush_all = l2x0_flush_all;
	outer_cache.inv_all = l2x0_inv_all;
	outer_cache.disable = l2x0_disable;
	outer_cache.set_debug = l2x0_set_debug;

	printk(KERN_INFO "%s cache controller enabled\n", type);
	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
			ways, cache_id, aux, l2x0_size);
}
Commit	Line	Data
	1	/*
	2	* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
	3	*
	4	* Copyright (C) 2007 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19	#include <linux/init.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/io.h>
	22
	23	#include <asm/cacheflush.h>
	24	#include <asm/hardware/cache-l2x0.h>
	25
	26	#define CACHE_LINE_SIZE 32
	27
	28	static void __iomem *l2x0_base;
	29	static DEFINE_SPINLOCK(l2x0_lock);
	30	static uint32_t l2x0_way_mask; /* Bitmask of active ways */
	31	static uint32_t l2x0_size;
	32
	33	static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
	34	{
	35	/* wait for cache operation by line or way to complete */
	36	while (readl_relaxed(reg) & mask)
	37	;
	38	}
	39
	40	#ifdef CONFIG_CACHE_PL310
	41	static inline void cache_wait(void __iomem *reg, unsigned long mask)
	42	{
	43	/* cache operations by line are atomic on PL310 */
	44	}
	45	#else
	46	#define cache_wait cache_wait_way
	47	#endif
	48
	49	static inline void cache_sync(void)
	50	{
	51	void __iomem *base = l2x0_base;
	52
	53	#ifdef CONFIG_ARM_ERRATA_753970
	54	/* write to an unmmapped register */
	55	writel_relaxed(0, base + L2X0_DUMMY_REG);
	56	#else
	57	writel_relaxed(0, base + L2X0_CACHE_SYNC);
	58	#endif
	59	cache_wait(base + L2X0_CACHE_SYNC, 1);
	60	}
	61
	62	static inline void l2x0_clean_line(unsigned long addr)
	63	{
	64	void __iomem *base = l2x0_base;
	65	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	66	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
	67	}
	68
	69	static inline void l2x0_inv_line(unsigned long addr)
	70	{
	71	void __iomem *base = l2x0_base;
	72	cache_wait(base + L2X0_INV_LINE_PA, 1);
	73	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
	74	}
	75
	76	#if defined(CONFIG_PL310_ERRATA_588369) \|\| defined(CONFIG_PL310_ERRATA_727915)
	77
	78	#define debug_writel(val) outer_cache.set_debug(val)
	79
	80	static void l2x0_set_debug(unsigned long val)
	81	{
	82	writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
	83	}
	84	#else
	85	/* Optimised out for non-errata case */
	86	static inline void debug_writel(unsigned long val)
	87	{
	88	}
	89
	90	#define l2x0_set_debug NULL
	91	#endif
	92
	93	#ifdef CONFIG_PL310_ERRATA_588369
	94	static inline void l2x0_flush_line(unsigned long addr)
	95	{
	96	void __iomem *base = l2x0_base;
	97
	98	/* Clean by PA followed by Invalidate by PA */
	99	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	100	writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
	101	cache_wait(base + L2X0_INV_LINE_PA, 1);
	102	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
	103	}
	104	#else
	105
	106	static inline void l2x0_flush_line(unsigned long addr)
	107	{
	108	void __iomem *base = l2x0_base;
	109	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	110	writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
	111	}
	112	#endif
	113
	114	static void l2x0_cache_sync(void)
	115	{
	116	unsigned long flags;
	117
	118	spin_lock_irqsave(&l2x0_lock, flags);
	119	cache_sync();
	120	spin_unlock_irqrestore(&l2x0_lock, flags);
	121	}
	122
	123	static void __l2x0_flush_all(void)
	124	{
	125	debug_writel(0x03);
	126	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
	127	cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
	128	cache_sync();
	129	debug_writel(0x00);
	130	}
	131
	132	static void l2x0_flush_all(void)
	133	{
	134	unsigned long flags;
	135
	136	/* clean all ways */
	137	spin_lock_irqsave(&l2x0_lock, flags);
	138	__l2x0_flush_all();
	139	spin_unlock_irqrestore(&l2x0_lock, flags);
	140	}
	141
	142	static void l2x0_clean_all(void)
	143	{
	144	unsigned long flags;
	145
	146	/* clean all ways */
	147	spin_lock_irqsave(&l2x0_lock, flags);
	148	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
	149	cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
	150	cache_sync();
	151	spin_unlock_irqrestore(&l2x0_lock, flags);
	152	}
	153
	154	static void l2x0_inv_all(void)
	155	{
	156	unsigned long flags;
	157
	158	/* invalidate all ways */
	159	spin_lock_irqsave(&l2x0_lock, flags);
	160	/* Invalidating when L2 is enabled is a nono */
	161	BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
	162	writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
	163	cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
	164	cache_sync();
	165	spin_unlock_irqrestore(&l2x0_lock, flags);
	166	}
	167
	168	static void l2x0_inv_range(unsigned long start, unsigned long end)
	169	{
	170	void __iomem *base = l2x0_base;
	171	unsigned long flags;
	172
	173	spin_lock_irqsave(&l2x0_lock, flags);
	174	if (start & (CACHE_LINE_SIZE - 1)) {
	175	start &= ~(CACHE_LINE_SIZE - 1);
	176	debug_writel(0x03);
	177	l2x0_flush_line(start);
	178	debug_writel(0x00);
	179	start += CACHE_LINE_SIZE;
	180	}
	181
	182	if (end & (CACHE_LINE_SIZE - 1)) {
	183	end &= ~(CACHE_LINE_SIZE - 1);
	184	debug_writel(0x03);
	185	l2x0_flush_line(end);
	186	debug_writel(0x00);
	187	}
	188
	189	while (start < end) {
	190	unsigned long blk_end = start + min(end - start, 4096UL);
	191
	192	while (start < blk_end) {
	193	l2x0_inv_line(start);
	194	start += CACHE_LINE_SIZE;
	195	}
	196
	197	if (blk_end < end) {
	198	spin_unlock_irqrestore(&l2x0_lock, flags);
	199	spin_lock_irqsave(&l2x0_lock, flags);
	200	}
	201	}
	202	cache_wait(base + L2X0_INV_LINE_PA, 1);
	203	cache_sync();
	204	spin_unlock_irqrestore(&l2x0_lock, flags);
	205	}
	206
	207	static void l2x0_clean_range(unsigned long start, unsigned long end)
	208	{
	209	void __iomem *base = l2x0_base;
	210	unsigned long flags;
	211
	212	if ((end - start) >= l2x0_size) {
	213	l2x0_clean_all();
	214	return;
	215	}
	216
	217	spin_lock_irqsave(&l2x0_lock, flags);
	218	start &= ~(CACHE_LINE_SIZE - 1);
	219	while (start < end) {
	220	unsigned long blk_end = start + min(end - start, 4096UL);
	221
	222	while (start < blk_end) {
	223	l2x0_clean_line(start);
	224	start += CACHE_LINE_SIZE;
	225	}
	226
	227	if (blk_end < end) {
	228	spin_unlock_irqrestore(&l2x0_lock, flags);
	229	spin_lock_irqsave(&l2x0_lock, flags);
	230	}
	231	}
	232	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
	233	cache_sync();
	234	spin_unlock_irqrestore(&l2x0_lock, flags);
	235	}
	236
	237	static void l2x0_flush_range(unsigned long start, unsigned long end)
	238	{
	239	void __iomem *base = l2x0_base;
	240	unsigned long flags;
	241
	242	if ((end - start) >= l2x0_size) {
	243	l2x0_flush_all();
	244	return;
	245	}
	246
	247	spin_lock_irqsave(&l2x0_lock, flags);
	248	start &= ~(CACHE_LINE_SIZE - 1);
	249	while (start < end) {
	250	unsigned long blk_end = start + min(end - start, 4096UL);
	251
	252	debug_writel(0x03);
	253	while (start < blk_end) {
	254	l2x0_flush_line(start);
	255	start += CACHE_LINE_SIZE;
	256	}
	257	debug_writel(0x00);
	258
	259	if (blk_end < end) {
	260	spin_unlock_irqrestore(&l2x0_lock, flags);
	261	spin_lock_irqsave(&l2x0_lock, flags);
	262	}
	263	}
	264	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
	265	cache_sync();
	266	spin_unlock_irqrestore(&l2x0_lock, flags);
	267	}
	268
	269	static void l2x0_disable(void)
	270	{
	271	unsigned long flags;
	272
	273	spin_lock_irqsave(&l2x0_lock, flags);
	274	__l2x0_flush_all();
	275	writel_relaxed(0, l2x0_base + L2X0_CTRL);
	276	dsb();
	277	spin_unlock_irqrestore(&l2x0_lock, flags);
	278	}
	279
	280	static void __init l2x0_unlock(__u32 cache_id)
	281	{
	282	int lockregs;
	283	int i;
	284
	285	if (cache_id == L2X0_CACHE_ID_PART_L310)
	286	lockregs = 8;
	287	else
	288	/* L210 and unknown types */
	289	lockregs = 1;
	290
	291	for (i = 0; i < lockregs; i++) {
	292	writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
	293	i * L2X0_LOCKDOWN_STRIDE);
	294	writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
	295	i * L2X0_LOCKDOWN_STRIDE);
	296	}
	297	}
	298
	299	void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
	300	{
	301	__u32 aux;
	302	__u32 cache_id;
	303	__u32 way_size = 0;
	304	int ways;
	305	const char *type;
	306
	307	l2x0_base = base;
	308
	309	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
	310	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
	311
	312	aux &= aux_mask;
	313	aux \|= aux_val;
	314
	315	/* Determine the number of ways */
	316	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
	317	case L2X0_CACHE_ID_PART_L310:
	318	if (aux & (1 << 16))
	319	ways = 16;
	320	else
	321	ways = 8;
	322	type = "L310";
	323	break;
	324	case L2X0_CACHE_ID_PART_L210:
	325	ways = (aux >> 13) & 0xf;
	326	type = "L210";
	327	break;
	328	default:
	329	/* Assume unknown chips have 8 ways */
	330	ways = 8;
	331	type = "L2x0 series";
	332	break;
	333	}
	334
	335	l2x0_way_mask = (1 << ways) - 1;
	336
	337	/*
	338	* L2 cache Size = Way size * Number of ways
	339	*/
	340	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
	341	way_size = 1 << (way_size + 3);
	342	l2x0_size = ways * way_size * SZ_1K;
	343
	344	/*
	345	* Check if l2x0 controller is already enabled.
	346	* If you are booting from non-secure mode
	347	* accessing the below registers will fault.
	348	*/
	349	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
	350	/* Make sure that I&D is not locked down when starting */
	351	l2x0_unlock(cache_id);
	352
	353	/* l2x0 controller is disabled */
	354	writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
	355
	356	l2x0_inv_all();
	357
	358	/* enable L2X0 */
	359	writel_relaxed(1, l2x0_base + L2X0_CTRL);
	360	}
	361
	362	outer_cache.inv_range = l2x0_inv_range;
	363	outer_cache.clean_range = l2x0_clean_range;
	364	outer_cache.flush_range = l2x0_flush_range;
	365	outer_cache.sync = l2x0_cache_sync;
	366	outer_cache.flush_all = l2x0_flush_all;
	367	outer_cache.inv_all = l2x0_inv_all;
	368	outer_cache.disable = l2x0_disable;
	369	outer_cache.set_debug = l2x0_set_debug;
	370
	371	printk(KERN_INFO "%s cache controller enabled\n", type);
	372	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
	373	ways, cache_id, aux, l2x0_size);
	374	}