| 1 | /* |
| 2 | * arch/arm/mach-ixp4xx/common.c |
| 3 | * |
| 4 | * Generic code shared across all IXP4XX platforms |
| 5 | * |
| 6 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> |
| 7 | * |
| 8 | * Copyright 2002 (c) Intel Corporation |
| 9 | * Copyright 2003-2004 (c) MontaVista, Software, Inc. |
| 10 | * |
| 11 | * This file is licensed under the terms of the GNU General Public |
| 12 | * License version 2. This program is licensed "as is" without any |
| 13 | * warranty of any kind, whether express or implied. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/mm.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/serial.h> |
| 20 | #include <linux/tty.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/serial_core.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/bitops.h> |
| 25 | #include <linux/time.h> |
| 26 | #include <linux/timex.h> |
| 27 | #include <linux/clocksource.h> |
| 28 | #include <linux/clockchips.h> |
| 29 | #include <linux/io.h> |
| 30 | #include <linux/export.h> |
| 31 | #include <linux/gpio.h> |
| 32 | #include <linux/cpu.h> |
| 33 | |
| 34 | #include <mach/udc.h> |
| 35 | #include <mach/hardware.h> |
| 36 | #include <mach/io.h> |
| 37 | #include <asm/uaccess.h> |
| 38 | #include <asm/pgtable.h> |
| 39 | #include <asm/page.h> |
| 40 | #include <asm/irq.h> |
| 41 | #include <asm/sched_clock.h> |
| 42 | #include <asm/system_misc.h> |
| 43 | |
| 44 | #include <asm/mach/map.h> |
| 45 | #include <asm/mach/irq.h> |
| 46 | #include <asm/mach/time.h> |
| 47 | |
| 48 | static void __init ixp4xx_clocksource_init(void); |
| 49 | static void __init ixp4xx_clockevent_init(void); |
| 50 | static struct clock_event_device clockevent_ixp4xx; |
| 51 | |
| 52 | /************************************************************************* |
| 53 | * IXP4xx chipset I/O mapping |
| 54 | *************************************************************************/ |
| 55 | static struct map_desc ixp4xx_io_desc[] __initdata = { |
| 56 | { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ |
| 57 | .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, |
| 58 | .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), |
| 59 | .length = IXP4XX_PERIPHERAL_REGION_SIZE, |
| 60 | .type = MT_DEVICE |
| 61 | }, { /* Expansion Bus Config Registers */ |
| 62 | .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, |
| 63 | .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), |
| 64 | .length = IXP4XX_EXP_CFG_REGION_SIZE, |
| 65 | .type = MT_DEVICE |
| 66 | }, { /* PCI Registers */ |
| 67 | .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, |
| 68 | .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), |
| 69 | .length = IXP4XX_PCI_CFG_REGION_SIZE, |
| 70 | .type = MT_DEVICE |
| 71 | }, { /* Queue Manager */ |
| 72 | .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT, |
| 73 | .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS), |
| 74 | .length = IXP4XX_QMGR_REGION_SIZE, |
| 75 | .type = MT_DEVICE |
| 76 | }, |
| 77 | }; |
| 78 | |
| 79 | void __init ixp4xx_map_io(void) |
| 80 | { |
| 81 | iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc)); |
| 82 | } |
| 83 | |
| 84 | |
| 85 | /************************************************************************* |
| 86 | * IXP4xx chipset IRQ handling |
| 87 | * |
| 88 | * TODO: GPIO IRQs should be marked invalid until the user of the IRQ |
| 89 | * (be it PCI or something else) configures that GPIO line |
| 90 | * as an IRQ. |
| 91 | **************************************************************************/ |
| 92 | enum ixp4xx_irq_type { |
| 93 | IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE |
| 94 | }; |
| 95 | |
| 96 | /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */ |
| 97 | static unsigned long long ixp4xx_irq_edge = 0; |
| 98 | |
| 99 | /* |
| 100 | * IRQ -> GPIO mapping table |
| 101 | */ |
| 102 | static signed char irq2gpio[32] = { |
| 103 | -1, -1, -1, -1, -1, -1, 0, 1, |
| 104 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 105 | -1, -1, -1, 2, 3, 4, 5, 6, |
| 106 | 7, 8, 9, 10, 11, 12, -1, -1, |
| 107 | }; |
| 108 | |
| 109 | static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) |
| 110 | { |
| 111 | int irq; |
| 112 | |
| 113 | for (irq = 0; irq < 32; irq++) { |
| 114 | if (irq2gpio[irq] == gpio) |
| 115 | return irq; |
| 116 | } |
| 117 | return -EINVAL; |
| 118 | } |
| 119 | |
| 120 | int irq_to_gpio(unsigned int irq) |
| 121 | { |
| 122 | int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; |
| 123 | |
| 124 | if (gpio == -1) |
| 125 | return -EINVAL; |
| 126 | |
| 127 | return gpio; |
| 128 | } |
| 129 | EXPORT_SYMBOL(irq_to_gpio); |
| 130 | |
| 131 | static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type) |
| 132 | { |
| 133 | int line = irq2gpio[d->irq]; |
| 134 | u32 int_style; |
| 135 | enum ixp4xx_irq_type irq_type; |
| 136 | volatile u32 *int_reg; |
| 137 | |
| 138 | /* |
| 139 | * Only for GPIO IRQs |
| 140 | */ |
| 141 | if (line < 0) |
| 142 | return -EINVAL; |
| 143 | |
| 144 | switch (type){ |
| 145 | case IRQ_TYPE_EDGE_BOTH: |
| 146 | int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; |
| 147 | irq_type = IXP4XX_IRQ_EDGE; |
| 148 | break; |
| 149 | case IRQ_TYPE_EDGE_RISING: |
| 150 | int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; |
| 151 | irq_type = IXP4XX_IRQ_EDGE; |
| 152 | break; |
| 153 | case IRQ_TYPE_EDGE_FALLING: |
| 154 | int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; |
| 155 | irq_type = IXP4XX_IRQ_EDGE; |
| 156 | break; |
| 157 | case IRQ_TYPE_LEVEL_HIGH: |
| 158 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; |
| 159 | irq_type = IXP4XX_IRQ_LEVEL; |
| 160 | break; |
| 161 | case IRQ_TYPE_LEVEL_LOW: |
| 162 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; |
| 163 | irq_type = IXP4XX_IRQ_LEVEL; |
| 164 | break; |
| 165 | default: |
| 166 | return -EINVAL; |
| 167 | } |
| 168 | |
| 169 | if (irq_type == IXP4XX_IRQ_EDGE) |
| 170 | ixp4xx_irq_edge |= (1 << d->irq); |
| 171 | else |
| 172 | ixp4xx_irq_edge &= ~(1 << d->irq); |
| 173 | |
| 174 | if (line >= 8) { /* pins 8-15 */ |
| 175 | line -= 8; |
| 176 | int_reg = IXP4XX_GPIO_GPIT2R; |
| 177 | } else { /* pins 0-7 */ |
| 178 | int_reg = IXP4XX_GPIO_GPIT1R; |
| 179 | } |
| 180 | |
| 181 | /* Clear the style for the appropriate pin */ |
| 182 | *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << |
| 183 | (line * IXP4XX_GPIO_STYLE_SIZE)); |
| 184 | |
| 185 | *IXP4XX_GPIO_GPISR = (1 << line); |
| 186 | |
| 187 | /* Set the new style */ |
| 188 | *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); |
| 189 | |
| 190 | /* Configure the line as an input */ |
| 191 | gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN); |
| 192 | |
| 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | static void ixp4xx_irq_mask(struct irq_data *d) |
| 197 | { |
| 198 | if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32) |
| 199 | *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32)); |
| 200 | else |
| 201 | *IXP4XX_ICMR &= ~(1 << d->irq); |
| 202 | } |
| 203 | |
| 204 | static void ixp4xx_irq_ack(struct irq_data *d) |
| 205 | { |
| 206 | int line = (d->irq < 32) ? irq2gpio[d->irq] : -1; |
| 207 | |
| 208 | if (line >= 0) |
| 209 | *IXP4XX_GPIO_GPISR = (1 << line); |
| 210 | } |
| 211 | |
| 212 | /* |
| 213 | * Level triggered interrupts on GPIO lines can only be cleared when the |
| 214 | * interrupt condition disappears. |
| 215 | */ |
| 216 | static void ixp4xx_irq_unmask(struct irq_data *d) |
| 217 | { |
| 218 | if (!(ixp4xx_irq_edge & (1 << d->irq))) |
| 219 | ixp4xx_irq_ack(d); |
| 220 | |
| 221 | if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32) |
| 222 | *IXP4XX_ICMR2 |= (1 << (d->irq - 32)); |
| 223 | else |
| 224 | *IXP4XX_ICMR |= (1 << d->irq); |
| 225 | } |
| 226 | |
| 227 | static struct irq_chip ixp4xx_irq_chip = { |
| 228 | .name = "IXP4xx", |
| 229 | .irq_ack = ixp4xx_irq_ack, |
| 230 | .irq_mask = ixp4xx_irq_mask, |
| 231 | .irq_unmask = ixp4xx_irq_unmask, |
| 232 | .irq_set_type = ixp4xx_set_irq_type, |
| 233 | }; |
| 234 | |
| 235 | void __init ixp4xx_init_irq(void) |
| 236 | { |
| 237 | int i = 0; |
| 238 | |
| 239 | /* |
| 240 | * ixp4xx does not implement the XScale PWRMODE register |
| 241 | * so it must not call cpu_do_idle(). |
| 242 | */ |
| 243 | cpu_idle_poll_ctrl(true); |
| 244 | |
| 245 | /* Route all sources to IRQ instead of FIQ */ |
| 246 | *IXP4XX_ICLR = 0x0; |
| 247 | |
| 248 | /* Disable all interrupt */ |
| 249 | *IXP4XX_ICMR = 0x0; |
| 250 | |
| 251 | if (cpu_is_ixp46x() || cpu_is_ixp43x()) { |
| 252 | /* Route upper 32 sources to IRQ instead of FIQ */ |
| 253 | *IXP4XX_ICLR2 = 0x00; |
| 254 | |
| 255 | /* Disable upper 32 interrupts */ |
| 256 | *IXP4XX_ICMR2 = 0x00; |
| 257 | } |
| 258 | |
| 259 | /* Default to all level triggered */ |
| 260 | for(i = 0; i < NR_IRQS; i++) { |
| 261 | irq_set_chip_and_handler(i, &ixp4xx_irq_chip, |
| 262 | handle_level_irq); |
| 263 | set_irq_flags(i, IRQF_VALID); |
| 264 | } |
| 265 | } |
| 266 | |
| 267 | |
| 268 | /************************************************************************* |
| 269 | * IXP4xx timer tick |
| 270 | * We use OS timer1 on the CPU for the timer tick and the timestamp |
| 271 | * counter as a source of real clock ticks to account for missed jiffies. |
| 272 | *************************************************************************/ |
| 273 | |
| 274 | static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id) |
| 275 | { |
| 276 | struct clock_event_device *evt = dev_id; |
| 277 | |
| 278 | /* Clear Pending Interrupt by writing '1' to it */ |
| 279 | *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND; |
| 280 | |
| 281 | evt->event_handler(evt); |
| 282 | |
| 283 | return IRQ_HANDLED; |
| 284 | } |
| 285 | |
| 286 | static struct irqaction ixp4xx_timer_irq = { |
| 287 | .name = "timer1", |
| 288 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
| 289 | .handler = ixp4xx_timer_interrupt, |
| 290 | .dev_id = &clockevent_ixp4xx, |
| 291 | }; |
| 292 | |
| 293 | void __init ixp4xx_timer_init(void) |
| 294 | { |
| 295 | /* Reset/disable counter */ |
| 296 | *IXP4XX_OSRT1 = 0; |
| 297 | |
| 298 | /* Clear Pending Interrupt by writing '1' to it */ |
| 299 | *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND; |
| 300 | |
| 301 | /* Reset time-stamp counter */ |
| 302 | *IXP4XX_OSTS = 0; |
| 303 | |
| 304 | /* Connect the interrupt handler and enable the interrupt */ |
| 305 | setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq); |
| 306 | |
| 307 | ixp4xx_clocksource_init(); |
| 308 | ixp4xx_clockevent_init(); |
| 309 | } |
| 310 | |
| 311 | static struct pxa2xx_udc_mach_info ixp4xx_udc_info; |
| 312 | |
| 313 | void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info) |
| 314 | { |
| 315 | memcpy(&ixp4xx_udc_info, info, sizeof *info); |
| 316 | } |
| 317 | |
| 318 | static struct resource ixp4xx_udc_resources[] = { |
| 319 | [0] = { |
| 320 | .start = 0xc800b000, |
| 321 | .end = 0xc800bfff, |
| 322 | .flags = IORESOURCE_MEM, |
| 323 | }, |
| 324 | [1] = { |
| 325 | .start = IRQ_IXP4XX_USB, |
| 326 | .end = IRQ_IXP4XX_USB, |
| 327 | .flags = IORESOURCE_IRQ, |
| 328 | }, |
| 329 | }; |
| 330 | |
| 331 | /* |
| 332 | * USB device controller. The IXP4xx uses the same controller as PXA25X, |
| 333 | * so we just use the same device. |
| 334 | */ |
| 335 | static struct platform_device ixp4xx_udc_device = { |
| 336 | .name = "pxa25x-udc", |
| 337 | .id = -1, |
| 338 | .num_resources = 2, |
| 339 | .resource = ixp4xx_udc_resources, |
| 340 | .dev = { |
| 341 | .platform_data = &ixp4xx_udc_info, |
| 342 | }, |
| 343 | }; |
| 344 | |
| 345 | static struct platform_device *ixp4xx_devices[] __initdata = { |
| 346 | &ixp4xx_udc_device, |
| 347 | }; |
| 348 | |
| 349 | static struct resource ixp46x_i2c_resources[] = { |
| 350 | [0] = { |
| 351 | .start = 0xc8011000, |
| 352 | .end = 0xc801101c, |
| 353 | .flags = IORESOURCE_MEM, |
| 354 | }, |
| 355 | [1] = { |
| 356 | .start = IRQ_IXP4XX_I2C, |
| 357 | .end = IRQ_IXP4XX_I2C, |
| 358 | .flags = IORESOURCE_IRQ |
| 359 | } |
| 360 | }; |
| 361 | |
| 362 | /* |
| 363 | * I2C controller. The IXP46x uses the same block as the IOP3xx, so |
| 364 | * we just use the same device name. |
| 365 | */ |
| 366 | static struct platform_device ixp46x_i2c_controller = { |
| 367 | .name = "IOP3xx-I2C", |
| 368 | .id = 0, |
| 369 | .num_resources = 2, |
| 370 | .resource = ixp46x_i2c_resources |
| 371 | }; |
| 372 | |
| 373 | static struct platform_device *ixp46x_devices[] __initdata = { |
| 374 | &ixp46x_i2c_controller |
| 375 | }; |
| 376 | |
| 377 | unsigned long ixp4xx_exp_bus_size; |
| 378 | EXPORT_SYMBOL(ixp4xx_exp_bus_size); |
| 379 | |
| 380 | static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
| 381 | { |
| 382 | gpio_line_config(gpio, IXP4XX_GPIO_IN); |
| 383 | |
| 384 | return 0; |
| 385 | } |
| 386 | |
| 387 | static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, |
| 388 | int level) |
| 389 | { |
| 390 | gpio_line_set(gpio, level); |
| 391 | gpio_line_config(gpio, IXP4XX_GPIO_OUT); |
| 392 | |
| 393 | return 0; |
| 394 | } |
| 395 | |
| 396 | static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio) |
| 397 | { |
| 398 | int value; |
| 399 | |
| 400 | gpio_line_get(gpio, &value); |
| 401 | |
| 402 | return value; |
| 403 | } |
| 404 | |
| 405 | static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, |
| 406 | int value) |
| 407 | { |
| 408 | gpio_line_set(gpio, value); |
| 409 | } |
| 410 | |
| 411 | static struct gpio_chip ixp4xx_gpio_chip = { |
| 412 | .label = "IXP4XX_GPIO_CHIP", |
| 413 | .direction_input = ixp4xx_gpio_direction_input, |
| 414 | .direction_output = ixp4xx_gpio_direction_output, |
| 415 | .get = ixp4xx_gpio_get_value, |
| 416 | .set = ixp4xx_gpio_set_value, |
| 417 | .to_irq = ixp4xx_gpio_to_irq, |
| 418 | .base = 0, |
| 419 | .ngpio = 16, |
| 420 | }; |
| 421 | |
| 422 | void __init ixp4xx_sys_init(void) |
| 423 | { |
| 424 | ixp4xx_exp_bus_size = SZ_16M; |
| 425 | |
| 426 | platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); |
| 427 | |
| 428 | gpiochip_add(&ixp4xx_gpio_chip); |
| 429 | |
| 430 | if (cpu_is_ixp46x()) { |
| 431 | int region; |
| 432 | |
| 433 | platform_add_devices(ixp46x_devices, |
| 434 | ARRAY_SIZE(ixp46x_devices)); |
| 435 | |
| 436 | for (region = 0; region < 7; region++) { |
| 437 | if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) { |
| 438 | ixp4xx_exp_bus_size = SZ_32M; |
| 439 | break; |
| 440 | } |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | printk("IXP4xx: Using %luMiB expansion bus window size\n", |
| 445 | ixp4xx_exp_bus_size >> 20); |
| 446 | } |
| 447 | |
| 448 | /* |
| 449 | * sched_clock() |
| 450 | */ |
| 451 | static u32 notrace ixp4xx_read_sched_clock(void) |
| 452 | { |
| 453 | return *IXP4XX_OSTS; |
| 454 | } |
| 455 | |
| 456 | /* |
| 457 | * clocksource |
| 458 | */ |
| 459 | |
| 460 | static cycle_t ixp4xx_clocksource_read(struct clocksource *c) |
| 461 | { |
| 462 | return *IXP4XX_OSTS; |
| 463 | } |
| 464 | |
| 465 | unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ; |
| 466 | EXPORT_SYMBOL(ixp4xx_timer_freq); |
| 467 | static void __init ixp4xx_clocksource_init(void) |
| 468 | { |
| 469 | setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq); |
| 470 | |
| 471 | clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32, |
| 472 | ixp4xx_clocksource_read); |
| 473 | } |
| 474 | |
| 475 | /* |
| 476 | * clockevents |
| 477 | */ |
| 478 | static int ixp4xx_set_next_event(unsigned long evt, |
| 479 | struct clock_event_device *unused) |
| 480 | { |
| 481 | unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK; |
| 482 | |
| 483 | *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts; |
| 484 | |
| 485 | return 0; |
| 486 | } |
| 487 | |
| 488 | static void ixp4xx_set_mode(enum clock_event_mode mode, |
| 489 | struct clock_event_device *evt) |
| 490 | { |
| 491 | unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK; |
| 492 | unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK; |
| 493 | |
| 494 | switch (mode) { |
| 495 | case CLOCK_EVT_MODE_PERIODIC: |
| 496 | osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK; |
| 497 | opts = IXP4XX_OST_ENABLE; |
| 498 | break; |
| 499 | case CLOCK_EVT_MODE_ONESHOT: |
| 500 | /* period set by 'set next_event' */ |
| 501 | osrt = 0; |
| 502 | opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT; |
| 503 | break; |
| 504 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 505 | opts &= ~IXP4XX_OST_ENABLE; |
| 506 | break; |
| 507 | case CLOCK_EVT_MODE_RESUME: |
| 508 | opts |= IXP4XX_OST_ENABLE; |
| 509 | break; |
| 510 | case CLOCK_EVT_MODE_UNUSED: |
| 511 | default: |
| 512 | osrt = opts = 0; |
| 513 | break; |
| 514 | } |
| 515 | |
| 516 | *IXP4XX_OSRT1 = osrt | opts; |
| 517 | } |
| 518 | |
| 519 | static struct clock_event_device clockevent_ixp4xx = { |
| 520 | .name = "ixp4xx timer1", |
| 521 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 522 | .rating = 200, |
| 523 | .set_mode = ixp4xx_set_mode, |
| 524 | .set_next_event = ixp4xx_set_next_event, |
| 525 | }; |
| 526 | |
| 527 | static void __init ixp4xx_clockevent_init(void) |
| 528 | { |
| 529 | clockevent_ixp4xx.cpumask = cpumask_of(0); |
| 530 | clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ, |
| 531 | 0xf, 0xfffffffe); |
| 532 | } |
| 533 | |
| 534 | void ixp4xx_restart(char mode, const char *cmd) |
| 535 | { |
| 536 | if ( 1 && mode == 's') { |
| 537 | /* Jump into ROM at address 0 */ |
| 538 | soft_restart(0); |
| 539 | } else { |
| 540 | /* Use on-chip reset capability */ |
| 541 | |
| 542 | /* set the "key" register to enable access to |
| 543 | * "timer" and "enable" registers |
| 544 | */ |
| 545 | *IXP4XX_OSWK = IXP4XX_WDT_KEY; |
| 546 | |
| 547 | /* write 0 to the timer register for an immediate reset */ |
| 548 | *IXP4XX_OSWT = 0; |
| 549 | |
| 550 | *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE; |
| 551 | } |
| 552 | } |
| 553 | |
| 554 | #ifdef CONFIG_IXP4XX_INDIRECT_PCI |
| 555 | /* |
| 556 | * In the case of using indirect PCI, we simply return the actual PCI |
| 557 | * address and our read/write implementation use that to drive the |
| 558 | * access registers. If something outside of PCI is ioremap'd, we |
| 559 | * fallback to the default. |
| 560 | */ |
| 561 | |
| 562 | static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size, |
| 563 | unsigned int mtype, void *caller) |
| 564 | { |
| 565 | if (!is_pci_memory(addr)) |
| 566 | return __arm_ioremap_caller(addr, size, mtype, caller); |
| 567 | |
| 568 | return (void __iomem *)addr; |
| 569 | } |
| 570 | |
| 571 | static void ixp4xx_iounmap(void __iomem *addr) |
| 572 | { |
| 573 | if (!is_pci_memory((__force u32)addr)) |
| 574 | __iounmap(addr); |
| 575 | } |
| 576 | |
| 577 | void __init ixp4xx_init_early(void) |
| 578 | { |
| 579 | arch_ioremap_caller = ixp4xx_ioremap_caller; |
| 580 | arch_iounmap = ixp4xx_iounmap; |
| 581 | } |
| 582 | #else |
| 583 | void __init ixp4xx_init_early(void) {} |
| 584 | #endif |