| 1 | /* |
| 2 | * arch/arm/mach-iop13xx/msi.c |
| 3 | * |
| 4 | * PCI MSI support for the iop13xx processor |
| 5 | * |
| 6 | * Copyright (c) 2006, Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms and conditions of the GNU General Public License, |
| 10 | * version 2, as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple |
| 19 | * Place - Suite 330, Boston, MA 02111-1307 USA. |
| 20 | * |
| 21 | */ |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/msi.h> |
| 24 | #include <asm/mach/irq.h> |
| 25 | #include <asm/irq.h> |
| 26 | |
| 27 | |
| 28 | #define IOP13XX_NUM_MSI_IRQS 128 |
| 29 | static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); |
| 30 | |
| 31 | /* IMIPR0 CP6 R8 Page 1 |
| 32 | */ |
| 33 | static u32 read_imipr_0(void) |
| 34 | { |
| 35 | u32 val; |
| 36 | asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); |
| 37 | return val; |
| 38 | } |
| 39 | static void write_imipr_0(u32 val) |
| 40 | { |
| 41 | asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); |
| 42 | } |
| 43 | |
| 44 | /* IMIPR1 CP6 R9 Page 1 |
| 45 | */ |
| 46 | static u32 read_imipr_1(void) |
| 47 | { |
| 48 | u32 val; |
| 49 | asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); |
| 50 | return val; |
| 51 | } |
| 52 | static void write_imipr_1(u32 val) |
| 53 | { |
| 54 | asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); |
| 55 | } |
| 56 | |
| 57 | /* IMIPR2 CP6 R10 Page 1 |
| 58 | */ |
| 59 | static u32 read_imipr_2(void) |
| 60 | { |
| 61 | u32 val; |
| 62 | asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); |
| 63 | return val; |
| 64 | } |
| 65 | static void write_imipr_2(u32 val) |
| 66 | { |
| 67 | asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); |
| 68 | } |
| 69 | |
| 70 | /* IMIPR3 CP6 R11 Page 1 |
| 71 | */ |
| 72 | static u32 read_imipr_3(void) |
| 73 | { |
| 74 | u32 val; |
| 75 | asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); |
| 76 | return val; |
| 77 | } |
| 78 | static void write_imipr_3(u32 val) |
| 79 | { |
| 80 | asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); |
| 81 | } |
| 82 | |
| 83 | static u32 (*read_imipr[])(void) = { |
| 84 | read_imipr_0, |
| 85 | read_imipr_1, |
| 86 | read_imipr_2, |
| 87 | read_imipr_3, |
| 88 | }; |
| 89 | |
| 90 | static void (*write_imipr[])(u32) = { |
| 91 | write_imipr_0, |
| 92 | write_imipr_1, |
| 93 | write_imipr_2, |
| 94 | write_imipr_3, |
| 95 | }; |
| 96 | |
| 97 | static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) |
| 98 | { |
| 99 | int i, j; |
| 100 | unsigned long status; |
| 101 | |
| 102 | /* read IMIPR registers and find any active interrupts, |
| 103 | * then call ISR for each active interrupt |
| 104 | */ |
| 105 | for (i = 0; i < ARRAY_SIZE(read_imipr); i++) { |
| 106 | status = (read_imipr[i])(); |
| 107 | if (!status) |
| 108 | continue; |
| 109 | |
| 110 | do { |
| 111 | j = find_first_bit(&status, 32); |
| 112 | (write_imipr[i])(1 << j); /* write back to clear bit */ |
| 113 | generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i)); |
| 114 | status = (read_imipr[i])(); |
| 115 | } while (status); |
| 116 | } |
| 117 | } |
| 118 | |
| 119 | void __init iop13xx_msi_init(void) |
| 120 | { |
| 121 | irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); |
| 122 | } |
| 123 | |
| 124 | /* |
| 125 | * Dynamic irq allocate and deallocation |
| 126 | */ |
| 127 | int create_irq(void) |
| 128 | { |
| 129 | int irq, pos; |
| 130 | |
| 131 | again: |
| 132 | pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); |
| 133 | irq = IRQ_IOP13XX_MSI_0 + pos; |
| 134 | if (irq > NR_IRQS) |
| 135 | return -ENOSPC; |
| 136 | /* test_and_set_bit operates on 32-bits at a time */ |
| 137 | if (test_and_set_bit(pos, msi_irq_in_use)) |
| 138 | goto again; |
| 139 | |
| 140 | dynamic_irq_init(irq); |
| 141 | |
| 142 | return irq; |
| 143 | } |
| 144 | |
| 145 | void destroy_irq(unsigned int irq) |
| 146 | { |
| 147 | int pos = irq - IRQ_IOP13XX_MSI_0; |
| 148 | |
| 149 | dynamic_irq_cleanup(irq); |
| 150 | |
| 151 | clear_bit(pos, msi_irq_in_use); |
| 152 | } |
| 153 | |
| 154 | void arch_teardown_msi_irq(unsigned int irq) |
| 155 | { |
| 156 | destroy_irq(irq); |
| 157 | } |
| 158 | |
| 159 | static void iop13xx_msi_nop(struct irq_data *d) |
| 160 | { |
| 161 | return; |
| 162 | } |
| 163 | |
| 164 | static struct irq_chip iop13xx_msi_chip = { |
| 165 | .name = "PCI-MSI", |
| 166 | .irq_ack = iop13xx_msi_nop, |
| 167 | .irq_enable = unmask_msi_irq, |
| 168 | .irq_disable = mask_msi_irq, |
| 169 | .irq_mask = mask_msi_irq, |
| 170 | .irq_unmask = unmask_msi_irq, |
| 171 | }; |
| 172 | |
| 173 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
| 174 | { |
| 175 | int id, irq = create_irq(); |
| 176 | struct msi_msg msg; |
| 177 | |
| 178 | if (irq < 0) |
| 179 | return irq; |
| 180 | |
| 181 | irq_set_msi_desc(irq, desc); |
| 182 | |
| 183 | msg.address_hi = 0x0; |
| 184 | msg.address_lo = IOP13XX_MU_MIMR_PCI; |
| 185 | |
| 186 | id = iop13xx_cpu_id(); |
| 187 | msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); |
| 188 | |
| 189 | write_msi_msg(irq, &msg); |
| 190 | irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); |
| 191 | |
| 192 | return 0; |
| 193 | } |