[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / virt / kvm / irq_comm.c

/*
 * irq_comm.c: Common API for in kernel interrupt controller
 * Copyright (c) 2007, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 * Authors:
 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
 *
 */

#include <linux/kvm_host.h>
#include <trace/events/kvm.h>

#include <asm/msidef.h>
#ifdef CONFIG_IA64
#include <asm/iosapic.h>
#endif

#include "irq.h"

#include "ioapic.h"

static inline int kvm_irq_line_state(unsigned long *irq_state,
				     int irq_source_id, int level)
{
	/* Logical OR for level trig interrupt */
	if (level)
		set_bit(irq_source_id, irq_state);
	else
		clear_bit(irq_source_id, irq_state);

	return !!(*irq_state);
}

static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
			   struct kvm *kvm, int irq_source_id, int level)
{
#ifdef CONFIG_X86
	struct kvm_pic *pic = pic_irqchip(kvm);
	level = kvm_irq_line_state(&pic->irq_states[e->irqchip.pin],
				   irq_source_id, level);
	return kvm_pic_set_irq(pic, e->irqchip.pin, level);
#else
	return -1;
#endif
}

static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
			      struct kvm *kvm, int irq_source_id, int level)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	level = kvm_irq_line_state(&ioapic->irq_states[e->irqchip.pin],
				   irq_source_id, level);

	return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, level);
}

inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq)
{
#ifdef CONFIG_IA64
	return irq->delivery_mode ==
		(IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
#else
	return irq->delivery_mode == APIC_DM_LOWEST;
#endif
}

int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
		struct kvm_lapic_irq *irq)
{
	int i, r = -1;
	struct kvm_vcpu *vcpu, *lowest = NULL;

	if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
			kvm_is_dm_lowest_prio(irq))
		printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");

	kvm_for_each_vcpu(i, vcpu, kvm) {
		if (!kvm_apic_present(vcpu))
			continue;

		if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
					irq->dest_id, irq->dest_mode))
			continue;

		if (!kvm_is_dm_lowest_prio(irq)) {
			if (r < 0)
				r = 0;
			r += kvm_apic_set_irq(vcpu, irq);
		} else {
			if (!lowest)
				lowest = vcpu;
			else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
				lowest = vcpu;
		}
	}

	if (lowest)
		r = kvm_apic_set_irq(lowest, irq);

	return r;
}

static int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
		       struct kvm *kvm, int irq_source_id, int level)
{
	struct kvm_lapic_irq irq;

	if (!level)
		return -1;

	trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data);

	irq.dest_id = (e->msi.address_lo &
			MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
	irq.vector = (e->msi.data &
			MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
	irq.dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
	irq.trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
	irq.delivery_mode = e->msi.data & 0x700;
	irq.level = 1;
	irq.shorthand = 0;

	/* TODO Deal with RH bit of MSI message address */
	return kvm_irq_delivery_to_apic(kvm, NULL, &irq);
}

/*
 * Return value:
 *  < 0   Interrupt was ignored (masked or not delivered for other reasons)
 *  = 0   Interrupt was coalesced (previous irq is still pending)
 *  > 0   Number of CPUs interrupt was delivered to
 */
int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level)
{
	struct kvm_kernel_irq_routing_entry *e, irq_set[KVM_NR_IRQCHIPS];
	int ret = -1, i = 0;
	struct kvm_irq_routing_table *irq_rt;
	struct hlist_node *n;

	trace_kvm_set_irq(irq, level, irq_source_id);

	/* Not possible to detect if the guest uses the PIC or the
	 * IOAPIC.  So set the bit in both. The guest will ignore
	 * writes to the unused one.
	 */
	rcu_read_lock();
	irq_rt = rcu_dereference(kvm->irq_routing);
	if (irq < irq_rt->nr_rt_entries)
		hlist_for_each_entry(e, n, &irq_rt->map[irq], link)
			irq_set[i++] = *e;
	rcu_read_unlock();

	while(i--) {
		int r;
		r = irq_set[i].set(&irq_set[i], kvm, irq_source_id, level);
		if (r < 0)
			continue;

		ret = r + ((ret < 0) ? 0 : ret);
	}

	return ret;
}

void kvm_notify_acked_irq(struct kvm *kvm, unsigned irqchip, unsigned pin)
{
	struct kvm_irq_ack_notifier *kian;
	struct hlist_node *n;
	int gsi;

	trace_kvm_ack_irq(irqchip, pin);

	rcu_read_lock();
	gsi = rcu_dereference(kvm->irq_routing)->chip[irqchip][pin];
	if (gsi != -1)
		hlist_for_each_entry_rcu(kian, n, &kvm->irq_ack_notifier_list,
					 link)
			if (kian->gsi == gsi)
				kian->irq_acked(kian);
	rcu_read_unlock();
}

void kvm_register_irq_ack_notifier(struct kvm *kvm,
				   struct kvm_irq_ack_notifier *kian)
{
	mutex_lock(&kvm->irq_lock);
	hlist_add_head_rcu(&kian->link, &kvm->irq_ack_notifier_list);
	mutex_unlock(&kvm->irq_lock);
}

void kvm_unregister_irq_ack_notifier(struct kvm *kvm,
				    struct kvm_irq_ack_notifier *kian)
{
	mutex_lock(&kvm->irq_lock);
	hlist_del_init_rcu(&kian->link);
	mutex_unlock(&kvm->irq_lock);
	synchronize_rcu();
}

int kvm_request_irq_source_id(struct kvm *kvm)
{
	unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
	int irq_source_id;

	mutex_lock(&kvm->irq_lock);
	irq_source_id = find_first_zero_bit(bitmap,
				sizeof(kvm->arch.irq_sources_bitmap));

	if (irq_source_id >= sizeof(kvm->arch.irq_sources_bitmap)) {
		printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
		return -EFAULT;
	}

	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
	set_bit(irq_source_id, bitmap);
	mutex_unlock(&kvm->irq_lock);

	return irq_source_id;
}

void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
{
	int i;

	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);

	mutex_lock(&kvm->irq_lock);
	if (irq_source_id < 0 ||
	    irq_source_id >= sizeof(kvm->arch.irq_sources_bitmap)) {
		printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
		return;
	}
	for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) {
		clear_bit(irq_source_id, &kvm->arch.vioapic->irq_states[i]);
		if (i >= 16)
			continue;
#ifdef CONFIG_X86
		clear_bit(irq_source_id, &pic_irqchip(kvm)->irq_states[i]);
#endif
	}
	clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
	mutex_unlock(&kvm->irq_lock);
}

void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
				    struct kvm_irq_mask_notifier *kimn)
{
	mutex_lock(&kvm->irq_lock);
	kimn->irq = irq;
	hlist_add_head_rcu(&kimn->link, &kvm->mask_notifier_list);
	mutex_unlock(&kvm->irq_lock);
}

void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
				      struct kvm_irq_mask_notifier *kimn)
{
	mutex_lock(&kvm->irq_lock);
	hlist_del_rcu(&kimn->link);
	mutex_unlock(&kvm->irq_lock);
	synchronize_rcu();
}

void kvm_fire_mask_notifiers(struct kvm *kvm, int irq, bool mask)
{
	struct kvm_irq_mask_notifier *kimn;
	struct hlist_node *n;

	rcu_read_lock();
	hlist_for_each_entry_rcu(kimn, n, &kvm->mask_notifier_list, link)
		if (kimn->irq == irq)
			kimn->func(kimn, mask);
	rcu_read_unlock();
}

void kvm_free_irq_routing(struct kvm *kvm)
{
	/* Called only during vm destruction. Nobody can use the pointer
	   at this stage */
	kfree(kvm->irq_routing);
}

static int setup_routing_entry(struct kvm_irq_routing_table *rt,
			       struct kvm_kernel_irq_routing_entry *e,
			       const struct kvm_irq_routing_entry *ue)
{
	int r = -EINVAL;
	int delta;
	struct kvm_kernel_irq_routing_entry *ei;
	struct hlist_node *n;

	/*
	 * Do not allow GSI to be mapped to the same irqchip more than once.
	 * Allow only one to one mapping between GSI and MSI.
	 */
	hlist_for_each_entry(ei, n, &rt->map[ue->gsi], link)
		if (ei->type == KVM_IRQ_ROUTING_MSI ||
		    ue->u.irqchip.irqchip == ei->irqchip.irqchip)
			return r;

	e->gsi = ue->gsi;
	e->type = ue->type;
	switch (ue->type) {
	case KVM_IRQ_ROUTING_IRQCHIP:
		delta = 0;
		switch (ue->u.irqchip.irqchip) {
		case KVM_IRQCHIP_PIC_MASTER:
			e->set = kvm_set_pic_irq;
			break;
		case KVM_IRQCHIP_PIC_SLAVE:
			e->set = kvm_set_pic_irq;
			delta = 8;
			break;
		case KVM_IRQCHIP_IOAPIC:
			e->set = kvm_set_ioapic_irq;
			break;
		default:
			goto out;
		}
		e->irqchip.irqchip = ue->u.irqchip.irqchip;
		e->irqchip.pin = ue->u.irqchip.pin + delta;
		if (e->irqchip.pin >= KVM_IOAPIC_NUM_PINS)
			goto out;
		rt->chip[ue->u.irqchip.irqchip][e->irqchip.pin] = ue->gsi;
		break;
	case KVM_IRQ_ROUTING_MSI:
		e->set = kvm_set_msi;
		e->msi.address_lo = ue->u.msi.address_lo;
		e->msi.address_hi = ue->u.msi.address_hi;
		e->msi.data = ue->u.msi.data;
		break;
	default:
		goto out;
	}

	hlist_add_head(&e->link, &rt->map[e->gsi]);
	r = 0;
out:
	return r;
}


int kvm_set_irq_routing(struct kvm *kvm,
			const struct kvm_irq_routing_entry *ue,
			unsigned nr,
			unsigned flags)
{
	struct kvm_irq_routing_table *new, *old;
	u32 i, j, nr_rt_entries = 0;
	int r;

	for (i = 0; i < nr; ++i) {
		if (ue[i].gsi >= KVM_MAX_IRQ_ROUTES)
			return -EINVAL;
		nr_rt_entries = max(nr_rt_entries, ue[i].gsi);
	}

	nr_rt_entries += 1;

	new = kzalloc(sizeof(*new) + (nr_rt_entries * sizeof(struct hlist_head))
		      + (nr * sizeof(struct kvm_kernel_irq_routing_entry)),
		      GFP_KERNEL);

	if (!new)
		return -ENOMEM;

	new->rt_entries = (void *)&new->map[nr_rt_entries];

	new->nr_rt_entries = nr_rt_entries;
	for (i = 0; i < 3; i++)
		for (j = 0; j < KVM_IOAPIC_NUM_PINS; j++)
			new->chip[i][j] = -1;

	for (i = 0; i < nr; ++i) {
		r = -EINVAL;
		if (ue->flags)
			goto out;
		r = setup_routing_entry(new, &new->rt_entries[i], ue);
		if (r)
			goto out;
		++ue;
	}

	mutex_lock(&kvm->irq_lock);
	old = kvm->irq_routing;
	rcu_assign_pointer(kvm->irq_routing, new);
	mutex_unlock(&kvm->irq_lock);
	synchronize_rcu();

	new = old;
	r = 0;

out:
	kfree(new);
	return r;
}

#define IOAPIC_ROUTING_ENTRY(irq) \
	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
	  .u.irqchip.irqchip = KVM_IRQCHIP_IOAPIC, .u.irqchip.pin = (irq) }
#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)

#ifdef CONFIG_X86
#  define PIC_ROUTING_ENTRY(irq) \
	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
	  .u.irqchip.irqchip = SELECT_PIC(irq), .u.irqchip.pin = (irq) % 8 }
#  define ROUTING_ENTRY2(irq) \
	IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
#else
#  define ROUTING_ENTRY2(irq) \
	IOAPIC_ROUTING_ENTRY(irq)
#endif

static const struct kvm_irq_routing_entry default_routing[] = {
	ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
	ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
	ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
	ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
	ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
	ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
	ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
	ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
	ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
	ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
	ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
	ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
#ifdef CONFIG_IA64
	ROUTING_ENTRY1(24), ROUTING_ENTRY1(25),
	ROUTING_ENTRY1(26), ROUTING_ENTRY1(27),
	ROUTING_ENTRY1(28), ROUTING_ENTRY1(29),
	ROUTING_ENTRY1(30), ROUTING_ENTRY1(31),
	ROUTING_ENTRY1(32), ROUTING_ENTRY1(33),
	ROUTING_ENTRY1(34), ROUTING_ENTRY1(35),
	ROUTING_ENTRY1(36), ROUTING_ENTRY1(37),
	ROUTING_ENTRY1(38), ROUTING_ENTRY1(39),
	ROUTING_ENTRY1(40), ROUTING_ENTRY1(41),
	ROUTING_ENTRY1(42), ROUTING_ENTRY1(43),
	ROUTING_ENTRY1(44), ROUTING_ENTRY1(45),
	ROUTING_ENTRY1(46), ROUTING_ENTRY1(47),
#endif
};

int kvm_setup_default_irq_routing(struct kvm *kvm)
{
	return kvm_set_irq_routing(kvm, default_routing,
				   ARRAY_SIZE(default_routing), 0);
}
Commit	Line	Data
3de42dc0 XZ	1	/*
	2	* irq_comm.c: Common API for in kernel interrupt controller
	3	* Copyright (c) 2007, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	16	* Place - Suite 330, Boston, MA 02111-1307 USA.
	17	* Authors:
	18	* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
	19	*
	20	*/
	21
	22	#include <linux/kvm_host.h>
229456fc	23	#include <trace/events/kvm.h>
79950e10	24
79950e10	25	#include <asm/msidef.h>
58c2dde1 GN	26	#ifdef CONFIG_IA64
	27	#include <asm/iosapic.h>
	28	#endif
79950e10	29
3de42dc0 XZ	30	#include "irq.h"
	31
	32	#include "ioapic.h"
	33
1a6e4a8c GN	34	static inline int kvm_irq_line_state(unsigned long *irq_state,
	35	int irq_source_id, int level)
	36	{
	37	/* Logical OR for level trig interrupt */
	38	if (level)
	39	set_bit(irq_source_id, irq_state);
	40	else
	41	clear_bit(irq_source_id, irq_state);
	42
	43	return !!(*irq_state);
	44	}
	45
4925663a	46	static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
1a6e4a8c	47	struct kvm *kvm, int irq_source_id, int level)
399ec807 AK	48	{
399ec807 AK	49	#ifdef CONFIG_X86
1a6e4a8c GN	50	struct kvm_pic *pic = pic_irqchip(kvm);
	51	level = kvm_irq_line_state(&pic->irq_states[e->irqchip.pin],
	52	irq_source_id, level);
	53	return kvm_pic_set_irq(pic, e->irqchip.pin, level);
4925663a GN	54	#else
4925663a GN	55	return -1;
399ec807 AK	56	#endif
	57	}
	58
4925663a	59	static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
1a6e4a8c	60	struct kvm *kvm, int irq_source_id, int level)
399ec807	61	{
1a6e4a8c GN	62	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	63	level = kvm_irq_line_state(&ioapic->irq_states[e->irqchip.pin],
	64	irq_source_id, level);
	65
	66	return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, level);
399ec807 AK	67	}
399ec807 AK	68
58c2dde1	69	inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq)
116191b6	70	{
58c2dde1 GN	71	#ifdef CONFIG_IA64
	72	return irq->delivery_mode ==
	73	(IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
	74	#else
	75	return irq->delivery_mode == APIC_DM_LOWEST;
	76	#endif
	77	}
116191b6	78
58c2dde1 GN	79	int kvm_irq_delivery_to_apic(struct kvm kvm, struct kvm_lapic src,
	80	struct kvm_lapic_irq *irq)
	81	{
	82	int i, r = -1;
	83	struct kvm_vcpu vcpu, lowest = NULL;
	84
	85	if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
	86	kvm_is_dm_lowest_prio(irq))
343f94fe GN	87	printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
343f94fe GN	88
988a2cae GN	89	kvm_for_each_vcpu(i, vcpu, kvm) {
988a2cae GN	90	if (!kvm_apic_present(vcpu))
343f94fe GN	91	continue;
343f94fe GN	92
58c2dde1 GN	93	if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
58c2dde1 GN	94	irq->dest_id, irq->dest_mode))
343f94fe GN	95	continue;
343f94fe GN	96
58c2dde1 GN	97	if (!kvm_is_dm_lowest_prio(irq)) {
	98	if (r < 0)
	99	r = 0;
	100	r += kvm_apic_set_irq(vcpu, irq);
e1035715	101	} else {
58c2dde1 GN	102	if (!lowest)
	103	lowest = vcpu;
	104	else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
	105	lowest = vcpu;
e1035715	106	}
343f94fe GN	107	}
343f94fe GN	108
58c2dde1 GN	109	if (lowest)
	110	r = kvm_apic_set_irq(lowest, irq);
	111
	112	return r;
116191b6 SY	113	}
116191b6 SY	114
4925663a	115	static int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
1a6e4a8c	116	struct kvm *kvm, int irq_source_id, int level)
79950e10	117	{
58c2dde1	118	struct kvm_lapic_irq irq;
79950e10	119
1a6e4a8c GN	120	if (!level)
	121	return -1;
	122
1000ff8d GN	123	trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data);
1000ff8d GN	124
58c2dde1	125	irq.dest_id = (e->msi.address_lo &
116191b6	126	MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
58c2dde1	127	irq.vector = (e->msi.data &
116191b6	128	MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
58c2dde1 GN	129	irq.dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
	130	irq.trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
	131	irq.delivery_mode = e->msi.data & 0x700;
	132	irq.level = 1;
	133	irq.shorthand = 0;
116191b6 SY	134
116191b6 SY	135	/* TODO Deal with RH bit of MSI message address */
58c2dde1	136	return kvm_irq_delivery_to_apic(kvm, NULL, &irq);
79950e10 SY	137	}
79950e10 SY	138
680b3648	139	/*
4925663a GN	140	* Return value:
	141	* < 0 Interrupt was ignored (masked or not delivered for other reasons)
	142	* = 0 Interrupt was coalesced (previous irq is still pending)
	143	* > 0 Number of CPUs interrupt was delivered to
	144	*/
46e624b9	145	int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level)
3de42dc0	146	{
eba0226b GN	147	struct kvm_kernel_irq_routing_entry *e, irq_set[KVM_NR_IRQCHIPS];
eba0226b GN	148	int ret = -1, i = 0;
46e624b9 GN	149	struct kvm_irq_routing_table *irq_rt;
46e624b9 GN	150	struct hlist_node *n;
79950e10	151
ae8c1c40	152	trace_kvm_set_irq(irq, level, irq_source_id);
229456fc	153
3de42dc0 XZ	154	/* Not possible to detect if the guest uses the PIC or the
	155	* IOAPIC. So set the bit in both. The guest will ignore
	156	* writes to the unused one.
	157	*/
e42bba90 GN	158	rcu_read_lock();
e42bba90 GN	159	irq_rt = rcu_dereference(kvm->irq_routing);
46e624b9	160	if (irq < irq_rt->nr_rt_entries)
eba0226b GN	161	hlist_for_each_entry(e, n, &irq_rt->map[irq], link)
eba0226b GN	162	irq_set[i++] = *e;
e42bba90	163	rcu_read_unlock();
eba0226b GN	164
	165	while(i--) {
	166	int r;
	167	r = irq_set[i].set(&irq_set[i], kvm, irq_source_id, level);
	168	if (r < 0)
	169	continue;
	170
	171	ret = r + ((ret < 0) ? 0 : ret);
	172	}
	173
4925663a	174	return ret;
3de42dc0 XZ	175	}
3de42dc0 XZ	176
44882eed	177	void kvm_notify_acked_irq(struct kvm *kvm, unsigned irqchip, unsigned pin)
3de42dc0 XZ	178	{
	179	struct kvm_irq_ack_notifier *kian;
	180	struct hlist_node *n;
3e71f88b	181	int gsi;
44882eed	182
229456fc MT	183	trace_kvm_ack_irq(irqchip, pin);
229456fc MT	184
e42bba90 GN	185	rcu_read_lock();
e42bba90 GN	186	gsi = rcu_dereference(kvm->irq_routing)->chip[irqchip][pin];
3e71f88b	187	if (gsi != -1)
280aa177 GN	188	hlist_for_each_entry_rcu(kian, n, &kvm->irq_ack_notifier_list,
280aa177 GN	189	link)
3e71f88b GN	190	if (kian->gsi == gsi)
3e71f88b GN	191	kian->irq_acked(kian);
280aa177	192	rcu_read_unlock();
3de42dc0 XZ	193	}
	194
	195	void kvm_register_irq_ack_notifier(struct kvm *kvm,
	196	struct kvm_irq_ack_notifier *kian)
	197	{
fa40a821	198	mutex_lock(&kvm->irq_lock);
280aa177	199	hlist_add_head_rcu(&kian->link, &kvm->irq_ack_notifier_list);
fa40a821	200	mutex_unlock(&kvm->irq_lock);
3de42dc0 XZ	201	}
3de42dc0 XZ	202
fa40a821 MT	203	void kvm_unregister_irq_ack_notifier(struct kvm *kvm,
fa40a821 MT	204	struct kvm_irq_ack_notifier *kian)
3de42dc0	205	{
fa40a821	206	mutex_lock(&kvm->irq_lock);
280aa177	207	hlist_del_init_rcu(&kian->link);
fa40a821	208	mutex_unlock(&kvm->irq_lock);
280aa177	209	synchronize_rcu();
3de42dc0	210	}
5550af4d	211
5550af4d SY	212	int kvm_request_irq_source_id(struct kvm *kvm)
	213	{
	214	unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
fa40a821 MT	215	int irq_source_id;
	216
	217	mutex_lock(&kvm->irq_lock);
	218	irq_source_id = find_first_zero_bit(bitmap,
5550af4d	219	sizeof(kvm->arch.irq_sources_bitmap));
61552367	220
5550af4d SY	221	if (irq_source_id >= sizeof(kvm->arch.irq_sources_bitmap)) {
5550af4d SY	222	printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
61552367 MM	223	return -EFAULT;
	224	}
	225
	226	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
	227	set_bit(irq_source_id, bitmap);
fa40a821	228	mutex_unlock(&kvm->irq_lock);
61552367	229
5550af4d SY	230	return irq_source_id;
	231	}
	232
	233	void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
	234	{
	235	int i;
	236
61552367 MM	237	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
61552367 MM	238
fa40a821	239	mutex_lock(&kvm->irq_lock);
61552367	240	if (irq_source_id < 0 \|\|
5550af4d SY	241	irq_source_id >= sizeof(kvm->arch.irq_sources_bitmap)) {
	242	printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
	243	return;
	244	}
1a6e4a8c GN	245	for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) {
	246	clear_bit(irq_source_id, &kvm->arch.vioapic->irq_states[i]);
	247	if (i >= 16)
	248	continue;
	249	#ifdef CONFIG_X86
	250	clear_bit(irq_source_id, &pic_irqchip(kvm)->irq_states[i]);
	251	#endif
	252	}
5550af4d	253	clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
fa40a821	254	mutex_unlock(&kvm->irq_lock);
5550af4d	255	}
75858a84 AK	256
	257	void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
	258	struct kvm_irq_mask_notifier *kimn)
	259	{
fa40a821	260	mutex_lock(&kvm->irq_lock);
75858a84	261	kimn->irq = irq;
280aa177	262	hlist_add_head_rcu(&kimn->link, &kvm->mask_notifier_list);
fa40a821	263	mutex_unlock(&kvm->irq_lock);
75858a84 AK	264	}
	265
	266	void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
	267	struct kvm_irq_mask_notifier *kimn)
	268	{
fa40a821	269	mutex_lock(&kvm->irq_lock);
280aa177	270	hlist_del_rcu(&kimn->link);
fa40a821	271	mutex_unlock(&kvm->irq_lock);
280aa177	272	synchronize_rcu();
75858a84 AK	273	}
	274
	275	void kvm_fire_mask_notifiers(struct kvm *kvm, int irq, bool mask)
	276	{
	277	struct kvm_irq_mask_notifier *kimn;
	278	struct hlist_node *n;
	279
280aa177 GN	280	rcu_read_lock();
280aa177 GN	281	hlist_for_each_entry_rcu(kimn, n, &kvm->mask_notifier_list, link)
75858a84 AK	282	if (kimn->irq == irq)
75858a84 AK	283	kimn->func(kimn, mask);
280aa177	284	rcu_read_unlock();
75858a84 AK	285	}
75858a84 AK	286
399ec807 AK	287	void kvm_free_irq_routing(struct kvm *kvm)
399ec807 AK	288	{
e42bba90 GN	289	/* Called only during vm destruction. Nobody can use the pointer
e42bba90 GN	290	at this stage */
46e624b9	291	kfree(kvm->irq_routing);
399ec807 AK	292	}
399ec807 AK	293
46e624b9 GN	294	static int setup_routing_entry(struct kvm_irq_routing_table *rt,
46e624b9 GN	295	struct kvm_kernel_irq_routing_entry *e,
cded19f3	296	const struct kvm_irq_routing_entry *ue)
399ec807 AK	297	{
	298	int r = -EINVAL;
	299	int delta;
46e624b9 GN	300	struct kvm_kernel_irq_routing_entry *ei;
	301	struct hlist_node *n;
	302
	303	/*
	304	* Do not allow GSI to be mapped to the same irqchip more than once.
	305	* Allow only one to one mapping between GSI and MSI.
	306	*/
	307	hlist_for_each_entry(ei, n, &rt->map[ue->gsi], link)
	308	if (ei->type == KVM_IRQ_ROUTING_MSI \|\|
	309	ue->u.irqchip.irqchip == ei->irqchip.irqchip)
	310	return r;
399ec807 AK	311
399ec807 AK	312	e->gsi = ue->gsi;
5116d8f6	313	e->type = ue->type;
399ec807 AK	314	switch (ue->type) {
	315	case KVM_IRQ_ROUTING_IRQCHIP:
	316	delta = 0;
	317	switch (ue->u.irqchip.irqchip) {
	318	case KVM_IRQCHIP_PIC_MASTER:
	319	e->set = kvm_set_pic_irq;
	320	break;
	321	case KVM_IRQCHIP_PIC_SLAVE:
4925663a	322	e->set = kvm_set_pic_irq;
399ec807 AK	323	delta = 8;
	324	break;
	325	case KVM_IRQCHIP_IOAPIC:
efbc100c	326	e->set = kvm_set_ioapic_irq;
399ec807 AK	327	break;
	328	default:
	329	goto out;
	330	}
	331	e->irqchip.irqchip = ue->u.irqchip.irqchip;
	332	e->irqchip.pin = ue->u.irqchip.pin + delta;
3e71f88b GN	333	if (e->irqchip.pin >= KVM_IOAPIC_NUM_PINS)
	334	goto out;
	335	rt->chip[ue->u.irqchip.irqchip][e->irqchip.pin] = ue->gsi;
399ec807	336	break;
79950e10 SY	337	case KVM_IRQ_ROUTING_MSI:
	338	e->set = kvm_set_msi;
	339	e->msi.address_lo = ue->u.msi.address_lo;
	340	e->msi.address_hi = ue->u.msi.address_hi;
	341	e->msi.data = ue->u.msi.data;
	342	break;
399ec807 AK	343	default:
	344	goto out;
	345	}
46e624b9 GN	346
46e624b9 GN	347	hlist_add_head(&e->link, &rt->map[e->gsi]);
399ec807 AK	348	r = 0;
	349	out:
	350	return r;
	351	}
	352
	353
	354	int kvm_set_irq_routing(struct kvm *kvm,
	355	const struct kvm_irq_routing_entry *ue,
	356	unsigned nr,
	357	unsigned flags)
	358	{
46e624b9	359	struct kvm_irq_routing_table new, old;
3e71f88b	360	u32 i, j, nr_rt_entries = 0;
399ec807 AK	361	int r;
399ec807 AK	362
46e624b9 GN	363	for (i = 0; i < nr; ++i) {
	364	if (ue[i].gsi >= KVM_MAX_IRQ_ROUTES)
	365	return -EINVAL;
	366	nr_rt_entries = max(nr_rt_entries, ue[i].gsi);
	367	}
	368
	369	nr_rt_entries += 1;
	370
	371	new = kzalloc(sizeof(new) + (nr_rt_entries sizeof(struct hlist_head))
	372	+ (nr * sizeof(struct kvm_kernel_irq_routing_entry)),
	373	GFP_KERNEL);
	374
	375	if (!new)
	376	return -ENOMEM;
	377
	378	new->rt_entries = (void *)&new->map[nr_rt_entries];
	379
	380	new->nr_rt_entries = nr_rt_entries;
3e71f88b GN	381	for (i = 0; i < 3; i++)
	382	for (j = 0; j < KVM_IOAPIC_NUM_PINS; j++)
	383	new->chip[i][j] = -1;
46e624b9	384
399ec807 AK	385	for (i = 0; i < nr; ++i) {
399ec807 AK	386	r = -EINVAL;
399ec807 AK	387	if (ue->flags)
399ec807 AK	388	goto out;
46e624b9	389	r = setup_routing_entry(new, &new->rt_entries[i], ue);
399ec807 AK	390	if (r)
	391	goto out;
	392	++ue;
399ec807 AK	393	}
399ec807 AK	394
fa40a821	395	mutex_lock(&kvm->irq_lock);
46e624b9	396	old = kvm->irq_routing;
e42bba90	397	rcu_assign_pointer(kvm->irq_routing, new);
fa40a821	398	mutex_unlock(&kvm->irq_lock);
e42bba90	399	synchronize_rcu();
399ec807	400
46e624b9	401	new = old;
399ec807 AK	402	r = 0;
	403
	404	out:
46e624b9	405	kfree(new);
399ec807 AK	406	return r;
	407	}
	408
	409	#define IOAPIC_ROUTING_ENTRY(irq) \
	410	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
	411	.u.irqchip.irqchip = KVM_IRQCHIP_IOAPIC, .u.irqchip.pin = (irq) }
	412	#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)
	413
	414	#ifdef CONFIG_X86
399ec807 AK	415	# define PIC_ROUTING_ENTRY(irq) \
	416	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
	417	.u.irqchip.irqchip = SELECT_PIC(irq), .u.irqchip.pin = (irq) % 8 }
	418	# define ROUTING_ENTRY2(irq) \
	419	IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
	420	#else
	421	# define ROUTING_ENTRY2(irq) \
	422	IOAPIC_ROUTING_ENTRY(irq)
	423	#endif
	424
	425	static const struct kvm_irq_routing_entry default_routing[] = {
	426	ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
	427	ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
	428	ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
	429	ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
	430	ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
	431	ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
	432	ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
	433	ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
	434	ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
	435	ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
	436	ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
	437	ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
	438	#ifdef CONFIG_IA64
	439	ROUTING_ENTRY1(24), ROUTING_ENTRY1(25),
	440	ROUTING_ENTRY1(26), ROUTING_ENTRY1(27),
	441	ROUTING_ENTRY1(28), ROUTING_ENTRY1(29),
	442	ROUTING_ENTRY1(30), ROUTING_ENTRY1(31),
	443	ROUTING_ENTRY1(32), ROUTING_ENTRY1(33),
	444	ROUTING_ENTRY1(34), ROUTING_ENTRY1(35),
	445	ROUTING_ENTRY1(36), ROUTING_ENTRY1(37),
	446	ROUTING_ENTRY1(38), ROUTING_ENTRY1(39),
	447	ROUTING_ENTRY1(40), ROUTING_ENTRY1(41),
	448	ROUTING_ENTRY1(42), ROUTING_ENTRY1(43),
	449	ROUTING_ENTRY1(44), ROUTING_ENTRY1(45),
	450	ROUTING_ENTRY1(46), ROUTING_ENTRY1(47),
	451	#endif
	452	};
	453
	454	int kvm_setup_default_irq_routing(struct kvm *kvm)
	455	{
	456	return kvm_set_irq_routing(kvm, default_routing,
	457	ARRAY_SIZE(default_routing), 0);
	458	}