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[ALSA] sparc dbri: removal of unused struct members
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / sparc / dbri.c
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1bd9debf
TI		 1/*
2 * Driver for DBRI sound chip found on Sparcs.
4338829e 3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
1bd9debf
TI		 4 *
5 * Based entirely upon drivers/sbus/audio/dbri.c which is:
6 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
7 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
8 *
9 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
10 * on Sun SPARCstation 10, 20, LX and Voyager models.
11 *
12 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
13 * data time multiplexer with ISDN support (aka T7259)
14 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
15 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
16 * Documentation:
17 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
18 * Sparc Technology Business (courtesy of Sun Support)
19 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
20 * available from the Lucent (formarly AT&T microelectronics) home
21 * page.
22 * - http://www.freesoft.org/Linux/DBRI/
23 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
24 * Interfaces: CHI, Audio In & Out, 2 bits parallel
25 * Documentation: from the Crystal Semiconductor home page.
26 *
27 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
28 * memory and a serial device (long pipes, nr 0-15) or between two serial
29 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
30 * device (short pipes).
31 * A timeslot defines the bit-offset and nr of bits read from a serial device.
32 * The timeslots are linked to 6 circular lists, one for each direction for
33 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
34 * (the second one is a monitor/tee pipe, valid only for serial input).
35 *
36 * The mmcodec is connected via the CHI bus and needs the data & some
5fc3a2b2 37 * parameters (volume, output selection) timemultiplexed in 8 byte
1bd9debf
TI		 38 * chunks. It also has a control mode, which serves for audio format setting.
39 *
40 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
41 * the same CHI bus, so I thought perhaps it is possible to use the onboard
42 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
43 * audio devices. But the SUN HW group decided against it, at least on my
44 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
45 * connected.
4338829e
MH		 46 *
47 * I've tried to stick to the following function naming conventions:
48 * snd_* ALSA stuff
d254c8f7 49 * cs4215_* CS4215 codec specific stuff
4338829e
MH		 50 * dbri_* DBRI high-level stuff
51 * other DBRI low-level stuff
1bd9debf
TI		 52 */
53
54#include <sound/driver.h>
55#include <linux/interrupt.h>
56#include <linux/delay.h>
57
58#include <sound/core.h>
59#include <sound/pcm.h>
60#include <sound/pcm_params.h>
61#include <sound/info.h>
62#include <sound/control.h>
63#include <sound/initval.h>
64
65#include <asm/irq.h>
66#include <asm/io.h>
67#include <asm/sbus.h>
68#include <asm/atomic.h>
69
70MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
71MODULE_DESCRIPTION("Sun DBRI");
72MODULE_LICENSE("GPL");
73MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
74
75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
78
79module_param_array(index, int, NULL, 0444);
80MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
81module_param_array(id, charp, NULL, 0444);
82MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
83module_param_array(enable, bool, NULL, 0444);
84MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
85
86#define DBRI_DEBUG
87
88#define D_INT (1<<0)
89#define D_GEN (1<<1)
90#define D_CMD (1<<2)
91#define D_MM (1<<3)
92#define D_USR (1<<4)
93#define D_DESC (1<<5)
94
6581f4e7 95static int dbri_debug;
4338829e 96module_param(dbri_debug, int, 0644);
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TI		 97MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
98
99#ifdef DBRI_DEBUG
100static char *cmds[] = {
101 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
102 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
103};
104
105#define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x)
106
1bd9debf
TI		 107#else
108#define dprintk(a, x...)
109
1bd9debf
TI		 110#endif /* DBRI_DEBUG */
111
42fe7647
KH		 112#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
113 (intr << 27) | \
114 value)
115
1bd9debf
TI		 116/***************************************************************************
117 CS4215 specific definitions and structures
118****************************************************************************/
119
120struct cs4215 {
121 __u8 data[4]; /* Data mode: Time slots 5-8 */
122 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
123 __u8 onboard;
124 __u8 offset; /* Bit offset from frame sync to time slot 1 */
125 volatile __u32 status;
126 volatile __u32 version;
127 __u8 precision; /* In bits, either 8 or 16 */
128 __u8 channels; /* 1 or 2 */
129};
130
131/*
132 * Control mode first
133 */
134
135/* Time Slot 1, Status register */
136#define CS4215_CLB (1<<2) /* Control Latch Bit */
137#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
138 /* 0: line: 2.8V, speaker 8V */
139#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
140#define CS4215_RSRVD_1 (1<<5)
141
142/* Time Slot 2, Data Format Register */
143#define CS4215_DFR_LINEAR16 0
144#define CS4215_DFR_ULAW 1
145#define CS4215_DFR_ALAW 2
146#define CS4215_DFR_LINEAR8 3
147#define CS4215_DFR_STEREO (1<<2)
148static struct {
149 unsigned short freq;
150 unsigned char xtal;
151 unsigned char csval;
152} CS4215_FREQ[] = {
153 { 8000, (1 << 4), (0 << 3) },
154 { 16000, (1 << 4), (1 << 3) },
155 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
156 { 32000, (1 << 4), (3 << 3) },
157 /* { NA, (1 << 4), (4 << 3) }, */
158 /* { NA, (1 << 4), (5 << 3) }, */
159 { 48000, (1 << 4), (6 << 3) },
160 { 9600, (1 << 4), (7 << 3) },
161 { 5513, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
162 { 11025, (2 << 4), (1 << 3) },
163 { 18900, (2 << 4), (2 << 3) },
164 { 22050, (2 << 4), (3 << 3) },
165 { 37800, (2 << 4), (4 << 3) },
166 { 44100, (2 << 4), (5 << 3) },
167 { 33075, (2 << 4), (6 << 3) },
168 { 6615, (2 << 4), (7 << 3) },
169 { 0, 0, 0}
170};
171
172#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
173
174#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
175
176/* Time Slot 3, Serial Port Control register */
177#define CS4215_XEN (1<<0) /* 0: Enable serial output */
178#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
179#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
180#define CS4215_BSEL_128 (1<<2)
181#define CS4215_BSEL_256 (2<<2)
182#define CS4215_MCK_MAST (0<<4) /* Master clock */
183#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
184#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
185#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
186#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
187
188/* Time Slot 4, Test Register */
189#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
190#define CS4215_ENL (1<<1) /* Enable Loopback Testing */
191
192/* Time Slot 5, Parallel Port Register */
193/* Read only here and the same as the in data mode */
194
195/* Time Slot 6, Reserved */
196
197/* Time Slot 7, Version Register */
198#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
199
200/* Time Slot 8, Reserved */
201
202/*
203 * Data mode
204 */
205/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
206
207/* Time Slot 5, Output Setting */
208#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
209#define CS4215_LE (1<<6) /* Line Out Enable */
210#define CS4215_HE (1<<7) /* Headphone Enable */
211
212/* Time Slot 6, Output Setting */
213#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
214#define CS4215_SE (1<<6) /* Speaker Enable */
215#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
216
217/* Time Slot 7, Input Setting */
218#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
219#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
220#define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */
221#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
222#define CS4215_PIO1 (1<<7)
223
224/* Time Slot 8, Input Setting */
225#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
226#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
227
228/***************************************************************************
229 DBRI specific definitions and structures
230****************************************************************************/
231
232/* DBRI main registers */
233#define REG0 0x00UL /* Status and Control */
234#define REG1 0x04UL /* Mode and Interrupt */
235#define REG2 0x08UL /* Parallel IO */
236#define REG3 0x0cUL /* Test */
237#define REG8 0x20UL /* Command Queue Pointer */
238#define REG9 0x24UL /* Interrupt Queue Pointer */
239
240#define DBRI_NO_CMDS 64
1bd9debf
TI		 241#define DBRI_INT_BLK 64
242#define DBRI_NO_DESCS 64
243#define DBRI_NO_PIPES 32
244
245#define DBRI_MM_ONB 1
246#define DBRI_MM_SB 2
247
248#define DBRI_REC 0
249#define DBRI_PLAY 1
250#define DBRI_NO_STREAMS 2
251
252/* One transmit/receive descriptor */
253struct dbri_mem {
254 volatile __u32 word1;
255 volatile __u32 ba; /* Transmit/Receive Buffer Address */
256 volatile __u32 nda; /* Next Descriptor Address */
257 volatile __u32 word4;
258};
259
260/* This structure is in a DMA region where it can accessed by both
261 * the CPU and the DBRI
262 */
263struct dbri_dma {
264 volatile s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
6fb98280 265 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
1bd9debf
TI		 266 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
267};
268
269#define dbri_dma_off(member, elem) \
270 ((u32)(unsigned long) \
271 (&(((struct dbri_dma *)0)->member[elem])))
272
273enum in_or_out { PIPEinput, PIPEoutput };
274
275struct dbri_pipe {
276 u32 sdp; /* SDP command word */
1bd9debf 277 int nextpipe; /* Next pipe in linked list */
1bd9debf
TI		 278 int cycle; /* Offset of timeslot (bits) */
279 int length; /* Length of timeslot (bits) */
280 int first_desc; /* Index of first descriptor */
281 int desc; /* Index of active descriptor */
282 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
283};
284
285struct dbri_desc {
286 int inuse; /* Boolean flag */
287 int next; /* Index of next desc, or -1 */
288 unsigned int len;
289};
290
291/* Per stream (playback or record) information */
475675d6
TI		 292struct dbri_streaminfo {
293 struct snd_pcm_substream *substream;
1bd9debf
TI		 294 u32 dvma_buffer; /* Device view of Alsa DMA buffer */
295 int left; /* # of bytes left in DMA buffer */
296 int size; /* Size of DMA buffer */
297 size_t offset; /* offset in user buffer */
298 int pipe; /* Data pipe used */
299 int left_gain; /* mixer elements */
300 int right_gain;
475675d6 301};
1bd9debf
TI		 302
303/* This structure holds the information for both chips (DBRI & CS4215) */
475675d6
TI		 304struct snd_dbri {
305 struct snd_card *card; /* ALSA card */
1bd9debf
TI		 306
307 int regs_size, irq; /* Needed for unload */
308 struct sbus_dev *sdev; /* SBUS device info */
309 spinlock_t lock;
310
311 volatile struct dbri_dma *dma; /* Pointer to our DMA block */
312 u32 dma_dvma; /* DBRI visible DMA address */
313
314 void __iomem *regs; /* dbri HW regs */
1bd9debf 315 int dbri_irqp; /* intr queue pointer */
4338829e
MH		 316 int wait_send; /* sequence of command buffers send */
317 int wait_ackd; /* sequence of command buffers acknowledged */
1bd9debf
TI		 318
319 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
320 struct dbri_desc descs[DBRI_NO_DESCS];
321
322 int chi_in_pipe;
323 int chi_out_pipe;
324 int chi_bpf;
325
326 struct cs4215 mm; /* mmcodec special info */
327 /* per stream (playback/record) info */
328 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
329
330 struct snd_dbri *next;
475675d6 331};
1bd9debf 332
1bd9debf
TI		 333#define DBRI_MAX_VOLUME 63 /* Output volume */
334#define DBRI_MAX_GAIN 15 /* Input gain */
1bd9debf
TI		 335
336/* DBRI Reg0 - Status Control Register - defines. (Page 17) */
337#define D_P (1<<15) /* Program command & queue pointer valid */
338#define D_G (1<<14) /* Allow 4-Word SBus Burst */
339#define D_S (1<<13) /* Allow 16-Word SBus Burst */
340#define D_E (1<<12) /* Allow 8-Word SBus Burst */
341#define D_X (1<<7) /* Sanity Timer Disable */
342#define D_T (1<<6) /* Permit activation of the TE interface */
343#define D_N (1<<5) /* Permit activation of the NT interface */
344#define D_C (1<<4) /* Permit activation of the CHI interface */
345#define D_F (1<<3) /* Force Sanity Timer Time-Out */
346#define D_D (1<<2) /* Disable Master Mode */
347#define D_H (1<<1) /* Halt for Analysis */
348#define D_R (1<<0) /* Soft Reset */
349
350/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
351#define D_LITTLE_END (1<<8) /* Byte Order */
352#define D_BIG_END (0<<8) /* Byte Order */
353#define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */
354#define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */
355#define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */
356#define D_MBE (1<<1) /* Burst Error on SBus (readonly) */
357#define D_IR (1<<0) /* Interrupt Indicator (readonly) */
358
359/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
360#define D_ENPIO3 (1<<7) /* Enable Pin 3 */
361#define D_ENPIO2 (1<<6) /* Enable Pin 2 */
362#define D_ENPIO1 (1<<5) /* Enable Pin 1 */
363#define D_ENPIO0 (1<<4) /* Enable Pin 0 */
364#define D_ENPIO (0xf0) /* Enable all the pins */
365#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
366#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
367#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
368#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
369
370/* DBRI Commands (Page 20) */
371#define D_WAIT 0x0 /* Stop execution */
372#define D_PAUSE 0x1 /* Flush long pipes */
373#define D_JUMP 0x2 /* New command queue */
374#define D_IIQ 0x3 /* Initialize Interrupt Queue */
375#define D_REX 0x4 /* Report command execution via interrupt */
376#define D_SDP 0x5 /* Setup Data Pipe */
377#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
378#define D_DTS 0x7 /* Define Time Slot */
379#define D_SSP 0x8 /* Set short Data Pipe */
380#define D_CHI 0x9 /* Set CHI Global Mode */
381#define D_NT 0xa /* NT Command */
382#define D_TE 0xb /* TE Command */
383#define D_CDEC 0xc /* Codec setup */
384#define D_TEST 0xd /* No comment */
385#define D_CDM 0xe /* CHI Data mode command */
386
387/* Special bits for some commands */
388#define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
389
390/* Setup Data Pipe */
391/* IRM */
392#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */
393#define D_SDP_CHANGE (2<<18) /* Report any changes */
394#define D_SDP_EVERY (3<<18) /* Report any changes */
395#define D_SDP_EOL (1<<17) /* EOL interrupt enable */
396#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
397
398/* Pipe data MODE */
399#define D_SDP_MEM (0<<13) /* To/from memory */
400#define D_SDP_HDLC (2<<13)
401#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
402#define D_SDP_SER (4<<13) /* Serial to serial */
403#define D_SDP_FIXED (6<<13) /* Short only */
404#define D_SDP_MODE(v) ((v)&(7<<13))
405
406#define D_SDP_TO_SER (1<<12) /* Direction */
407#define D_SDP_FROM_SER (0<<12) /* Direction */
408#define D_SDP_MSB (1<<11) /* Bit order within Byte */
409#define D_SDP_LSB (0<<11) /* Bit order within Byte */
410#define D_SDP_P (1<<10) /* Pointer Valid */
411#define D_SDP_A (1<<8) /* Abort */
412#define D_SDP_C (1<<7) /* Clear */
413
414/* Define Time Slot */
415#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
416#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
417#define D_DTS_INS (1<<15) /* Insert Time Slot */
418#define D_DTS_DEL (0<<15) /* Delete Time Slot */
419#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
420#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
421
422/* Time Slot defines */
423#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
424#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
425#define D_TS_DI (1<<13) /* Data Invert */
426#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
427#define D_TS_MONITOR (2<<10) /* Monitor pipe */
428#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
429#define D_TS_ANCHOR (7<<10) /* Starting short pipes */
430#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
431#define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
432
433/* Concentration Highway Interface Modes */
434#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
435#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
436#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
437#define D_CHI_OD (1<<13) /* Open Drain Enable */
438#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
439#define D_CHI_FD (1<<11) /* Frame Drive */
440#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
441
442/* NT: These are here for completeness */
443#define D_NT_FBIT (1<<17) /* Frame Bit */
444#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
445#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
446#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
447#define D_NT_ISNT (1<<13) /* Configfure interface as NT */
448#define D_NT_FT (1<<12) /* Fixed Timing */
449#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
450#define D_NT_IFA (1<<10) /* Inhibit Final Activation */
451#define D_NT_ACT (1<<9) /* Activate Interface */
452#define D_NT_MFE (1<<8) /* Multiframe Enable */
453#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
454#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
455#define D_NT_FACT (1<<1) /* Force Activation */
456#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
457
458/* Codec Setup */
459#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
460#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
461#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
462
463/* Test */
464#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
465#define D_TEST_SIZE(v) ((v)<<11) /* */
466#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
467#define D_TEST_PROC 0x6 /* MicroProcessor test */
468#define D_TEST_SER 0x7 /* Serial-Controller test */
469#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
470#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
471#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
472#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
473#define D_TEST_DUMP 0xe /* ROM Dump */
474
475/* CHI Data Mode */
476#define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */
477#define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */
478#define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */
479#define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */
480#define D_CDM_XEN (1<<1) /* Transmit Highway Enable */
481#define D_CDM_REN (1<<0) /* Receive Highway Enable */
482
483/* The Interrupts */
484#define D_INTR_BRDY 1 /* Buffer Ready for processing */
485#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
486#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
487#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
488#define D_INTR_EOL 5 /* End of List */
489#define D_INTR_CMDI 6 /* Command has bean read */
490#define D_INTR_XCMP 8 /* Transmission of frame complete */
491#define D_INTR_SBRI 9 /* BRI status change info */
492#define D_INTR_FXDT 10 /* Fixed data change */
493#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
494#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
495#define D_INTR_DBYT 12 /* Dropped by frame slip */
496#define D_INTR_RBYT 13 /* Repeated by frame slip */
497#define D_INTR_LINT 14 /* Lost Interrupt */
498#define D_INTR_UNDR 15 /* DMA underrun */
499
500#define D_INTR_TE 32
501#define D_INTR_NT 34
502#define D_INTR_CHI 36
503#define D_INTR_CMD 38
504
505#define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f)
506#define D_INTR_GETCODE(v) (((v)>>20) & 0xf)
507#define D_INTR_GETCMD(v) (((v)>>16) & 0xf)
508#define D_INTR_GETVAL(v) ((v) & 0xffff)
509#define D_INTR_GETRVAL(v) ((v) & 0xfffff)
510
511#define D_P_0 0 /* TE receive anchor */
512#define D_P_1 1 /* TE transmit anchor */
513#define D_P_2 2 /* NT transmit anchor */
514#define D_P_3 3 /* NT receive anchor */
515#define D_P_4 4 /* CHI send data */
516#define D_P_5 5 /* CHI receive data */
517#define D_P_6 6 /* */
518#define D_P_7 7 /* */
519#define D_P_8 8 /* */
520#define D_P_9 9 /* */
521#define D_P_10 10 /* */
522#define D_P_11 11 /* */
523#define D_P_12 12 /* */
524#define D_P_13 13 /* */
525#define D_P_14 14 /* */
526#define D_P_15 15 /* */
527#define D_P_16 16 /* CHI anchor pipe */
528#define D_P_17 17 /* CHI send */
529#define D_P_18 18 /* CHI receive */
530#define D_P_19 19 /* CHI receive */
531#define D_P_20 20 /* CHI receive */
532#define D_P_21 21 /* */
533#define D_P_22 22 /* */
534#define D_P_23 23 /* */
535#define D_P_24 24 /* */
536#define D_P_25 25 /* */
537#define D_P_26 26 /* */
538#define D_P_27 27 /* */
539#define D_P_28 28 /* */
540#define D_P_29 29 /* */
541#define D_P_30 30 /* */
542#define D_P_31 31 /* */
543
544/* Transmit descriptor defines */
545#define DBRI_TD_F (1<<31) /* End of Frame */
546#define DBRI_TD_D (1<<30) /* Do not append CRC */
547#define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */
548#define DBRI_TD_B (1<<15) /* Final interrupt */
549#define DBRI_TD_M (1<<14) /* Marker interrupt */
550#define DBRI_TD_I (1<<13) /* Transmit Idle Characters */
551#define DBRI_TD_FCNT(v) (v) /* Flag Count */
552#define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */
553#define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */
554#define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */
555#define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */
556 /* Maximum buffer size per TD: almost 8Kb */
557#define DBRI_TD_MAXCNT ((1 << 13) - 1)
558
559/* Receive descriptor defines */
560#define DBRI_RD_F (1<<31) /* End of Frame */
561#define DBRI_RD_C (1<<30) /* Completed buffer */
562#define DBRI_RD_B (1<<15) /* Final interrupt */
563#define DBRI_RD_M (1<<14) /* Marker interrupt */
564#define DBRI_RD_BCNT(v) (v) /* Buffer size */
565#define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */
566#define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */
567#define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */
568#define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */
569#define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */
570#define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */
571
572/* stream_info[] access */
573/* Translate the ALSA direction into the array index */
574#define DBRI_STREAMNO(substream) \
575 (substream->stream == \
576 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC)
577
578/* Return a pointer to dbri_streaminfo */
579#define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)]
580
6581f4e7 581static struct snd_dbri *dbri_list; /* All DBRI devices */
1bd9debf
TI		 582
583/*
584 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
585 * So we have to reverse the bits. Note: not all bit lengths are supported
586 */
587static __u32 reverse_bytes(__u32 b, int len)
588{
589 switch (len) {
590 case 32:
591 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
592 case 16:
593 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
594 case 8:
595 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
596 case 4:
597 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
598 case 2:
599 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
600 case 1:
601 case 0:
602 break;
603 default:
604 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
605 };
606
607 return b;
608}
609
610/*
611****************************************************************************
612************** DBRI initialization and command synchronization *************
613****************************************************************************
614
615Commands are sent to the DBRI by building a list of them in memory,
616then writing the address of the first list item to DBRI register 8.
4338829e
MH		 617The list is terminated with a WAIT command, which generates a
618CPU interrupt to signal completion.
1bd9debf
TI		 619
620Since the DBRI can run in parallel with the CPU, several means of
4338829e
MH		 621synchronization present themselves. The method implemented here is close
622to the original scheme (Rudolf's), and uses 2 counters (wait_send and
623wait_ackd) to synchronize the command buffer between the CPU and the DBRI.
1bd9debf
TI		 624
625A more sophisticated scheme might involve a circular command buffer
626or an array of command buffers. A routine could fill one with
627commands and link it onto a list. When a interrupt signaled
628completion of the current command buffer, look on the list for
629the next one.
630
1bd9debf
TI		 631Every time a routine wants to write commands to the DBRI, it must
632first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd
4338829e
MH		 633in return. dbri_cmdlock() will block if the previous commands have not
634been completed yet. After this the commands can be written to the buffer,
635and dbri_cmdsend() is called with the final pointer value to send them
636to the DBRI.
1bd9debf
TI		 637
638*/
639
475675d6 640static void dbri_process_interrupt_buffer(struct snd_dbri * dbri);
4338829e 641
475675d6 642enum dbri_lock { NoGetLock, GetLock };
4338829e 643#define MAXLOOPS 10
1bd9debf 644
475675d6 645static volatile s32 *dbri_cmdlock(struct snd_dbri * dbri, enum dbri_lock get)
1bd9debf 646{
4338829e
MH		 647 int maxloops = MAXLOOPS;
648
1bd9debf
TI		 649#ifndef SMP
650 if ((get == GetLock) && spin_is_locked(&dbri->lock)) {
651 printk(KERN_ERR "DBRI: cmdlock called while in spinlock.");
652 }
653#endif
654
4338829e
MH		 655 /* Delay if previous commands are still being processed */
656 while ((--maxloops) > 0 && (dbri->wait_send != dbri->wait_ackd)) {
657 msleep_interruptible(1);
658 /* If dbri_cmdlock() got called from inside the
659 * interrupt handler, this will do the processing.
660 */
661 dbri_process_interrupt_buffer(dbri);
662 }
663 if (maxloops == 0) {
664 printk(KERN_ERR "DBRI: Chip never completed command buffer %d\n",
665 dbri->wait_send);
666 } else {
667 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
668 MAXLOOPS - maxloops - 1);
669 }
670
1bd9debf
TI		 671 /*if (get == GetLock) spin_lock(&dbri->lock); */
672 return &dbri->dma->cmd[0];
673}
674
475675d6 675static void dbri_cmdsend(struct snd_dbri * dbri, volatile s32 * cmd)
1bd9debf 676{
1bd9debf
TI		 677 volatile s32 *ptr;
678
679 for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) {
680 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
681 }
682
683 if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS - 1) {
4338829e 684 printk(KERN_ERR "DBRI: Command buffer overflow! (bug in driver)\n");
1bd9debf
TI		 685 /* Ignore the last part. */
686 cmd = &dbri->dma->cmd[DBRI_NO_CMDS - 3];
687 }
688
4338829e
MH		 689 dbri->wait_send++;
690 dbri->wait_send &= 0xffff; /* restrict it to a 16 bit counter. */
1bd9debf 691 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
4338829e
MH		 692 *(cmd++) = DBRI_CMD(D_WAIT, 1, dbri->wait_send);
693
694 /* Set command pointer and signal it is valid. */
1bd9debf 695 sbus_writel(dbri->dma_dvma, dbri->regs + REG8);
1bd9debf
TI		 696
697 /*spin_unlock(&dbri->lock); */
698}
699
700/* Lock must be held when calling this */
475675d6 701static void dbri_reset(struct snd_dbri * dbri)
1bd9debf
TI		 702{
703 int i;
704
705 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
706 sbus_readl(dbri->regs + REG0),
707 sbus_readl(dbri->regs + REG2),
708 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
709
710 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
711 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
712 udelay(10);
713}
714
715/* Lock must not be held before calling this */
475675d6 716static void dbri_initialize(struct snd_dbri * dbri)
1bd9debf
TI		 717{
718 volatile s32 *cmd;
719 u32 dma_addr, tmp;
720 unsigned long flags;
721 int n;
722
723 spin_lock_irqsave(&dbri->lock, flags);
724
725 dbri_reset(dbri);
726
727 cmd = dbri_cmdlock(dbri, NoGetLock);
728 dprintk(D_GEN, "init: cmd: %p, int: %p\n",
729 &dbri->dma->cmd[0], &dbri->dma->intr[0]);
730
1bd9debf
TI		 731 /* Initialize pipes */
732 for (n = 0; n < DBRI_NO_PIPES; n++)
733 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
734
4338829e
MH		 735 /* A brute approach - DBRI falls back to working burst size by itself
736 * On SS20 D_S does not work, so do not try so high. */
1bd9debf 737 tmp = sbus_readl(dbri->regs + REG0);
4338829e
MH		 738 tmp |= D_G | D_E;
739 tmp &= ~D_S;
1bd9debf
TI		 740 sbus_writel(tmp, dbri->regs + REG0);
741
742 /*
6fb98280 743 * Initialize the interrupt ringbuffer.
1bd9debf
TI		 744 */
745 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
6fb98280
KH		 746 dbri->dma->intr[0] = dma_addr;
747 dbri->dbri_irqp = 1;
748 /*
749 * Set up the interrupt queue
750 */
1bd9debf
TI		 751 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
752 *(cmd++) = dma_addr;
753
754 dbri_cmdsend(dbri, cmd);
755 spin_unlock_irqrestore(&dbri->lock, flags);
756}
757
758/*
759****************************************************************************
760************************** DBRI data pipe management ***********************
761****************************************************************************
762
763While DBRI control functions use the command and interrupt buffers, the
764main data path takes the form of data pipes, which can be short (command
765and interrupt driven), or long (attached to DMA buffers). These functions
766provide a rudimentary means of setting up and managing the DBRI's pipes,
767but the calling functions have to make sure they respect the pipes' linked
768list ordering, among other things. The transmit and receive functions
769here interface closely with the transmit and receive interrupt code.
770
771*/
475675d6 772static int pipe_active(struct snd_dbri * dbri, int pipe)
1bd9debf
TI		 773{
774 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
775}
776
777/* reset_pipe(dbri, pipe)
778 *
779 * Called on an in-use pipe to clear anything being transmitted or received
780 * Lock must be held before calling this.
781 */
475675d6 782static void reset_pipe(struct snd_dbri * dbri, int pipe)
1bd9debf
TI		 783{
784 int sdp;
785 int desc;
786 volatile int *cmd;
787
788 if (pipe < 0 || pipe > 31) {
4338829e 789 printk(KERN_ERR "DBRI: reset_pipe called with illegal pipe number\n");
1bd9debf
TI		 790 return;
791 }
792
793 sdp = dbri->pipes[pipe].sdp;
794 if (sdp == 0) {
4338829e 795 printk(KERN_ERR "DBRI: reset_pipe called on uninitialized pipe\n");
1bd9debf
TI		 796 return;
797 }
798
799 cmd = dbri_cmdlock(dbri, NoGetLock);
800 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
801 *(cmd++) = 0;
802 dbri_cmdsend(dbri, cmd);
803
804 desc = dbri->pipes[pipe].first_desc;
805 while (desc != -1) {
806 dbri->descs[desc].inuse = 0;
807 desc = dbri->descs[desc].next;
808 }
809
810 dbri->pipes[pipe].desc = -1;
811 dbri->pipes[pipe].first_desc = -1;
812}
813
814/* FIXME: direction as an argument? */
475675d6 815static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp)
1bd9debf
TI		 816{
817 if (pipe < 0 || pipe > 31) {
4338829e 818 printk(KERN_ERR "DBRI: setup_pipe called with illegal pipe number\n");
1bd9debf
TI		 819 return;
820 }
821
822 if ((sdp & 0xf800) != sdp) {
4338829e 823 printk(KERN_ERR "DBRI: setup_pipe called with strange SDP value\n");
1bd9debf
TI		 824 /* sdp &= 0xf800; */
825 }
826
827 /* If this is a fixed receive pipe, arrange for an interrupt
828 * every time its data changes
829 */
830 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
831 sdp |= D_SDP_CHANGE;
832
833 sdp |= D_PIPE(pipe);
834 dbri->pipes[pipe].sdp = sdp;
835 dbri->pipes[pipe].desc = -1;
836 dbri->pipes[pipe].first_desc = -1;
1bd9debf
TI		 837
838 reset_pipe(dbri, pipe);
839}
840
841/* FIXME: direction not needed */
475675d6 842static void link_time_slot(struct snd_dbri * dbri, int pipe,
1bd9debf
TI		 843 enum in_or_out direction, int basepipe,
844 int length, int cycle)
845{
846 volatile s32 *cmd;
847 int val;
848 int prevpipe;
849 int nextpipe;
850
851 if (pipe < 0 || pipe > 31 || basepipe < 0 || basepipe > 31) {
4338829e
MH		 852 printk(KERN_ERR
853 "DBRI: link_time_slot called with illegal pipe number\n");
1bd9debf
TI		 854 return;
855 }
856
857 if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) {
4338829e 858 printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n");
1bd9debf
TI		 859 return;
860 }
861
862 /* Deal with CHI special case:
863 * "If transmission on edges 0 or 1 is desired, then cycle n
864 * (where n = # of bit times per frame...) must be used."
865 * - DBRI data sheet, page 11
866 */
867 if (basepipe == 16 && direction == PIPEoutput && cycle == 0)
868 cycle = dbri->chi_bpf;
869
870 if (basepipe == pipe) {
871 prevpipe = pipe;
872 nextpipe = pipe;
873 } else {
874 /* We're not initializing a new linked list (basepipe != pipe),
875 * so run through the linked list and find where this pipe
876 * should be sloted in, based on its cycle. CHI confuses
877 * things a bit, since it has a single anchor for both its
878 * transmit and receive lists.
879 */
880 if (basepipe == 16) {
881 if (direction == PIPEinput) {
882 prevpipe = dbri->chi_in_pipe;
883 } else {
884 prevpipe = dbri->chi_out_pipe;
885 }
886 } else {
887 prevpipe = basepipe;
888 }
889
890 nextpipe = dbri->pipes[prevpipe].nextpipe;
891
892 while (dbri->pipes[nextpipe].cycle < cycle
893 && dbri->pipes[nextpipe].nextpipe != basepipe) {
894 prevpipe = nextpipe;
895 nextpipe = dbri->pipes[nextpipe].nextpipe;
896 }
897 }
898
899 if (prevpipe == 16) {
900 if (direction == PIPEinput) {
901 dbri->chi_in_pipe = pipe;
902 } else {
903 dbri->chi_out_pipe = pipe;
904 }
905 } else {
906 dbri->pipes[prevpipe].nextpipe = pipe;
907 }
908
909 dbri->pipes[pipe].nextpipe = nextpipe;
910 dbri->pipes[pipe].cycle = cycle;
911 dbri->pipes[pipe].length = length;
912
913 cmd = dbri_cmdlock(dbri, NoGetLock);
914
915 if (direction == PIPEinput) {
916 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
917 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
918 *(cmd++) =
919 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
920 *(cmd++) = 0;
921 } else {
922 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
923 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
924 *(cmd++) = 0;
925 *(cmd++) =
926 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
927 }
928
929 dbri_cmdsend(dbri, cmd);
930}
931
475675d6 932static void unlink_time_slot(struct snd_dbri * dbri, int pipe,
1bd9debf
TI		 933 enum in_or_out direction, int prevpipe,
934 int nextpipe)
935{
936 volatile s32 *cmd;
937 int val;
938
939 if (pipe < 0 || pipe > 31 || prevpipe < 0 || prevpipe > 31) {
4338829e
MH		 940 printk(KERN_ERR
941 "DBRI: unlink_time_slot called with illegal pipe number\n");
1bd9debf
TI		 942 return;
943 }
944
945 cmd = dbri_cmdlock(dbri, NoGetLock);
946
947 if (direction == PIPEinput) {
948 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
949 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
950 *(cmd++) = D_TS_NEXT(nextpipe);
951 *(cmd++) = 0;
952 } else {
953 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
954 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
955 *(cmd++) = 0;
956 *(cmd++) = D_TS_NEXT(nextpipe);
957 }
958
959 dbri_cmdsend(dbri, cmd);
960}
961
962/* xmit_fixed() / recv_fixed()
963 *
964 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
965 * expected to change much, and which we don't need to buffer.
966 * The DBRI only interrupts us when the data changes (receive pipes),
967 * or only changes the data when this function is called (transmit pipes).
968 * Only short pipes (numbers 16-31) can be used in fixed data mode.
969 *
970 * These function operate on a 32-bit field, no matter how large
971 * the actual time slot is. The interrupt handler takes care of bit
972 * ordering and alignment. An 8-bit time slot will always end up
973 * in the low-order 8 bits, filled either MSB-first or LSB-first,
974 * depending on the settings passed to setup_pipe()
975 */
475675d6 976static void xmit_fixed(struct snd_dbri * dbri, int pipe, unsigned int data)
1bd9debf
TI		 977{
978 volatile s32 *cmd;
979
980 if (pipe < 16 || pipe > 31) {
4338829e 981 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
1bd9debf
TI		 982 return;
983 }
984
985 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
4338829e 986 printk(KERN_ERR "DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
1bd9debf
TI		 987 return;
988 }
989
990 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
4338829e 991 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1bd9debf
TI		 992 return;
993 }
994
995 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
4338829e 996 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
1bd9debf
TI		 997 return;
998 }
999
1000 /* DBRI short pipes always transmit LSB first */
1001
1002 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1003 data = reverse_bytes(data, dbri->pipes[pipe].length);
1004
1005 cmd = dbri_cmdlock(dbri, GetLock);
1006
1007 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1008 *(cmd++) = data;
1009
1010 dbri_cmdsend(dbri, cmd);
1011}
1012
475675d6 1013static void recv_fixed(struct snd_dbri * dbri, int pipe, volatile __u32 * ptr)
1bd9debf
TI		 1014{
1015 if (pipe < 16 || pipe > 31) {
4338829e 1016 printk(KERN_ERR "DBRI: recv_fixed called with illegal pipe number\n");
1bd9debf
TI		 1017 return;
1018 }
1019
1020 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
4338829e 1021 printk(KERN_ERR "DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
1bd9debf
TI		 1022 return;
1023 }
1024
1025 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
4338829e 1026 printk(KERN_ERR "DBRI: recv_fixed called on transmit pipe %d\n", pipe);
1bd9debf
TI		 1027 return;
1028 }
1029
1030 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1031}
1032
1033/* setup_descs()
1034 *
1035 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1036 * with a DMA buffer.
1037 *
1038 * Only pipe numbers 0-15 can be used in this mode.
1039 *
1040 * This function takes a stream number pointing to a data buffer,
1041 * and work by building chains of descriptors which identify the
1042 * data buffers. Buffers too large for a single descriptor will
1043 * be spread across multiple descriptors.
1044 */
475675d6 1045static int setup_descs(struct snd_dbri * dbri, int streamno, unsigned int period)
1bd9debf 1046{
475675d6 1047 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1bd9debf
TI		 1048 __u32 dvma_buffer;
1049 int desc = 0;
1050 int len;
1051 int first_desc = -1;
1052 int last_desc = -1;
1053
1054 if (info->pipe < 0 || info->pipe > 15) {
4338829e 1055 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1bd9debf
TI		 1056 return -2;
1057 }
1058
1059 if (dbri->pipes[info->pipe].sdp == 0) {
4338829e 1060 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1bd9debf
TI		 1061 info->pipe);
1062 return -2;
1063 }
1064
1065 dvma_buffer = info->dvma_buffer;
1066 len = info->size;
1067
1068 if (streamno == DBRI_PLAY) {
1069 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
4338829e 1070 printk(KERN_ERR "DBRI: setup_descs: Called on receive pipe %d\n",
1bd9debf
TI		 1071 info->pipe);
1072 return -2;
1073 }
1074 } else {
1075 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
4338829e
MH		 1076 printk(KERN_ERR
1077 "DBRI: setup_descs: Called on transmit pipe %d\n",
1bd9debf
TI		 1078 info->pipe);
1079 return -2;
1080 }
1081 /* Should be able to queue multiple buffers to receive on a pipe */
1082 if (pipe_active(dbri, info->pipe)) {
4338829e 1083 printk(KERN_ERR "DBRI: recv_on_pipe: Called on active pipe %d\n",
1bd9debf
TI		 1084 info->pipe);
1085 return -2;
1086 }
1087
1088 /* Make sure buffer size is multiple of four */
1089 len &= ~3;
1090 }
1091
1092 while (len > 0) {
1093 int mylen;
1094
1095 for (; desc < DBRI_NO_DESCS; desc++) {
1096 if (!dbri->descs[desc].inuse)
1097 break;
1098 }
1099 if (desc == DBRI_NO_DESCS) {
4338829e 1100 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1bd9debf
TI		 1101 return -1;
1102 }
1103
1104 if (len > DBRI_TD_MAXCNT) {
1105 mylen = DBRI_TD_MAXCNT; /* 8KB - 1 */
1106 } else {
1107 mylen = len;
1108 }
1109 if (mylen > period) {
1110 mylen = period;
1111 }
1112
1113 dbri->descs[desc].inuse = 1;
1114 dbri->descs[desc].next = -1;
1115 dbri->dma->desc[desc].ba = dvma_buffer;
1116 dbri->dma->desc[desc].nda = 0;
1117
1118 if (streamno == DBRI_PLAY) {
1119 dbri->descs[desc].len = mylen;
1120 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1121 dbri->dma->desc[desc].word4 = 0;
1122 if (first_desc != -1)
1123 dbri->dma->desc[desc].word1 |= DBRI_TD_M;
1124 } else {
1125 dbri->descs[desc].len = 0;
1126 dbri->dma->desc[desc].word1 = 0;
1127 dbri->dma->desc[desc].word4 =
1128 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1129 }
1130
1131 if (first_desc == -1) {
1132 first_desc = desc;
1133 } else {
1134 dbri->descs[last_desc].next = desc;
1135 dbri->dma->desc[last_desc].nda =
1136 dbri->dma_dvma + dbri_dma_off(desc, desc);
1137 }
1138
1139 last_desc = desc;
1140 dvma_buffer += mylen;
1141 len -= mylen;
1142 }
1143
1144 if (first_desc == -1 || last_desc == -1) {
4338829e 1145 printk(KERN_ERR "DBRI: setup_descs: Not enough descriptors available\n");
1bd9debf
TI		 1146 return -1;
1147 }
1148
1149 dbri->dma->desc[last_desc].word1 &= ~DBRI_TD_M;
1150 if (streamno == DBRI_PLAY) {
1151 dbri->dma->desc[last_desc].word1 |=
1152 DBRI_TD_I | DBRI_TD_F | DBRI_TD_B;
1153 }
1154 dbri->pipes[info->pipe].first_desc = first_desc;
1155 dbri->pipes[info->pipe].desc = first_desc;
1156
1157 for (desc = first_desc; desc != -1; desc = dbri->descs[desc].next) {
1158 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1159 desc,
1160 dbri->dma->desc[desc].word1,
1161 dbri->dma->desc[desc].ba,
1162 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1163 }
1164 return 0;
1165}
1166
1167/*
1168****************************************************************************
1169************************** DBRI - CHI interface ****************************
1170****************************************************************************
1171
1172The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1173multiplexed serial interface which the DBRI can operate in either master
1174(give clock/frame sync) or slave (take clock/frame sync) mode.
1175
1176*/
1177
1178enum master_or_slave { CHImaster, CHIslave };
1179
475675d6 1180static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_slave,
1bd9debf
TI		 1181 int bits_per_frame)
1182{
1183 volatile s32 *cmd;
1184 int val;
1185 static int chi_initialized = 0; /* FIXME: mutex? */
1186
1187 if (!chi_initialized) {
1188
1189 cmd = dbri_cmdlock(dbri, GetLock);
1190
1191 /* Set CHI Anchor: Pipe 16 */
1192
1193 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(16) | D_PIPE(16);
1194 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1195 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1196 *(cmd++) = 0;
1197
1198 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(16) | D_PIPE(16);
1199 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1200 *(cmd++) = 0;
1201 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1202
1203 dbri->pipes[16].sdp = 1;
1204 dbri->pipes[16].nextpipe = 16;
1205 dbri->chi_in_pipe = 16;
1206 dbri->chi_out_pipe = 16;
1207
1208#if 0
1209 chi_initialized++;
1210#endif
1211 } else {
1212 int pipe;
1213
1214 for (pipe = dbri->chi_in_pipe;
1215 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
1216 unlink_time_slot(dbri, pipe, PIPEinput,
1217 16, dbri->pipes[pipe].nextpipe);
1218 }
1219 for (pipe = dbri->chi_out_pipe;
1220 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
1221 unlink_time_slot(dbri, pipe, PIPEoutput,
1222 16, dbri->pipes[pipe].nextpipe);
1223 }
1224
1225 dbri->chi_in_pipe = 16;
1226 dbri->chi_out_pipe = 16;
1227
1228 cmd = dbri_cmdlock(dbri, GetLock);
1229 }
1230
1231 if (master_or_slave == CHIslave) {
1232 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1233 *
1234 * CHICM = 0 (slave mode, 8 kHz frame rate)
1235 * IR = give immediate CHI status interrupt
1236 * EN = give CHI status interrupt upon change
1237 */
1238 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1239 } else {
1240 /* Setup DBRI for CHI Master - generate clock, FS
1241 *
1242 * BPF = bits per 8 kHz frame
1243 * 12.288 MHz / CHICM_divisor = clock rate
1244 * FD = 1 - drive CHIFS on rising edge of CHICK
1245 */
1246 int clockrate = bits_per_frame * 8;
1247 int divisor = 12288 / clockrate;
1248
1249 if (divisor > 255 || divisor * clockrate != 12288)
4338829e 1250 printk(KERN_ERR "DBRI: illegal bits_per_frame in setup_chi\n");
1bd9debf
TI		 1251
1252 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1253 | D_CHI_BPF(bits_per_frame));
1254 }
1255
1256 dbri->chi_bpf = bits_per_frame;
1257
1258 /* CHI Data Mode
1259 *
1260 * RCE = 0 - receive on falling edge of CHICK
1261 * XCE = 1 - transmit on rising edge of CHICK
1262 * XEN = 1 - enable transmitter
1263 * REN = 1 - enable receiver
1264 */
1265
1266 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1267 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1268
1269 dbri_cmdsend(dbri, cmd);
1270}
1271
1272/*
1273****************************************************************************
1274*********************** CS4215 audio codec management **********************
1275****************************************************************************
1276
1277In the standard SPARC audio configuration, the CS4215 codec is attached
1278to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1279
1280*/
475675d6 1281static void cs4215_setup_pipes(struct snd_dbri * dbri)
1bd9debf
TI		 1282{
1283 /*
1284 * Data mode:
1285 * Pipe 4: Send timeslots 1-4 (audio data)
1286 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1287 * Pipe 6: Receive timeslots 1-4 (audio data)
1288 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1289 * interrupt, and the rest of the data (slot 5 and 8) is
1290 * not relevant for us (only for doublechecking).
1291 *
1292 * Control mode:
1293 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1294 * Pipe 18: Receive timeslot 1 (clb).
1295 * Pipe 19: Receive timeslot 7 (version).
1296 */
1297
1298 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1299 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1300 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1301 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1302
1303 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1304 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1305 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1306}
1307
1308static int cs4215_init_data(struct cs4215 *mm)
1309{
1310 /*
1311 * No action, memory resetting only.
1312 *
1313 * Data Time Slot 5-8
1314 * Speaker,Line and Headphone enable. Gain set to the half.
1315 * Input is mike.
1316 */
1317 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1318 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1319 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1320 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1321
1322 /*
1323 * Control Time Slot 1-4
1324 * 0: Default I/O voltage scale
1325 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1326 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1327 * 3: Tests disabled
1328 */
1329 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1330 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1331 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1332 mm->ctrl[3] = 0;
1333
1334 mm->status = 0;
1335 mm->version = 0xff;
1336 mm->precision = 8; /* For ULAW */
1337 mm->channels = 2;
1338
1339 return 0;
1340}
1341
475675d6 1342static void cs4215_setdata(struct snd_dbri * dbri, int muted)
1bd9debf
TI		 1343{
1344 if (muted) {
1345 dbri->mm.data[0] |= 63;
1346 dbri->mm.data[1] |= 63;
1347 dbri->mm.data[2] &= ~15;
1348 dbri->mm.data[3] &= ~15;
1349 } else {
1350 /* Start by setting the playback attenuation. */
475675d6 1351 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1bd9debf
TI		 1352 int left_gain = info->left_gain % 64;
1353 int right_gain = info->right_gain % 64;
1354
1bd9debf
TI		 1355 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1356 dbri->mm.data[1] &= ~0x3f;
1357 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1358 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1359
1360 /* Now set the recording gain. */
1361 info = &dbri->stream_info[DBRI_REC];
1362 left_gain = info->left_gain % 16;
1363 right_gain = info->right_gain % 16;
1364 dbri->mm.data[2] |= CS4215_LG(left_gain);
1365 dbri->mm.data[3] |= CS4215_RG(right_gain);
1366 }
1367
1368 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1369}
1370
1371/*
1372 * Set the CS4215 to data mode.
1373 */
475675d6 1374static void cs4215_open(struct snd_dbri * dbri)
1bd9debf
TI		 1375{
1376 int data_width;
1377 u32 tmp;
1378
1379 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1380 dbri->mm.channels, dbri->mm.precision);
1381
1382 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1383 * to make sure this takes. This avoids clicking noises.
1384 */
1385
1386 cs4215_setdata(dbri, 1);
1387 udelay(125);
1388
1389 /*
1390 * Data mode:
1391 * Pipe 4: Send timeslots 1-4 (audio data)
1392 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1393 * Pipe 6: Receive timeslots 1-4 (audio data)
1394 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1395 * interrupt, and the rest of the data (slot 5 and 8) is
1396 * not relevant for us (only for doublechecking).
1397 *
1398 * Just like in control mode, the time slots are all offset by eight
1399 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1400 * even if it's the CHI master. Don't ask me...
1401 */
1402 tmp = sbus_readl(dbri->regs + REG0);
1403 tmp &= ~(D_C); /* Disable CHI */
1404 sbus_writel(tmp, dbri->regs + REG0);
1405
1406 /* Switch CS4215 to data mode - set PIO3 to 1 */
1407 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1408 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1409
1410 reset_chi(dbri, CHIslave, 128);
1411
1412 /* Note: this next doesn't work for 8-bit stereo, because the two
1413 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1414 * (See CS4215 datasheet Fig 15)
1415 *
1416 * DBRI non-contiguous mode would be required to make this work.
1417 */
1418 data_width = dbri->mm.channels * dbri->mm.precision;
1419
1420 link_time_slot(dbri, 20, PIPEoutput, 16, 32, dbri->mm.offset + 32);
1421 link_time_slot(dbri, 4, PIPEoutput, 16, data_width, dbri->mm.offset);
1422 link_time_slot(dbri, 6, PIPEinput, 16, data_width, dbri->mm.offset);
1423 link_time_slot(dbri, 21, PIPEinput, 16, 16, dbri->mm.offset + 40);
1424
1425 /* FIXME: enable CHI after _setdata? */
1426 tmp = sbus_readl(dbri->regs + REG0);
1427 tmp |= D_C; /* Enable CHI */
1428 sbus_writel(tmp, dbri->regs + REG0);
1429
1430 cs4215_setdata(dbri, 0);
1431}
1432
1433/*
1434 * Send the control information (i.e. audio format)
1435 */
475675d6 1436static int cs4215_setctrl(struct snd_dbri * dbri)
1bd9debf
TI		 1437{
1438 int i, val;
1439 u32 tmp;
1440
1441 /* FIXME - let the CPU do something useful during these delays */
1442
1443 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1444 * to make sure this takes. This avoids clicking noises.
1445 */
1bd9debf
TI		 1446 cs4215_setdata(dbri, 1);
1447 udelay(125);
1448
1449 /*
1450 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1451 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1452 */
1453 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1454 sbus_writel(val, dbri->regs + REG2);
1455 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1456 udelay(34);
1457
1458 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1459 * operate as CHI master, supplying clocking and frame synchronization.
1460 *
1461 * In Data mode, however, the CS4215 must be CHI master to insure
1462 * that its data stream is synchronous with its codec.
1463 *
1464 * The upshot of all this? We start by putting the DBRI into master
1465 * mode, program the CS4215 in Control mode, then switch the CS4215
1466 * into Data mode and put the DBRI into slave mode. Various timing
1467 * requirements must be observed along the way.
1468 *
1469 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1470 * others?), the addressing of the CS4215's time slots is
1471 * offset by eight bits, so we add eight to all the "cycle"
1472 * values in the Define Time Slot (DTS) commands. This is
1473 * done in hardware by a TI 248 that delays the DBRI->4215
1474 * frame sync signal by eight clock cycles. Anybody know why?
1475 */
1476 tmp = sbus_readl(dbri->regs + REG0);
1477 tmp &= ~D_C; /* Disable CHI */
1478 sbus_writel(tmp, dbri->regs + REG0);
1479
1480 reset_chi(dbri, CHImaster, 128);
1481
1482 /*
1483 * Control mode:
1484 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1485 * Pipe 18: Receive timeslot 1 (clb).
1486 * Pipe 19: Receive timeslot 7 (version).
1487 */
1488
1489 link_time_slot(dbri, 17, PIPEoutput, 16, 32, dbri->mm.offset);
1490 link_time_slot(dbri, 18, PIPEinput, 16, 8, dbri->mm.offset);
1491 link_time_slot(dbri, 19, PIPEinput, 16, 8, dbri->mm.offset + 48);
1492
1493 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1494 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1495 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1496
1497 tmp = sbus_readl(dbri->regs + REG0);
1498 tmp |= D_C; /* Enable CHI */
1499 sbus_writel(tmp, dbri->regs + REG0);
1500
4338829e
MH		 1501 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) {
1502 msleep_interruptible(1);
1bd9debf
TI		 1503 }
1504 if (i == 0) {
1505 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1506 dbri->mm.status);
1507 return -1;
1508 }
1509
1510 /* Disable changes to our copy of the version number, as we are about
1511 * to leave control mode.
1512 */
1513 recv_fixed(dbri, 19, NULL);
1514
1515 /* Terminate CS4215 control mode - data sheet says
1516 * "Set CLB=1 and send two more frames of valid control info"
1517 */
1518 dbri->mm.ctrl[0] |= CS4215_CLB;
1519 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1520
1521 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1522 udelay(250);
1523
1524 cs4215_setdata(dbri, 0);
1525
1526 return 0;
1527}
1528
1529/*
1530 * Setup the codec with the sampling rate, audio format and number of
1531 * channels.
1532 * As part of the process we resend the settings for the data
1533 * timeslots as well.
1534 */
475675d6 1535static int cs4215_prepare(struct snd_dbri * dbri, unsigned int rate,
1bd9debf
TI		 1536 snd_pcm_format_t format, unsigned int channels)
1537{
1538 int freq_idx;
1539 int ret = 0;
1540
1541 /* Lookup index for this rate */
1542 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1543 if (CS4215_FREQ[freq_idx].freq == rate)
1544 break;
1545 }
1546 if (CS4215_FREQ[freq_idx].freq != rate) {
1547 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1548 return -1;
1549 }
1550
1551 switch (format) {
1552 case SNDRV_PCM_FORMAT_MU_LAW:
1553 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1554 dbri->mm.precision = 8;
1555 break;
1556 case SNDRV_PCM_FORMAT_A_LAW:
1557 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1558 dbri->mm.precision = 8;
1559 break;
1560 case SNDRV_PCM_FORMAT_U8:
1561 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1562 dbri->mm.precision = 8;
1563 break;
1564 case SNDRV_PCM_FORMAT_S16_BE:
1565 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1566 dbri->mm.precision = 16;
1567 break;
1568 default:
1569 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1570 return -1;
1571 }
1572
1573 /* Add rate parameters */
1574 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1575 dbri->mm.ctrl[2] = CS4215_XCLK |
1576 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1577
1578 dbri->mm.channels = channels;
1579 /* Stereo bit: 8 bit stereo not working yet. */
1580 if ((channels > 1) && (dbri->mm.precision == 16))
1581 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1582
1583 ret = cs4215_setctrl(dbri);
1584 if (ret == 0)
1585 cs4215_open(dbri); /* set codec to data mode */
1586
1587 return ret;
1588}
1589
1590/*
1591 *
1592 */
475675d6 1593static int cs4215_init(struct snd_dbri * dbri)
1bd9debf
TI		 1594{
1595 u32 reg2 = sbus_readl(dbri->regs + REG2);
1596 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1597
1598 /* Look for the cs4215 chips */
1599 if (reg2 & D_PIO2) {
1600 dprintk(D_MM, "Onboard CS4215 detected\n");
1601 dbri->mm.onboard = 1;
1602 }
1603 if (reg2 & D_PIO0) {
1604 dprintk(D_MM, "Speakerbox detected\n");
1605 dbri->mm.onboard = 0;
1606
1607 if (reg2 & D_PIO2) {
1608 printk(KERN_INFO "DBRI: Using speakerbox / "
1609 "ignoring onboard mmcodec.\n");
1610 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1611 }
1612 }
1613
1614 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1615 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1616 return -EIO;
1617 }
1618
1619 cs4215_setup_pipes(dbri);
1620
1621 cs4215_init_data(&dbri->mm);
1622
1623 /* Enable capture of the status & version timeslots. */
1624 recv_fixed(dbri, 18, &dbri->mm.status);
1625 recv_fixed(dbri, 19, &dbri->mm.version);
1626
1627 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1628 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1629 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1630 dbri->mm.offset);
1631 return -EIO;
1632 }
1633 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1634
1635 return 0;
1636}
1637
1638/*
1639****************************************************************************
1640*************************** DBRI interrupt handler *************************
1641****************************************************************************
1642
1643The DBRI communicates with the CPU mainly via a circular interrupt
1644buffer. When an interrupt is signaled, the CPU walks through the
1645buffer and calls dbri_process_one_interrupt() for each interrupt word.
1646Complicated interrupts are handled by dedicated functions (which
1647appear first in this file). Any pending interrupts can be serviced by
1648calling dbri_process_interrupt_buffer(), which works even if the CPU's
4338829e
MH		 1649interrupts are disabled. This function is used by dbri_cmdlock()
1650to make sure we're synced up with the chip before each command sequence,
1bd9debf
TI		 1651even if we're running cli'ed.
1652
1653*/
1654
1655/* xmit_descs()
1656 *
1657 * Transmit the current TD's for recording/playing, if needed.
1658 * For playback, ALSA has filled the DMA memory with new data (we hope).
1659 */
1660static void xmit_descs(unsigned long data)
1661{
475675d6
TI		 1662 struct snd_dbri *dbri = (struct snd_dbri *) data;
1663 struct dbri_streaminfo *info;
1bd9debf
TI		 1664 volatile s32 *cmd;
1665 unsigned long flags;
1666 int first_td;
1667
1668 if (dbri == NULL)
1669 return; /* Disabled */
1670
1671 /* First check the recording stream for buffer overflow */
1672 info = &dbri->stream_info[DBRI_REC];
1673 spin_lock_irqsave(&dbri->lock, flags);
1674
1675 if ((info->left >= info->size) && (info->pipe >= 0)) {
1676 first_td = dbri->pipes[info->pipe].first_desc;
1677
1678 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1679
1680 /* Stream could be closed by the time we run. */
1681 if (first_td < 0) {
1682 goto play;
1683 }
1684
1685 cmd = dbri_cmdlock(dbri, NoGetLock);
1686 *(cmd++) = DBRI_CMD(D_SDP, 0,
1687 dbri->pipes[info->pipe].sdp
1688 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1689 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1690 dbri_cmdsend(dbri, cmd);
1691
1692 /* Reset our admin of the pipe & bytes read. */
1693 dbri->pipes[info->pipe].desc = first_td;
1694 info->left = 0;
1695 }
1696
1697play:
1698 spin_unlock_irqrestore(&dbri->lock, flags);
1699
1700 /* Now check the playback stream for buffer underflow */
1701 info = &dbri->stream_info[DBRI_PLAY];
1702 spin_lock_irqsave(&dbri->lock, flags);
1703
1704 if ((info->left <= 0) && (info->pipe >= 0)) {
1705 first_td = dbri->pipes[info->pipe].first_desc;
1706
1707 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1708
1709 /* Stream could be closed by the time we run. */
1710 if (first_td < 0) {
1711 spin_unlock_irqrestore(&dbri->lock, flags);
1712 return;
1713 }
1714
1715 cmd = dbri_cmdlock(dbri, NoGetLock);
1716 *(cmd++) = DBRI_CMD(D_SDP, 0,
1717 dbri->pipes[info->pipe].sdp
1718 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1719 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1720 dbri_cmdsend(dbri, cmd);
1721
1722 /* Reset our admin of the pipe & bytes written. */
1723 dbri->pipes[info->pipe].desc = first_td;
1724 info->left = info->size;
1725 }
1726 spin_unlock_irqrestore(&dbri->lock, flags);
1727}
1728
063859c8 1729static DECLARE_TASKLET(xmit_descs_task, xmit_descs, 0);
1bd9debf
TI		 1730
1731/* transmission_complete_intr()
1732 *
1733 * Called by main interrupt handler when DBRI signals transmission complete
1734 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1735 *
4338829e
MH		 1736 * Walks through the pipe's list of transmit buffer descriptors and marks
1737 * them as available. Stops when the first descriptor is found without
1bd9debf 1738 * TBC (Transmit Buffer Complete) set, or we've run through them all.
4338829e
MH		 1739 *
1740 * The DMA buffers are not released, but re-used. Since the transmit buffer
1741 * descriptors are not clobbered, they can be re-submitted as is. This is
1742 * done by the xmit_descs() tasklet above since that could take longer.
1bd9debf
TI		 1743 */
1744
475675d6 1745static void transmission_complete_intr(struct snd_dbri * dbri, int pipe)
1bd9debf 1746{
475675d6 1747 struct dbri_streaminfo *info;
1bd9debf
TI		 1748 int td;
1749 int status;
1750
1751 info = &dbri->stream_info[DBRI_PLAY];
1752
1753 td = dbri->pipes[pipe].desc;
1754 while (td >= 0) {
1755 if (td >= DBRI_NO_DESCS) {
1756 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1757 return;
1758 }
1759
1760 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1761 if (!(status & DBRI_TD_TBC)) {
1762 break;
1763 }
1764
1765 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1766
1767 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1768 info->offset += dbri->descs[td].len;
1769 info->left -= dbri->descs[td].len;
1770
1771 /* On the last TD, transmit them all again. */
1772 if (dbri->descs[td].next == -1) {
1773 if (info->left > 0) {
1774 printk(KERN_WARNING
1775 "%d bytes left after last transfer.\n",
1776 info->left);
1777 info->left = 0;
1778 }
1779 tasklet_schedule(&xmit_descs_task);
1780 }
1781
1782 td = dbri->descs[td].next;
1783 dbri->pipes[pipe].desc = td;
1784 }
1785
1786 /* Notify ALSA */
1787 if (spin_is_locked(&dbri->lock)) {
1788 spin_unlock(&dbri->lock);
1789 snd_pcm_period_elapsed(info->substream);
1790 spin_lock(&dbri->lock);
1791 } else
1792 snd_pcm_period_elapsed(info->substream);
1793}
1794
475675d6 1795static void reception_complete_intr(struct snd_dbri * dbri, int pipe)
1bd9debf 1796{
475675d6 1797 struct dbri_streaminfo *info;
1bd9debf
TI		 1798 int rd = dbri->pipes[pipe].desc;
1799 s32 status;
1800
1801 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1802 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1803 return;
1804 }
1805
1806 dbri->descs[rd].inuse = 0;
1807 dbri->pipes[pipe].desc = dbri->descs[rd].next;
1808 status = dbri->dma->desc[rd].word1;
1809 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1810
1811 info = &dbri->stream_info[DBRI_REC];
1812 info->offset += DBRI_RD_CNT(status);
1813 info->left += DBRI_RD_CNT(status);
1814
1815 /* FIXME: Check status */
1816
1817 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1818 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1819
1820 /* On the last TD, transmit them all again. */
1821 if (dbri->descs[rd].next == -1) {
1822 if (info->left > info->size) {
1823 printk(KERN_WARNING
1824 "%d bytes recorded in %d size buffer.\n",
1825 info->left, info->size);
1826 }
1827 tasklet_schedule(&xmit_descs_task);
1828 }
1829
1830 /* Notify ALSA */
1831 if (spin_is_locked(&dbri->lock)) {
1832 spin_unlock(&dbri->lock);
1833 snd_pcm_period_elapsed(info->substream);
1834 spin_lock(&dbri->lock);
1835 } else
1836 snd_pcm_period_elapsed(info->substream);
1837}
1838
475675d6 1839static void dbri_process_one_interrupt(struct snd_dbri * dbri, int x)
1bd9debf
TI		 1840{
1841 int val = D_INTR_GETVAL(x);
1842 int channel = D_INTR_GETCHAN(x);
1843 int command = D_INTR_GETCMD(x);
1844 int code = D_INTR_GETCODE(x);
1845#ifdef DBRI_DEBUG
1846 int rval = D_INTR_GETRVAL(x);
1847#endif
1848
1849 if (channel == D_INTR_CMD) {
1850 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1851 cmds[command], val);
1852 } else {
1853 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1854 channel, code, rval);
1855 }
1856
1857 if (channel == D_INTR_CMD && command == D_WAIT) {
4338829e
MH		 1858 dbri->wait_ackd = val;
1859 if (dbri->wait_send != val) {
1860 printk(KERN_ERR "Processing wait command %d when %d was send.\n",
1861 val, dbri->wait_send);
1862 }
1bd9debf
TI		 1863 return;
1864 }
1865
1866 switch (code) {
1867 case D_INTR_BRDY:
1868 reception_complete_intr(dbri, channel);
1869 break;
1870 case D_INTR_XCMP:
1871 case D_INTR_MINT:
1872 transmission_complete_intr(dbri, channel);
1873 break;
1874 case D_INTR_UNDR:
1875 /* UNDR - Transmission underrun
1876 * resend SDP command with clear pipe bit (C) set
1877 */
1878 {
1879 volatile s32 *cmd;
1880
1881 int pipe = channel;
1882 int td = dbri->pipes[pipe].desc;
1883
1884 dbri->dma->desc[td].word4 = 0;
1885 cmd = dbri_cmdlock(dbri, NoGetLock);
1886 *(cmd++) = DBRI_CMD(D_SDP, 0,
1887 dbri->pipes[pipe].sdp
1888 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1889 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1890 dbri_cmdsend(dbri, cmd);
1891 }
1892 break;
1893 case D_INTR_FXDT:
1894 /* FXDT - Fixed data change */
1895 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1896 val = reverse_bytes(val, dbri->pipes[channel].length);
1897
1898 if (dbri->pipes[channel].recv_fixed_ptr)
1899 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1900 break;
1901 default:
1902 if (channel != D_INTR_CMD)
1903 printk(KERN_WARNING
1904 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1905 }
1906}
1907
1908/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1909 * buffer until it finds a zero word (indicating nothing more to do
1910 * right now). Non-zero words require processing and are handed off
1911 * to dbri_process_one_interrupt AFTER advancing the pointer. This
1912 * order is important since we might recurse back into this function
1913 * and need to make sure the pointer has been advanced first.
1914 */
475675d6 1915static void dbri_process_interrupt_buffer(struct snd_dbri * dbri)
1bd9debf
TI		 1916{
1917 s32 x;
1918
1919 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1920 dbri->dma->intr[dbri->dbri_irqp] = 0;
1921 dbri->dbri_irqp++;
6fb98280 1922 if (dbri->dbri_irqp == DBRI_INT_BLK)
1bd9debf 1923 dbri->dbri_irqp = 1;
1bd9debf
TI		 1924
1925 dbri_process_one_interrupt(dbri, x);
1926 }
1927}
1928
1929static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id,
1930 struct pt_regs *regs)
1931{
475675d6 1932 struct snd_dbri *dbri = dev_id;
1bd9debf
TI		 1933 static int errcnt = 0;
1934 int x;
1935
1936 if (dbri == NULL)
1937 return IRQ_NONE;
1938 spin_lock(&dbri->lock);
1939
1940 /*
1941 * Read it, so the interrupt goes away.
1942 */
1943 x = sbus_readl(dbri->regs + REG1);
1944
1945 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1946 u32 tmp;
1947
1948 if (x & D_MRR)
1949 printk(KERN_ERR
1950 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1951 x);
1952 if (x & D_MLE)
1953 printk(KERN_ERR
1954 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1955 x);
1956 if (x & D_LBG)
1957 printk(KERN_ERR
1958 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1959 if (x & D_MBE)
1960 printk(KERN_ERR
1961 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1962
1963 /* Some of these SBus errors cause the chip's SBus circuitry
1964 * to be disabled, so just re-enable and try to keep going.
1965 *
1966 * The only one I've seen is MRR, which will be triggered
1967 * if you let a transmit pipe underrun, then try to CDP it.
1968 *
4338829e 1969 * If these things persist, we reset the chip.
1bd9debf
TI		 1970 */
1971 if ((++errcnt) % 10 == 0) {
1972 dprintk(D_INT, "Interrupt errors exceeded.\n");
1973 dbri_reset(dbri);
1974 } else {
1975 tmp = sbus_readl(dbri->regs + REG0);
1976 tmp &= ~(D_D);
1977 sbus_writel(tmp, dbri->regs + REG0);
1978 }
1979 }
1980
1981 dbri_process_interrupt_buffer(dbri);
1982
1983 /* FIXME: Write 0 into regs to ACK interrupt */
1984
1985 spin_unlock(&dbri->lock);
1986
1987 return IRQ_HANDLED;
1988}
1989
1990/****************************************************************************
1991 PCM Interface
1992****************************************************************************/
475675d6 1993static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1bd9debf
TI		 1994 .info = (SNDRV_PCM_INFO_MMAP |
1995 SNDRV_PCM_INFO_INTERLEAVED |
1996 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1997 SNDRV_PCM_INFO_MMAP_VALID),
1998 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1999 SNDRV_PCM_FMTBIT_A_LAW |
2000 SNDRV_PCM_FMTBIT_U8 |
2001 SNDRV_PCM_FMTBIT_S16_BE,
2002 .rates = SNDRV_PCM_RATE_8000_48000,
2003 .rate_min = 8000,
2004 .rate_max = 48000,
2005 .channels_min = 1,
2006 .channels_max = 2,
2007 .buffer_bytes_max = (64 * 1024),
2008 .period_bytes_min = 1,
2009 .period_bytes_max = DBRI_TD_MAXCNT,
2010 .periods_min = 1,
2011 .periods_max = 1024,
2012};
2013
475675d6 2014static int snd_dbri_open(struct snd_pcm_substream *substream)
1bd9debf 2015{
475675d6
TI		 2016 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2017 struct snd_pcm_runtime *runtime = substream->runtime;
2018 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1bd9debf
TI		 2019 unsigned long flags;
2020
2021 dprintk(D_USR, "open audio output.\n");
2022 runtime->hw = snd_dbri_pcm_hw;
2023
2024 spin_lock_irqsave(&dbri->lock, flags);
2025 info->substream = substream;
2026 info->left = 0;
2027 info->offset = 0;
2028 info->dvma_buffer = 0;
2029 info->pipe = -1;
2030 spin_unlock_irqrestore(&dbri->lock, flags);
2031
2032 cs4215_open(dbri);
2033
2034 return 0;
2035}
2036
475675d6 2037static int snd_dbri_close(struct snd_pcm_substream *substream)
1bd9debf 2038{
475675d6
TI		 2039 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2040 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1bd9debf
TI		 2041
2042 dprintk(D_USR, "close audio output.\n");
2043 info->substream = NULL;
2044 info->left = 0;
2045 info->offset = 0;
2046
2047 return 0;
2048}
2049
475675d6
TI		 2050static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2051 struct snd_pcm_hw_params *hw_params)
1bd9debf 2052{
475675d6
TI		 2053 struct snd_pcm_runtime *runtime = substream->runtime;
2054 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2055 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1bd9debf
TI		 2056 int direction;
2057 int ret;
2058
2059 /* set sampling rate, audio format and number of channels */
2060 ret = cs4215_prepare(dbri, params_rate(hw_params),
2061 params_format(hw_params),
2062 params_channels(hw_params));
2063 if (ret != 0)
2064 return ret;
2065
2066 if ((ret = snd_pcm_lib_malloc_pages(substream,
2067 params_buffer_bytes(hw_params))) < 0) {
4338829e 2068 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
1bd9debf
TI		 2069 return ret;
2070 }
2071
2072 /* hw_params can get called multiple times. Only map the DMA once.
2073 */
2074 if (info->dvma_buffer == 0) {
2075 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2076 direction = SBUS_DMA_TODEVICE;
2077 else
2078 direction = SBUS_DMA_FROMDEVICE;
2079
2080 info->dvma_buffer = sbus_map_single(dbri->sdev,
2081 runtime->dma_area,
2082 params_buffer_bytes(hw_params),
2083 direction);
2084 }
2085
2086 direction = params_buffer_bytes(hw_params);
2087 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2088 direction, info->dvma_buffer);
2089 return 0;
2090}
2091
475675d6 2092static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
1bd9debf 2093{
475675d6
TI		 2094 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2095 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1bd9debf
TI		 2096 int direction;
2097 dprintk(D_USR, "hw_free.\n");
2098
2099 /* hw_free can get called multiple times. Only unmap the DMA once.
2100 */
2101 if (info->dvma_buffer) {
2102 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2103 direction = SBUS_DMA_TODEVICE;
2104 else
2105 direction = SBUS_DMA_FROMDEVICE;
2106
2107 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2108 substream->runtime->buffer_size, direction);
2109 info->dvma_buffer = 0;
2110 }
2111 info->pipe = -1;
2112
2113 return snd_pcm_lib_free_pages(substream);
2114}
2115
475675d6 2116static int snd_dbri_prepare(struct snd_pcm_substream *substream)
1bd9debf 2117{
475675d6
TI		 2118 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2119 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2120 struct snd_pcm_runtime *runtime = substream->runtime;
1bd9debf
TI		 2121 int ret;
2122
2123 info->size = snd_pcm_lib_buffer_bytes(substream);
2124 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2125 info->pipe = 4; /* Send pipe */
2126 else {
2127 info->pipe = 6; /* Receive pipe */
2128 info->left = info->size; /* To trigger submittal */
2129 }
2130
2131 spin_lock_irq(&dbri->lock);
2132
2133 /* Setup the all the transmit/receive desciptors to cover the
2134 * whole DMA buffer.
2135 */
2136 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2137 snd_pcm_lib_period_bytes(substream));
2138
2139 runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels;
2140
2141 spin_unlock_irq(&dbri->lock);
2142
2143 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2144 return ret;
2145}
2146
475675d6 2147static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
1bd9debf 2148{
475675d6
TI		 2149 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2150 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1bd9debf
TI		 2151 int ret = 0;
2152
2153 switch (cmd) {
2154 case SNDRV_PCM_TRIGGER_START:
2155 dprintk(D_USR, "start audio, period is %d bytes\n",
2156 (int)snd_pcm_lib_period_bytes(substream));
2157 /* Enable & schedule the tasklet that re-submits the TDs. */
2158 xmit_descs_task.data = (unsigned long)dbri;
2159 tasklet_schedule(&xmit_descs_task);
2160 break;
2161 case SNDRV_PCM_TRIGGER_STOP:
2162 dprintk(D_USR, "stop audio.\n");
2163 /* Make the tasklet bail out immediately. */
2164 xmit_descs_task.data = 0;
2165 reset_pipe(dbri, info->pipe);
2166 break;
2167 default:
2168 ret = -EINVAL;
2169 }
2170
2171 return ret;
2172}
2173
475675d6 2174static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
1bd9debf 2175{
475675d6
TI		 2176 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2177 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1bd9debf
TI		 2178 snd_pcm_uframes_t ret;
2179
2180 ret = bytes_to_frames(substream->runtime, info->offset)
2181 % substream->runtime->buffer_size;
2182 dprintk(D_USR, "I/O pointer: %ld frames, %d bytes left.\n",
2183 ret, info->left);
2184 return ret;
2185}
2186
475675d6 2187static struct snd_pcm_ops snd_dbri_ops = {
1bd9debf
TI		 2188 .open = snd_dbri_open,
2189 .close = snd_dbri_close,
2190 .ioctl = snd_pcm_lib_ioctl,
2191 .hw_params = snd_dbri_hw_params,
2192 .hw_free = snd_dbri_hw_free,
2193 .prepare = snd_dbri_prepare,
2194 .trigger = snd_dbri_trigger,
2195 .pointer = snd_dbri_pointer,
2196};
2197
475675d6 2198static int __devinit snd_dbri_pcm(struct snd_dbri * dbri)
1bd9debf 2199{
475675d6 2200 struct snd_pcm *pcm;
1bd9debf
TI		 2201 int err;
2202
2203 if ((err = snd_pcm_new(dbri->card,
2204 /* ID */ "sun_dbri",
2205 /* device */ 0,
2206 /* playback count */ 1,
2207 /* capture count */ 1, &pcm)) < 0)
2208 return err;
2209 snd_assert(pcm != NULL, return -EINVAL);
2210
2211 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2212 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2213
2214 pcm->private_data = dbri;
2215 pcm->info_flags = 0;
2216 strcpy(pcm->name, dbri->card->shortname);
1bd9debf
TI		 2217
2218 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2219 SNDRV_DMA_TYPE_CONTINUOUS,
2220 snd_dma_continuous_data(GFP_KERNEL),
2221 64 * 1024, 64 * 1024)) < 0) {
2222 return err;
2223 }
2224
2225 return 0;
2226}
2227
2228/*****************************************************************************
2229 Mixer interface
2230*****************************************************************************/
2231
475675d6
TI		 2232static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2233 struct snd_ctl_elem_info *uinfo)
1bd9debf
TI		 2234{
2235 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2236 uinfo->count = 2;
2237 uinfo->value.integer.min = 0;
2238 if (kcontrol->private_value == DBRI_PLAY) {
2239 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2240 } else {
2241 uinfo->value.integer.max = DBRI_MAX_GAIN;
2242 }
2243 return 0;
2244}
2245
475675d6
TI		 2246static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2247 struct snd_ctl_elem_value *ucontrol)
1bd9debf 2248{
475675d6
TI		 2249 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2250 struct dbri_streaminfo *info;
1bd9debf
TI		 2251 snd_assert(dbri != NULL, return -EINVAL);
2252 info = &dbri->stream_info[kcontrol->private_value];
2253 snd_assert(info != NULL, return -EINVAL);
2254
2255 ucontrol->value.integer.value[0] = info->left_gain;
2256 ucontrol->value.integer.value[1] = info->right_gain;
2257 return 0;
2258}
2259
475675d6
TI		 2260static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2261 struct snd_ctl_elem_value *ucontrol)
1bd9debf 2262{
475675d6
TI		 2263 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2264 struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value];
1bd9debf
TI		 2265 unsigned long flags;
2266 int changed = 0;
2267
2268 if (info->left_gain != ucontrol->value.integer.value[0]) {
2269 info->left_gain = ucontrol->value.integer.value[0];
2270 changed = 1;
2271 }
2272 if (info->right_gain != ucontrol->value.integer.value[1]) {
2273 info->right_gain = ucontrol->value.integer.value[1];
2274 changed = 1;
2275 }
2276 if (changed == 1) {
2277 /* First mute outputs, and wait 1/8000 sec (125 us)
2278 * to make sure this takes. This avoids clicking noises.
2279 */
2280 spin_lock_irqsave(&dbri->lock, flags);
2281
2282 cs4215_setdata(dbri, 1);
2283 udelay(125);
2284 cs4215_setdata(dbri, 0);
2285
2286 spin_unlock_irqrestore(&dbri->lock, flags);
2287 }
2288 return changed;
2289}
2290
475675d6
TI		 2291static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2292 struct snd_ctl_elem_info *uinfo)
1bd9debf
TI		 2293{
2294 int mask = (kcontrol->private_value >> 16) & 0xff;
2295
2296 uinfo->type = (mask == 1) ?
2297 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2298 uinfo->count = 1;
2299 uinfo->value.integer.min = 0;
2300 uinfo->value.integer.max = mask;
2301 return 0;
2302}
2303
475675d6
TI		 2304static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2305 struct snd_ctl_elem_value *ucontrol)
1bd9debf 2306{
475675d6 2307 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
1bd9debf
TI		 2308 int elem = kcontrol->private_value & 0xff;
2309 int shift = (kcontrol->private_value >> 8) & 0xff;
2310 int mask = (kcontrol->private_value >> 16) & 0xff;
2311 int invert = (kcontrol->private_value >> 24) & 1;
2312 snd_assert(dbri != NULL, return -EINVAL);
2313
2314 if (elem < 4) {
2315 ucontrol->value.integer.value[0] =
2316 (dbri->mm.data[elem] >> shift) & mask;
2317 } else {
2318 ucontrol->value.integer.value[0] =
2319 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2320 }
2321
2322 if (invert == 1) {
2323 ucontrol->value.integer.value[0] =
2324 mask - ucontrol->value.integer.value[0];
2325 }
2326 return 0;
2327}
2328
475675d6
TI		 2329static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2330 struct snd_ctl_elem_value *ucontrol)
1bd9debf 2331{
475675d6 2332 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
1bd9debf
TI		 2333 unsigned long flags;
2334 int elem = kcontrol->private_value & 0xff;
2335 int shift = (kcontrol->private_value >> 8) & 0xff;
2336 int mask = (kcontrol->private_value >> 16) & 0xff;
2337 int invert = (kcontrol->private_value >> 24) & 1;
2338 int changed = 0;
2339 unsigned short val;
2340 snd_assert(dbri != NULL, return -EINVAL);
2341
2342 val = (ucontrol->value.integer.value[0] & mask);
2343 if (invert == 1)
2344 val = mask - val;
2345 val <<= shift;
2346
2347 if (elem < 4) {
2348 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2349 ~(mask << shift)) | val;
2350 changed = (val != dbri->mm.data[elem]);
2351 } else {
2352 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2353 ~(mask << shift)) | val;
2354 changed = (val != dbri->mm.ctrl[elem - 4]);
2355 }
2356
2357 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2358 "mixer-value=%ld, mm-value=0x%x\n",
2359 mask, changed, ucontrol->value.integer.value[0],
2360 dbri->mm.data[elem & 3]);
2361
2362 if (changed) {
2363 /* First mute outputs, and wait 1/8000 sec (125 us)
2364 * to make sure this takes. This avoids clicking noises.
2365 */
2366 spin_lock_irqsave(&dbri->lock, flags);
2367
2368 cs4215_setdata(dbri, 1);
2369 udelay(125);
2370 cs4215_setdata(dbri, 0);
2371
2372 spin_unlock_irqrestore(&dbri->lock, flags);
2373 }
2374 return changed;
2375}
2376
2377/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2378 timeslots. Shift is the bit offset in the timeslot, mask defines the
2379 number of bits. invert is a boolean for use with attenuation.
2380 */
2381#define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2382{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2383 .info = snd_cs4215_info_single, \
2384 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2385 .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) },
2386
475675d6 2387static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
1bd9debf
TI		 2388 {
2389 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2390 .name = "Playback Volume",
2391 .info = snd_cs4215_info_volume,
2392 .get = snd_cs4215_get_volume,
2393 .put = snd_cs4215_put_volume,
2394 .private_value = DBRI_PLAY,
2395 },
2396 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2397 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2398 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2399 {
2400 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2401 .name = "Capture Volume",
2402 .info = snd_cs4215_info_volume,
2403 .get = snd_cs4215_get_volume,
2404 .put = snd_cs4215_put_volume,
2405 .private_value = DBRI_REC,
2406 },
2407 /* FIXME: mic/line switch */
2408 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2409 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2410 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2411 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2412};
2413
475675d6 2414#define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(struct snd_kcontrol_new))
1bd9debf 2415
475675d6 2416static int __init snd_dbri_mixer(struct snd_dbri * dbri)
1bd9debf 2417{
475675d6 2418 struct snd_card *card;
1bd9debf
TI		 2419 int idx, err;
2420
2421 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2422
2423 card = dbri->card;
2424 strcpy(card->mixername, card->shortname);
2425
2426 for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) {
2427 if ((err = snd_ctl_add(card,
4338829e 2428 snd_ctl_new1(&dbri_controls[idx], dbri))) < 0)
1bd9debf
TI		 2429 return err;
2430 }
2431
2432 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2433 dbri->stream_info[idx].left_gain = 0;
2434 dbri->stream_info[idx].right_gain = 0;
1bd9debf
TI		 2435 }
2436
2437 return 0;
2438}
2439
2440/****************************************************************************
2441 /proc interface
2442****************************************************************************/
475675d6 2443static void dbri_regs_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1bd9debf 2444{
475675d6 2445 struct snd_dbri *dbri = entry->private_data;
1bd9debf
TI		 2446
2447 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2448 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2449 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2450 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2451}
2452
2453#ifdef DBRI_DEBUG
475675d6
TI		 2454static void dbri_debug_read(struct snd_info_entry * entry,
2455 struct snd_info_buffer *buffer)
1bd9debf 2456{
475675d6 2457 struct snd_dbri *dbri = entry->private_data;
1bd9debf
TI		 2458 int pipe;
2459 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2460
1bd9debf
TI		 2461 for (pipe = 0; pipe < 32; pipe++) {
2462 if (pipe_active(dbri, pipe)) {
2463 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2464 snd_iprintf(buffer,
2465 "Pipe %d: %s SDP=0x%x desc=%d, "
5fc3a2b2 2466 "len=%d @ %d next %d\n",
1bd9debf 2467 pipe,
5fc3a2b2
KH		 2468 ((pptr->sdp & D_SDP_TO_SER) ? "output" : "input"),
2469 pptr->sdp, pptr->desc,
2470 pptr->length, pptr->cycle, pptr->nextpipe);
1bd9debf
TI		 2471 }
2472 }
2473}
1bd9debf
TI		 2474#endif
2475
475675d6 2476void snd_dbri_proc(struct snd_dbri * dbri)
1bd9debf 2477{
475675d6 2478 struct snd_info_entry *entry;
1bd9debf 2479
8cb7b63f 2480 if (! snd_card_proc_new(dbri->card, "regs", &entry))
bf850204 2481 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
1bd9debf
TI		 2482
2483#ifdef DBRI_DEBUG
8cb7b63f 2484 if (! snd_card_proc_new(dbri->card, "debug", &entry)) {
bf850204 2485 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
8cb7b63f
TI		 2486 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2487 }
1bd9debf
TI		 2488#endif
2489}
2490
2491/*
2492****************************************************************************
2493**************************** Initialization ********************************
2494****************************************************************************
2495*/
475675d6 2496static void snd_dbri_free(struct snd_dbri * dbri);
1bd9debf 2497
475675d6 2498static int __init snd_dbri_create(struct snd_card *card,
1bd9debf
TI		 2499 struct sbus_dev *sdev,
2500 struct linux_prom_irqs *irq, int dev)
2501{
475675d6 2502 struct snd_dbri *dbri = card->private_data;
1bd9debf
TI		 2503 int err;
2504
2505 spin_lock_init(&dbri->lock);
2506 dbri->card = card;
2507 dbri->sdev = sdev;
2508 dbri->irq = irq->pri;
1bd9debf
TI		 2509
2510 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2511 &dbri->dma_dvma);
2512 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2513
2514 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2515 dbri->dma, dbri->dma_dvma);
2516
2517 /* Map the registers into memory. */
2518 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2519 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2520 dbri->regs_size, "DBRI Registers");
2521 if (!dbri->regs) {
2522 printk(KERN_ERR "DBRI: could not allocate registers\n");
2523 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2524 (void *)dbri->dma, dbri->dma_dvma);
2525 return -EIO;
2526 }
2527
65ca68b3 2528 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
1bd9debf
TI		 2529 "DBRI audio", dbri);
2530 if (err) {
2531 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2532 sbus_iounmap(dbri->regs, dbri->regs_size);
2533 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2534 (void *)dbri->dma, dbri->dma_dvma);
2535 return err;
2536 }
2537
2538 /* Do low level initialization of the DBRI and CS4215 chips */
2539 dbri_initialize(dbri);
2540 err = cs4215_init(dbri);
2541 if (err) {
2542 snd_dbri_free(dbri);
2543 return err;
2544 }
2545
2546 dbri->next = dbri_list;
2547 dbri_list = dbri;
2548
2549 return 0;
2550}
2551
475675d6 2552static void snd_dbri_free(struct snd_dbri * dbri)
1bd9debf
TI		 2553{
2554 dprintk(D_GEN, "snd_dbri_free\n");
2555 dbri_reset(dbri);
2556
2557 if (dbri->irq)
2558 free_irq(dbri->irq, dbri);
2559
2560 if (dbri->regs)
2561 sbus_iounmap(dbri->regs, dbri->regs_size);
2562
2563 if (dbri->dma)
2564 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2565 (void *)dbri->dma, dbri->dma_dvma);
2566}
2567
2568static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2569{
475675d6 2570 struct snd_dbri *dbri;
1bd9debf
TI		 2571 struct linux_prom_irqs irq;
2572 struct resource *rp;
475675d6 2573 struct snd_card *card;
1bd9debf
TI		 2574 static int dev = 0;
2575 int err;
2576
2577 if (sdev->prom_name[9] < 'e') {
2578 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2579 sdev->prom_name[9]);
2580 return -EIO;
2581 }
2582
2583 if (dev >= SNDRV_CARDS)
2584 return -ENODEV;
2585 if (!enable[dev]) {
2586 dev++;
2587 return -ENOENT;
2588 }
2589
4338829e
MH		 2590 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2591 if (err < 0) {
2592 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n", dev);
2593 return -ENODEV;
2594 }
1bd9debf
TI		 2595
2596 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
475675d6 2597 sizeof(struct snd_dbri));
1bd9debf
TI		 2598 if (card == NULL)
2599 return -ENOMEM;
2600
2601 strcpy(card->driver, "DBRI");
2602 strcpy(card->shortname, "Sun DBRI");
2603 rp = &sdev->resource[0];
5863aa65 2604 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
1bd9debf 2605 card->shortname,
aa0a2ddc 2606 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri);
1bd9debf
TI		 2607
2608 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2609 snd_card_free(card);
2610 return err;
2611 }
2612
475675d6 2613 dbri = card->private_data;
16dab54b
TI		 2614 if ((err = snd_dbri_pcm(dbri)) < 0)
2615 goto _err;
1bd9debf 2616
16dab54b
TI		 2617 if ((err = snd_dbri_mixer(dbri)) < 0)
2618 goto _err;
1bd9debf
TI		 2619
2620 /* /proc file handling */
2621 snd_dbri_proc(dbri);
2622
16dab54b
TI		 2623 if ((err = snd_card_register(card)) < 0)
2624 goto _err;
1bd9debf
TI		 2625
2626 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2627 dev, dbri->regs,
5fc3a2b2 2628 dbri->irq, sdev->prom_name[9], dbri->mm.version);
1bd9debf
TI		 2629 dev++;
2630
2631 return 0;
16dab54b
TI		 2632
2633 _err:
2634 snd_dbri_free(dbri);
2635 snd_card_free(card);
2636 return err;
1bd9debf
TI		 2637}
2638
2639/* Probe for the dbri chip and then attach the driver. */
2640static int __init dbri_init(void)
2641{
2642 struct sbus_bus *sbus;
2643 struct sbus_dev *sdev;
2644 int found = 0;
2645
2646 /* Probe each SBUS for the DBRI chip(s). */
2647 for_all_sbusdev(sdev, sbus) {
2648 /*
2649 * The version is coded in the last character
2650 */
2651 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2652 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2653 sdev->prom_name, sdev->slot);
2654
2655 if (dbri_attach(sdev->prom_node, sdev) == 0)
2656 found++;
2657 }
2658 }
2659
2660 return (found > 0) ? 0 : -EIO;
2661}
2662
2663static void __exit dbri_exit(void)
2664{
475675d6 2665 struct snd_dbri *this = dbri_list;
1bd9debf
TI		 2666
2667 while (this != NULL) {
475675d6
TI		 2668 struct snd_dbri *next = this->next;
2669 struct snd_card *card = this->card;
1bd9debf
TI		 2670
2671 snd_dbri_free(this);
2672 snd_card_free(card);
2673 this = next;
2674 }
2675 dbri_list = NULL;
2676}
2677
2678module_init(dbri_init);
2679module_exit(dbri_exit);
kernel source for telekom puls (alcatel/mediatek)