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[ALSA] This simplifies and fixes waiting loops of the mce_down()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / sparc / cs4231.c
CommitLineData
1da177e4
LT		 1/*
2 * Driver for CS4231 sound chips found on Sparcs.
3 * Copyright (C) 2002 David S. Miller <davem@redhat.com>
4 *
5 * Based entirely upon drivers/sbus/audio/cs4231.c which is:
9e9abb4f 6 * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
1da177e4 7 * and also sound/isa/cs423x/cs4231_lib.c which is:
c1017a4c 8 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/delay.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/moduleparam.h>
9e9abb4f
KH		 18#include <linux/irq.h>
19#include <linux/io.h>
20
1da177e4
LT		 21
22#include <sound/driver.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/info.h>
26#include <sound/control.h>
27#include <sound/timer.h>
28#include <sound/initval.h>
29#include <sound/pcm_params.h>
30
1da177e4
LT		 31#ifdef CONFIG_SBUS
32#define SBUS_SUPPORT
1da177e4
LT		 33#include <asm/sbus.h>
34#endif
35
36#if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
37#define EBUS_SUPPORT
1da177e4
LT		 38#include <linux/pci.h>
39#include <asm/ebus.h>
40#endif
41
42static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
43static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
9e9abb4f
KH		 44/* Enable this card */
45static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
1da177e4
LT		 46
47module_param_array(index, int, NULL, 0444);
48MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
49module_param_array(id, charp, NULL, 0444);
50MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
51module_param_array(enable, bool, NULL, 0444);
52MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
53MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
54MODULE_DESCRIPTION("Sun CS4231");
55MODULE_LICENSE("GPL");
56MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
57
5a820fa7 58#ifdef SBUS_SUPPORT
be9b7e8c 59struct sbus_dma_info {
9e9abb4f
KH		 60 spinlock_t lock; /* DMA access lock */
61 int dir;
62 void __iomem *regs;
be9b7e8c 63};
5a820fa7
GC		 64#endif
65
4f3f2f6f 66struct snd_cs4231;
be9b7e8c 67struct cs4231_dma_control {
9e9abb4f
KH		 68 void (*prepare)(struct cs4231_dma_control *dma_cont,
69 int dir);
70 void (*enable)(struct cs4231_dma_control *dma_cont, int on);
71 int (*request)(struct cs4231_dma_control *dma_cont,
72 dma_addr_t bus_addr, size_t len);
73 unsigned int (*address)(struct cs4231_dma_control *dma_cont);
74 void (*preallocate)(struct snd_cs4231 *chip,
75 struct snd_pcm *pcm);
1da177e4 76#ifdef EBUS_SUPPORT
b128254f 77 struct ebus_dma_info ebus_info;
1da177e4 78#endif
5a820fa7 79#ifdef SBUS_SUPPORT
b128254f 80 struct sbus_dma_info sbus_info;
5a820fa7 81#endif
be9b7e8c 82};
b128254f
GC		 83
84struct snd_cs4231 {
9e9abb4f 85 spinlock_t lock; /* registers access lock */
b128254f
GC		 86 void __iomem *port;
87
be9b7e8c
TI		 88 struct cs4231_dma_control p_dma;
89 struct cs4231_dma_control c_dma;
5a820fa7 90
1da177e4
LT		 91 u32 flags;
92#define CS4231_FLAG_EBUS 0x00000001
93#define CS4231_FLAG_PLAYBACK 0x00000002
94#define CS4231_FLAG_CAPTURE 0x00000004
95
be9b7e8c
TI		 96 struct snd_card *card;
97 struct snd_pcm *pcm;
98 struct snd_pcm_substream *playback_substream;
1da177e4 99 unsigned int p_periods_sent;
be9b7e8c 100 struct snd_pcm_substream *capture_substream;
1da177e4 101 unsigned int c_periods_sent;
be9b7e8c 102 struct snd_timer *timer;
1da177e4
LT		 103
104 unsigned short mode;
105#define CS4231_MODE_NONE 0x0000
106#define CS4231_MODE_PLAY 0x0001
107#define CS4231_MODE_RECORD 0x0002
108#define CS4231_MODE_TIMER 0x0004
9e9abb4f
KH		 109#define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \
110 CS4231_MODE_TIMER)
1da177e4
LT		 111
112 unsigned char image[32]; /* registers image */
113 int mce_bit;
114 int calibrate_mute;
9e9abb4f
KH		 115 struct mutex mce_mutex; /* mutex for mce register */
116 struct mutex open_mutex; /* mutex for ALSA open/close */
1da177e4
LT		 117
118 union {
119#ifdef SBUS_SUPPORT
120 struct sbus_dev *sdev;
121#endif
122#ifdef EBUS_SUPPORT
123 struct pci_dev *pdev;
124#endif
125 } dev_u;
126 unsigned int irq[2];
127 unsigned int regs_size;
128 struct snd_cs4231 *next;
b128254f 129};
1da177e4 130
be9b7e8c 131static struct snd_cs4231 *cs4231_list;
1da177e4
LT		 132
133/* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
134 * now.... -DaveM
135 */
136
137/* IO ports */
138
139#define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x)
140
141/* XXX offsets are different than PC ISA chips... */
142#define c_d_c_CS4231REGSEL 0x0
143#define c_d_c_CS4231REG 0x4
144#define c_d_c_CS4231STATUS 0x8
145#define c_d_c_CS4231PIO 0xc
146
147/* codec registers */
148
149#define CS4231_LEFT_INPUT 0x00 /* left input control */
150#define CS4231_RIGHT_INPUT 0x01 /* right input control */
151#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
152#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
153#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
154#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
155#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
156#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
157#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
158#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
159#define CS4231_PIN_CTRL 0x0a /* pin control */
160#define CS4231_TEST_INIT 0x0b /* test and initialization */
161#define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
162#define CS4231_LOOPBACK 0x0d /* loopback control */
163#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
164#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
165#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
166#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
167#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
168#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
169#define CS4231_TIMER_LOW 0x14 /* timer low byte */
170#define CS4231_TIMER_HIGH 0x15 /* timer high byte */
171#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
172#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
173#define CS4236_EXT_REG 0x17 /* extended register access */
174#define CS4231_IRQ_STATUS 0x18 /* irq status register */
175#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
176#define CS4231_VERSION 0x19 /* CS4231(A) - version values */
177#define CS4231_MONO_CTRL 0x1a /* mono input/output control */
178#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
179#define CS4235_LEFT_MASTER 0x1b /* left master output control */
180#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
181#define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
182#define CS4235_RIGHT_MASTER 0x1d /* right master output control */
183#define CS4231_REC_UPR_CNT 0x1e /* record upper count */
184#define CS4231_REC_LWR_CNT 0x1f /* record lower count */
185
186/* definitions for codec register select port - CODECP( REGSEL ) */
187
188#define CS4231_INIT 0x80 /* CODEC is initializing */
189#define CS4231_MCE 0x40 /* mode change enable */
190#define CS4231_TRD 0x20 /* transfer request disable */
191
192/* definitions for codec status register - CODECP( STATUS ) */
193
194#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
195
a131430c 196/* definitions for codec irq status - CS4231_IRQ_STATUS */
1da177e4
LT		 197
198#define CS4231_PLAYBACK_IRQ 0x10
199#define CS4231_RECORD_IRQ 0x20
200#define CS4231_TIMER_IRQ 0x40
201#define CS4231_ALL_IRQS 0x70
202#define CS4231_REC_UNDERRUN 0x08
203#define CS4231_REC_OVERRUN 0x04
204#define CS4231_PLY_OVERRUN 0x02
205#define CS4231_PLY_UNDERRUN 0x01
206
207/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
208
209#define CS4231_ENABLE_MIC_GAIN 0x20
210
211#define CS4231_MIXS_LINE 0x00
212#define CS4231_MIXS_AUX1 0x40
213#define CS4231_MIXS_MIC 0x80
214#define CS4231_MIXS_ALL 0xc0
215
216/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
217
218#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
219#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
220#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
221#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
222#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
223#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
224#define CS4231_STEREO 0x10 /* stereo mode */
225/* bits 3-1 define frequency divisor */
226#define CS4231_XTAL1 0x00 /* 24.576 crystal */
227#define CS4231_XTAL2 0x01 /* 16.9344 crystal */
228
229/* definitions for interface control register - CS4231_IFACE_CTRL */
230
231#define CS4231_RECORD_PIO 0x80 /* record PIO enable */
232#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
233#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
234#define CS4231_AUTOCALIB 0x08 /* auto calibrate */
235#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
236#define CS4231_RECORD_ENABLE 0x02 /* record enable */
237#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
238
239/* definitions for pin control register - CS4231_PIN_CTRL */
240
241#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
242#define CS4231_XCTL1 0x40 /* external control #1 */
243#define CS4231_XCTL0 0x80 /* external control #0 */
244
245/* definitions for test and init register - CS4231_TEST_INIT */
246
247#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
248#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
249
250/* definitions for misc control register - CS4231_MISC_INFO */
251
252#define CS4231_MODE2 0x40 /* MODE 2 */
253#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
254#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
255
256/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
257
258#define CS4231_DACZ 0x01 /* zero DAC when underrun */
259#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
260#define CS4231_OLB 0x80 /* output level bit */
261
262/* SBUS DMA register defines. */
263
264#define APCCSR 0x10UL /* APC DMA CSR */
265#define APCCVA 0x20UL /* APC Capture DMA Address */
266#define APCCC 0x24UL /* APC Capture Count */
267#define APCCNVA 0x28UL /* APC Capture DMA Next Address */
268#define APCCNC 0x2cUL /* APC Capture Next Count */
269#define APCPVA 0x30UL /* APC Play DMA Address */
270#define APCPC 0x34UL /* APC Play Count */
271#define APCPNVA 0x38UL /* APC Play DMA Next Address */
272#define APCPNC 0x3cUL /* APC Play Next Count */
273
5a820fa7
GC		 274/* Defines for SBUS DMA-routines */
275
276#define APCVA 0x0UL /* APC DMA Address */
277#define APCC 0x4UL /* APC Count */
278#define APCNVA 0x8UL /* APC DMA Next Address */
279#define APCNC 0xcUL /* APC Next Count */
280#define APC_PLAY 0x30UL /* Play registers start at 0x30 */
281#define APC_RECORD 0x20UL /* Record registers start at 0x20 */
282
1da177e4
LT		 283/* APCCSR bits */
284
285#define APC_INT_PENDING 0x800000 /* Interrupt Pending */
286#define APC_PLAY_INT 0x400000 /* Playback interrupt */
287#define APC_CAPT_INT 0x200000 /* Capture interrupt */
288#define APC_GENL_INT 0x100000 /* General interrupt */
289#define APC_XINT_ENA 0x80000 /* General ext int. enable */
290#define APC_XINT_PLAY 0x40000 /* Playback ext intr */
291#define APC_XINT_CAPT 0x20000 /* Capture ext intr */
292#define APC_XINT_GENL 0x10000 /* Error ext intr */
293#define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
294#define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
295#define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
296#define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
297#define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
298#define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
299#define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
300#define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
301#define APC_PPAUSE 0x80 /* Pause the play DMA */
302#define APC_CPAUSE 0x40 /* Pause the capture DMA */
303#define APC_CDC_RESET 0x20 /* CODEC RESET */
304#define APC_PDMA_READY 0x08 /* Play DMA Go */
305#define APC_CDMA_READY 0x04 /* Capture DMA Go */
306#define APC_CHIP_RESET 0x01 /* Reset the chip */
307
308/* EBUS DMA register offsets */
309
310#define EBDMA_CSR 0x00UL /* Control/Status */
311#define EBDMA_ADDR 0x04UL /* DMA Address */
312#define EBDMA_COUNT 0x08UL /* DMA Count */
313
314/*
315 * Some variables
316 */
317
318static unsigned char freq_bits[14] = {
319 /* 5510 */ 0x00 | CS4231_XTAL2,
320 /* 6620 */ 0x0E | CS4231_XTAL2,
321 /* 8000 */ 0x00 | CS4231_XTAL1,
322 /* 9600 */ 0x0E | CS4231_XTAL1,
323 /* 11025 */ 0x02 | CS4231_XTAL2,
324 /* 16000 */ 0x02 | CS4231_XTAL1,
325 /* 18900 */ 0x04 | CS4231_XTAL2,
326 /* 22050 */ 0x06 | CS4231_XTAL2,
327 /* 27042 */ 0x04 | CS4231_XTAL1,
328 /* 32000 */ 0x06 | CS4231_XTAL1,
329 /* 33075 */ 0x0C | CS4231_XTAL2,
330 /* 37800 */ 0x08 | CS4231_XTAL2,
331 /* 44100 */ 0x0A | CS4231_XTAL2,
332 /* 48000 */ 0x0C | CS4231_XTAL1
333};
334
335static unsigned int rates[14] = {
336 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
337 27042, 32000, 33075, 37800, 44100, 48000
338};
339
be9b7e8c 340static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
c6c2d57b 341 .count = ARRAY_SIZE(rates),
1da177e4
LT		 342 .list = rates,
343};
344
be9b7e8c 345static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
1da177e4
LT		 346{
347 return snd_pcm_hw_constraint_list(runtime, 0,
348 SNDRV_PCM_HW_PARAM_RATE,
349 &hw_constraints_rates);
350}
351
352static unsigned char snd_cs4231_original_image[32] =
353{
354 0x00, /* 00/00 - lic */
355 0x00, /* 01/01 - ric */
356 0x9f, /* 02/02 - la1ic */
357 0x9f, /* 03/03 - ra1ic */
358 0x9f, /* 04/04 - la2ic */
359 0x9f, /* 05/05 - ra2ic */
360 0xbf, /* 06/06 - loc */
361 0xbf, /* 07/07 - roc */
362 0x20, /* 08/08 - pdfr */
363 CS4231_AUTOCALIB, /* 09/09 - ic */
364 0x00, /* 0a/10 - pc */
365 0x00, /* 0b/11 - ti */
366 CS4231_MODE2, /* 0c/12 - mi */
367 0x00, /* 0d/13 - lbc */
368 0x00, /* 0e/14 - pbru */
369 0x00, /* 0f/15 - pbrl */
370 0x80, /* 10/16 - afei */
371 0x01, /* 11/17 - afeii */
372 0x9f, /* 12/18 - llic */
373 0x9f, /* 13/19 - rlic */
374 0x00, /* 14/20 - tlb */
375 0x00, /* 15/21 - thb */
376 0x00, /* 16/22 - la3mic/reserved */
377 0x00, /* 17/23 - ra3mic/reserved */
378 0x00, /* 18/24 - afs */
379 0x00, /* 19/25 - lamoc/version */
380 0x00, /* 1a/26 - mioc */
381 0x00, /* 1b/27 - ramoc/reserved */
382 0x20, /* 1c/28 - cdfr */
383 0x00, /* 1d/29 - res4 */
384 0x00, /* 1e/30 - cbru */
385 0x00, /* 1f/31 - cbrl */
386};
387
be9b7e8c 388static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
1da177e4
LT		 389{
390#ifdef EBUS_SUPPORT
c6c2d57b 391 if (cp->flags & CS4231_FLAG_EBUS)
1da177e4 392 return readb(reg_addr);
c6c2d57b 393 else
1da177e4
LT		 394#endif
395#ifdef SBUS_SUPPORT
396 return sbus_readb(reg_addr);
397#endif
1da177e4
LT		 398}
399
9e9abb4f
KH		 400static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val,
401 void __iomem *reg_addr)
1da177e4
LT		 402{
403#ifdef EBUS_SUPPORT
c6c2d57b 404 if (cp->flags & CS4231_FLAG_EBUS)
1da177e4 405 return writeb(val, reg_addr);
c6c2d57b 406 else
1da177e4
LT		 407#endif
408#ifdef SBUS_SUPPORT
409 return sbus_writeb(val, reg_addr);
410#endif
1da177e4
LT		 411}
412
413/*
414 * Basic I/O functions
415 */
416
c6c2d57b 417static void snd_cs4231_ready(struct snd_cs4231 *chip)
1da177e4
LT		 418{
419 int timeout;
1da177e4
LT		 420
421 for (timeout = 250;
422 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
423 timeout--)
424 udelay(100);
1da177e4
LT		 425}
426
9e9abb4f
KH		 427static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
428 unsigned char value)
1da177e4 429{
c6c2d57b 430 snd_cs4231_ready(chip);
a131430c
CZ		 431#ifdef CONFIG_SND_DEBUG
432 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
c6c2d57b
KH		 433 snd_printdd("out: auto calibration time out - reg = 0x%x, "
434 "value = 0x%x\n",
435 reg, value);
a131430c 436#endif
1da177e4 437 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
c6c2d57b 438 wmb();
1da177e4
LT		 439 __cs4231_writeb(chip, value, CS4231P(chip, REG));
440 mb();
441}
442
c6c2d57b
KH		 443static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
444 unsigned char mask, unsigned char value)
1da177e4 445{
c6c2d57b 446 unsigned char tmp = (chip->image[reg] & mask) | value;
1da177e4 447
c6c2d57b
KH		 448 chip->image[reg] = tmp;
449 if (!chip->calibrate_mute)
450 snd_cs4231_dout(chip, reg, tmp);
451}
452
453static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
454 unsigned char value)
455{
456 snd_cs4231_dout(chip, reg, value);
1da177e4
LT		 457 chip->image[reg] = value;
458 mb();
1da177e4
LT		 459}
460
be9b7e8c 461static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
1da177e4 462{
c6c2d57b 463 snd_cs4231_ready(chip);
1da177e4
LT		 464#ifdef CONFIG_SND_DEBUG
465 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
c6c2d57b
KH		 466 snd_printdd("in: auto calibration time out - reg = 0x%x\n",
467 reg);
1da177e4
LT		 468#endif
469 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
470 mb();
c6c2d57b 471 return __cs4231_readb(chip, CS4231P(chip, REG));
1da177e4
LT		 472}
473
1da177e4
LT		 474/*
475 * CS4231 detection / MCE routines
476 */
477
be9b7e8c 478static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
1da177e4
LT		 479{
480 int timeout;
481
9e9abb4f 482 /* looks like this sequence is proper for CS4231A chip (GUS MAX) */
1da177e4
LT		 483 for (timeout = 5; timeout > 0; timeout--)
484 __cs4231_readb(chip, CS4231P(chip, REGSEL));
a131430c 485
1da177e4 486 /* end of cleanup sequence */
a131430c 487 for (timeout = 500;
1da177e4
LT		 488 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
489 timeout--)
c6c2d57b 490 msleep(1);
1da177e4
LT		 491}
492
be9b7e8c 493static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
1da177e4
LT		 494{
495 unsigned long flags;
496 int timeout;
497
498 spin_lock_irqsave(&chip->lock, flags);
c6c2d57b 499 snd_cs4231_ready(chip);
1da177e4
LT		 500#ifdef CONFIG_SND_DEBUG
501 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
a131430c 502 snd_printdd("mce_up - auto calibration time out (0)\n");
1da177e4
LT		 503#endif
504 chip->mce_bit |= CS4231_MCE;
505 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
506 if (timeout == 0x80)
9e9abb4f
KH		 507 snd_printdd("mce_up [%p]: serious init problem - "
508 "codec still busy\n",
509 chip->port);
1da177e4
LT		 510 if (!(timeout & CS4231_MCE))
511 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
512 spin_unlock_irqrestore(&chip->lock, flags);
513}
514
be9b7e8c 515static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
1da177e4
LT		 516{
517 unsigned long flags;
518 int timeout;
519
520 spin_lock_irqsave(&chip->lock, flags);
521 snd_cs4231_busy_wait(chip);
1da177e4
LT		 522#ifdef CONFIG_SND_DEBUG
523 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
a131430c 524 snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
1da177e4
LT		 525#endif
526 chip->mce_bit &= ~CS4231_MCE;
527 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
528 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
529 if (timeout == 0x80)
9e9abb4f
KH		 530 snd_printdd("mce_down [%p]: serious init problem - "
531 "codec still busy\n",
532 chip->port);
1da177e4
LT		 533 if ((timeout & CS4231_MCE) == 0) {
534 spin_unlock_irqrestore(&chip->lock, flags);
535 return;
536 }
537 snd_cs4231_busy_wait(chip);
538
539 /* calibration process */
540
c6c2d57b
KH		 541 snd_cs4231_ready(chip);
542 snd_cs4231_ready(chip);
9e9abb4f
KH		 543 timeout = snd_cs4231_in(chip, CS4231_TEST_INIT);
544 if ((timeout & CS4231_CALIB_IN_PROGRESS) == 0) {
1da177e4
LT		 545 snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
546 spin_unlock_irqrestore(&chip->lock, flags);
547 return;
548 }
a131430c 549
1da177e4
LT		 550 /* in 10ms increments, check condition, up to 250ms */
551 timeout = 25;
9e9abb4f
KH		 552 while (snd_cs4231_in(chip, CS4231_TEST_INIT) &
553 CS4231_CALIB_IN_PROGRESS) {
554
1da177e4
LT		 555 spin_unlock_irqrestore(&chip->lock, flags);
556 if (--timeout < 0) {
9e9abb4f
KH		 557 snd_printk("mce_down - "
558 "auto calibration time out (2)\n");
1da177e4
LT		 559 return;
560 }
561 msleep(10);
562 spin_lock_irqsave(&chip->lock, flags);
563 }
a131430c 564
1da177e4
LT		 565 /* in 10ms increments, check condition, up to 100ms */
566 timeout = 10;
567 while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
568 spin_unlock_irqrestore(&chip->lock, flags);
569 if (--timeout < 0) {
9e9abb4f
KH		 570 snd_printk("mce_down - "
571 "auto calibration time out (3)\n");
1da177e4
LT		 572 return;
573 }
574 msleep(10);
575 spin_lock_irqsave(&chip->lock, flags);
576 }
577 spin_unlock_irqrestore(&chip->lock, flags);
1da177e4
LT		 578}
579
be9b7e8c
TI		 580static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
581 struct snd_pcm_substream *substream,
582 unsigned int *periods_sent)
1da177e4 583{
be9b7e8c 584 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 585
586 while (1) {
a131430c
CZ		 587 unsigned int period_size = snd_pcm_lib_period_bytes(substream);
588 unsigned int offset = period_size * (*periods_sent);
1da177e4 589
817dd6ee 590 BUG_ON(period_size >= (1 << 24));
1da177e4 591
9e9abb4f
KH		 592 if (dma_cont->request(dma_cont,
593 runtime->dma_addr + offset, period_size))
1da177e4 594 return;
1da177e4
LT		 595 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
596 }
597}
a131430c 598
be9b7e8c
TI		 599static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
600 unsigned int what, int on)
1da177e4 601{
be9b7e8c
TI		 602 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
603 struct cs4231_dma_control *dma_cont;
a131430c 604
5a820fa7 605 if (what & CS4231_PLAYBACK_ENABLE) {
b128254f 606 dma_cont = &chip->p_dma;
a131430c 607 if (on) {
b128254f
GC		 608 dma_cont->prepare(dma_cont, 0);
609 dma_cont->enable(dma_cont, 1);
610 snd_cs4231_advance_dma(dma_cont,
5a820fa7
GC		 611 chip->playback_substream,
612 &chip->p_periods_sent);
a131430c 613 } else {
b128254f 614 dma_cont->enable(dma_cont, 0);
a131430c 615 }
5a820fa7
GC		 616 }
617 if (what & CS4231_RECORD_ENABLE) {
b128254f 618 dma_cont = &chip->c_dma;
a131430c 619 if (on) {
b128254f
GC		 620 dma_cont->prepare(dma_cont, 1);
621 dma_cont->enable(dma_cont, 1);
622 snd_cs4231_advance_dma(dma_cont,
5a820fa7
GC		 623 chip->capture_substream,
624 &chip->c_periods_sent);
a131430c 625 } else {
b128254f 626 dma_cont->enable(dma_cont, 0);
a131430c 627 }
a131430c 628 }
1da177e4
LT		 629}
630
be9b7e8c 631static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 632{
be9b7e8c 633 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 634 int result = 0;
635
636 switch (cmd) {
637 case SNDRV_PCM_TRIGGER_START:
638 case SNDRV_PCM_TRIGGER_STOP:
639 {
640 unsigned int what = 0;
be9b7e8c 641 struct snd_pcm_substream *s;
1da177e4
LT		 642 unsigned long flags;
643
ef991b95 644 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 645 if (s == chip->playback_substream) {
646 what |= CS4231_PLAYBACK_ENABLE;
647 snd_pcm_trigger_done(s, substream);
648 } else if (s == chip->capture_substream) {
649 what |= CS4231_RECORD_ENABLE;
650 snd_pcm_trigger_done(s, substream);
651 }
652 }
653
1da177e4
LT		 654 spin_lock_irqsave(&chip->lock, flags);
655 if (cmd == SNDRV_PCM_TRIGGER_START) {
a131430c 656 cs4231_dma_trigger(substream, what, 1);
1da177e4 657 chip->image[CS4231_IFACE_CTRL] |= what;
1da177e4 658 } else {
a131430c 659 cs4231_dma_trigger(substream, what, 0);
1da177e4
LT		 660 chip->image[CS4231_IFACE_CTRL] &= ~what;
661 }
662 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
663 chip->image[CS4231_IFACE_CTRL]);
664 spin_unlock_irqrestore(&chip->lock, flags);
665 break;
666 }
667 default:
668 result = -EINVAL;
669 break;
670 }
a131430c 671
1da177e4
LT		 672 return result;
673}
674
675/*
676 * CODEC I/O
677 */
678
679static unsigned char snd_cs4231_get_rate(unsigned int rate)
680{
681 int i;
682
683 for (i = 0; i < 14; i++)
684 if (rate == rates[i])
685 return freq_bits[i];
9e9abb4f 686
1da177e4
LT		 687 return freq_bits[13];
688}
689
9e9abb4f
KH		 690static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format,
691 int channels)
1da177e4
LT		 692{
693 unsigned char rformat;
694
695 rformat = CS4231_LINEAR_8;
696 switch (format) {
9e9abb4f
KH		 697 case SNDRV_PCM_FORMAT_MU_LAW:
698 rformat = CS4231_ULAW_8;
699 break;
700 case SNDRV_PCM_FORMAT_A_LAW:
701 rformat = CS4231_ALAW_8;
702 break;
703 case SNDRV_PCM_FORMAT_S16_LE:
704 rformat = CS4231_LINEAR_16;
705 break;
706 case SNDRV_PCM_FORMAT_S16_BE:
707 rformat = CS4231_LINEAR_16_BIG;
708 break;
709 case SNDRV_PCM_FORMAT_IMA_ADPCM:
710 rformat = CS4231_ADPCM_16;
711 break;
1da177e4
LT		 712 }
713 if (channels > 1)
714 rformat |= CS4231_STEREO;
1da177e4
LT		 715 return rformat;
716}
717
be9b7e8c 718static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
1da177e4
LT		 719{
720 unsigned long flags;
721
722 mute = mute ? 1 : 0;
723 spin_lock_irqsave(&chip->lock, flags);
724 if (chip->calibrate_mute == mute) {
725 spin_unlock_irqrestore(&chip->lock, flags);
726 return;
727 }
728 if (!mute) {
729 snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
730 chip->image[CS4231_LEFT_INPUT]);
731 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
732 chip->image[CS4231_RIGHT_INPUT]);
733 snd_cs4231_dout(chip, CS4231_LOOPBACK,
734 chip->image[CS4231_LOOPBACK]);
735 }
736 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
737 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
738 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
739 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
740 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
741 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
742 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
743 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
744 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
745 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
746 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
747 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
748 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
749 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
750 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
751 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
752 snd_cs4231_dout(chip, CS4231_MONO_CTRL,
753 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
754 chip->calibrate_mute = mute;
755 spin_unlock_irqrestore(&chip->lock, flags);
756}
757
9e9abb4f
KH		 758static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
759 struct snd_pcm_hw_params *params,
1da177e4
LT		 760 unsigned char pdfr)
761{
762 unsigned long flags;
763
12aa7579 764 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 765 snd_cs4231_calibrate_mute(chip, 1);
766
767 snd_cs4231_mce_up(chip);
768
769 spin_lock_irqsave(&chip->lock, flags);
770 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
771 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
772 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
773 pdfr);
774 spin_unlock_irqrestore(&chip->lock, flags);
775
776 snd_cs4231_mce_down(chip);
777
778 snd_cs4231_calibrate_mute(chip, 0);
12aa7579 779 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 780}
781
9e9abb4f
KH		 782static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
783 struct snd_pcm_hw_params *params,
784 unsigned char cdfr)
1da177e4
LT		 785{
786 unsigned long flags;
787
12aa7579 788 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 789 snd_cs4231_calibrate_mute(chip, 1);
790
791 snd_cs4231_mce_up(chip);
792
793 spin_lock_irqsave(&chip->lock, flags);
794 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
795 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
796 ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
797 (cdfr & 0x0f));
798 spin_unlock_irqrestore(&chip->lock, flags);
799 snd_cs4231_mce_down(chip);
800 snd_cs4231_mce_up(chip);
801 spin_lock_irqsave(&chip->lock, flags);
802 }
803 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
804 spin_unlock_irqrestore(&chip->lock, flags);
805
806 snd_cs4231_mce_down(chip);
807
808 snd_cs4231_calibrate_mute(chip, 0);
12aa7579 809 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 810}
811
812/*
813 * Timer interface
814 */
815
be9b7e8c 816static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
1da177e4 817{
be9b7e8c 818 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 819
820 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
821}
822
be9b7e8c 823static int snd_cs4231_timer_start(struct snd_timer *timer)
1da177e4
LT		 824{
825 unsigned long flags;
826 unsigned int ticks;
be9b7e8c 827 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 828
829 spin_lock_irqsave(&chip->lock, flags);
830 ticks = timer->sticks;
831 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
832 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
833 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
834 snd_cs4231_out(chip, CS4231_TIMER_HIGH,
835 chip->image[CS4231_TIMER_HIGH] =
836 (unsigned char) (ticks >> 8));
837 snd_cs4231_out(chip, CS4231_TIMER_LOW,
838 chip->image[CS4231_TIMER_LOW] =
839 (unsigned char) ticks);
840 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
9e9abb4f
KH		 841 chip->image[CS4231_ALT_FEATURE_1] |
842 CS4231_TIMER_ENABLE);
1da177e4
LT		 843 }
844 spin_unlock_irqrestore(&chip->lock, flags);
845
846 return 0;
847}
848
be9b7e8c 849static int snd_cs4231_timer_stop(struct snd_timer *timer)
1da177e4
LT		 850{
851 unsigned long flags;
be9b7e8c 852 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 853
854 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f 855 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
1da177e4 856 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
9e9abb4f 857 chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 858 spin_unlock_irqrestore(&chip->lock, flags);
859
860 return 0;
861}
862
be9b7e8c 863static void __init snd_cs4231_init(struct snd_cs4231 *chip)
1da177e4
LT		 864{
865 unsigned long flags;
866
867 snd_cs4231_mce_down(chip);
868
869#ifdef SNDRV_DEBUG_MCE
a131430c 870 snd_printdd("init: (1)\n");
1da177e4
LT		 871#endif
872 snd_cs4231_mce_up(chip);
873 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 874 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
875 CS4231_PLAYBACK_PIO |
876 CS4231_RECORD_ENABLE |
877 CS4231_RECORD_PIO |
1da177e4
LT		 878 CS4231_CALIB_MODE);
879 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
880 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
881 spin_unlock_irqrestore(&chip->lock, flags);
882 snd_cs4231_mce_down(chip);
883
884#ifdef SNDRV_DEBUG_MCE
a131430c 885 snd_printdd("init: (2)\n");
1da177e4
LT		 886#endif
887
888 snd_cs4231_mce_up(chip);
889 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 890 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
891 chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 892 spin_unlock_irqrestore(&chip->lock, flags);
893 snd_cs4231_mce_down(chip);
894
895#ifdef SNDRV_DEBUG_MCE
9e9abb4f
KH		 896 snd_printdd("init: (3) - afei = 0x%x\n",
897 chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 898#endif
899
900 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 901 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2,
902 chip->image[CS4231_ALT_FEATURE_2]);
1da177e4
LT		 903 spin_unlock_irqrestore(&chip->lock, flags);
904
905 snd_cs4231_mce_up(chip);
906 spin_lock_irqsave(&chip->lock, flags);
9e9abb4f
KH		 907 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
908 chip->image[CS4231_PLAYBK_FORMAT]);
1da177e4
LT		 909 spin_unlock_irqrestore(&chip->lock, flags);
910 snd_cs4231_mce_down(chip);
911
912#ifdef SNDRV_DEBUG_MCE
a131430c 913 snd_printdd("init: (4)\n");
1da177e4
LT		 914#endif
915
916 snd_cs4231_mce_up(chip);
917 spin_lock_irqsave(&chip->lock, flags);
918 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
919 spin_unlock_irqrestore(&chip->lock, flags);
920 snd_cs4231_mce_down(chip);
921
922#ifdef SNDRV_DEBUG_MCE
a131430c 923 snd_printdd("init: (5)\n");
1da177e4
LT		 924#endif
925}
926
be9b7e8c 927static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 928{
929 unsigned long flags;
930
12aa7579 931 mutex_lock(&chip->open_mutex);
1da177e4 932 if ((chip->mode & mode)) {
12aa7579 933 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 934 return -EAGAIN;
935 }
936 if (chip->mode & CS4231_MODE_OPEN) {
937 chip->mode |= mode;
12aa7579 938 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 939 return 0;
940 }
941 /* ok. now enable and ack CODEC IRQ */
942 spin_lock_irqsave(&chip->lock, flags);
943 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
944 CS4231_RECORD_IRQ |
945 CS4231_TIMER_IRQ);
946 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
947 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
948 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
949
950 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
951 CS4231_RECORD_IRQ |
952 CS4231_TIMER_IRQ);
953 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
a131430c 954
1da177e4
LT		 955 spin_unlock_irqrestore(&chip->lock, flags);
956
957 chip->mode = mode;
12aa7579 958 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 959 return 0;
960}
961
be9b7e8c 962static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 963{
964 unsigned long flags;
965
12aa7579 966 mutex_lock(&chip->open_mutex);
1da177e4
LT		 967 chip->mode &= ~mode;
968 if (chip->mode & CS4231_MODE_OPEN) {
12aa7579 969 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 970 return;
971 }
972 snd_cs4231_calibrate_mute(chip, 1);
973
974 /* disable IRQ */
975 spin_lock_irqsave(&chip->lock, flags);
976 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
977 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
978 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
979
980 /* now disable record & playback */
981
982 if (chip->image[CS4231_IFACE_CTRL] &
983 (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
984 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
985 spin_unlock_irqrestore(&chip->lock, flags);
986 snd_cs4231_mce_up(chip);
987 spin_lock_irqsave(&chip->lock, flags);
988 chip->image[CS4231_IFACE_CTRL] &=
989 ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
990 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
9e9abb4f
KH		 991 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
992 chip->image[CS4231_IFACE_CTRL]);
1da177e4
LT		 993 spin_unlock_irqrestore(&chip->lock, flags);
994 snd_cs4231_mce_down(chip);
995 spin_lock_irqsave(&chip->lock, flags);
996 }
997
998 /* clear IRQ again */
999 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1000 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1001 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1002 spin_unlock_irqrestore(&chip->lock, flags);
1003
1004 snd_cs4231_calibrate_mute(chip, 0);
1005
1006 chip->mode = 0;
12aa7579 1007 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1008}
1009
1010/*
1011 * timer open/close
1012 */
1013
be9b7e8c 1014static int snd_cs4231_timer_open(struct snd_timer *timer)
1da177e4 1015{
be9b7e8c 1016 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 1017 snd_cs4231_open(chip, CS4231_MODE_TIMER);
1018 return 0;
1019}
1020
9e9abb4f 1021static int snd_cs4231_timer_close(struct snd_timer *timer)
1da177e4 1022{
be9b7e8c 1023 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 1024 snd_cs4231_close(chip, CS4231_MODE_TIMER);
1025 return 0;
1026}
1027
9e9abb4f 1028static struct snd_timer_hardware snd_cs4231_timer_table = {
1da177e4
LT		 1029 .flags = SNDRV_TIMER_HW_AUTO,
1030 .resolution = 9945,
1031 .ticks = 65535,
1032 .open = snd_cs4231_timer_open,
1033 .close = snd_cs4231_timer_close,
1034 .c_resolution = snd_cs4231_timer_resolution,
1035 .start = snd_cs4231_timer_start,
1036 .stop = snd_cs4231_timer_stop,
1037};
1038
1039/*
1040 * ok.. exported functions..
1041 */
1042
be9b7e8c
TI		 1043static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
1044 struct snd_pcm_hw_params *hw_params)
1da177e4 1045{
be9b7e8c 1046 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1047 unsigned char new_pdfr;
1048 int err;
1049
9e9abb4f
KH		 1050 err = snd_pcm_lib_malloc_pages(substream,
1051 params_buffer_bytes(hw_params));
1052 if (err < 0)
1da177e4
LT		 1053 return err;
1054 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1055 params_channels(hw_params)) |
1056 snd_cs4231_get_rate(params_rate(hw_params));
1057 snd_cs4231_playback_format(chip, hw_params, new_pdfr);
1058
1059 return 0;
1060}
1061
be9b7e8c 1062static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1063{
be9b7e8c
TI		 1064 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1065 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1066 unsigned long flags;
1067
1068 spin_lock_irqsave(&chip->lock, flags);
a131430c 1069
1da177e4
LT		 1070 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
1071 CS4231_PLAYBACK_PIO);
a131430c 1072
817dd6ee 1073 BUG_ON(runtime->period_size > 0xffff + 1);
a131430c 1074
a131430c 1075 chip->p_periods_sent = 0;
1da177e4
LT		 1076 spin_unlock_irqrestore(&chip->lock, flags);
1077
1078 return 0;
1079}
1080
be9b7e8c
TI		 1081static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
1082 struct snd_pcm_hw_params *hw_params)
1da177e4 1083{
be9b7e8c 1084 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1085 unsigned char new_cdfr;
1086 int err;
1087
9e9abb4f
KH		 1088 err = snd_pcm_lib_malloc_pages(substream,
1089 params_buffer_bytes(hw_params));
1090 if (err < 0)
1da177e4
LT		 1091 return err;
1092 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1093 params_channels(hw_params)) |
1094 snd_cs4231_get_rate(params_rate(hw_params));
1095 snd_cs4231_capture_format(chip, hw_params, new_cdfr);
1096
1097 return 0;
1098}
1099
be9b7e8c 1100static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1101{
be9b7e8c 1102 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1103 unsigned long flags;
1104
1105 spin_lock_irqsave(&chip->lock, flags);
1106 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
1107 CS4231_RECORD_PIO);
1108
a131430c 1109
5a820fa7 1110 chip->c_periods_sent = 0;
1da177e4
LT		 1111 spin_unlock_irqrestore(&chip->lock, flags);
1112
1113 return 0;
1114}
1115
be9b7e8c 1116static void snd_cs4231_overrange(struct snd_cs4231 *chip)
1da177e4
LT		 1117{
1118 unsigned long flags;
1119 unsigned char res;
1120
1121 spin_lock_irqsave(&chip->lock, flags);
1122 res = snd_cs4231_in(chip, CS4231_TEST_INIT);
1123 spin_unlock_irqrestore(&chip->lock, flags);
1124
9e9abb4f
KH		 1125 /* detect overrange only above 0dB; may be user selectable? */
1126 if (res & (0x08 | 0x02))
1da177e4
LT		 1127 chip->capture_substream->runtime->overrange++;
1128}
1129
be9b7e8c 1130static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
1da177e4 1131{
1da177e4
LT		 1132 if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
1133 snd_pcm_period_elapsed(chip->playback_substream);
b128254f 1134 snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
1da177e4
LT		 1135 &chip->p_periods_sent);
1136 }
1137}
1138
be9b7e8c 1139static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
1da177e4 1140{
1da177e4
LT		 1141 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
1142 snd_pcm_period_elapsed(chip->capture_substream);
b128254f 1143 snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
1da177e4
LT		 1144 &chip->c_periods_sent);
1145 }
1146}
1da177e4 1147
9e9abb4f
KH		 1148static snd_pcm_uframes_t snd_cs4231_playback_pointer(
1149 struct snd_pcm_substream *substream)
1da177e4 1150{
be9b7e8c
TI		 1151 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1152 struct cs4231_dma_control *dma_cont = &chip->p_dma;
5a820fa7 1153 size_t ptr;
9e9abb4f 1154
1da177e4
LT		 1155 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1156 return 0;
b128254f
GC		 1157 ptr = dma_cont->address(dma_cont);
1158 if (ptr != 0)
1159 ptr -= substream->runtime->dma_addr;
9e9abb4f 1160
1da177e4
LT		 1161 return bytes_to_frames(substream->runtime, ptr);
1162}
1163
9e9abb4f
KH		 1164static snd_pcm_uframes_t snd_cs4231_capture_pointer(
1165 struct snd_pcm_substream *substream)
1da177e4 1166{
be9b7e8c
TI		 1167 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1168 struct cs4231_dma_control *dma_cont = &chip->c_dma;
5a820fa7 1169 size_t ptr;
9e9abb4f 1170
1da177e4
LT		 1171 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1172 return 0;
b128254f
GC		 1173 ptr = dma_cont->address(dma_cont);
1174 if (ptr != 0)
1175 ptr -= substream->runtime->dma_addr;
9e9abb4f 1176
1da177e4
LT		 1177 return bytes_to_frames(substream->runtime, ptr);
1178}
1179
be9b7e8c 1180static int __init snd_cs4231_probe(struct snd_cs4231 *chip)
1da177e4
LT		 1181{
1182 unsigned long flags;
9e9abb4f
KH		 1183 int i;
1184 int id = 0;
1185 int vers = 0;
1da177e4
LT		 1186 unsigned char *ptr;
1187
1da177e4
LT		 1188 for (i = 0; i < 50; i++) {
1189 mb();
1190 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
9e9abb4f 1191 msleep(2);
1da177e4
LT		 1192 else {
1193 spin_lock_irqsave(&chip->lock, flags);
1194 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1195 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
1196 vers = snd_cs4231_in(chip, CS4231_VERSION);
1197 spin_unlock_irqrestore(&chip->lock, flags);
1198 if (id == 0x0a)
1199 break; /* this is valid value */
1200 }
1201 }
1202 snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
1203 if (id != 0x0a)
1204 return -ENODEV; /* no valid device found */
1205
1206 spin_lock_irqsave(&chip->lock, flags);
1207
1da177e4
LT		 1208 __cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */
1209 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));
1210 mb();
1211
1212 spin_unlock_irqrestore(&chip->lock, flags);
1213
1214 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1215 chip->image[CS4231_IFACE_CTRL] =
1216 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
1217 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1218 chip->image[CS4231_ALT_FEATURE_2] = 0x01;
1219 if (vers & 0x20)
1220 chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
1221
1222 ptr = (unsigned char *) &chip->image;
1223
1224 snd_cs4231_mce_down(chip);
1225
1226 spin_lock_irqsave(&chip->lock, flags);
1227
1228 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
1229 snd_cs4231_out(chip, i, *ptr++);
1230
1231 spin_unlock_irqrestore(&chip->lock, flags);
1232
1233 snd_cs4231_mce_up(chip);
1234
1235 snd_cs4231_mce_down(chip);
1236
1237 mdelay(2);
1238
1239 return 0; /* all things are ok.. */
1240}
1241
9e9abb4f
KH		 1242static struct snd_pcm_hardware snd_cs4231_playback = {
1243 .info = SNDRV_PCM_INFO_MMAP |
1244 SNDRV_PCM_INFO_INTERLEAVED |
1245 SNDRV_PCM_INFO_MMAP_VALID |
1246 SNDRV_PCM_INFO_SYNC_START,
1247 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1248 SNDRV_PCM_FMTBIT_A_LAW |
1249 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1250 SNDRV_PCM_FMTBIT_U8 |
1251 SNDRV_PCM_FMTBIT_S16_LE |
1252 SNDRV_PCM_FMTBIT_S16_BE,
1253 .rates = SNDRV_PCM_RATE_KNOT |
1254 SNDRV_PCM_RATE_8000_48000,
1da177e4
LT		 1255 .rate_min = 5510,
1256 .rate_max = 48000,
1257 .channels_min = 1,
1258 .channels_max = 2,
9e9abb4f 1259 .buffer_bytes_max = 32 * 1024,
f9af1d9d 1260 .period_bytes_min = 64,
9e9abb4f 1261 .period_bytes_max = 32 * 1024,
1da177e4
LT		 1262 .periods_min = 1,
1263 .periods_max = 1024,
1264};
1265
9e9abb4f
KH		 1266static struct snd_pcm_hardware snd_cs4231_capture = {
1267 .info = SNDRV_PCM_INFO_MMAP |
1268 SNDRV_PCM_INFO_INTERLEAVED |
1269 SNDRV_PCM_INFO_MMAP_VALID |
1270 SNDRV_PCM_INFO_SYNC_START,
1271 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1272 SNDRV_PCM_FMTBIT_A_LAW |
1273 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1274 SNDRV_PCM_FMTBIT_U8 |
1275 SNDRV_PCM_FMTBIT_S16_LE |
1276 SNDRV_PCM_FMTBIT_S16_BE,
1277 .rates = SNDRV_PCM_RATE_KNOT |
1278 SNDRV_PCM_RATE_8000_48000,
1da177e4
LT		 1279 .rate_min = 5510,
1280 .rate_max = 48000,
1281 .channels_min = 1,
1282 .channels_max = 2,
9e9abb4f 1283 .buffer_bytes_max = 32 * 1024,
f9af1d9d 1284 .period_bytes_min = 64,
9e9abb4f 1285 .period_bytes_max = 32 * 1024,
1da177e4
LT		 1286 .periods_min = 1,
1287 .periods_max = 1024,
1288};
1289
be9b7e8c 1290static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
1da177e4 1291{
be9b7e8c
TI		 1292 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1293 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1294 int err;
1295
1296 runtime->hw = snd_cs4231_playback;
1297
9e9abb4f
KH		 1298 err = snd_cs4231_open(chip, CS4231_MODE_PLAY);
1299 if (err < 0) {
1da177e4
LT		 1300 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1301 return err;
1302 }
1303 chip->playback_substream = substream;
1304 chip->p_periods_sent = 0;
1305 snd_pcm_set_sync(substream);
1306 snd_cs4231_xrate(runtime);
1307
1308 return 0;
1309}
1310
be9b7e8c 1311static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
1da177e4 1312{
be9b7e8c
TI		 1313 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1314 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1315 int err;
1316
1317 runtime->hw = snd_cs4231_capture;
1318
9e9abb4f
KH		 1319 err = snd_cs4231_open(chip, CS4231_MODE_RECORD);
1320 if (err < 0) {
1da177e4
LT		 1321 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1322 return err;
1323 }
1324 chip->capture_substream = substream;
1325 chip->c_periods_sent = 0;
1326 snd_pcm_set_sync(substream);
1327 snd_cs4231_xrate(runtime);
1328
1329 return 0;
1330}
1331
be9b7e8c 1332static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
1da177e4 1333{
be9b7e8c 1334 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4 1335
1da177e4 1336 snd_cs4231_close(chip, CS4231_MODE_PLAY);
b128254f 1337 chip->playback_substream = NULL;
1da177e4
LT		 1338
1339 return 0;
1340}
1341
be9b7e8c 1342static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
1da177e4 1343{
be9b7e8c 1344 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4 1345
1da177e4 1346 snd_cs4231_close(chip, CS4231_MODE_RECORD);
b128254f 1347 chip->capture_substream = NULL;
1da177e4
LT		 1348
1349 return 0;
1350}
1351
1352/* XXX We can do some power-management, in particular on EBUS using
1353 * XXX the audio AUXIO register...
1354 */
1355
be9b7e8c 1356static struct snd_pcm_ops snd_cs4231_playback_ops = {
1da177e4
LT		 1357 .open = snd_cs4231_playback_open,
1358 .close = snd_cs4231_playback_close,
1359 .ioctl = snd_pcm_lib_ioctl,
1360 .hw_params = snd_cs4231_playback_hw_params,
c6c2d57b 1361 .hw_free = snd_pcm_lib_free_pages,
1da177e4
LT		 1362 .prepare = snd_cs4231_playback_prepare,
1363 .trigger = snd_cs4231_trigger,
1364 .pointer = snd_cs4231_playback_pointer,
1365};
1366
be9b7e8c 1367static struct snd_pcm_ops snd_cs4231_capture_ops = {
1da177e4
LT		 1368 .open = snd_cs4231_capture_open,
1369 .close = snd_cs4231_capture_close,
1370 .ioctl = snd_pcm_lib_ioctl,
1371 .hw_params = snd_cs4231_capture_hw_params,
c6c2d57b 1372 .hw_free = snd_pcm_lib_free_pages,
1da177e4
LT		 1373 .prepare = snd_cs4231_capture_prepare,
1374 .trigger = snd_cs4231_trigger,
1375 .pointer = snd_cs4231_capture_pointer,
1376};
1377
c6c2d57b 1378static int __init snd_cs4231_pcm(struct snd_card *card)
1da177e4 1379{
c6c2d57b 1380 struct snd_cs4231 *chip = card->private_data;
be9b7e8c 1381 struct snd_pcm *pcm;
1da177e4
LT		 1382 int err;
1383
c6c2d57b
KH		 1384 err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
1385 if (err < 0)
1da177e4
LT		 1386 return err;
1387
9e9abb4f
KH		 1388 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1389 &snd_cs4231_playback_ops);
1390 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1391 &snd_cs4231_capture_ops);
1392
1da177e4
LT		 1393 /* global setup */
1394 pcm->private_data = chip;
1da177e4
LT		 1395 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1396 strcpy(pcm->name, "CS4231");
1397
b128254f 1398 chip->p_dma.preallocate(chip, pcm);
1da177e4
LT		 1399
1400 chip->pcm = pcm;
1401
1402 return 0;
1403}
1404
c6c2d57b 1405static int __init snd_cs4231_timer(struct snd_card *card)
1da177e4 1406{
c6c2d57b 1407 struct snd_cs4231 *chip = card->private_data;
be9b7e8c
TI		 1408 struct snd_timer *timer;
1409 struct snd_timer_id tid;
1da177e4
LT		 1410 int err;
1411
1412 /* Timer initialization */
1413 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1414 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
c6c2d57b 1415 tid.card = card->number;
1da177e4
LT		 1416 tid.device = 0;
1417 tid.subdevice = 0;
c6c2d57b
KH		 1418 err = snd_timer_new(card, "CS4231", &tid, &timer);
1419 if (err < 0)
1da177e4
LT		 1420 return err;
1421 strcpy(timer->name, "CS4231");
1422 timer->private_data = chip;
1da177e4
LT		 1423 timer->hw = snd_cs4231_timer_table;
1424 chip->timer = timer;
1425
1426 return 0;
1427}
9e9abb4f 1428
1da177e4
LT		 1429/*
1430 * MIXER part
1431 */
1432
be9b7e8c
TI		 1433static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
1434 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1435{
1436 static char *texts[4] = {
1437 "Line", "CD", "Mic", "Mix"
1438 };
1da177e4 1439
1da177e4
LT		 1440 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1441 uinfo->count = 2;
1442 uinfo->value.enumerated.items = 4;
1443 if (uinfo->value.enumerated.item > 3)
1444 uinfo->value.enumerated.item = 3;
9e9abb4f
KH		 1445 strcpy(uinfo->value.enumerated.name,
1446 texts[uinfo->value.enumerated.item]);
1da177e4
LT		 1447
1448 return 0;
1449}
1450
be9b7e8c
TI		 1451static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
1452 struct snd_ctl_elem_value *ucontrol)
1da177e4 1453{
be9b7e8c 1454 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4 1455 unsigned long flags;
9e9abb4f 1456
1da177e4
LT		 1457 spin_lock_irqsave(&chip->lock, flags);
1458 ucontrol->value.enumerated.item[0] =
1459 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1460 ucontrol->value.enumerated.item[1] =
1461 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1462 spin_unlock_irqrestore(&chip->lock, flags);
1463
1464 return 0;
1465}
1466
be9b7e8c
TI		 1467static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
1468 struct snd_ctl_elem_value *ucontrol)
1da177e4 1469{
be9b7e8c 1470 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1471 unsigned long flags;
1472 unsigned short left, right;
1473 int change;
9e9abb4f 1474
1da177e4
LT		 1475 if (ucontrol->value.enumerated.item[0] > 3 ||
1476 ucontrol->value.enumerated.item[1] > 3)
1477 return -EINVAL;
1478 left = ucontrol->value.enumerated.item[0] << 6;
1479 right = ucontrol->value.enumerated.item[1] << 6;
1480
1481 spin_lock_irqsave(&chip->lock, flags);
1482
1483 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1484 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1485 change = left != chip->image[CS4231_LEFT_INPUT] ||
9e9abb4f 1486 right != chip->image[CS4231_RIGHT_INPUT];
1da177e4
LT		 1487 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1488 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1489
1490 spin_unlock_irqrestore(&chip->lock, flags);
1491
1492 return change;
1493}
1494
be9b7e8c
TI		 1495static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
1496 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1497{
1498 int mask = (kcontrol->private_value >> 16) & 0xff;
1499
1500 uinfo->type = (mask == 1) ?
1501 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1502 uinfo->count = 1;
1503 uinfo->value.integer.min = 0;
1504 uinfo->value.integer.max = mask;
1505
1506 return 0;
1507}
1508
be9b7e8c
TI		 1509static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
1510 struct snd_ctl_elem_value *ucontrol)
1da177e4 1511{
be9b7e8c 1512 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1513 unsigned long flags;
1514 int reg = kcontrol->private_value & 0xff;
1515 int shift = (kcontrol->private_value >> 8) & 0xff;
1516 int mask = (kcontrol->private_value >> 16) & 0xff;
1517 int invert = (kcontrol->private_value >> 24) & 0xff;
9e9abb4f 1518
1da177e4
LT		 1519 spin_lock_irqsave(&chip->lock, flags);
1520
1521 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1522
1523 spin_unlock_irqrestore(&chip->lock, flags);
1524
1525 if (invert)
1526 ucontrol->value.integer.value[0] =
1527 (mask - ucontrol->value.integer.value[0]);
1528
1529 return 0;
1530}
1531
be9b7e8c
TI		 1532static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
1533 struct snd_ctl_elem_value *ucontrol)
1da177e4 1534{
be9b7e8c 1535 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1536 unsigned long flags;
1537 int reg = kcontrol->private_value & 0xff;
1538 int shift = (kcontrol->private_value >> 8) & 0xff;
1539 int mask = (kcontrol->private_value >> 16) & 0xff;
1540 int invert = (kcontrol->private_value >> 24) & 0xff;
1541 int change;
1542 unsigned short val;
9e9abb4f 1543
1da177e4
LT		 1544 val = (ucontrol->value.integer.value[0] & mask);
1545 if (invert)
1546 val = mask - val;
1547 val <<= shift;
1548
1549 spin_lock_irqsave(&chip->lock, flags);
1550
1551 val = (chip->image[reg] & ~(mask << shift)) | val;
1552 change = val != chip->image[reg];
1553 snd_cs4231_out(chip, reg, val);
1554
1555 spin_unlock_irqrestore(&chip->lock, flags);
1556
1557 return change;
1558}
1559
be9b7e8c
TI		 1560static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
1561 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1562{
1563 int mask = (kcontrol->private_value >> 24) & 0xff;
1564
1565 uinfo->type = mask == 1 ?
1566 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1567 uinfo->count = 2;
1568 uinfo->value.integer.min = 0;
1569 uinfo->value.integer.max = mask;
1570
1571 return 0;
1572}
1573
be9b7e8c
TI		 1574static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
1575 struct snd_ctl_elem_value *ucontrol)
1da177e4 1576{
be9b7e8c 1577 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1578 unsigned long flags;
1579 int left_reg = kcontrol->private_value & 0xff;
1580 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1581 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1582 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1583 int mask = (kcontrol->private_value >> 24) & 0xff;
1584 int invert = (kcontrol->private_value >> 22) & 1;
9e9abb4f 1585
1da177e4
LT		 1586 spin_lock_irqsave(&chip->lock, flags);
1587
9e9abb4f
KH		 1588 ucontrol->value.integer.value[0] =
1589 (chip->image[left_reg] >> shift_left) & mask;
1590 ucontrol->value.integer.value[1] =
1591 (chip->image[right_reg] >> shift_right) & mask;
1da177e4
LT		 1592
1593 spin_unlock_irqrestore(&chip->lock, flags);
1594
1595 if (invert) {
1596 ucontrol->value.integer.value[0] =
1597 (mask - ucontrol->value.integer.value[0]);
1598 ucontrol->value.integer.value[1] =
1599 (mask - ucontrol->value.integer.value[1]);
1600 }
1601
1602 return 0;
1603}
1604
be9b7e8c
TI		 1605static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
1606 struct snd_ctl_elem_value *ucontrol)
1da177e4 1607{
be9b7e8c 1608 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1609 unsigned long flags;
1610 int left_reg = kcontrol->private_value & 0xff;
1611 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1612 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1613 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1614 int mask = (kcontrol->private_value >> 24) & 0xff;
1615 int invert = (kcontrol->private_value >> 22) & 1;
1616 int change;
1617 unsigned short val1, val2;
9e9abb4f 1618
1da177e4
LT		 1619 val1 = ucontrol->value.integer.value[0] & mask;
1620 val2 = ucontrol->value.integer.value[1] & mask;
1621 if (invert) {
1622 val1 = mask - val1;
1623 val2 = mask - val2;
1624 }
1625 val1 <<= shift_left;
1626 val2 <<= shift_right;
1627
1628 spin_lock_irqsave(&chip->lock, flags);
1629
1630 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1631 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
9e9abb4f
KH		 1632 change = val1 != chip->image[left_reg];
1633 change |= val2 != chip->image[right_reg];
1da177e4
LT		 1634 snd_cs4231_out(chip, left_reg, val1);
1635 snd_cs4231_out(chip, right_reg, val2);
1636
1637 spin_unlock_irqrestore(&chip->lock, flags);
1638
1639 return change;
1640}
1641
1642#define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
9e9abb4f
KH		 1643{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
1644 .info = snd_cs4231_info_single, \
1645 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
1646 .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) }
1647
1648#define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \
1649 shift_right, mask, invert) \
1650{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
1651 .info = snd_cs4231_info_double, \
1652 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
1653 .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \
1654 ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) }
1da177e4 1655
be9b7e8c 1656static struct snd_kcontrol_new snd_cs4231_controls[] __initdata = {
9e9abb4f
KH		 1657CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT,
1658 CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1659CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT,
1660 CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1661CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN,
1662 CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1663CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN,
1664 CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1665CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT,
1666 CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1667CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT,
1668 CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1669CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT,
1670 CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1671CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT,
1672 CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1da177e4
LT		 1673CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1674CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1675CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1676CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
9e9abb4f
KH		 1677CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0,
1678 15, 0),
1da177e4
LT		 1679{
1680 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1681 .name = "Capture Source",
1682 .info = snd_cs4231_info_mux,
1683 .get = snd_cs4231_get_mux,
1684 .put = snd_cs4231_put_mux,
1685},
9e9abb4f
KH		 1686CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5,
1687 1, 0),
1da177e4
LT		 1688CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1689CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
1690/* SPARC specific uses of XCTL{0,1} general purpose outputs. */
1691CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
1692CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
1693};
9e9abb4f 1694
c6c2d57b 1695static int __init snd_cs4231_mixer(struct snd_card *card)
1da177e4 1696{
c6c2d57b 1697 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1698 int err, idx;
1699
1700 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
1701
1da177e4
LT		 1702 strcpy(card->mixername, chip->pcm->name);
1703
1704 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
c6c2d57b
KH		 1705 err = snd_ctl_add(card,
1706 snd_ctl_new1(&snd_cs4231_controls[idx], chip));
1707 if (err < 0)
1da177e4
LT		 1708 return err;
1709 }
1710 return 0;
1711}
1712
1713static int dev;
1714
be9b7e8c 1715static int __init cs4231_attach_begin(struct snd_card **rcard)
1da177e4 1716{
be9b7e8c 1717 struct snd_card *card;
c6c2d57b 1718 struct snd_cs4231 *chip;
1da177e4
LT		 1719
1720 *rcard = NULL;
1721
1722 if (dev >= SNDRV_CARDS)
1723 return -ENODEV;
1724
1725 if (!enable[dev]) {
1726 dev++;
1727 return -ENOENT;
1728 }
1729
c6c2d57b
KH		 1730 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
1731 sizeof(struct snd_cs4231));
1da177e4
LT		 1732 if (card == NULL)
1733 return -ENOMEM;
1734
1735 strcpy(card->driver, "CS4231");
1736 strcpy(card->shortname, "Sun CS4231");
1737
c6c2d57b
KH		 1738 chip = card->private_data;
1739 chip->card = card;
1740
1da177e4
LT		 1741 *rcard = card;
1742 return 0;
1743}
1744
c6c2d57b 1745static int __init cs4231_attach_finish(struct snd_card *card)
1da177e4 1746{
c6c2d57b 1747 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1748 int err;
1749
c6c2d57b
KH		 1750 err = snd_cs4231_pcm(card);
1751 if (err < 0)
1da177e4
LT		 1752 goto out_err;
1753
c6c2d57b
KH		 1754 err = snd_cs4231_mixer(card);
1755 if (err < 0)
1da177e4
LT		 1756 goto out_err;
1757
c6c2d57b
KH		 1758 err = snd_cs4231_timer(card);
1759 if (err < 0)
1da177e4
LT		 1760 goto out_err;
1761
c6c2d57b
KH		 1762 err = snd_card_register(card);
1763 if (err < 0)
1da177e4
LT		 1764 goto out_err;
1765
1766 chip->next = cs4231_list;
1767 cs4231_list = chip;
1768
1769 dev++;
1770 return 0;
1771
1772out_err:
1773 snd_card_free(card);
1774 return err;
1775}
1776
1777#ifdef SBUS_SUPPORT
b128254f 1778
7d12e780 1779static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
b128254f
GC		 1780{
1781 unsigned long flags;
1782 unsigned char status;
1783 u32 csr;
be9b7e8c 1784 struct snd_cs4231 *chip = dev_id;
b128254f
GC		 1785
1786 /*This is IRQ is not raised by the cs4231*/
1787 if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ))
1788 return IRQ_NONE;
1789
1790 /* ACK the APC interrupt. */
1791 csr = sbus_readl(chip->port + APCCSR);
1792
1793 sbus_writel(csr, chip->port + APCCSR);
1794
9e9abb4f
KH		 1795 if ((csr & APC_PDMA_READY) &&
1796 (csr & APC_PLAY_INT) &&
b128254f
GC		 1797 (csr & APC_XINT_PNVA) &&
1798 !(csr & APC_XINT_EMPT))
1799 snd_cs4231_play_callback(chip);
1800
9e9abb4f
KH		 1801 if ((csr & APC_CDMA_READY) &&
1802 (csr & APC_CAPT_INT) &&
b128254f
GC		 1803 (csr & APC_XINT_CNVA) &&
1804 !(csr & APC_XINT_EMPT))
1805 snd_cs4231_capture_callback(chip);
9e9abb4f 1806
b128254f
GC		 1807 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
1808
1809 if (status & CS4231_TIMER_IRQ) {
1810 if (chip->timer)
1811 snd_timer_interrupt(chip->timer, chip->timer->sticks);
9e9abb4f 1812 }
b128254f
GC		 1813
1814 if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
1815 snd_cs4231_overrange(chip);
1816
1817 /* ACK the CS4231 interrupt. */
1818 spin_lock_irqsave(&chip->lock, flags);
1819 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
1820 spin_unlock_irqrestore(&chip->lock, flags);
1821
d35a1b9e 1822 return IRQ_HANDLED;
b128254f
GC		 1823}
1824
1825/*
1826 * SBUS DMA routines
1827 */
1828
9e9abb4f
KH		 1829static int sbus_dma_request(struct cs4231_dma_control *dma_cont,
1830 dma_addr_t bus_addr, size_t len)
b128254f
GC		 1831{
1832 unsigned long flags;
1833 u32 test, csr;
1834 int err;
be9b7e8c 1835 struct sbus_dma_info *base = &dma_cont->sbus_info;
9e9abb4f 1836
b128254f
GC		 1837 if (len >= (1 << 24))
1838 return -EINVAL;
1839 spin_lock_irqsave(&base->lock, flags);
1840 csr = sbus_readl(base->regs + APCCSR);
1841 err = -EINVAL;
1842 test = APC_CDMA_READY;
9e9abb4f 1843 if (base->dir == APC_PLAY)
b128254f
GC		 1844 test = APC_PDMA_READY;
1845 if (!(csr & test))
1846 goto out;
1847 err = -EBUSY;
b128254f 1848 test = APC_XINT_CNVA;
9e9abb4f 1849 if (base->dir == APC_PLAY)
b128254f
GC		 1850 test = APC_XINT_PNVA;
1851 if (!(csr & test))
1852 goto out;
1853 err = 0;
1854 sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
1855 sbus_writel(len, base->regs + base->dir + APCNC);
1856out:
1857 spin_unlock_irqrestore(&base->lock, flags);
1858 return err;
1859}
1860
be9b7e8c 1861static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
b128254f
GC		 1862{
1863 unsigned long flags;
1864 u32 csr, test;
be9b7e8c 1865 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1866
1867 spin_lock_irqsave(&base->lock, flags);
1868 csr = sbus_readl(base->regs + APCCSR);
1869 test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
1870 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
1871 APC_XINT_PENA;
9e9abb4f 1872 if (base->dir == APC_RECORD)
b128254f
GC		 1873 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
1874 APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
1875 csr |= test;
1876 sbus_writel(csr, base->regs + APCCSR);
1877 spin_unlock_irqrestore(&base->lock, flags);
1878}
1879
be9b7e8c 1880static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
b128254f
GC		 1881{
1882 unsigned long flags;
1883 u32 csr, shift;
be9b7e8c 1884 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1885
1886 spin_lock_irqsave(&base->lock, flags);
1887 if (!on) {
d35a1b9e
GC		 1888 sbus_writel(0, base->regs + base->dir + APCNC);
1889 sbus_writel(0, base->regs + base->dir + APCNVA);
9e9abb4f 1890 if (base->dir == APC_PLAY) {
3daadf33
GC		 1891 sbus_writel(0, base->regs + base->dir + APCC);
1892 sbus_writel(0, base->regs + base->dir + APCVA);
1893 }
d35a1b9e 1894
3daadf33 1895 udelay(1200);
9e9abb4f 1896 }
b128254f
GC		 1897 csr = sbus_readl(base->regs + APCCSR);
1898 shift = 0;
9e9abb4f 1899 if (base->dir == APC_PLAY)
b128254f
GC		 1900 shift = 1;
1901 if (on)
1902 csr &= ~(APC_CPAUSE << shift);
1903 else
9e9abb4f 1904 csr |= (APC_CPAUSE << shift);
b128254f
GC		 1905 sbus_writel(csr, base->regs + APCCSR);
1906 if (on)
1907 csr |= (APC_CDMA_READY << shift);
1908 else
1909 csr &= ~(APC_CDMA_READY << shift);
1910 sbus_writel(csr, base->regs + APCCSR);
9e9abb4f 1911
b128254f
GC		 1912 spin_unlock_irqrestore(&base->lock, flags);
1913}
1914
be9b7e8c 1915static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
b128254f 1916{
be9b7e8c 1917 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f 1918
9e9abb4f 1919 return sbus_readl(base->regs + base->dir + APCVA);
b128254f
GC		 1920}
1921
be9b7e8c 1922static void sbus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
b128254f
GC		 1923{
1924 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS,
9e9abb4f
KH		 1925 snd_dma_sbus_data(chip->dev_u.sdev),
1926 64 * 1024, 128 * 1024);
b128254f
GC		 1927}
1928
1929/*
1930 * Init and exit routines
1931 */
1932
be9b7e8c 1933static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
1da177e4
LT		 1934{
1935 if (chip->irq[0])
1936 free_irq(chip->irq[0], chip);
1937
1938 if (chip->port)
1939 sbus_iounmap(chip->port, chip->regs_size);
1940
1da177e4
LT		 1941 return 0;
1942}
1943
be9b7e8c 1944static int snd_cs4231_sbus_dev_free(struct snd_device *device)
1da177e4 1945{
be9b7e8c 1946 struct snd_cs4231 *cp = device->device_data;
1da177e4
LT		 1947
1948 return snd_cs4231_sbus_free(cp);
1949}
1950
be9b7e8c 1951static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
1da177e4
LT		 1952 .dev_free = snd_cs4231_sbus_dev_free,
1953};
1954
be9b7e8c 1955static int __init snd_cs4231_sbus_create(struct snd_card *card,
1da177e4 1956 struct sbus_dev *sdev,
c6c2d57b 1957 int dev)
1da177e4 1958{
c6c2d57b 1959 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 1960 int err;
1961
1da177e4 1962 spin_lock_init(&chip->lock);
b128254f
GC		 1963 spin_lock_init(&chip->c_dma.sbus_info.lock);
1964 spin_lock_init(&chip->p_dma.sbus_info.lock);
12aa7579
IM		 1965 mutex_init(&chip->mce_mutex);
1966 mutex_init(&chip->open_mutex);
1da177e4
LT		 1967 chip->dev_u.sdev = sdev;
1968 chip->regs_size = sdev->reg_addrs[0].reg_size;
1969 memcpy(&chip->image, &snd_cs4231_original_image,
1970 sizeof(snd_cs4231_original_image));
1971
1972 chip->port = sbus_ioremap(&sdev->resource[0], 0,
1973 chip->regs_size, "cs4231");
1974 if (!chip->port) {
a131430c 1975 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1da177e4
LT		 1976 return -EIO;
1977 }
1978
b128254f
GC		 1979 chip->c_dma.sbus_info.regs = chip->port;
1980 chip->p_dma.sbus_info.regs = chip->port;
1981 chip->c_dma.sbus_info.dir = APC_RECORD;
1982 chip->p_dma.sbus_info.dir = APC_PLAY;
1983
1984 chip->p_dma.prepare = sbus_dma_prepare;
1985 chip->p_dma.enable = sbus_dma_enable;
1986 chip->p_dma.request = sbus_dma_request;
1987 chip->p_dma.address = sbus_dma_addr;
b128254f
GC		 1988 chip->p_dma.preallocate = sbus_dma_preallocate;
1989
1990 chip->c_dma.prepare = sbus_dma_prepare;
1991 chip->c_dma.enable = sbus_dma_enable;
1992 chip->c_dma.request = sbus_dma_request;
1993 chip->c_dma.address = sbus_dma_addr;
b128254f 1994 chip->c_dma.preallocate = sbus_dma_preallocate;
5a820fa7 1995
1da177e4 1996 if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
65ca68b3 1997 IRQF_SHARED, "cs4231", chip)) {
c6387a48
DM		 1998 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
1999 dev, sdev->irqs[0]);
1da177e4
LT		 2000 snd_cs4231_sbus_free(chip);
2001 return -EBUSY;
2002 }
2003 chip->irq[0] = sdev->irqs[0];
2004
2005 if (snd_cs4231_probe(chip) < 0) {
2006 snd_cs4231_sbus_free(chip);
2007 return -ENODEV;
2008 }
2009 snd_cs4231_init(chip);
2010
2011 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2012 chip, &snd_cs4231_sbus_dev_ops)) < 0) {
2013 snd_cs4231_sbus_free(chip);
2014 return err;
2015 }
2016
1da177e4
LT		 2017 return 0;
2018}
2019
be9b7e8c 2020static int __init cs4231_sbus_attach(struct sbus_dev *sdev)
1da177e4
LT		 2021{
2022 struct resource *rp = &sdev->resource[0];
be9b7e8c 2023 struct snd_card *card;
1da177e4
LT		 2024 int err;
2025
2026 err = cs4231_attach_begin(&card);
2027 if (err)
2028 return err;
2029
5863aa65 2030 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
1da177e4
LT		 2031 card->shortname,
2032 rp->flags & 0xffL,
aa0a2ddc 2033 (unsigned long long)rp->start,
c6387a48 2034 sdev->irqs[0]);
1da177e4 2035
c6c2d57b
KH		 2036 err = snd_cs4231_sbus_create(card, sdev, dev);
2037 if (err < 0) {
1da177e4
LT		 2038 snd_card_free(card);
2039 return err;
2040 }
2041
c6c2d57b 2042 return cs4231_attach_finish(card);
1da177e4
LT		 2043}
2044#endif
2045
2046#ifdef EBUS_SUPPORT
b128254f 2047
9e9abb4f
KH		 2048static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event,
2049 void *cookie)
b128254f 2050{
be9b7e8c 2051 struct snd_cs4231 *chip = cookie;
9e9abb4f 2052
b128254f
GC		 2053 snd_cs4231_play_callback(chip);
2054}
2055
9e9abb4f
KH		 2056static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p,
2057 int event, void *cookie)
b128254f 2058{
be9b7e8c 2059 struct snd_cs4231 *chip = cookie;
b128254f
GC		 2060
2061 snd_cs4231_capture_callback(chip);
2062}
2063
2064/*
2065 * EBUS DMA wrappers
2066 */
2067
9e9abb4f
KH		 2068static int _ebus_dma_request(struct cs4231_dma_control *dma_cont,
2069 dma_addr_t bus_addr, size_t len)
b128254f
GC		 2070{
2071 return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
2072}
2073
be9b7e8c 2074static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
b128254f
GC		 2075{
2076 ebus_dma_enable(&dma_cont->ebus_info, on);
2077}
2078
be9b7e8c 2079static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
b128254f
GC		 2080{
2081 ebus_dma_prepare(&dma_cont->ebus_info, dir);
2082}
2083
be9b7e8c 2084static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
b128254f
GC		 2085{
2086 return ebus_dma_addr(&dma_cont->ebus_info);
2087}
2088
be9b7e8c 2089static void _ebus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
b128254f
GC		 2090{
2091 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
2092 snd_dma_pci_data(chip->dev_u.pdev),
2093 64*1024, 128*1024);
2094}
2095
2096/*
2097 * Init and exit routines
2098 */
2099
be9b7e8c 2100static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
1da177e4 2101{
b128254f
GC		 2102 if (chip->c_dma.ebus_info.regs) {
2103 ebus_dma_unregister(&chip->c_dma.ebus_info);
2104 iounmap(chip->c_dma.ebus_info.regs);
1da177e4 2105 }
b128254f
GC		 2106 if (chip->p_dma.ebus_info.regs) {
2107 ebus_dma_unregister(&chip->p_dma.ebus_info);
2108 iounmap(chip->p_dma.ebus_info.regs);
1da177e4
LT		 2109 }
2110
2111 if (chip->port)
2112 iounmap(chip->port);
1da177e4 2113
1da177e4
LT		 2114 return 0;
2115}
2116
be9b7e8c 2117static int snd_cs4231_ebus_dev_free(struct snd_device *device)
1da177e4 2118{
be9b7e8c 2119 struct snd_cs4231 *cp = device->device_data;
1da177e4
LT		 2120
2121 return snd_cs4231_ebus_free(cp);
2122}
2123
be9b7e8c 2124static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
1da177e4
LT		 2125 .dev_free = snd_cs4231_ebus_dev_free,
2126};
2127
be9b7e8c 2128static int __init snd_cs4231_ebus_create(struct snd_card *card,
1da177e4 2129 struct linux_ebus_device *edev,
c6c2d57b 2130 int dev)
1da177e4 2131{
c6c2d57b 2132 struct snd_cs4231 *chip = card->private_data;
1da177e4
LT		 2133 int err;
2134
1da177e4 2135 spin_lock_init(&chip->lock);
b128254f
GC		 2136 spin_lock_init(&chip->c_dma.ebus_info.lock);
2137 spin_lock_init(&chip->p_dma.ebus_info.lock);
12aa7579
IM		 2138 mutex_init(&chip->mce_mutex);
2139 mutex_init(&chip->open_mutex);
1da177e4 2140 chip->flags |= CS4231_FLAG_EBUS;
1da177e4
LT		 2141 chip->dev_u.pdev = edev->bus->self;
2142 memcpy(&chip->image, &snd_cs4231_original_image,
2143 sizeof(snd_cs4231_original_image));
b128254f
GC		 2144 strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
2145 chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2146 chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
2147 chip->c_dma.ebus_info.client_cookie = chip;
2148 chip->c_dma.ebus_info.irq = edev->irqs[0];
2149 strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
2150 chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2151 chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
2152 chip->p_dma.ebus_info.client_cookie = chip;
2153 chip->p_dma.ebus_info.irq = edev->irqs[1];
2154
2155 chip->p_dma.prepare = _ebus_dma_prepare;
2156 chip->p_dma.enable = _ebus_dma_enable;
2157 chip->p_dma.request = _ebus_dma_request;
2158 chip->p_dma.address = _ebus_dma_addr;
b128254f
GC		 2159 chip->p_dma.preallocate = _ebus_dma_preallocate;
2160
2161 chip->c_dma.prepare = _ebus_dma_prepare;
2162 chip->c_dma.enable = _ebus_dma_enable;
2163 chip->c_dma.request = _ebus_dma_request;
2164 chip->c_dma.address = _ebus_dma_addr;
b128254f 2165 chip->c_dma.preallocate = _ebus_dma_preallocate;
1da177e4
LT		 2166
2167 chip->port = ioremap(edev->resource[0].start, 0x10);
b128254f
GC		 2168 chip->p_dma.ebus_info.regs = ioremap(edev->resource[1].start, 0x10);
2169 chip->c_dma.ebus_info.regs = ioremap(edev->resource[2].start, 0x10);
9e9abb4f
KH		 2170 if (!chip->port || !chip->p_dma.ebus_info.regs ||
2171 !chip->c_dma.ebus_info.regs) {
1da177e4 2172 snd_cs4231_ebus_free(chip);
a131430c 2173 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1da177e4
LT		 2174 return -EIO;
2175 }
2176
b128254f 2177 if (ebus_dma_register(&chip->c_dma.ebus_info)) {
1da177e4 2178 snd_cs4231_ebus_free(chip);
9e9abb4f
KH		 2179 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n",
2180 dev);
1da177e4
LT		 2181 return -EBUSY;
2182 }
b128254f 2183 if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
1da177e4 2184 snd_cs4231_ebus_free(chip);
9e9abb4f
KH		 2185 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n",
2186 dev);
1da177e4
LT		 2187 return -EBUSY;
2188 }
2189
b128254f 2190 if (ebus_dma_register(&chip->p_dma.ebus_info)) {
1da177e4 2191 snd_cs4231_ebus_free(chip);
9e9abb4f
KH		 2192 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n",
2193 dev);
1da177e4
LT		 2194 return -EBUSY;
2195 }
b128254f 2196 if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
1da177e4 2197 snd_cs4231_ebus_free(chip);
a131430c 2198 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
1da177e4
LT		 2199 return -EBUSY;
2200 }
2201
2202 if (snd_cs4231_probe(chip) < 0) {
2203 snd_cs4231_ebus_free(chip);
2204 return -ENODEV;
2205 }
2206 snd_cs4231_init(chip);
2207
2208 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2209 chip, &snd_cs4231_ebus_dev_ops)) < 0) {
2210 snd_cs4231_ebus_free(chip);
2211 return err;
2212 }
2213
1da177e4
LT		 2214 return 0;
2215}
2216
be9b7e8c 2217static int __init cs4231_ebus_attach(struct linux_ebus_device *edev)
1da177e4 2218{
be9b7e8c 2219 struct snd_card *card;
1da177e4
LT		 2220 int err;
2221
2222 err = cs4231_attach_begin(&card);
2223 if (err)
2224 return err;
2225
c6387a48 2226 sprintf(card->longname, "%s at 0x%lx, irq %d",
1da177e4
LT		 2227 card->shortname,
2228 edev->resource[0].start,
c6387a48 2229 edev->irqs[0]);
1da177e4 2230
c6c2d57b
KH		 2231 err = snd_cs4231_ebus_create(card, edev, dev);
2232 if (err < 0) {
1da177e4
LT		 2233 snd_card_free(card);
2234 return err;
2235 }
2236
c6c2d57b 2237 return cs4231_attach_finish(card);
1da177e4
LT		 2238}
2239#endif
2240
2241static int __init cs4231_init(void)
2242{
2243#ifdef SBUS_SUPPORT
2244 struct sbus_bus *sbus;
2245 struct sbus_dev *sdev;
2246#endif
2247#ifdef EBUS_SUPPORT
2248 struct linux_ebus *ebus;
2249 struct linux_ebus_device *edev;
2250#endif
2251 int found;
2252
2253 found = 0;
2254
2255#ifdef SBUS_SUPPORT
2256 for_all_sbusdev(sdev, sbus) {
2257 if (!strcmp(sdev->prom_name, "SUNW,CS4231")) {
2258 if (cs4231_sbus_attach(sdev) == 0)
2259 found++;
2260 }
2261 }
2262#endif
2263#ifdef EBUS_SUPPORT
2264 for_each_ebus(ebus) {
2265 for_each_ebusdev(edev, ebus) {
2266 int match = 0;
2267
690c8fd3 2268 if (!strcmp(edev->prom_node->name, "SUNW,CS4231")) {
1da177e4 2269 match = 1;
690c8fd3 2270 } else if (!strcmp(edev->prom_node->name, "audio")) {
3198514d 2271 const char *compat;
1da177e4 2272
690c8fd3
DM		 2273 compat = of_get_property(edev->prom_node,
2274 "compatible", NULL);
2275 if (compat && !strcmp(compat, "SUNW,CS4231"))
1da177e4
LT		 2276 match = 1;
2277 }
2278
2279 if (match &&
2280 cs4231_ebus_attach(edev) == 0)
2281 found++;
2282 }
2283 }
2284#endif
2285
2286
2287 return (found > 0) ? 0 : -EIO;
2288}
2289
2290static void __exit cs4231_exit(void)
2291{
be9b7e8c 2292 struct snd_cs4231 *p = cs4231_list;
1da177e4
LT		 2293
2294 while (p != NULL) {
be9b7e8c 2295 struct snd_cs4231 *next = p->next;
1da177e4
LT		 2296
2297 snd_card_free(p->card);
2298
2299 p = next;
2300 }
2301
2302 cs4231_list = NULL;
2303}
2304
2305module_init(cs4231_init);
2306module_exit(cs4231_exit);
kernel source for telekom puls (alcatel/mediatek)