Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Driver for CS4231 sound chips found on Sparcs. | |
3 | * Copyright (C) 2002 David S. Miller <davem@redhat.com> | |
4 | * | |
5 | * Based entirely upon drivers/sbus/audio/cs4231.c which is: | |
6 | * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu) | |
7 | * and also sound/isa/cs423x/cs4231_lib.c which is: | |
8 | * Copyright (c) by Jaroslav Kysela <perex@suse.cz> | |
9 | */ | |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/moduleparam.h> | |
18 | ||
19 | #include <sound/driver.h> | |
20 | #include <sound/core.h> | |
21 | #include <sound/pcm.h> | |
22 | #include <sound/info.h> | |
23 | #include <sound/control.h> | |
24 | #include <sound/timer.h> | |
25 | #include <sound/initval.h> | |
26 | #include <sound/pcm_params.h> | |
27 | ||
28 | #include <asm/io.h> | |
29 | #include <asm/irq.h> | |
30 | ||
31 | #ifdef CONFIG_SBUS | |
32 | #define SBUS_SUPPORT | |
1da177e4 LT |
33 | #include <asm/sbus.h> |
34 | #endif | |
35 | ||
36 | #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64) | |
37 | #define EBUS_SUPPORT | |
1da177e4 LT |
38 | #include <linux/pci.h> |
39 | #include <asm/ebus.h> | |
40 | #endif | |
41 | ||
42 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
43 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
44 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ | |
45 | ||
46 | module_param_array(index, int, NULL, 0444); | |
47 | MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard."); | |
48 | module_param_array(id, charp, NULL, 0444); | |
49 | MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard."); | |
50 | module_param_array(enable, bool, NULL, 0444); | |
51 | MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard."); | |
52 | MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller"); | |
53 | MODULE_DESCRIPTION("Sun CS4231"); | |
54 | MODULE_LICENSE("GPL"); | |
55 | MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}"); | |
56 | ||
5a820fa7 | 57 | #ifdef SBUS_SUPPORT |
be9b7e8c | 58 | struct sbus_dma_info { |
5a820fa7 GC |
59 | spinlock_t lock; |
60 | int dir; | |
61 | void __iomem *regs; | |
be9b7e8c | 62 | }; |
5a820fa7 GC |
63 | #endif |
64 | ||
4f3f2f6f | 65 | struct snd_cs4231; |
be9b7e8c | 66 | struct cs4231_dma_control { |
b128254f GC |
67 | void (*prepare)(struct cs4231_dma_control *dma_cont, int dir); |
68 | void (*enable)(struct cs4231_dma_control *dma_cont, int on); | |
69 | int (*request)(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len); | |
70 | unsigned int (*address)(struct cs4231_dma_control *dma_cont); | |
4f3f2f6f | 71 | void (*preallocate)(struct snd_cs4231 *chip, struct snd_pcm *pcm); |
1da177e4 | 72 | #ifdef EBUS_SUPPORT |
b128254f | 73 | struct ebus_dma_info ebus_info; |
1da177e4 | 74 | #endif |
5a820fa7 | 75 | #ifdef SBUS_SUPPORT |
b128254f | 76 | struct sbus_dma_info sbus_info; |
5a820fa7 | 77 | #endif |
be9b7e8c | 78 | }; |
b128254f GC |
79 | |
80 | struct snd_cs4231 { | |
81 | spinlock_t lock; | |
82 | void __iomem *port; | |
83 | ||
be9b7e8c TI |
84 | struct cs4231_dma_control p_dma; |
85 | struct cs4231_dma_control c_dma; | |
5a820fa7 | 86 | |
1da177e4 LT |
87 | u32 flags; |
88 | #define CS4231_FLAG_EBUS 0x00000001 | |
89 | #define CS4231_FLAG_PLAYBACK 0x00000002 | |
90 | #define CS4231_FLAG_CAPTURE 0x00000004 | |
91 | ||
be9b7e8c TI |
92 | struct snd_card *card; |
93 | struct snd_pcm *pcm; | |
94 | struct snd_pcm_substream *playback_substream; | |
1da177e4 | 95 | unsigned int p_periods_sent; |
be9b7e8c | 96 | struct snd_pcm_substream *capture_substream; |
1da177e4 | 97 | unsigned int c_periods_sent; |
be9b7e8c | 98 | struct snd_timer *timer; |
1da177e4 LT |
99 | |
100 | unsigned short mode; | |
101 | #define CS4231_MODE_NONE 0x0000 | |
102 | #define CS4231_MODE_PLAY 0x0001 | |
103 | #define CS4231_MODE_RECORD 0x0002 | |
104 | #define CS4231_MODE_TIMER 0x0004 | |
105 | #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER) | |
106 | ||
107 | unsigned char image[32]; /* registers image */ | |
108 | int mce_bit; | |
109 | int calibrate_mute; | |
12aa7579 IM |
110 | struct mutex mce_mutex; |
111 | struct mutex open_mutex; | |
1da177e4 LT |
112 | |
113 | union { | |
114 | #ifdef SBUS_SUPPORT | |
115 | struct sbus_dev *sdev; | |
116 | #endif | |
117 | #ifdef EBUS_SUPPORT | |
118 | struct pci_dev *pdev; | |
119 | #endif | |
120 | } dev_u; | |
121 | unsigned int irq[2]; | |
122 | unsigned int regs_size; | |
123 | struct snd_cs4231 *next; | |
b128254f | 124 | }; |
1da177e4 | 125 | |
be9b7e8c | 126 | static struct snd_cs4231 *cs4231_list; |
1da177e4 LT |
127 | |
128 | /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for | |
129 | * now.... -DaveM | |
130 | */ | |
131 | ||
132 | /* IO ports */ | |
133 | ||
134 | #define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x) | |
135 | ||
136 | /* XXX offsets are different than PC ISA chips... */ | |
137 | #define c_d_c_CS4231REGSEL 0x0 | |
138 | #define c_d_c_CS4231REG 0x4 | |
139 | #define c_d_c_CS4231STATUS 0x8 | |
140 | #define c_d_c_CS4231PIO 0xc | |
141 | ||
142 | /* codec registers */ | |
143 | ||
144 | #define CS4231_LEFT_INPUT 0x00 /* left input control */ | |
145 | #define CS4231_RIGHT_INPUT 0x01 /* right input control */ | |
146 | #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ | |
147 | #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ | |
148 | #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ | |
149 | #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ | |
150 | #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ | |
151 | #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ | |
152 | #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ | |
153 | #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ | |
154 | #define CS4231_PIN_CTRL 0x0a /* pin control */ | |
155 | #define CS4231_TEST_INIT 0x0b /* test and initialization */ | |
156 | #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */ | |
157 | #define CS4231_LOOPBACK 0x0d /* loopback control */ | |
158 | #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ | |
159 | #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ | |
160 | #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ | |
161 | #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ | |
162 | #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ | |
163 | #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ | |
164 | #define CS4231_TIMER_LOW 0x14 /* timer low byte */ | |
165 | #define CS4231_TIMER_HIGH 0x15 /* timer high byte */ | |
166 | #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ | |
167 | #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ | |
168 | #define CS4236_EXT_REG 0x17 /* extended register access */ | |
169 | #define CS4231_IRQ_STATUS 0x18 /* irq status register */ | |
170 | #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ | |
171 | #define CS4231_VERSION 0x19 /* CS4231(A) - version values */ | |
172 | #define CS4231_MONO_CTRL 0x1a /* mono input/output control */ | |
173 | #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ | |
174 | #define CS4235_LEFT_MASTER 0x1b /* left master output control */ | |
175 | #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ | |
176 | #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */ | |
177 | #define CS4235_RIGHT_MASTER 0x1d /* right master output control */ | |
178 | #define CS4231_REC_UPR_CNT 0x1e /* record upper count */ | |
179 | #define CS4231_REC_LWR_CNT 0x1f /* record lower count */ | |
180 | ||
181 | /* definitions for codec register select port - CODECP( REGSEL ) */ | |
182 | ||
183 | #define CS4231_INIT 0x80 /* CODEC is initializing */ | |
184 | #define CS4231_MCE 0x40 /* mode change enable */ | |
185 | #define CS4231_TRD 0x20 /* transfer request disable */ | |
186 | ||
187 | /* definitions for codec status register - CODECP( STATUS ) */ | |
188 | ||
189 | #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ | |
190 | ||
a131430c | 191 | /* definitions for codec irq status - CS4231_IRQ_STATUS */ |
1da177e4 LT |
192 | |
193 | #define CS4231_PLAYBACK_IRQ 0x10 | |
194 | #define CS4231_RECORD_IRQ 0x20 | |
195 | #define CS4231_TIMER_IRQ 0x40 | |
196 | #define CS4231_ALL_IRQS 0x70 | |
197 | #define CS4231_REC_UNDERRUN 0x08 | |
198 | #define CS4231_REC_OVERRUN 0x04 | |
199 | #define CS4231_PLY_OVERRUN 0x02 | |
200 | #define CS4231_PLY_UNDERRUN 0x01 | |
201 | ||
202 | /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ | |
203 | ||
204 | #define CS4231_ENABLE_MIC_GAIN 0x20 | |
205 | ||
206 | #define CS4231_MIXS_LINE 0x00 | |
207 | #define CS4231_MIXS_AUX1 0x40 | |
208 | #define CS4231_MIXS_MIC 0x80 | |
209 | #define CS4231_MIXS_ALL 0xc0 | |
210 | ||
211 | /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ | |
212 | ||
213 | #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ | |
214 | #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ | |
215 | #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ | |
216 | #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ | |
217 | #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ | |
218 | #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ | |
219 | #define CS4231_STEREO 0x10 /* stereo mode */ | |
220 | /* bits 3-1 define frequency divisor */ | |
221 | #define CS4231_XTAL1 0x00 /* 24.576 crystal */ | |
222 | #define CS4231_XTAL2 0x01 /* 16.9344 crystal */ | |
223 | ||
224 | /* definitions for interface control register - CS4231_IFACE_CTRL */ | |
225 | ||
226 | #define CS4231_RECORD_PIO 0x80 /* record PIO enable */ | |
227 | #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ | |
228 | #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ | |
229 | #define CS4231_AUTOCALIB 0x08 /* auto calibrate */ | |
230 | #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ | |
231 | #define CS4231_RECORD_ENABLE 0x02 /* record enable */ | |
232 | #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ | |
233 | ||
234 | /* definitions for pin control register - CS4231_PIN_CTRL */ | |
235 | ||
236 | #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ | |
237 | #define CS4231_XCTL1 0x40 /* external control #1 */ | |
238 | #define CS4231_XCTL0 0x80 /* external control #0 */ | |
239 | ||
240 | /* definitions for test and init register - CS4231_TEST_INIT */ | |
241 | ||
242 | #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ | |
243 | #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ | |
244 | ||
245 | /* definitions for misc control register - CS4231_MISC_INFO */ | |
246 | ||
247 | #define CS4231_MODE2 0x40 /* MODE 2 */ | |
248 | #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ | |
249 | #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ | |
250 | ||
251 | /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ | |
252 | ||
253 | #define CS4231_DACZ 0x01 /* zero DAC when underrun */ | |
254 | #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ | |
255 | #define CS4231_OLB 0x80 /* output level bit */ | |
256 | ||
257 | /* SBUS DMA register defines. */ | |
258 | ||
259 | #define APCCSR 0x10UL /* APC DMA CSR */ | |
260 | #define APCCVA 0x20UL /* APC Capture DMA Address */ | |
261 | #define APCCC 0x24UL /* APC Capture Count */ | |
262 | #define APCCNVA 0x28UL /* APC Capture DMA Next Address */ | |
263 | #define APCCNC 0x2cUL /* APC Capture Next Count */ | |
264 | #define APCPVA 0x30UL /* APC Play DMA Address */ | |
265 | #define APCPC 0x34UL /* APC Play Count */ | |
266 | #define APCPNVA 0x38UL /* APC Play DMA Next Address */ | |
267 | #define APCPNC 0x3cUL /* APC Play Next Count */ | |
268 | ||
5a820fa7 GC |
269 | /* Defines for SBUS DMA-routines */ |
270 | ||
271 | #define APCVA 0x0UL /* APC DMA Address */ | |
272 | #define APCC 0x4UL /* APC Count */ | |
273 | #define APCNVA 0x8UL /* APC DMA Next Address */ | |
274 | #define APCNC 0xcUL /* APC Next Count */ | |
275 | #define APC_PLAY 0x30UL /* Play registers start at 0x30 */ | |
276 | #define APC_RECORD 0x20UL /* Record registers start at 0x20 */ | |
277 | ||
1da177e4 LT |
278 | /* APCCSR bits */ |
279 | ||
280 | #define APC_INT_PENDING 0x800000 /* Interrupt Pending */ | |
281 | #define APC_PLAY_INT 0x400000 /* Playback interrupt */ | |
282 | #define APC_CAPT_INT 0x200000 /* Capture interrupt */ | |
283 | #define APC_GENL_INT 0x100000 /* General interrupt */ | |
284 | #define APC_XINT_ENA 0x80000 /* General ext int. enable */ | |
285 | #define APC_XINT_PLAY 0x40000 /* Playback ext intr */ | |
286 | #define APC_XINT_CAPT 0x20000 /* Capture ext intr */ | |
287 | #define APC_XINT_GENL 0x10000 /* Error ext intr */ | |
288 | #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */ | |
289 | #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */ | |
290 | #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */ | |
291 | #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */ | |
292 | #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */ | |
293 | #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */ | |
294 | #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */ | |
295 | #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */ | |
296 | #define APC_PPAUSE 0x80 /* Pause the play DMA */ | |
297 | #define APC_CPAUSE 0x40 /* Pause the capture DMA */ | |
298 | #define APC_CDC_RESET 0x20 /* CODEC RESET */ | |
299 | #define APC_PDMA_READY 0x08 /* Play DMA Go */ | |
300 | #define APC_CDMA_READY 0x04 /* Capture DMA Go */ | |
301 | #define APC_CHIP_RESET 0x01 /* Reset the chip */ | |
302 | ||
303 | /* EBUS DMA register offsets */ | |
304 | ||
305 | #define EBDMA_CSR 0x00UL /* Control/Status */ | |
306 | #define EBDMA_ADDR 0x04UL /* DMA Address */ | |
307 | #define EBDMA_COUNT 0x08UL /* DMA Count */ | |
308 | ||
309 | /* | |
310 | * Some variables | |
311 | */ | |
312 | ||
313 | static unsigned char freq_bits[14] = { | |
314 | /* 5510 */ 0x00 | CS4231_XTAL2, | |
315 | /* 6620 */ 0x0E | CS4231_XTAL2, | |
316 | /* 8000 */ 0x00 | CS4231_XTAL1, | |
317 | /* 9600 */ 0x0E | CS4231_XTAL1, | |
318 | /* 11025 */ 0x02 | CS4231_XTAL2, | |
319 | /* 16000 */ 0x02 | CS4231_XTAL1, | |
320 | /* 18900 */ 0x04 | CS4231_XTAL2, | |
321 | /* 22050 */ 0x06 | CS4231_XTAL2, | |
322 | /* 27042 */ 0x04 | CS4231_XTAL1, | |
323 | /* 32000 */ 0x06 | CS4231_XTAL1, | |
324 | /* 33075 */ 0x0C | CS4231_XTAL2, | |
325 | /* 37800 */ 0x08 | CS4231_XTAL2, | |
326 | /* 44100 */ 0x0A | CS4231_XTAL2, | |
327 | /* 48000 */ 0x0C | CS4231_XTAL1 | |
328 | }; | |
329 | ||
330 | static unsigned int rates[14] = { | |
331 | 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050, | |
332 | 27042, 32000, 33075, 37800, 44100, 48000 | |
333 | }; | |
334 | ||
be9b7e8c | 335 | static struct snd_pcm_hw_constraint_list hw_constraints_rates = { |
c6c2d57b | 336 | .count = ARRAY_SIZE(rates), |
1da177e4 LT |
337 | .list = rates, |
338 | }; | |
339 | ||
be9b7e8c | 340 | static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime) |
1da177e4 LT |
341 | { |
342 | return snd_pcm_hw_constraint_list(runtime, 0, | |
343 | SNDRV_PCM_HW_PARAM_RATE, | |
344 | &hw_constraints_rates); | |
345 | } | |
346 | ||
347 | static unsigned char snd_cs4231_original_image[32] = | |
348 | { | |
349 | 0x00, /* 00/00 - lic */ | |
350 | 0x00, /* 01/01 - ric */ | |
351 | 0x9f, /* 02/02 - la1ic */ | |
352 | 0x9f, /* 03/03 - ra1ic */ | |
353 | 0x9f, /* 04/04 - la2ic */ | |
354 | 0x9f, /* 05/05 - ra2ic */ | |
355 | 0xbf, /* 06/06 - loc */ | |
356 | 0xbf, /* 07/07 - roc */ | |
357 | 0x20, /* 08/08 - pdfr */ | |
358 | CS4231_AUTOCALIB, /* 09/09 - ic */ | |
359 | 0x00, /* 0a/10 - pc */ | |
360 | 0x00, /* 0b/11 - ti */ | |
361 | CS4231_MODE2, /* 0c/12 - mi */ | |
362 | 0x00, /* 0d/13 - lbc */ | |
363 | 0x00, /* 0e/14 - pbru */ | |
364 | 0x00, /* 0f/15 - pbrl */ | |
365 | 0x80, /* 10/16 - afei */ | |
366 | 0x01, /* 11/17 - afeii */ | |
367 | 0x9f, /* 12/18 - llic */ | |
368 | 0x9f, /* 13/19 - rlic */ | |
369 | 0x00, /* 14/20 - tlb */ | |
370 | 0x00, /* 15/21 - thb */ | |
371 | 0x00, /* 16/22 - la3mic/reserved */ | |
372 | 0x00, /* 17/23 - ra3mic/reserved */ | |
373 | 0x00, /* 18/24 - afs */ | |
374 | 0x00, /* 19/25 - lamoc/version */ | |
375 | 0x00, /* 1a/26 - mioc */ | |
376 | 0x00, /* 1b/27 - ramoc/reserved */ | |
377 | 0x20, /* 1c/28 - cdfr */ | |
378 | 0x00, /* 1d/29 - res4 */ | |
379 | 0x00, /* 1e/30 - cbru */ | |
380 | 0x00, /* 1f/31 - cbrl */ | |
381 | }; | |
382 | ||
be9b7e8c | 383 | static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr) |
1da177e4 LT |
384 | { |
385 | #ifdef EBUS_SUPPORT | |
c6c2d57b | 386 | if (cp->flags & CS4231_FLAG_EBUS) |
1da177e4 | 387 | return readb(reg_addr); |
c6c2d57b | 388 | else |
1da177e4 LT |
389 | #endif |
390 | #ifdef SBUS_SUPPORT | |
391 | return sbus_readb(reg_addr); | |
392 | #endif | |
1da177e4 LT |
393 | } |
394 | ||
be9b7e8c | 395 | static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val, void __iomem *reg_addr) |
1da177e4 LT |
396 | { |
397 | #ifdef EBUS_SUPPORT | |
c6c2d57b | 398 | if (cp->flags & CS4231_FLAG_EBUS) |
1da177e4 | 399 | return writeb(val, reg_addr); |
c6c2d57b | 400 | else |
1da177e4 LT |
401 | #endif |
402 | #ifdef SBUS_SUPPORT | |
403 | return sbus_writeb(val, reg_addr); | |
404 | #endif | |
1da177e4 LT |
405 | } |
406 | ||
407 | /* | |
408 | * Basic I/O functions | |
409 | */ | |
410 | ||
c6c2d57b | 411 | static void snd_cs4231_ready(struct snd_cs4231 *chip) |
1da177e4 LT |
412 | { |
413 | int timeout; | |
1da177e4 LT |
414 | |
415 | for (timeout = 250; | |
416 | timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); | |
417 | timeout--) | |
418 | udelay(100); | |
1da177e4 LT |
419 | } |
420 | ||
be9b7e8c | 421 | static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value) |
1da177e4 | 422 | { |
c6c2d57b | 423 | snd_cs4231_ready(chip); |
a131430c CZ |
424 | #ifdef CONFIG_SND_DEBUG |
425 | if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) | |
c6c2d57b KH |
426 | snd_printdd("out: auto calibration time out - reg = 0x%x, " |
427 | "value = 0x%x\n", | |
428 | reg, value); | |
a131430c | 429 | #endif |
1da177e4 | 430 | __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); |
c6c2d57b | 431 | wmb(); |
1da177e4 LT |
432 | __cs4231_writeb(chip, value, CS4231P(chip, REG)); |
433 | mb(); | |
434 | } | |
435 | ||
c6c2d57b KH |
436 | static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg, |
437 | unsigned char mask, unsigned char value) | |
1da177e4 | 438 | { |
c6c2d57b | 439 | unsigned char tmp = (chip->image[reg] & mask) | value; |
1da177e4 | 440 | |
c6c2d57b KH |
441 | chip->image[reg] = tmp; |
442 | if (!chip->calibrate_mute) | |
443 | snd_cs4231_dout(chip, reg, tmp); | |
444 | } | |
445 | ||
446 | static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, | |
447 | unsigned char value) | |
448 | { | |
449 | snd_cs4231_dout(chip, reg, value); | |
1da177e4 LT |
450 | chip->image[reg] = value; |
451 | mb(); | |
1da177e4 LT |
452 | } |
453 | ||
be9b7e8c | 454 | static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg) |
1da177e4 | 455 | { |
c6c2d57b | 456 | snd_cs4231_ready(chip); |
1da177e4 LT |
457 | #ifdef CONFIG_SND_DEBUG |
458 | if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) | |
c6c2d57b KH |
459 | snd_printdd("in: auto calibration time out - reg = 0x%x\n", |
460 | reg); | |
1da177e4 LT |
461 | #endif |
462 | __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); | |
463 | mb(); | |
c6c2d57b | 464 | return __cs4231_readb(chip, CS4231P(chip, REG)); |
1da177e4 LT |
465 | } |
466 | ||
1da177e4 LT |
467 | /* |
468 | * CS4231 detection / MCE routines | |
469 | */ | |
470 | ||
be9b7e8c | 471 | static void snd_cs4231_busy_wait(struct snd_cs4231 *chip) |
1da177e4 LT |
472 | { |
473 | int timeout; | |
474 | ||
475 | /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */ | |
476 | for (timeout = 5; timeout > 0; timeout--) | |
477 | __cs4231_readb(chip, CS4231P(chip, REGSEL)); | |
a131430c | 478 | |
1da177e4 | 479 | /* end of cleanup sequence */ |
a131430c | 480 | for (timeout = 500; |
1da177e4 LT |
481 | timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); |
482 | timeout--) | |
c6c2d57b | 483 | msleep(1); |
1da177e4 LT |
484 | } |
485 | ||
be9b7e8c | 486 | static void snd_cs4231_mce_up(struct snd_cs4231 *chip) |
1da177e4 LT |
487 | { |
488 | unsigned long flags; | |
489 | int timeout; | |
490 | ||
491 | spin_lock_irqsave(&chip->lock, flags); | |
c6c2d57b | 492 | snd_cs4231_ready(chip); |
1da177e4 LT |
493 | #ifdef CONFIG_SND_DEBUG |
494 | if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) | |
a131430c | 495 | snd_printdd("mce_up - auto calibration time out (0)\n"); |
1da177e4 LT |
496 | #endif |
497 | chip->mce_bit |= CS4231_MCE; | |
498 | timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL)); | |
499 | if (timeout == 0x80) | |
a131430c | 500 | snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip->port); |
1da177e4 LT |
501 | if (!(timeout & CS4231_MCE)) |
502 | __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL)); | |
503 | spin_unlock_irqrestore(&chip->lock, flags); | |
504 | } | |
505 | ||
be9b7e8c | 506 | static void snd_cs4231_mce_down(struct snd_cs4231 *chip) |
1da177e4 LT |
507 | { |
508 | unsigned long flags; | |
509 | int timeout; | |
510 | ||
511 | spin_lock_irqsave(&chip->lock, flags); | |
512 | snd_cs4231_busy_wait(chip); | |
1da177e4 LT |
513 | #ifdef CONFIG_SND_DEBUG |
514 | if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) | |
a131430c | 515 | snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL)); |
1da177e4 LT |
516 | #endif |
517 | chip->mce_bit &= ~CS4231_MCE; | |
518 | timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL)); | |
519 | __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL)); | |
520 | if (timeout == 0x80) | |
a131430c | 521 | snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip->port); |
1da177e4 LT |
522 | if ((timeout & CS4231_MCE) == 0) { |
523 | spin_unlock_irqrestore(&chip->lock, flags); | |
524 | return; | |
525 | } | |
526 | snd_cs4231_busy_wait(chip); | |
527 | ||
528 | /* calibration process */ | |
529 | ||
c6c2d57b KH |
530 | snd_cs4231_ready(chip); |
531 | snd_cs4231_ready(chip); | |
1da177e4 LT |
532 | if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) { |
533 | snd_printd("cs4231_mce_down - auto calibration time out (1)\n"); | |
534 | spin_unlock_irqrestore(&chip->lock, flags); | |
535 | return; | |
536 | } | |
a131430c | 537 | |
1da177e4 LT |
538 | /* in 10ms increments, check condition, up to 250ms */ |
539 | timeout = 25; | |
540 | while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) { | |
541 | spin_unlock_irqrestore(&chip->lock, flags); | |
542 | if (--timeout < 0) { | |
543 | snd_printk("mce_down - auto calibration time out (2)\n"); | |
544 | return; | |
545 | } | |
546 | msleep(10); | |
547 | spin_lock_irqsave(&chip->lock, flags); | |
548 | } | |
a131430c | 549 | |
1da177e4 LT |
550 | /* in 10ms increments, check condition, up to 100ms */ |
551 | timeout = 10; | |
552 | while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) { | |
553 | spin_unlock_irqrestore(&chip->lock, flags); | |
554 | if (--timeout < 0) { | |
555 | snd_printk("mce_down - auto calibration time out (3)\n"); | |
556 | return; | |
557 | } | |
558 | msleep(10); | |
559 | spin_lock_irqsave(&chip->lock, flags); | |
560 | } | |
561 | spin_unlock_irqrestore(&chip->lock, flags); | |
1da177e4 LT |
562 | } |
563 | ||
be9b7e8c TI |
564 | static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont, |
565 | struct snd_pcm_substream *substream, | |
566 | unsigned int *periods_sent) | |
1da177e4 | 567 | { |
be9b7e8c | 568 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
569 | |
570 | while (1) { | |
a131430c CZ |
571 | unsigned int period_size = snd_pcm_lib_period_bytes(substream); |
572 | unsigned int offset = period_size * (*periods_sent); | |
1da177e4 | 573 | |
817dd6ee | 574 | BUG_ON(period_size >= (1 << 24)); |
1da177e4 | 575 | |
b128254f | 576 | if (dma_cont->request(dma_cont, runtime->dma_addr + offset, period_size)) |
1da177e4 | 577 | return; |
1da177e4 LT |
578 | (*periods_sent) = ((*periods_sent) + 1) % runtime->periods; |
579 | } | |
580 | } | |
a131430c | 581 | |
be9b7e8c TI |
582 | static void cs4231_dma_trigger(struct snd_pcm_substream *substream, |
583 | unsigned int what, int on) | |
1da177e4 | 584 | { |
be9b7e8c TI |
585 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
586 | struct cs4231_dma_control *dma_cont; | |
a131430c | 587 | |
5a820fa7 | 588 | if (what & CS4231_PLAYBACK_ENABLE) { |
b128254f | 589 | dma_cont = &chip->p_dma; |
a131430c | 590 | if (on) { |
b128254f GC |
591 | dma_cont->prepare(dma_cont, 0); |
592 | dma_cont->enable(dma_cont, 1); | |
593 | snd_cs4231_advance_dma(dma_cont, | |
5a820fa7 GC |
594 | chip->playback_substream, |
595 | &chip->p_periods_sent); | |
a131430c | 596 | } else { |
b128254f | 597 | dma_cont->enable(dma_cont, 0); |
a131430c | 598 | } |
5a820fa7 GC |
599 | } |
600 | if (what & CS4231_RECORD_ENABLE) { | |
b128254f | 601 | dma_cont = &chip->c_dma; |
a131430c | 602 | if (on) { |
b128254f GC |
603 | dma_cont->prepare(dma_cont, 1); |
604 | dma_cont->enable(dma_cont, 1); | |
605 | snd_cs4231_advance_dma(dma_cont, | |
5a820fa7 GC |
606 | chip->capture_substream, |
607 | &chip->c_periods_sent); | |
a131430c | 608 | } else { |
b128254f | 609 | dma_cont->enable(dma_cont, 0); |
a131430c | 610 | } |
a131430c | 611 | } |
1da177e4 LT |
612 | } |
613 | ||
be9b7e8c | 614 | static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 615 | { |
be9b7e8c | 616 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
617 | int result = 0; |
618 | ||
619 | switch (cmd) { | |
620 | case SNDRV_PCM_TRIGGER_START: | |
621 | case SNDRV_PCM_TRIGGER_STOP: | |
622 | { | |
623 | unsigned int what = 0; | |
be9b7e8c | 624 | struct snd_pcm_substream *s; |
1da177e4 LT |
625 | unsigned long flags; |
626 | ||
ef991b95 | 627 | snd_pcm_group_for_each_entry(s, substream) { |
1da177e4 LT |
628 | if (s == chip->playback_substream) { |
629 | what |= CS4231_PLAYBACK_ENABLE; | |
630 | snd_pcm_trigger_done(s, substream); | |
631 | } else if (s == chip->capture_substream) { | |
632 | what |= CS4231_RECORD_ENABLE; | |
633 | snd_pcm_trigger_done(s, substream); | |
634 | } | |
635 | } | |
636 | ||
1da177e4 LT |
637 | spin_lock_irqsave(&chip->lock, flags); |
638 | if (cmd == SNDRV_PCM_TRIGGER_START) { | |
a131430c | 639 | cs4231_dma_trigger(substream, what, 1); |
1da177e4 | 640 | chip->image[CS4231_IFACE_CTRL] |= what; |
1da177e4 | 641 | } else { |
a131430c | 642 | cs4231_dma_trigger(substream, what, 0); |
1da177e4 LT |
643 | chip->image[CS4231_IFACE_CTRL] &= ~what; |
644 | } | |
645 | snd_cs4231_out(chip, CS4231_IFACE_CTRL, | |
646 | chip->image[CS4231_IFACE_CTRL]); | |
647 | spin_unlock_irqrestore(&chip->lock, flags); | |
648 | break; | |
649 | } | |
650 | default: | |
651 | result = -EINVAL; | |
652 | break; | |
653 | } | |
a131430c | 654 | |
1da177e4 LT |
655 | return result; |
656 | } | |
657 | ||
658 | /* | |
659 | * CODEC I/O | |
660 | */ | |
661 | ||
662 | static unsigned char snd_cs4231_get_rate(unsigned int rate) | |
663 | { | |
664 | int i; | |
665 | ||
666 | for (i = 0; i < 14; i++) | |
667 | if (rate == rates[i]) | |
668 | return freq_bits[i]; | |
669 | // snd_BUG(); | |
670 | return freq_bits[13]; | |
671 | } | |
672 | ||
be9b7e8c | 673 | static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format, int channels) |
1da177e4 LT |
674 | { |
675 | unsigned char rformat; | |
676 | ||
677 | rformat = CS4231_LINEAR_8; | |
678 | switch (format) { | |
679 | case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break; | |
680 | case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break; | |
681 | case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break; | |
682 | case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break; | |
683 | case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break; | |
684 | } | |
685 | if (channels > 1) | |
686 | rformat |= CS4231_STEREO; | |
1da177e4 LT |
687 | return rformat; |
688 | } | |
689 | ||
be9b7e8c | 690 | static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute) |
1da177e4 LT |
691 | { |
692 | unsigned long flags; | |
693 | ||
694 | mute = mute ? 1 : 0; | |
695 | spin_lock_irqsave(&chip->lock, flags); | |
696 | if (chip->calibrate_mute == mute) { | |
697 | spin_unlock_irqrestore(&chip->lock, flags); | |
698 | return; | |
699 | } | |
700 | if (!mute) { | |
701 | snd_cs4231_dout(chip, CS4231_LEFT_INPUT, | |
702 | chip->image[CS4231_LEFT_INPUT]); | |
703 | snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, | |
704 | chip->image[CS4231_RIGHT_INPUT]); | |
705 | snd_cs4231_dout(chip, CS4231_LOOPBACK, | |
706 | chip->image[CS4231_LOOPBACK]); | |
707 | } | |
708 | snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, | |
709 | mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]); | |
710 | snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, | |
711 | mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]); | |
712 | snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, | |
713 | mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]); | |
714 | snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, | |
715 | mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]); | |
716 | snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, | |
717 | mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]); | |
718 | snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, | |
719 | mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]); | |
720 | snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, | |
721 | mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]); | |
722 | snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, | |
723 | mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]); | |
724 | snd_cs4231_dout(chip, CS4231_MONO_CTRL, | |
725 | mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]); | |
726 | chip->calibrate_mute = mute; | |
727 | spin_unlock_irqrestore(&chip->lock, flags); | |
728 | } | |
729 | ||
be9b7e8c | 730 | static void snd_cs4231_playback_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params, |
1da177e4 LT |
731 | unsigned char pdfr) |
732 | { | |
733 | unsigned long flags; | |
734 | ||
12aa7579 | 735 | mutex_lock(&chip->mce_mutex); |
1da177e4 LT |
736 | snd_cs4231_calibrate_mute(chip, 1); |
737 | ||
738 | snd_cs4231_mce_up(chip); | |
739 | ||
740 | spin_lock_irqsave(&chip->lock, flags); | |
741 | snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, | |
742 | (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ? | |
743 | (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) : | |
744 | pdfr); | |
745 | spin_unlock_irqrestore(&chip->lock, flags); | |
746 | ||
747 | snd_cs4231_mce_down(chip); | |
748 | ||
749 | snd_cs4231_calibrate_mute(chip, 0); | |
12aa7579 | 750 | mutex_unlock(&chip->mce_mutex); |
1da177e4 LT |
751 | } |
752 | ||
be9b7e8c | 753 | static void snd_cs4231_capture_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params, |
1da177e4 LT |
754 | unsigned char cdfr) |
755 | { | |
756 | unsigned long flags; | |
757 | ||
12aa7579 | 758 | mutex_lock(&chip->mce_mutex); |
1da177e4 LT |
759 | snd_cs4231_calibrate_mute(chip, 1); |
760 | ||
761 | snd_cs4231_mce_up(chip); | |
762 | ||
763 | spin_lock_irqsave(&chip->lock, flags); | |
764 | if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) { | |
765 | snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, | |
766 | ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) | | |
767 | (cdfr & 0x0f)); | |
768 | spin_unlock_irqrestore(&chip->lock, flags); | |
769 | snd_cs4231_mce_down(chip); | |
770 | snd_cs4231_mce_up(chip); | |
771 | spin_lock_irqsave(&chip->lock, flags); | |
772 | } | |
773 | snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr); | |
774 | spin_unlock_irqrestore(&chip->lock, flags); | |
775 | ||
776 | snd_cs4231_mce_down(chip); | |
777 | ||
778 | snd_cs4231_calibrate_mute(chip, 0); | |
12aa7579 | 779 | mutex_unlock(&chip->mce_mutex); |
1da177e4 LT |
780 | } |
781 | ||
782 | /* | |
783 | * Timer interface | |
784 | */ | |
785 | ||
be9b7e8c | 786 | static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer) |
1da177e4 | 787 | { |
be9b7e8c | 788 | struct snd_cs4231 *chip = snd_timer_chip(timer); |
1da177e4 LT |
789 | |
790 | return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920; | |
791 | } | |
792 | ||
be9b7e8c | 793 | static int snd_cs4231_timer_start(struct snd_timer *timer) |
1da177e4 LT |
794 | { |
795 | unsigned long flags; | |
796 | unsigned int ticks; | |
be9b7e8c | 797 | struct snd_cs4231 *chip = snd_timer_chip(timer); |
1da177e4 LT |
798 | |
799 | spin_lock_irqsave(&chip->lock, flags); | |
800 | ticks = timer->sticks; | |
801 | if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 || | |
802 | (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] || | |
803 | (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) { | |
804 | snd_cs4231_out(chip, CS4231_TIMER_HIGH, | |
805 | chip->image[CS4231_TIMER_HIGH] = | |
806 | (unsigned char) (ticks >> 8)); | |
807 | snd_cs4231_out(chip, CS4231_TIMER_LOW, | |
808 | chip->image[CS4231_TIMER_LOW] = | |
809 | (unsigned char) ticks); | |
810 | snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, | |
811 | chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE); | |
812 | } | |
813 | spin_unlock_irqrestore(&chip->lock, flags); | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
be9b7e8c | 818 | static int snd_cs4231_timer_stop(struct snd_timer *timer) |
1da177e4 LT |
819 | { |
820 | unsigned long flags; | |
be9b7e8c | 821 | struct snd_cs4231 *chip = snd_timer_chip(timer); |
1da177e4 LT |
822 | |
823 | spin_lock_irqsave(&chip->lock, flags); | |
824 | snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, | |
825 | chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE); | |
826 | spin_unlock_irqrestore(&chip->lock, flags); | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
be9b7e8c | 831 | static void __init snd_cs4231_init(struct snd_cs4231 *chip) |
1da177e4 LT |
832 | { |
833 | unsigned long flags; | |
834 | ||
835 | snd_cs4231_mce_down(chip); | |
836 | ||
837 | #ifdef SNDRV_DEBUG_MCE | |
a131430c | 838 | snd_printdd("init: (1)\n"); |
1da177e4 LT |
839 | #endif |
840 | snd_cs4231_mce_up(chip); | |
841 | spin_lock_irqsave(&chip->lock, flags); | |
842 | chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | | |
843 | CS4231_RECORD_ENABLE | CS4231_RECORD_PIO | | |
844 | CS4231_CALIB_MODE); | |
845 | chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB; | |
846 | snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); | |
847 | spin_unlock_irqrestore(&chip->lock, flags); | |
848 | snd_cs4231_mce_down(chip); | |
849 | ||
850 | #ifdef SNDRV_DEBUG_MCE | |
a131430c | 851 | snd_printdd("init: (2)\n"); |
1da177e4 LT |
852 | #endif |
853 | ||
854 | snd_cs4231_mce_up(chip); | |
855 | spin_lock_irqsave(&chip->lock, flags); | |
856 | snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]); | |
857 | spin_unlock_irqrestore(&chip->lock, flags); | |
858 | snd_cs4231_mce_down(chip); | |
859 | ||
860 | #ifdef SNDRV_DEBUG_MCE | |
a131430c | 861 | snd_printdd("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]); |
1da177e4 LT |
862 | #endif |
863 | ||
864 | spin_lock_irqsave(&chip->lock, flags); | |
865 | snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]); | |
866 | spin_unlock_irqrestore(&chip->lock, flags); | |
867 | ||
868 | snd_cs4231_mce_up(chip); | |
869 | spin_lock_irqsave(&chip->lock, flags); | |
870 | snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]); | |
871 | spin_unlock_irqrestore(&chip->lock, flags); | |
872 | snd_cs4231_mce_down(chip); | |
873 | ||
874 | #ifdef SNDRV_DEBUG_MCE | |
a131430c | 875 | snd_printdd("init: (4)\n"); |
1da177e4 LT |
876 | #endif |
877 | ||
878 | snd_cs4231_mce_up(chip); | |
879 | spin_lock_irqsave(&chip->lock, flags); | |
880 | snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]); | |
881 | spin_unlock_irqrestore(&chip->lock, flags); | |
882 | snd_cs4231_mce_down(chip); | |
883 | ||
884 | #ifdef SNDRV_DEBUG_MCE | |
a131430c | 885 | snd_printdd("init: (5)\n"); |
1da177e4 LT |
886 | #endif |
887 | } | |
888 | ||
be9b7e8c | 889 | static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode) |
1da177e4 LT |
890 | { |
891 | unsigned long flags; | |
892 | ||
12aa7579 | 893 | mutex_lock(&chip->open_mutex); |
1da177e4 | 894 | if ((chip->mode & mode)) { |
12aa7579 | 895 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
896 | return -EAGAIN; |
897 | } | |
898 | if (chip->mode & CS4231_MODE_OPEN) { | |
899 | chip->mode |= mode; | |
12aa7579 | 900 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
901 | return 0; |
902 | } | |
903 | /* ok. now enable and ack CODEC IRQ */ | |
904 | spin_lock_irqsave(&chip->lock, flags); | |
905 | snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | | |
906 | CS4231_RECORD_IRQ | | |
907 | CS4231_TIMER_IRQ); | |
908 | snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); | |
909 | __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ | |
910 | __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ | |
911 | ||
912 | snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | | |
913 | CS4231_RECORD_IRQ | | |
914 | CS4231_TIMER_IRQ); | |
915 | snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); | |
a131430c | 916 | |
1da177e4 LT |
917 | spin_unlock_irqrestore(&chip->lock, flags); |
918 | ||
919 | chip->mode = mode; | |
12aa7579 | 920 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
921 | return 0; |
922 | } | |
923 | ||
be9b7e8c | 924 | static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode) |
1da177e4 LT |
925 | { |
926 | unsigned long flags; | |
927 | ||
12aa7579 | 928 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
929 | chip->mode &= ~mode; |
930 | if (chip->mode & CS4231_MODE_OPEN) { | |
12aa7579 | 931 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
932 | return; |
933 | } | |
934 | snd_cs4231_calibrate_mute(chip, 1); | |
935 | ||
936 | /* disable IRQ */ | |
937 | spin_lock_irqsave(&chip->lock, flags); | |
938 | snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); | |
939 | __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ | |
940 | __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ | |
941 | ||
942 | /* now disable record & playback */ | |
943 | ||
944 | if (chip->image[CS4231_IFACE_CTRL] & | |
945 | (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | | |
946 | CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) { | |
947 | spin_unlock_irqrestore(&chip->lock, flags); | |
948 | snd_cs4231_mce_up(chip); | |
949 | spin_lock_irqsave(&chip->lock, flags); | |
950 | chip->image[CS4231_IFACE_CTRL] &= | |
951 | ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | | |
952 | CS4231_RECORD_ENABLE | CS4231_RECORD_PIO); | |
953 | snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); | |
954 | spin_unlock_irqrestore(&chip->lock, flags); | |
955 | snd_cs4231_mce_down(chip); | |
956 | spin_lock_irqsave(&chip->lock, flags); | |
957 | } | |
958 | ||
959 | /* clear IRQ again */ | |
960 | snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); | |
961 | __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ | |
962 | __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ | |
963 | spin_unlock_irqrestore(&chip->lock, flags); | |
964 | ||
965 | snd_cs4231_calibrate_mute(chip, 0); | |
966 | ||
967 | chip->mode = 0; | |
12aa7579 | 968 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
969 | } |
970 | ||
971 | /* | |
972 | * timer open/close | |
973 | */ | |
974 | ||
be9b7e8c | 975 | static int snd_cs4231_timer_open(struct snd_timer *timer) |
1da177e4 | 976 | { |
be9b7e8c | 977 | struct snd_cs4231 *chip = snd_timer_chip(timer); |
1da177e4 LT |
978 | snd_cs4231_open(chip, CS4231_MODE_TIMER); |
979 | return 0; | |
980 | } | |
981 | ||
be9b7e8c | 982 | static int snd_cs4231_timer_close(struct snd_timer * timer) |
1da177e4 | 983 | { |
be9b7e8c | 984 | struct snd_cs4231 *chip = snd_timer_chip(timer); |
1da177e4 LT |
985 | snd_cs4231_close(chip, CS4231_MODE_TIMER); |
986 | return 0; | |
987 | } | |
988 | ||
be9b7e8c | 989 | static struct snd_timer_hardware snd_cs4231_timer_table = |
1da177e4 LT |
990 | { |
991 | .flags = SNDRV_TIMER_HW_AUTO, | |
992 | .resolution = 9945, | |
993 | .ticks = 65535, | |
994 | .open = snd_cs4231_timer_open, | |
995 | .close = snd_cs4231_timer_close, | |
996 | .c_resolution = snd_cs4231_timer_resolution, | |
997 | .start = snd_cs4231_timer_start, | |
998 | .stop = snd_cs4231_timer_stop, | |
999 | }; | |
1000 | ||
1001 | /* | |
1002 | * ok.. exported functions.. | |
1003 | */ | |
1004 | ||
be9b7e8c TI |
1005 | static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream, |
1006 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 1007 | { |
be9b7e8c | 1008 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1009 | unsigned char new_pdfr; |
1010 | int err; | |
1011 | ||
1012 | if ((err = snd_pcm_lib_malloc_pages(substream, | |
1013 | params_buffer_bytes(hw_params))) < 0) | |
1014 | return err; | |
1015 | new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), | |
1016 | params_channels(hw_params)) | | |
1017 | snd_cs4231_get_rate(params_rate(hw_params)); | |
1018 | snd_cs4231_playback_format(chip, hw_params, new_pdfr); | |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
be9b7e8c | 1023 | static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1024 | { |
be9b7e8c TI |
1025 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1026 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1027 | unsigned long flags; |
1028 | ||
1029 | spin_lock_irqsave(&chip->lock, flags); | |
a131430c | 1030 | |
1da177e4 LT |
1031 | chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | |
1032 | CS4231_PLAYBACK_PIO); | |
a131430c | 1033 | |
817dd6ee | 1034 | BUG_ON(runtime->period_size > 0xffff + 1); |
a131430c | 1035 | |
a131430c | 1036 | chip->p_periods_sent = 0; |
1da177e4 LT |
1037 | spin_unlock_irqrestore(&chip->lock, flags); |
1038 | ||
1039 | return 0; | |
1040 | } | |
1041 | ||
be9b7e8c TI |
1042 | static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream, |
1043 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 1044 | { |
be9b7e8c | 1045 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1046 | unsigned char new_cdfr; |
1047 | int err; | |
1048 | ||
1049 | if ((err = snd_pcm_lib_malloc_pages(substream, | |
1050 | params_buffer_bytes(hw_params))) < 0) | |
1051 | return err; | |
1052 | new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), | |
1053 | params_channels(hw_params)) | | |
1054 | snd_cs4231_get_rate(params_rate(hw_params)); | |
1055 | snd_cs4231_capture_format(chip, hw_params, new_cdfr); | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
be9b7e8c | 1060 | static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1061 | { |
be9b7e8c | 1062 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1063 | unsigned long flags; |
1064 | ||
1065 | spin_lock_irqsave(&chip->lock, flags); | |
1066 | chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | | |
1067 | CS4231_RECORD_PIO); | |
1068 | ||
a131430c | 1069 | |
5a820fa7 | 1070 | chip->c_periods_sent = 0; |
1da177e4 LT |
1071 | spin_unlock_irqrestore(&chip->lock, flags); |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
be9b7e8c | 1076 | static void snd_cs4231_overrange(struct snd_cs4231 *chip) |
1da177e4 LT |
1077 | { |
1078 | unsigned long flags; | |
1079 | unsigned char res; | |
1080 | ||
1081 | spin_lock_irqsave(&chip->lock, flags); | |
1082 | res = snd_cs4231_in(chip, CS4231_TEST_INIT); | |
1083 | spin_unlock_irqrestore(&chip->lock, flags); | |
1084 | ||
1085 | if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */ | |
1086 | chip->capture_substream->runtime->overrange++; | |
1087 | } | |
1088 | ||
be9b7e8c | 1089 | static void snd_cs4231_play_callback(struct snd_cs4231 *chip) |
1da177e4 | 1090 | { |
1da177e4 LT |
1091 | if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) { |
1092 | snd_pcm_period_elapsed(chip->playback_substream); | |
b128254f | 1093 | snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream, |
1da177e4 LT |
1094 | &chip->p_periods_sent); |
1095 | } | |
1096 | } | |
1097 | ||
be9b7e8c | 1098 | static void snd_cs4231_capture_callback(struct snd_cs4231 *chip) |
1da177e4 | 1099 | { |
1da177e4 LT |
1100 | if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) { |
1101 | snd_pcm_period_elapsed(chip->capture_substream); | |
b128254f | 1102 | snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream, |
1da177e4 LT |
1103 | &chip->c_periods_sent); |
1104 | } | |
1105 | } | |
1da177e4 | 1106 | |
be9b7e8c | 1107 | static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1108 | { |
be9b7e8c TI |
1109 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1110 | struct cs4231_dma_control *dma_cont = &chip->p_dma; | |
5a820fa7 | 1111 | size_t ptr; |
5a820fa7 | 1112 | |
1da177e4 LT |
1113 | if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) |
1114 | return 0; | |
b128254f GC |
1115 | ptr = dma_cont->address(dma_cont); |
1116 | if (ptr != 0) | |
1117 | ptr -= substream->runtime->dma_addr; | |
1118 | ||
1da177e4 LT |
1119 | return bytes_to_frames(substream->runtime, ptr); |
1120 | } | |
1121 | ||
be9b7e8c | 1122 | static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1123 | { |
be9b7e8c TI |
1124 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1125 | struct cs4231_dma_control *dma_cont = &chip->c_dma; | |
5a820fa7 | 1126 | size_t ptr; |
1da177e4 LT |
1127 | |
1128 | if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)) | |
1129 | return 0; | |
b128254f GC |
1130 | ptr = dma_cont->address(dma_cont); |
1131 | if (ptr != 0) | |
1132 | ptr -= substream->runtime->dma_addr; | |
1133 | ||
1da177e4 LT |
1134 | return bytes_to_frames(substream->runtime, ptr); |
1135 | } | |
1136 | ||
be9b7e8c | 1137 | static int __init snd_cs4231_probe(struct snd_cs4231 *chip) |
1da177e4 LT |
1138 | { |
1139 | unsigned long flags; | |
1140 | int i, id, vers; | |
1141 | unsigned char *ptr; | |
1142 | ||
1da177e4 LT |
1143 | id = vers = 0; |
1144 | for (i = 0; i < 50; i++) { | |
1145 | mb(); | |
1146 | if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) | |
1147 | udelay(2000); | |
1148 | else { | |
1149 | spin_lock_irqsave(&chip->lock, flags); | |
1150 | snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2); | |
1151 | id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f; | |
1152 | vers = snd_cs4231_in(chip, CS4231_VERSION); | |
1153 | spin_unlock_irqrestore(&chip->lock, flags); | |
1154 | if (id == 0x0a) | |
1155 | break; /* this is valid value */ | |
1156 | } | |
1157 | } | |
1158 | snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id); | |
1159 | if (id != 0x0a) | |
1160 | return -ENODEV; /* no valid device found */ | |
1161 | ||
1162 | spin_lock_irqsave(&chip->lock, flags); | |
1163 | ||
1da177e4 LT |
1164 | __cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */ |
1165 | __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); | |
1166 | mb(); | |
1167 | ||
1168 | spin_unlock_irqrestore(&chip->lock, flags); | |
1169 | ||
1170 | chip->image[CS4231_MISC_INFO] = CS4231_MODE2; | |
1171 | chip->image[CS4231_IFACE_CTRL] = | |
1172 | chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA; | |
1173 | chip->image[CS4231_ALT_FEATURE_1] = 0x80; | |
1174 | chip->image[CS4231_ALT_FEATURE_2] = 0x01; | |
1175 | if (vers & 0x20) | |
1176 | chip->image[CS4231_ALT_FEATURE_2] |= 0x02; | |
1177 | ||
1178 | ptr = (unsigned char *) &chip->image; | |
1179 | ||
1180 | snd_cs4231_mce_down(chip); | |
1181 | ||
1182 | spin_lock_irqsave(&chip->lock, flags); | |
1183 | ||
1184 | for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */ | |
1185 | snd_cs4231_out(chip, i, *ptr++); | |
1186 | ||
1187 | spin_unlock_irqrestore(&chip->lock, flags); | |
1188 | ||
1189 | snd_cs4231_mce_up(chip); | |
1190 | ||
1191 | snd_cs4231_mce_down(chip); | |
1192 | ||
1193 | mdelay(2); | |
1194 | ||
1195 | return 0; /* all things are ok.. */ | |
1196 | } | |
1197 | ||
be9b7e8c | 1198 | static struct snd_pcm_hardware snd_cs4231_playback = |
1da177e4 LT |
1199 | { |
1200 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1201 | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), | |
1202 | .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | | |
1203 | SNDRV_PCM_FMTBIT_IMA_ADPCM | | |
1204 | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | | |
1205 | SNDRV_PCM_FMTBIT_S16_BE), | |
1206 | .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, | |
1207 | .rate_min = 5510, | |
1208 | .rate_max = 48000, | |
1209 | .channels_min = 1, | |
1210 | .channels_max = 2, | |
1211 | .buffer_bytes_max = (32*1024), | |
f9af1d9d | 1212 | .period_bytes_min = 64, |
1da177e4 LT |
1213 | .period_bytes_max = (32*1024), |
1214 | .periods_min = 1, | |
1215 | .periods_max = 1024, | |
1216 | }; | |
1217 | ||
be9b7e8c | 1218 | static struct snd_pcm_hardware snd_cs4231_capture = |
1da177e4 LT |
1219 | { |
1220 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1221 | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), | |
1222 | .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | | |
1223 | SNDRV_PCM_FMTBIT_IMA_ADPCM | | |
1224 | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | | |
1225 | SNDRV_PCM_FMTBIT_S16_BE), | |
1226 | .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, | |
1227 | .rate_min = 5510, | |
1228 | .rate_max = 48000, | |
1229 | .channels_min = 1, | |
1230 | .channels_max = 2, | |
1231 | .buffer_bytes_max = (32*1024), | |
f9af1d9d | 1232 | .period_bytes_min = 64, |
1da177e4 LT |
1233 | .period_bytes_max = (32*1024), |
1234 | .periods_min = 1, | |
1235 | .periods_max = 1024, | |
1236 | }; | |
1237 | ||
be9b7e8c | 1238 | static int snd_cs4231_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 1239 | { |
be9b7e8c TI |
1240 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1241 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1242 | int err; |
1243 | ||
1244 | runtime->hw = snd_cs4231_playback; | |
1245 | ||
1246 | if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) { | |
1247 | snd_free_pages(runtime->dma_area, runtime->dma_bytes); | |
1248 | return err; | |
1249 | } | |
1250 | chip->playback_substream = substream; | |
1251 | chip->p_periods_sent = 0; | |
1252 | snd_pcm_set_sync(substream); | |
1253 | snd_cs4231_xrate(runtime); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
be9b7e8c | 1258 | static int snd_cs4231_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 1259 | { |
be9b7e8c TI |
1260 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1261 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1262 | int err; |
1263 | ||
1264 | runtime->hw = snd_cs4231_capture; | |
1265 | ||
1266 | if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) { | |
1267 | snd_free_pages(runtime->dma_area, runtime->dma_bytes); | |
1268 | return err; | |
1269 | } | |
1270 | chip->capture_substream = substream; | |
1271 | chip->c_periods_sent = 0; | |
1272 | snd_pcm_set_sync(substream); | |
1273 | snd_cs4231_xrate(runtime); | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
be9b7e8c | 1278 | static int snd_cs4231_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 1279 | { |
be9b7e8c | 1280 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 1281 | |
1da177e4 | 1282 | snd_cs4231_close(chip, CS4231_MODE_PLAY); |
b128254f | 1283 | chip->playback_substream = NULL; |
1da177e4 LT |
1284 | |
1285 | return 0; | |
1286 | } | |
1287 | ||
be9b7e8c | 1288 | static int snd_cs4231_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1289 | { |
be9b7e8c | 1290 | struct snd_cs4231 *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 1291 | |
1da177e4 | 1292 | snd_cs4231_close(chip, CS4231_MODE_RECORD); |
b128254f | 1293 | chip->capture_substream = NULL; |
1da177e4 LT |
1294 | |
1295 | return 0; | |
1296 | } | |
1297 | ||
1298 | /* XXX We can do some power-management, in particular on EBUS using | |
1299 | * XXX the audio AUXIO register... | |
1300 | */ | |
1301 | ||
be9b7e8c | 1302 | static struct snd_pcm_ops snd_cs4231_playback_ops = { |
1da177e4 LT |
1303 | .open = snd_cs4231_playback_open, |
1304 | .close = snd_cs4231_playback_close, | |
1305 | .ioctl = snd_pcm_lib_ioctl, | |
1306 | .hw_params = snd_cs4231_playback_hw_params, | |
c6c2d57b | 1307 | .hw_free = snd_pcm_lib_free_pages, |
1da177e4 LT |
1308 | .prepare = snd_cs4231_playback_prepare, |
1309 | .trigger = snd_cs4231_trigger, | |
1310 | .pointer = snd_cs4231_playback_pointer, | |
1311 | }; | |
1312 | ||
be9b7e8c | 1313 | static struct snd_pcm_ops snd_cs4231_capture_ops = { |
1da177e4 LT |
1314 | .open = snd_cs4231_capture_open, |
1315 | .close = snd_cs4231_capture_close, | |
1316 | .ioctl = snd_pcm_lib_ioctl, | |
1317 | .hw_params = snd_cs4231_capture_hw_params, | |
c6c2d57b | 1318 | .hw_free = snd_pcm_lib_free_pages, |
1da177e4 LT |
1319 | .prepare = snd_cs4231_capture_prepare, |
1320 | .trigger = snd_cs4231_trigger, | |
1321 | .pointer = snd_cs4231_capture_pointer, | |
1322 | }; | |
1323 | ||
c6c2d57b | 1324 | static int __init snd_cs4231_pcm(struct snd_card *card) |
1da177e4 | 1325 | { |
c6c2d57b | 1326 | struct snd_cs4231 *chip = card->private_data; |
be9b7e8c | 1327 | struct snd_pcm *pcm; |
1da177e4 LT |
1328 | int err; |
1329 | ||
c6c2d57b KH |
1330 | err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm); |
1331 | if (err < 0) | |
1da177e4 LT |
1332 | return err; |
1333 | ||
1334 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops); | |
1335 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops); | |
1336 | ||
1337 | /* global setup */ | |
1338 | pcm->private_data = chip; | |
1da177e4 LT |
1339 | pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; |
1340 | strcpy(pcm->name, "CS4231"); | |
1341 | ||
b128254f | 1342 | chip->p_dma.preallocate(chip, pcm); |
1da177e4 LT |
1343 | |
1344 | chip->pcm = pcm; | |
1345 | ||
1346 | return 0; | |
1347 | } | |
1348 | ||
c6c2d57b | 1349 | static int __init snd_cs4231_timer(struct snd_card *card) |
1da177e4 | 1350 | { |
c6c2d57b | 1351 | struct snd_cs4231 *chip = card->private_data; |
be9b7e8c TI |
1352 | struct snd_timer *timer; |
1353 | struct snd_timer_id tid; | |
1da177e4 LT |
1354 | int err; |
1355 | ||
1356 | /* Timer initialization */ | |
1357 | tid.dev_class = SNDRV_TIMER_CLASS_CARD; | |
1358 | tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; | |
c6c2d57b | 1359 | tid.card = card->number; |
1da177e4 LT |
1360 | tid.device = 0; |
1361 | tid.subdevice = 0; | |
c6c2d57b KH |
1362 | err = snd_timer_new(card, "CS4231", &tid, &timer); |
1363 | if (err < 0) | |
1da177e4 LT |
1364 | return err; |
1365 | strcpy(timer->name, "CS4231"); | |
1366 | timer->private_data = chip; | |
1da177e4 LT |
1367 | timer->hw = snd_cs4231_timer_table; |
1368 | chip->timer = timer; | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | /* | |
1374 | * MIXER part | |
1375 | */ | |
1376 | ||
be9b7e8c TI |
1377 | static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, |
1378 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1379 | { |
1380 | static char *texts[4] = { | |
1381 | "Line", "CD", "Mic", "Mix" | |
1382 | }; | |
1da177e4 | 1383 | |
1da177e4 LT |
1384 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
1385 | uinfo->count = 2; | |
1386 | uinfo->value.enumerated.items = 4; | |
1387 | if (uinfo->value.enumerated.item > 3) | |
1388 | uinfo->value.enumerated.item = 3; | |
1389 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
1390 | ||
1391 | return 0; | |
1392 | } | |
1393 | ||
be9b7e8c TI |
1394 | static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, |
1395 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1396 | { |
be9b7e8c | 1397 | struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1398 | unsigned long flags; |
1399 | ||
1400 | spin_lock_irqsave(&chip->lock, flags); | |
1401 | ucontrol->value.enumerated.item[0] = | |
1402 | (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6; | |
1403 | ucontrol->value.enumerated.item[1] = | |
1404 | (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6; | |
1405 | spin_unlock_irqrestore(&chip->lock, flags); | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
be9b7e8c TI |
1410 | static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, |
1411 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1412 | { |
be9b7e8c | 1413 | struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1414 | unsigned long flags; |
1415 | unsigned short left, right; | |
1416 | int change; | |
1417 | ||
1418 | if (ucontrol->value.enumerated.item[0] > 3 || | |
1419 | ucontrol->value.enumerated.item[1] > 3) | |
1420 | return -EINVAL; | |
1421 | left = ucontrol->value.enumerated.item[0] << 6; | |
1422 | right = ucontrol->value.enumerated.item[1] << 6; | |
1423 | ||
1424 | spin_lock_irqsave(&chip->lock, flags); | |
1425 | ||
1426 | left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left; | |
1427 | right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right; | |
1428 | change = left != chip->image[CS4231_LEFT_INPUT] || | |
1429 | right != chip->image[CS4231_RIGHT_INPUT]; | |
1430 | snd_cs4231_out(chip, CS4231_LEFT_INPUT, left); | |
1431 | snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right); | |
1432 | ||
1433 | spin_unlock_irqrestore(&chip->lock, flags); | |
1434 | ||
1435 | return change; | |
1436 | } | |
1437 | ||
be9b7e8c TI |
1438 | static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, |
1439 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1440 | { |
1441 | int mask = (kcontrol->private_value >> 16) & 0xff; | |
1442 | ||
1443 | uinfo->type = (mask == 1) ? | |
1444 | SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1445 | uinfo->count = 1; | |
1446 | uinfo->value.integer.min = 0; | |
1447 | uinfo->value.integer.max = mask; | |
1448 | ||
1449 | return 0; | |
1450 | } | |
1451 | ||
be9b7e8c TI |
1452 | static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, |
1453 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1454 | { |
be9b7e8c | 1455 | struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1456 | unsigned long flags; |
1457 | int reg = kcontrol->private_value & 0xff; | |
1458 | int shift = (kcontrol->private_value >> 8) & 0xff; | |
1459 | int mask = (kcontrol->private_value >> 16) & 0xff; | |
1460 | int invert = (kcontrol->private_value >> 24) & 0xff; | |
1461 | ||
1462 | spin_lock_irqsave(&chip->lock, flags); | |
1463 | ||
1464 | ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask; | |
1465 | ||
1466 | spin_unlock_irqrestore(&chip->lock, flags); | |
1467 | ||
1468 | if (invert) | |
1469 | ucontrol->value.integer.value[0] = | |
1470 | (mask - ucontrol->value.integer.value[0]); | |
1471 | ||
1472 | return 0; | |
1473 | } | |
1474 | ||
be9b7e8c TI |
1475 | static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, |
1476 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1477 | { |
be9b7e8c | 1478 | struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1479 | unsigned long flags; |
1480 | int reg = kcontrol->private_value & 0xff; | |
1481 | int shift = (kcontrol->private_value >> 8) & 0xff; | |
1482 | int mask = (kcontrol->private_value >> 16) & 0xff; | |
1483 | int invert = (kcontrol->private_value >> 24) & 0xff; | |
1484 | int change; | |
1485 | unsigned short val; | |
1486 | ||
1487 | val = (ucontrol->value.integer.value[0] & mask); | |
1488 | if (invert) | |
1489 | val = mask - val; | |
1490 | val <<= shift; | |
1491 | ||
1492 | spin_lock_irqsave(&chip->lock, flags); | |
1493 | ||
1494 | val = (chip->image[reg] & ~(mask << shift)) | val; | |
1495 | change = val != chip->image[reg]; | |
1496 | snd_cs4231_out(chip, reg, val); | |
1497 | ||
1498 | spin_unlock_irqrestore(&chip->lock, flags); | |
1499 | ||
1500 | return change; | |
1501 | } | |
1502 | ||
be9b7e8c TI |
1503 | static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, |
1504 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1505 | { |
1506 | int mask = (kcontrol->private_value >> 24) & 0xff; | |
1507 | ||
1508 | uinfo->type = mask == 1 ? | |
1509 | SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1510 | uinfo->count = 2; | |
1511 | uinfo->value.integer.min = 0; | |
1512 | uinfo->value.integer.max = mask; | |
1513 | ||
1514 | return 0; | |
1515 | } | |
1516 | ||
be9b7e8c TI |
1517 | static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, |
1518 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1519 | { |
be9b7e8c | 1520 | struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1521 | unsigned long flags; |
1522 | int left_reg = kcontrol->private_value & 0xff; | |
1523 | int right_reg = (kcontrol->private_value >> 8) & 0xff; | |
1524 | int shift_left = (kcontrol->private_value >> 16) & 0x07; | |
1525 | int shift_right = (kcontrol->private_value >> 19) & 0x07; | |
1526 | int mask = (kcontrol->private_value >> 24) & 0xff; | |
1527 | int invert = (kcontrol->private_value >> 22) & 1; | |
1528 | ||
1529 | spin_lock_irqsave(&chip->lock, flags); | |
1530 | ||
1531 | ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask; | |
1532 | ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask; | |
1533 | ||
1534 | spin_unlock_irqrestore(&chip->lock, flags); | |
1535 | ||
1536 | if (invert) { | |
1537 | ucontrol->value.integer.value[0] = | |
1538 | (mask - ucontrol->value.integer.value[0]); | |
1539 | ucontrol->value.integer.value[1] = | |
1540 | (mask - ucontrol->value.integer.value[1]); | |
1541 | } | |
1542 | ||
1543 | return 0; | |
1544 | } | |
1545 | ||
be9b7e8c TI |
1546 | static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, |
1547 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1548 | { |
be9b7e8c | 1549 | struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1550 | unsigned long flags; |
1551 | int left_reg = kcontrol->private_value & 0xff; | |
1552 | int right_reg = (kcontrol->private_value >> 8) & 0xff; | |
1553 | int shift_left = (kcontrol->private_value >> 16) & 0x07; | |
1554 | int shift_right = (kcontrol->private_value >> 19) & 0x07; | |
1555 | int mask = (kcontrol->private_value >> 24) & 0xff; | |
1556 | int invert = (kcontrol->private_value >> 22) & 1; | |
1557 | int change; | |
1558 | unsigned short val1, val2; | |
1559 | ||
1560 | val1 = ucontrol->value.integer.value[0] & mask; | |
1561 | val2 = ucontrol->value.integer.value[1] & mask; | |
1562 | if (invert) { | |
1563 | val1 = mask - val1; | |
1564 | val2 = mask - val2; | |
1565 | } | |
1566 | val1 <<= shift_left; | |
1567 | val2 <<= shift_right; | |
1568 | ||
1569 | spin_lock_irqsave(&chip->lock, flags); | |
1570 | ||
1571 | val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1; | |
1572 | val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2; | |
1573 | change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg]; | |
1574 | snd_cs4231_out(chip, left_reg, val1); | |
1575 | snd_cs4231_out(chip, right_reg, val2); | |
1576 | ||
1577 | spin_unlock_irqrestore(&chip->lock, flags); | |
1578 | ||
1579 | return change; | |
1580 | } | |
1581 | ||
1582 | #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \ | |
1583 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ | |
1584 | .info = snd_cs4231_info_single, \ | |
1585 | .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \ | |
1586 | .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } | |
1587 | ||
1588 | #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ | |
1589 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ | |
1590 | .info = snd_cs4231_info_double, \ | |
1591 | .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \ | |
1592 | .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } | |
1593 | ||
be9b7e8c | 1594 | static struct snd_kcontrol_new snd_cs4231_controls[] __initdata = { |
1da177e4 LT |
1595 | CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1), |
1596 | CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1), | |
1597 | CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1), | |
1598 | CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1), | |
1599 | CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1), | |
1600 | CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1), | |
1601 | CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1), | |
1602 | CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1), | |
1603 | CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1), | |
1604 | CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1), | |
1605 | CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1), | |
1606 | CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0), | |
1607 | CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0), | |
1608 | { | |
1609 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
1610 | .name = "Capture Source", | |
1611 | .info = snd_cs4231_info_mux, | |
1612 | .get = snd_cs4231_get_mux, | |
1613 | .put = snd_cs4231_put_mux, | |
1614 | }, | |
1615 | CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0), | |
1616 | CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0), | |
1617 | CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1), | |
1618 | /* SPARC specific uses of XCTL{0,1} general purpose outputs. */ | |
1619 | CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1), | |
1620 | CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1) | |
1621 | }; | |
1622 | ||
c6c2d57b | 1623 | static int __init snd_cs4231_mixer(struct snd_card *card) |
1da177e4 | 1624 | { |
c6c2d57b | 1625 | struct snd_cs4231 *chip = card->private_data; |
1da177e4 LT |
1626 | int err, idx; |
1627 | ||
1628 | snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL); | |
1629 | ||
1da177e4 LT |
1630 | strcpy(card->mixername, chip->pcm->name); |
1631 | ||
1632 | for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) { | |
c6c2d57b KH |
1633 | err = snd_ctl_add(card, |
1634 | snd_ctl_new1(&snd_cs4231_controls[idx], chip)); | |
1635 | if (err < 0) | |
1da177e4 LT |
1636 | return err; |
1637 | } | |
1638 | return 0; | |
1639 | } | |
1640 | ||
1641 | static int dev; | |
1642 | ||
be9b7e8c | 1643 | static int __init cs4231_attach_begin(struct snd_card **rcard) |
1da177e4 | 1644 | { |
be9b7e8c | 1645 | struct snd_card *card; |
c6c2d57b | 1646 | struct snd_cs4231 *chip; |
1da177e4 LT |
1647 | |
1648 | *rcard = NULL; | |
1649 | ||
1650 | if (dev >= SNDRV_CARDS) | |
1651 | return -ENODEV; | |
1652 | ||
1653 | if (!enable[dev]) { | |
1654 | dev++; | |
1655 | return -ENOENT; | |
1656 | } | |
1657 | ||
c6c2d57b KH |
1658 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, |
1659 | sizeof(struct snd_cs4231)); | |
1da177e4 LT |
1660 | if (card == NULL) |
1661 | return -ENOMEM; | |
1662 | ||
1663 | strcpy(card->driver, "CS4231"); | |
1664 | strcpy(card->shortname, "Sun CS4231"); | |
1665 | ||
c6c2d57b KH |
1666 | chip = card->private_data; |
1667 | chip->card = card; | |
1668 | ||
1da177e4 LT |
1669 | *rcard = card; |
1670 | return 0; | |
1671 | } | |
1672 | ||
c6c2d57b | 1673 | static int __init cs4231_attach_finish(struct snd_card *card) |
1da177e4 | 1674 | { |
c6c2d57b | 1675 | struct snd_cs4231 *chip = card->private_data; |
1da177e4 LT |
1676 | int err; |
1677 | ||
c6c2d57b KH |
1678 | err = snd_cs4231_pcm(card); |
1679 | if (err < 0) | |
1da177e4 LT |
1680 | goto out_err; |
1681 | ||
c6c2d57b KH |
1682 | err = snd_cs4231_mixer(card); |
1683 | if (err < 0) | |
1da177e4 LT |
1684 | goto out_err; |
1685 | ||
c6c2d57b KH |
1686 | err = snd_cs4231_timer(card); |
1687 | if (err < 0) | |
1da177e4 LT |
1688 | goto out_err; |
1689 | ||
c6c2d57b KH |
1690 | err = snd_card_register(card); |
1691 | if (err < 0) | |
1da177e4 LT |
1692 | goto out_err; |
1693 | ||
1694 | chip->next = cs4231_list; | |
1695 | cs4231_list = chip; | |
1696 | ||
1697 | dev++; | |
1698 | return 0; | |
1699 | ||
1700 | out_err: | |
1701 | snd_card_free(card); | |
1702 | return err; | |
1703 | } | |
1704 | ||
1705 | #ifdef SBUS_SUPPORT | |
b128254f | 1706 | |
7d12e780 | 1707 | static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id) |
b128254f GC |
1708 | { |
1709 | unsigned long flags; | |
1710 | unsigned char status; | |
1711 | u32 csr; | |
be9b7e8c | 1712 | struct snd_cs4231 *chip = dev_id; |
b128254f GC |
1713 | |
1714 | /*This is IRQ is not raised by the cs4231*/ | |
1715 | if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ)) | |
1716 | return IRQ_NONE; | |
1717 | ||
1718 | /* ACK the APC interrupt. */ | |
1719 | csr = sbus_readl(chip->port + APCCSR); | |
1720 | ||
1721 | sbus_writel(csr, chip->port + APCCSR); | |
1722 | ||
1723 | if ((csr & APC_PDMA_READY) && | |
1724 | (csr & APC_PLAY_INT) && | |
1725 | (csr & APC_XINT_PNVA) && | |
1726 | !(csr & APC_XINT_EMPT)) | |
1727 | snd_cs4231_play_callback(chip); | |
1728 | ||
1729 | if ((csr & APC_CDMA_READY) && | |
1730 | (csr & APC_CAPT_INT) && | |
1731 | (csr & APC_XINT_CNVA) && | |
1732 | !(csr & APC_XINT_EMPT)) | |
1733 | snd_cs4231_capture_callback(chip); | |
1734 | ||
1735 | status = snd_cs4231_in(chip, CS4231_IRQ_STATUS); | |
1736 | ||
1737 | if (status & CS4231_TIMER_IRQ) { | |
1738 | if (chip->timer) | |
1739 | snd_timer_interrupt(chip->timer, chip->timer->sticks); | |
1740 | } | |
1741 | ||
1742 | if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY)) | |
1743 | snd_cs4231_overrange(chip); | |
1744 | ||
1745 | /* ACK the CS4231 interrupt. */ | |
1746 | spin_lock_irqsave(&chip->lock, flags); | |
1747 | snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0); | |
1748 | spin_unlock_irqrestore(&chip->lock, flags); | |
1749 | ||
d35a1b9e | 1750 | return IRQ_HANDLED; |
b128254f GC |
1751 | } |
1752 | ||
1753 | /* | |
1754 | * SBUS DMA routines | |
1755 | */ | |
1756 | ||
be9b7e8c | 1757 | static int sbus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len) |
b128254f GC |
1758 | { |
1759 | unsigned long flags; | |
1760 | u32 test, csr; | |
1761 | int err; | |
be9b7e8c | 1762 | struct sbus_dma_info *base = &dma_cont->sbus_info; |
b128254f GC |
1763 | |
1764 | if (len >= (1 << 24)) | |
1765 | return -EINVAL; | |
1766 | spin_lock_irqsave(&base->lock, flags); | |
1767 | csr = sbus_readl(base->regs + APCCSR); | |
1768 | err = -EINVAL; | |
1769 | test = APC_CDMA_READY; | |
1770 | if ( base->dir == APC_PLAY ) | |
1771 | test = APC_PDMA_READY; | |
1772 | if (!(csr & test)) | |
1773 | goto out; | |
1774 | err = -EBUSY; | |
b128254f GC |
1775 | test = APC_XINT_CNVA; |
1776 | if ( base->dir == APC_PLAY ) | |
1777 | test = APC_XINT_PNVA; | |
1778 | if (!(csr & test)) | |
1779 | goto out; | |
1780 | err = 0; | |
1781 | sbus_writel(bus_addr, base->regs + base->dir + APCNVA); | |
1782 | sbus_writel(len, base->regs + base->dir + APCNC); | |
1783 | out: | |
1784 | spin_unlock_irqrestore(&base->lock, flags); | |
1785 | return err; | |
1786 | } | |
1787 | ||
be9b7e8c | 1788 | static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d) |
b128254f GC |
1789 | { |
1790 | unsigned long flags; | |
1791 | u32 csr, test; | |
be9b7e8c | 1792 | struct sbus_dma_info *base = &dma_cont->sbus_info; |
b128254f GC |
1793 | |
1794 | spin_lock_irqsave(&base->lock, flags); | |
1795 | csr = sbus_readl(base->regs + APCCSR); | |
1796 | test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA | | |
1797 | APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL | | |
1798 | APC_XINT_PENA; | |
1799 | if ( base->dir == APC_RECORD ) | |
1800 | test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA | | |
1801 | APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL; | |
1802 | csr |= test; | |
1803 | sbus_writel(csr, base->regs + APCCSR); | |
1804 | spin_unlock_irqrestore(&base->lock, flags); | |
1805 | } | |
1806 | ||
be9b7e8c | 1807 | static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on) |
b128254f GC |
1808 | { |
1809 | unsigned long flags; | |
1810 | u32 csr, shift; | |
be9b7e8c | 1811 | struct sbus_dma_info *base = &dma_cont->sbus_info; |
b128254f GC |
1812 | |
1813 | spin_lock_irqsave(&base->lock, flags); | |
1814 | if (!on) { | |
d35a1b9e GC |
1815 | sbus_writel(0, base->regs + base->dir + APCNC); |
1816 | sbus_writel(0, base->regs + base->dir + APCNVA); | |
3daadf33 GC |
1817 | if ( base->dir == APC_PLAY ) { |
1818 | sbus_writel(0, base->regs + base->dir + APCC); | |
1819 | sbus_writel(0, base->regs + base->dir + APCVA); | |
1820 | } | |
d35a1b9e | 1821 | |
3daadf33 | 1822 | udelay(1200); |
b128254f | 1823 | } |
b128254f GC |
1824 | csr = sbus_readl(base->regs + APCCSR); |
1825 | shift = 0; | |
1826 | if ( base->dir == APC_PLAY ) | |
1827 | shift = 1; | |
1828 | if (on) | |
1829 | csr &= ~(APC_CPAUSE << shift); | |
1830 | else | |
1831 | csr |= (APC_CPAUSE << shift); | |
1832 | sbus_writel(csr, base->regs + APCCSR); | |
1833 | if (on) | |
1834 | csr |= (APC_CDMA_READY << shift); | |
1835 | else | |
1836 | csr &= ~(APC_CDMA_READY << shift); | |
1837 | sbus_writel(csr, base->regs + APCCSR); | |
1838 | ||
1839 | spin_unlock_irqrestore(&base->lock, flags); | |
1840 | } | |
1841 | ||
be9b7e8c | 1842 | static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont) |
b128254f | 1843 | { |
be9b7e8c | 1844 | struct sbus_dma_info *base = &dma_cont->sbus_info; |
b128254f GC |
1845 | |
1846 | return sbus_readl(base->regs + base->dir + APCVA); | |
1847 | } | |
1848 | ||
be9b7e8c | 1849 | static void sbus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm) |
b128254f GC |
1850 | { |
1851 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS, | |
1852 | snd_dma_sbus_data(chip->dev_u.sdev), | |
1853 | 64*1024, 128*1024); | |
1854 | } | |
1855 | ||
1856 | /* | |
1857 | * Init and exit routines | |
1858 | */ | |
1859 | ||
be9b7e8c | 1860 | static int snd_cs4231_sbus_free(struct snd_cs4231 *chip) |
1da177e4 LT |
1861 | { |
1862 | if (chip->irq[0]) | |
1863 | free_irq(chip->irq[0], chip); | |
1864 | ||
1865 | if (chip->port) | |
1866 | sbus_iounmap(chip->port, chip->regs_size); | |
1867 | ||
1da177e4 LT |
1868 | return 0; |
1869 | } | |
1870 | ||
be9b7e8c | 1871 | static int snd_cs4231_sbus_dev_free(struct snd_device *device) |
1da177e4 | 1872 | { |
be9b7e8c | 1873 | struct snd_cs4231 *cp = device->device_data; |
1da177e4 LT |
1874 | |
1875 | return snd_cs4231_sbus_free(cp); | |
1876 | } | |
1877 | ||
be9b7e8c | 1878 | static struct snd_device_ops snd_cs4231_sbus_dev_ops = { |
1da177e4 LT |
1879 | .dev_free = snd_cs4231_sbus_dev_free, |
1880 | }; | |
1881 | ||
be9b7e8c | 1882 | static int __init snd_cs4231_sbus_create(struct snd_card *card, |
1da177e4 | 1883 | struct sbus_dev *sdev, |
c6c2d57b | 1884 | int dev) |
1da177e4 | 1885 | { |
c6c2d57b | 1886 | struct snd_cs4231 *chip = card->private_data; |
1da177e4 LT |
1887 | int err; |
1888 | ||
1da177e4 | 1889 | spin_lock_init(&chip->lock); |
b128254f GC |
1890 | spin_lock_init(&chip->c_dma.sbus_info.lock); |
1891 | spin_lock_init(&chip->p_dma.sbus_info.lock); | |
12aa7579 IM |
1892 | mutex_init(&chip->mce_mutex); |
1893 | mutex_init(&chip->open_mutex); | |
1da177e4 LT |
1894 | chip->dev_u.sdev = sdev; |
1895 | chip->regs_size = sdev->reg_addrs[0].reg_size; | |
1896 | memcpy(&chip->image, &snd_cs4231_original_image, | |
1897 | sizeof(snd_cs4231_original_image)); | |
1898 | ||
1899 | chip->port = sbus_ioremap(&sdev->resource[0], 0, | |
1900 | chip->regs_size, "cs4231"); | |
1901 | if (!chip->port) { | |
a131430c | 1902 | snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev); |
1da177e4 LT |
1903 | return -EIO; |
1904 | } | |
1905 | ||
b128254f GC |
1906 | chip->c_dma.sbus_info.regs = chip->port; |
1907 | chip->p_dma.sbus_info.regs = chip->port; | |
1908 | chip->c_dma.sbus_info.dir = APC_RECORD; | |
1909 | chip->p_dma.sbus_info.dir = APC_PLAY; | |
1910 | ||
1911 | chip->p_dma.prepare = sbus_dma_prepare; | |
1912 | chip->p_dma.enable = sbus_dma_enable; | |
1913 | chip->p_dma.request = sbus_dma_request; | |
1914 | chip->p_dma.address = sbus_dma_addr; | |
b128254f GC |
1915 | chip->p_dma.preallocate = sbus_dma_preallocate; |
1916 | ||
1917 | chip->c_dma.prepare = sbus_dma_prepare; | |
1918 | chip->c_dma.enable = sbus_dma_enable; | |
1919 | chip->c_dma.request = sbus_dma_request; | |
1920 | chip->c_dma.address = sbus_dma_addr; | |
b128254f | 1921 | chip->c_dma.preallocate = sbus_dma_preallocate; |
5a820fa7 | 1922 | |
1da177e4 | 1923 | if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt, |
65ca68b3 | 1924 | IRQF_SHARED, "cs4231", chip)) { |
c6387a48 DM |
1925 | snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n", |
1926 | dev, sdev->irqs[0]); | |
1da177e4 LT |
1927 | snd_cs4231_sbus_free(chip); |
1928 | return -EBUSY; | |
1929 | } | |
1930 | chip->irq[0] = sdev->irqs[0]; | |
1931 | ||
1932 | if (snd_cs4231_probe(chip) < 0) { | |
1933 | snd_cs4231_sbus_free(chip); | |
1934 | return -ENODEV; | |
1935 | } | |
1936 | snd_cs4231_init(chip); | |
1937 | ||
1938 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, | |
1939 | chip, &snd_cs4231_sbus_dev_ops)) < 0) { | |
1940 | snd_cs4231_sbus_free(chip); | |
1941 | return err; | |
1942 | } | |
1943 | ||
1da177e4 LT |
1944 | return 0; |
1945 | } | |
1946 | ||
be9b7e8c | 1947 | static int __init cs4231_sbus_attach(struct sbus_dev *sdev) |
1da177e4 LT |
1948 | { |
1949 | struct resource *rp = &sdev->resource[0]; | |
be9b7e8c | 1950 | struct snd_card *card; |
1da177e4 LT |
1951 | int err; |
1952 | ||
1953 | err = cs4231_attach_begin(&card); | |
1954 | if (err) | |
1955 | return err; | |
1956 | ||
5863aa65 | 1957 | sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d", |
1da177e4 LT |
1958 | card->shortname, |
1959 | rp->flags & 0xffL, | |
aa0a2ddc | 1960 | (unsigned long long)rp->start, |
c6387a48 | 1961 | sdev->irqs[0]); |
1da177e4 | 1962 | |
c6c2d57b KH |
1963 | err = snd_cs4231_sbus_create(card, sdev, dev); |
1964 | if (err < 0) { | |
1da177e4 LT |
1965 | snd_card_free(card); |
1966 | return err; | |
1967 | } | |
1968 | ||
c6c2d57b | 1969 | return cs4231_attach_finish(card); |
1da177e4 LT |
1970 | } |
1971 | #endif | |
1972 | ||
1973 | #ifdef EBUS_SUPPORT | |
b128254f GC |
1974 | |
1975 | static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie) | |
1976 | { | |
be9b7e8c | 1977 | struct snd_cs4231 *chip = cookie; |
b128254f GC |
1978 | |
1979 | snd_cs4231_play_callback(chip); | |
1980 | } | |
1981 | ||
1982 | static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie) | |
1983 | { | |
be9b7e8c | 1984 | struct snd_cs4231 *chip = cookie; |
b128254f GC |
1985 | |
1986 | snd_cs4231_capture_callback(chip); | |
1987 | } | |
1988 | ||
1989 | /* | |
1990 | * EBUS DMA wrappers | |
1991 | */ | |
1992 | ||
be9b7e8c | 1993 | static int _ebus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len) |
b128254f GC |
1994 | { |
1995 | return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len); | |
1996 | } | |
1997 | ||
be9b7e8c | 1998 | static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on) |
b128254f GC |
1999 | { |
2000 | ebus_dma_enable(&dma_cont->ebus_info, on); | |
2001 | } | |
2002 | ||
be9b7e8c | 2003 | static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir) |
b128254f GC |
2004 | { |
2005 | ebus_dma_prepare(&dma_cont->ebus_info, dir); | |
2006 | } | |
2007 | ||
be9b7e8c | 2008 | static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont) |
b128254f GC |
2009 | { |
2010 | return ebus_dma_addr(&dma_cont->ebus_info); | |
2011 | } | |
2012 | ||
be9b7e8c | 2013 | static void _ebus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm) |
b128254f GC |
2014 | { |
2015 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
2016 | snd_dma_pci_data(chip->dev_u.pdev), | |
2017 | 64*1024, 128*1024); | |
2018 | } | |
2019 | ||
2020 | /* | |
2021 | * Init and exit routines | |
2022 | */ | |
2023 | ||
be9b7e8c | 2024 | static int snd_cs4231_ebus_free(struct snd_cs4231 *chip) |
1da177e4 | 2025 | { |
b128254f GC |
2026 | if (chip->c_dma.ebus_info.regs) { |
2027 | ebus_dma_unregister(&chip->c_dma.ebus_info); | |
2028 | iounmap(chip->c_dma.ebus_info.regs); | |
1da177e4 | 2029 | } |
b128254f GC |
2030 | if (chip->p_dma.ebus_info.regs) { |
2031 | ebus_dma_unregister(&chip->p_dma.ebus_info); | |
2032 | iounmap(chip->p_dma.ebus_info.regs); | |
1da177e4 LT |
2033 | } |
2034 | ||
2035 | if (chip->port) | |
2036 | iounmap(chip->port); | |
1da177e4 | 2037 | |
1da177e4 LT |
2038 | return 0; |
2039 | } | |
2040 | ||
be9b7e8c | 2041 | static int snd_cs4231_ebus_dev_free(struct snd_device *device) |
1da177e4 | 2042 | { |
be9b7e8c | 2043 | struct snd_cs4231 *cp = device->device_data; |
1da177e4 LT |
2044 | |
2045 | return snd_cs4231_ebus_free(cp); | |
2046 | } | |
2047 | ||
be9b7e8c | 2048 | static struct snd_device_ops snd_cs4231_ebus_dev_ops = { |
1da177e4 LT |
2049 | .dev_free = snd_cs4231_ebus_dev_free, |
2050 | }; | |
2051 | ||
be9b7e8c | 2052 | static int __init snd_cs4231_ebus_create(struct snd_card *card, |
1da177e4 | 2053 | struct linux_ebus_device *edev, |
c6c2d57b | 2054 | int dev) |
1da177e4 | 2055 | { |
c6c2d57b | 2056 | struct snd_cs4231 *chip = card->private_data; |
1da177e4 LT |
2057 | int err; |
2058 | ||
1da177e4 | 2059 | spin_lock_init(&chip->lock); |
b128254f GC |
2060 | spin_lock_init(&chip->c_dma.ebus_info.lock); |
2061 | spin_lock_init(&chip->p_dma.ebus_info.lock); | |
12aa7579 IM |
2062 | mutex_init(&chip->mce_mutex); |
2063 | mutex_init(&chip->open_mutex); | |
1da177e4 | 2064 | chip->flags |= CS4231_FLAG_EBUS; |
1da177e4 LT |
2065 | chip->dev_u.pdev = edev->bus->self; |
2066 | memcpy(&chip->image, &snd_cs4231_original_image, | |
2067 | sizeof(snd_cs4231_original_image)); | |
b128254f GC |
2068 | strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)"); |
2069 | chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER; | |
2070 | chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback; | |
2071 | chip->c_dma.ebus_info.client_cookie = chip; | |
2072 | chip->c_dma.ebus_info.irq = edev->irqs[0]; | |
2073 | strcpy(chip->p_dma.ebus_info.name, "cs4231(play)"); | |
2074 | chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER; | |
2075 | chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback; | |
2076 | chip->p_dma.ebus_info.client_cookie = chip; | |
2077 | chip->p_dma.ebus_info.irq = edev->irqs[1]; | |
2078 | ||
2079 | chip->p_dma.prepare = _ebus_dma_prepare; | |
2080 | chip->p_dma.enable = _ebus_dma_enable; | |
2081 | chip->p_dma.request = _ebus_dma_request; | |
2082 | chip->p_dma.address = _ebus_dma_addr; | |
b128254f GC |
2083 | chip->p_dma.preallocate = _ebus_dma_preallocate; |
2084 | ||
2085 | chip->c_dma.prepare = _ebus_dma_prepare; | |
2086 | chip->c_dma.enable = _ebus_dma_enable; | |
2087 | chip->c_dma.request = _ebus_dma_request; | |
2088 | chip->c_dma.address = _ebus_dma_addr; | |
b128254f | 2089 | chip->c_dma.preallocate = _ebus_dma_preallocate; |
1da177e4 LT |
2090 | |
2091 | chip->port = ioremap(edev->resource[0].start, 0x10); | |
b128254f GC |
2092 | chip->p_dma.ebus_info.regs = ioremap(edev->resource[1].start, 0x10); |
2093 | chip->c_dma.ebus_info.regs = ioremap(edev->resource[2].start, 0x10); | |
2094 | if (!chip->port || !chip->p_dma.ebus_info.regs || !chip->c_dma.ebus_info.regs) { | |
1da177e4 | 2095 | snd_cs4231_ebus_free(chip); |
a131430c | 2096 | snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev); |
1da177e4 LT |
2097 | return -EIO; |
2098 | } | |
2099 | ||
b128254f | 2100 | if (ebus_dma_register(&chip->c_dma.ebus_info)) { |
1da177e4 | 2101 | snd_cs4231_ebus_free(chip); |
a131430c | 2102 | snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev); |
1da177e4 LT |
2103 | return -EBUSY; |
2104 | } | |
b128254f | 2105 | if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) { |
1da177e4 | 2106 | snd_cs4231_ebus_free(chip); |
a131430c | 2107 | snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev); |
1da177e4 LT |
2108 | return -EBUSY; |
2109 | } | |
2110 | ||
b128254f | 2111 | if (ebus_dma_register(&chip->p_dma.ebus_info)) { |
1da177e4 | 2112 | snd_cs4231_ebus_free(chip); |
a131430c | 2113 | snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev); |
1da177e4 LT |
2114 | return -EBUSY; |
2115 | } | |
b128254f | 2116 | if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) { |
1da177e4 | 2117 | snd_cs4231_ebus_free(chip); |
a131430c | 2118 | snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev); |
1da177e4 LT |
2119 | return -EBUSY; |
2120 | } | |
2121 | ||
2122 | if (snd_cs4231_probe(chip) < 0) { | |
2123 | snd_cs4231_ebus_free(chip); | |
2124 | return -ENODEV; | |
2125 | } | |
2126 | snd_cs4231_init(chip); | |
2127 | ||
2128 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, | |
2129 | chip, &snd_cs4231_ebus_dev_ops)) < 0) { | |
2130 | snd_cs4231_ebus_free(chip); | |
2131 | return err; | |
2132 | } | |
2133 | ||
1da177e4 LT |
2134 | return 0; |
2135 | } | |
2136 | ||
be9b7e8c | 2137 | static int __init cs4231_ebus_attach(struct linux_ebus_device *edev) |
1da177e4 | 2138 | { |
be9b7e8c | 2139 | struct snd_card *card; |
1da177e4 LT |
2140 | int err; |
2141 | ||
2142 | err = cs4231_attach_begin(&card); | |
2143 | if (err) | |
2144 | return err; | |
2145 | ||
c6387a48 | 2146 | sprintf(card->longname, "%s at 0x%lx, irq %d", |
1da177e4 LT |
2147 | card->shortname, |
2148 | edev->resource[0].start, | |
c6387a48 | 2149 | edev->irqs[0]); |
1da177e4 | 2150 | |
c6c2d57b KH |
2151 | err = snd_cs4231_ebus_create(card, edev, dev); |
2152 | if (err < 0) { | |
1da177e4 LT |
2153 | snd_card_free(card); |
2154 | return err; | |
2155 | } | |
2156 | ||
c6c2d57b | 2157 | return cs4231_attach_finish(card); |
1da177e4 LT |
2158 | } |
2159 | #endif | |
2160 | ||
2161 | static int __init cs4231_init(void) | |
2162 | { | |
2163 | #ifdef SBUS_SUPPORT | |
2164 | struct sbus_bus *sbus; | |
2165 | struct sbus_dev *sdev; | |
2166 | #endif | |
2167 | #ifdef EBUS_SUPPORT | |
2168 | struct linux_ebus *ebus; | |
2169 | struct linux_ebus_device *edev; | |
2170 | #endif | |
2171 | int found; | |
2172 | ||
2173 | found = 0; | |
2174 | ||
2175 | #ifdef SBUS_SUPPORT | |
2176 | for_all_sbusdev(sdev, sbus) { | |
2177 | if (!strcmp(sdev->prom_name, "SUNW,CS4231")) { | |
2178 | if (cs4231_sbus_attach(sdev) == 0) | |
2179 | found++; | |
2180 | } | |
2181 | } | |
2182 | #endif | |
2183 | #ifdef EBUS_SUPPORT | |
2184 | for_each_ebus(ebus) { | |
2185 | for_each_ebusdev(edev, ebus) { | |
2186 | int match = 0; | |
2187 | ||
690c8fd3 | 2188 | if (!strcmp(edev->prom_node->name, "SUNW,CS4231")) { |
1da177e4 | 2189 | match = 1; |
690c8fd3 | 2190 | } else if (!strcmp(edev->prom_node->name, "audio")) { |
3198514d | 2191 | const char *compat; |
1da177e4 | 2192 | |
690c8fd3 DM |
2193 | compat = of_get_property(edev->prom_node, |
2194 | "compatible", NULL); | |
2195 | if (compat && !strcmp(compat, "SUNW,CS4231")) | |
1da177e4 LT |
2196 | match = 1; |
2197 | } | |
2198 | ||
2199 | if (match && | |
2200 | cs4231_ebus_attach(edev) == 0) | |
2201 | found++; | |
2202 | } | |
2203 | } | |
2204 | #endif | |
2205 | ||
2206 | ||
2207 | return (found > 0) ? 0 : -EIO; | |
2208 | } | |
2209 | ||
2210 | static void __exit cs4231_exit(void) | |
2211 | { | |
be9b7e8c | 2212 | struct snd_cs4231 *p = cs4231_list; |
1da177e4 LT |
2213 | |
2214 | while (p != NULL) { | |
be9b7e8c | 2215 | struct snd_cs4231 *next = p->next; |
1da177e4 LT |
2216 | |
2217 | snd_card_free(p->card); | |
2218 | ||
2219 | p = next; | |
2220 | } | |
2221 | ||
2222 | cs4231_list = NULL; | |
2223 | } | |
2224 | ||
2225 | module_init(cs4231_init); | |
2226 | module_exit(cs4231_exit); |