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17a52fd6 MB |
1 | /* |
2 | * soc-cache.c -- ASoC register cache helpers | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics PLC. | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
7084a42b | 14 | #include <linux/i2c.h> |
27ded041 | 15 | #include <linux/spi/spi.h> |
17a52fd6 MB |
16 | #include <sound/soc.h> |
17 | ||
63b62ab0 BS |
18 | static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec, |
19 | unsigned int reg) | |
20 | { | |
21 | u16 *cache = codec->reg_cache; | |
22 | if (reg >= codec->reg_cache_size) | |
23 | return -1; | |
24 | return cache[reg]; | |
25 | } | |
26 | ||
27 | static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg, | |
28 | unsigned int value) | |
29 | { | |
30 | u16 *cache = codec->reg_cache; | |
31 | u8 data[2]; | |
32 | int ret; | |
33 | ||
34 | BUG_ON(codec->volatile_register); | |
35 | ||
36 | data[0] = (reg << 4) | ((value >> 8) & 0x000f); | |
37 | data[1] = value & 0x00ff; | |
38 | ||
39 | if (reg < codec->reg_cache_size) | |
40 | cache[reg] = value; | |
8c961bcc | 41 | |
a3032b47 MB |
42 | if (codec->cache_only) { |
43 | codec->cache_sync = 1; | |
8c961bcc | 44 | return 0; |
a3032b47 | 45 | } |
8c961bcc | 46 | |
63b62ab0 BS |
47 | ret = codec->hw_write(codec->control_data, data, 2); |
48 | if (ret == 2) | |
49 | return 0; | |
50 | if (ret < 0) | |
51 | return ret; | |
52 | else | |
53 | return -EIO; | |
54 | } | |
55 | ||
56 | #if defined(CONFIG_SPI_MASTER) | |
57 | static int snd_soc_4_12_spi_write(void *control_data, const char *data, | |
58 | int len) | |
59 | { | |
60 | struct spi_device *spi = control_data; | |
61 | struct spi_transfer t; | |
62 | struct spi_message m; | |
63 | u8 msg[2]; | |
64 | ||
65 | if (len <= 0) | |
66 | return 0; | |
67 | ||
68 | msg[0] = data[1]; | |
69 | msg[1] = data[0]; | |
70 | ||
71 | spi_message_init(&m); | |
72 | memset(&t, 0, (sizeof t)); | |
73 | ||
74 | t.tx_buf = &msg[0]; | |
75 | t.len = len; | |
76 | ||
77 | spi_message_add_tail(&t, &m); | |
78 | spi_sync(spi, &m); | |
79 | ||
80 | return len; | |
81 | } | |
82 | #else | |
83 | #define snd_soc_4_12_spi_write NULL | |
84 | #endif | |
85 | ||
17a52fd6 MB |
86 | static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec, |
87 | unsigned int reg) | |
88 | { | |
89 | u16 *cache = codec->reg_cache; | |
90 | if (reg >= codec->reg_cache_size) | |
91 | return -1; | |
92 | return cache[reg]; | |
93 | } | |
94 | ||
95 | static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg, | |
96 | unsigned int value) | |
97 | { | |
98 | u16 *cache = codec->reg_cache; | |
99 | u8 data[2]; | |
100 | int ret; | |
101 | ||
102 | BUG_ON(codec->volatile_register); | |
103 | ||
104 | data[0] = (reg << 1) | ((value >> 8) & 0x0001); | |
105 | data[1] = value & 0x00ff; | |
106 | ||
107 | if (reg < codec->reg_cache_size) | |
108 | cache[reg] = value; | |
8c961bcc | 109 | |
a3032b47 MB |
110 | if (codec->cache_only) { |
111 | codec->cache_sync = 1; | |
8c961bcc | 112 | return 0; |
a3032b47 | 113 | } |
8c961bcc | 114 | |
17a52fd6 MB |
115 | ret = codec->hw_write(codec->control_data, data, 2); |
116 | if (ret == 2) | |
117 | return 0; | |
118 | if (ret < 0) | |
119 | return ret; | |
120 | else | |
121 | return -EIO; | |
122 | } | |
123 | ||
27ded041 MB |
124 | #if defined(CONFIG_SPI_MASTER) |
125 | static int snd_soc_7_9_spi_write(void *control_data, const char *data, | |
126 | int len) | |
127 | { | |
128 | struct spi_device *spi = control_data; | |
129 | struct spi_transfer t; | |
130 | struct spi_message m; | |
131 | u8 msg[2]; | |
132 | ||
133 | if (len <= 0) | |
134 | return 0; | |
135 | ||
136 | msg[0] = data[0]; | |
137 | msg[1] = data[1]; | |
138 | ||
139 | spi_message_init(&m); | |
140 | memset(&t, 0, (sizeof t)); | |
141 | ||
142 | t.tx_buf = &msg[0]; | |
143 | t.len = len; | |
144 | ||
145 | spi_message_add_tail(&t, &m); | |
146 | spi_sync(spi, &m); | |
147 | ||
148 | return len; | |
149 | } | |
150 | #else | |
151 | #define snd_soc_7_9_spi_write NULL | |
152 | #endif | |
153 | ||
341c9b84 JS |
154 | static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg, |
155 | unsigned int value) | |
156 | { | |
157 | u8 *cache = codec->reg_cache; | |
158 | u8 data[2]; | |
159 | ||
160 | BUG_ON(codec->volatile_register); | |
161 | ||
162 | data[0] = reg & 0xff; | |
163 | data[1] = value & 0xff; | |
164 | ||
165 | if (reg < codec->reg_cache_size) | |
166 | cache[reg] = value; | |
167 | ||
a3032b47 MB |
168 | if (codec->cache_only) { |
169 | codec->cache_sync = 1; | |
8c961bcc | 170 | return 0; |
a3032b47 | 171 | } |
8c961bcc | 172 | |
341c9b84 JS |
173 | if (codec->hw_write(codec->control_data, data, 2) == 2) |
174 | return 0; | |
175 | else | |
176 | return -EIO; | |
177 | } | |
178 | ||
179 | static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec, | |
180 | unsigned int reg) | |
181 | { | |
182 | u8 *cache = codec->reg_cache; | |
183 | if (reg >= codec->reg_cache_size) | |
184 | return -1; | |
185 | return cache[reg]; | |
186 | } | |
187 | ||
afa2f106 MB |
188 | static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg, |
189 | unsigned int value) | |
190 | { | |
191 | u16 *reg_cache = codec->reg_cache; | |
192 | u8 data[3]; | |
193 | ||
194 | data[0] = reg; | |
195 | data[1] = (value >> 8) & 0xff; | |
196 | data[2] = value & 0xff; | |
197 | ||
198 | if (!snd_soc_codec_volatile_register(codec, reg)) | |
199 | reg_cache[reg] = value; | |
200 | ||
a3032b47 MB |
201 | if (codec->cache_only) { |
202 | codec->cache_sync = 1; | |
8c961bcc | 203 | return 0; |
a3032b47 | 204 | } |
8c961bcc | 205 | |
afa2f106 MB |
206 | if (codec->hw_write(codec->control_data, data, 3) == 3) |
207 | return 0; | |
208 | else | |
209 | return -EIO; | |
210 | } | |
211 | ||
212 | static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec, | |
213 | unsigned int reg) | |
214 | { | |
215 | u16 *cache = codec->reg_cache; | |
216 | ||
217 | if (reg >= codec->reg_cache_size || | |
8c961bcc MB |
218 | snd_soc_codec_volatile_register(codec, reg)) { |
219 | if (codec->cache_only) | |
220 | return -EINVAL; | |
221 | ||
afa2f106 | 222 | return codec->hw_read(codec, reg); |
8c961bcc | 223 | } else { |
afa2f106 | 224 | return cache[reg]; |
8c961bcc | 225 | } |
afa2f106 MB |
226 | } |
227 | ||
85dfcdff CC |
228 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
229 | static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec, | |
230 | unsigned int r) | |
231 | { | |
232 | struct i2c_msg xfer[2]; | |
233 | u8 reg = r; | |
234 | u8 data; | |
235 | int ret; | |
236 | struct i2c_client *client = codec->control_data; | |
237 | ||
238 | /* Write register */ | |
239 | xfer[0].addr = client->addr; | |
240 | xfer[0].flags = 0; | |
241 | xfer[0].len = 1; | |
242 | xfer[0].buf = ® | |
243 | ||
244 | /* Read data */ | |
245 | xfer[1].addr = client->addr; | |
246 | xfer[1].flags = I2C_M_RD; | |
247 | xfer[1].len = 1; | |
248 | xfer[1].buf = &data; | |
249 | ||
250 | ret = i2c_transfer(client->adapter, xfer, 2); | |
251 | if (ret != 2) { | |
252 | dev_err(&client->dev, "i2c_transfer() returned %d\n", ret); | |
253 | return 0; | |
254 | } | |
255 | ||
256 | return data; | |
257 | } | |
258 | #else | |
259 | #define snd_soc_8_8_read_i2c NULL | |
260 | #endif | |
261 | ||
17244c24 | 262 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
afa2f106 MB |
263 | static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec, |
264 | unsigned int r) | |
265 | { | |
266 | struct i2c_msg xfer[2]; | |
267 | u8 reg = r; | |
268 | u16 data; | |
269 | int ret; | |
270 | struct i2c_client *client = codec->control_data; | |
271 | ||
272 | /* Write register */ | |
273 | xfer[0].addr = client->addr; | |
274 | xfer[0].flags = 0; | |
275 | xfer[0].len = 1; | |
276 | xfer[0].buf = ® | |
277 | ||
278 | /* Read data */ | |
279 | xfer[1].addr = client->addr; | |
280 | xfer[1].flags = I2C_M_RD; | |
281 | xfer[1].len = 2; | |
282 | xfer[1].buf = (u8 *)&data; | |
283 | ||
284 | ret = i2c_transfer(client->adapter, xfer, 2); | |
285 | if (ret != 2) { | |
286 | dev_err(&client->dev, "i2c_transfer() returned %d\n", ret); | |
287 | return 0; | |
288 | } | |
289 | ||
290 | return (data >> 8) | ((data & 0xff) << 8); | |
291 | } | |
292 | #else | |
293 | #define snd_soc_8_16_read_i2c NULL | |
294 | #endif | |
17a52fd6 | 295 | |
994dc424 BS |
296 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
297 | static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec, | |
298 | unsigned int r) | |
299 | { | |
300 | struct i2c_msg xfer[2]; | |
301 | u16 reg = r; | |
302 | u8 data; | |
303 | int ret; | |
304 | struct i2c_client *client = codec->control_data; | |
305 | ||
306 | /* Write register */ | |
307 | xfer[0].addr = client->addr; | |
308 | xfer[0].flags = 0; | |
309 | xfer[0].len = 2; | |
310 | xfer[0].buf = (u8 *)® | |
311 | ||
312 | /* Read data */ | |
313 | xfer[1].addr = client->addr; | |
314 | xfer[1].flags = I2C_M_RD; | |
315 | xfer[1].len = 1; | |
316 | xfer[1].buf = &data; | |
317 | ||
318 | ret = i2c_transfer(client->adapter, xfer, 2); | |
319 | if (ret != 2) { | |
320 | dev_err(&client->dev, "i2c_transfer() returned %d\n", ret); | |
321 | return 0; | |
322 | } | |
323 | ||
324 | return data; | |
325 | } | |
326 | #else | |
327 | #define snd_soc_16_8_read_i2c NULL | |
328 | #endif | |
329 | ||
330 | static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec, | |
331 | unsigned int reg) | |
332 | { | |
333 | u16 *cache = codec->reg_cache; | |
334 | ||
335 | reg &= 0xff; | |
336 | if (reg >= codec->reg_cache_size) | |
337 | return -1; | |
338 | return cache[reg]; | |
339 | } | |
340 | ||
341 | static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg, | |
342 | unsigned int value) | |
343 | { | |
344 | u16 *cache = codec->reg_cache; | |
345 | u8 data[3]; | |
346 | int ret; | |
347 | ||
348 | BUG_ON(codec->volatile_register); | |
349 | ||
350 | data[0] = (reg >> 8) & 0xff; | |
351 | data[1] = reg & 0xff; | |
352 | data[2] = value; | |
353 | ||
354 | reg &= 0xff; | |
355 | if (reg < codec->reg_cache_size) | |
356 | cache[reg] = value; | |
8c961bcc | 357 | |
a3032b47 MB |
358 | if (codec->cache_only) { |
359 | codec->cache_sync = 1; | |
8c961bcc | 360 | return 0; |
a3032b47 | 361 | } |
8c961bcc | 362 | |
994dc424 BS |
363 | ret = codec->hw_write(codec->control_data, data, 3); |
364 | if (ret == 3) | |
365 | return 0; | |
366 | if (ret < 0) | |
367 | return ret; | |
368 | else | |
369 | return -EIO; | |
370 | } | |
371 | ||
372 | #if defined(CONFIG_SPI_MASTER) | |
373 | static int snd_soc_16_8_spi_write(void *control_data, const char *data, | |
374 | int len) | |
375 | { | |
376 | struct spi_device *spi = control_data; | |
377 | struct spi_transfer t; | |
378 | struct spi_message m; | |
379 | u8 msg[3]; | |
380 | ||
381 | if (len <= 0) | |
382 | return 0; | |
383 | ||
384 | msg[0] = data[0]; | |
385 | msg[1] = data[1]; | |
386 | msg[2] = data[2]; | |
387 | ||
388 | spi_message_init(&m); | |
389 | memset(&t, 0, (sizeof t)); | |
390 | ||
391 | t.tx_buf = &msg[0]; | |
392 | t.len = len; | |
393 | ||
394 | spi_message_add_tail(&t, &m); | |
395 | spi_sync(spi, &m); | |
396 | ||
397 | return len; | |
398 | } | |
399 | #else | |
400 | #define snd_soc_16_8_spi_write NULL | |
401 | #endif | |
402 | ||
bc6552f4 MB |
403 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
404 | static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec, | |
405 | unsigned int r) | |
406 | { | |
407 | struct i2c_msg xfer[2]; | |
408 | u16 reg = cpu_to_be16(r); | |
409 | u16 data; | |
410 | int ret; | |
411 | struct i2c_client *client = codec->control_data; | |
412 | ||
413 | /* Write register */ | |
414 | xfer[0].addr = client->addr; | |
415 | xfer[0].flags = 0; | |
416 | xfer[0].len = 2; | |
417 | xfer[0].buf = (u8 *)® | |
418 | ||
419 | /* Read data */ | |
420 | xfer[1].addr = client->addr; | |
421 | xfer[1].flags = I2C_M_RD; | |
422 | xfer[1].len = 2; | |
423 | xfer[1].buf = (u8 *)&data; | |
424 | ||
425 | ret = i2c_transfer(client->adapter, xfer, 2); | |
426 | if (ret != 2) { | |
427 | dev_err(&client->dev, "i2c_transfer() returned %d\n", ret); | |
428 | return 0; | |
429 | } | |
430 | ||
431 | return be16_to_cpu(data); | |
432 | } | |
433 | #else | |
434 | #define snd_soc_16_16_read_i2c NULL | |
435 | #endif | |
436 | ||
437 | static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec, | |
438 | unsigned int reg) | |
439 | { | |
440 | u16 *cache = codec->reg_cache; | |
441 | ||
442 | if (reg >= codec->reg_cache_size || | |
443 | snd_soc_codec_volatile_register(codec, reg)) { | |
444 | if (codec->cache_only) | |
445 | return -EINVAL; | |
446 | ||
447 | return codec->hw_read(codec, reg); | |
448 | } | |
449 | ||
450 | return cache[reg]; | |
451 | } | |
452 | ||
453 | static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg, | |
454 | unsigned int value) | |
455 | { | |
456 | u16 *cache = codec->reg_cache; | |
457 | u8 data[4]; | |
458 | int ret; | |
459 | ||
460 | data[0] = (reg >> 8) & 0xff; | |
461 | data[1] = reg & 0xff; | |
462 | data[2] = (value >> 8) & 0xff; | |
463 | data[3] = value & 0xff; | |
464 | ||
465 | if (reg < codec->reg_cache_size) | |
466 | cache[reg] = value; | |
467 | ||
468 | if (codec->cache_only) { | |
469 | codec->cache_sync = 1; | |
470 | return 0; | |
471 | } | |
472 | ||
473 | ret = codec->hw_write(codec->control_data, data, 4); | |
474 | if (ret == 4) | |
475 | return 0; | |
476 | if (ret < 0) | |
477 | return ret; | |
478 | else | |
479 | return -EIO; | |
480 | } | |
994dc424 | 481 | |
17a52fd6 MB |
482 | static struct { |
483 | int addr_bits; | |
484 | int data_bits; | |
afa2f106 | 485 | int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int); |
27ded041 | 486 | int (*spi_write)(void *, const char *, int); |
17a52fd6 | 487 | unsigned int (*read)(struct snd_soc_codec *, unsigned int); |
afa2f106 | 488 | unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int); |
17a52fd6 | 489 | } io_types[] = { |
63b62ab0 BS |
490 | { |
491 | .addr_bits = 4, .data_bits = 12, | |
492 | .write = snd_soc_4_12_write, .read = snd_soc_4_12_read, | |
493 | .spi_write = snd_soc_4_12_spi_write, | |
494 | }, | |
d62ab358 MB |
495 | { |
496 | .addr_bits = 7, .data_bits = 9, | |
497 | .write = snd_soc_7_9_write, .read = snd_soc_7_9_read, | |
8998c899 | 498 | .spi_write = snd_soc_7_9_spi_write, |
d62ab358 MB |
499 | }, |
500 | { | |
501 | .addr_bits = 8, .data_bits = 8, | |
502 | .write = snd_soc_8_8_write, .read = snd_soc_8_8_read, | |
85dfcdff | 503 | .i2c_read = snd_soc_8_8_read_i2c, |
d62ab358 MB |
504 | }, |
505 | { | |
506 | .addr_bits = 8, .data_bits = 16, | |
507 | .write = snd_soc_8_16_write, .read = snd_soc_8_16_read, | |
508 | .i2c_read = snd_soc_8_16_read_i2c, | |
509 | }, | |
994dc424 BS |
510 | { |
511 | .addr_bits = 16, .data_bits = 8, | |
512 | .write = snd_soc_16_8_write, .read = snd_soc_16_8_read, | |
513 | .i2c_read = snd_soc_16_8_read_i2c, | |
514 | .spi_write = snd_soc_16_8_spi_write, | |
515 | }, | |
bc6552f4 MB |
516 | { |
517 | .addr_bits = 16, .data_bits = 16, | |
518 | .write = snd_soc_16_16_write, .read = snd_soc_16_16_read, | |
519 | .i2c_read = snd_soc_16_16_read_i2c, | |
520 | }, | |
17a52fd6 MB |
521 | }; |
522 | ||
523 | /** | |
524 | * snd_soc_codec_set_cache_io: Set up standard I/O functions. | |
525 | * | |
526 | * @codec: CODEC to configure. | |
527 | * @type: Type of cache. | |
528 | * @addr_bits: Number of bits of register address data. | |
529 | * @data_bits: Number of bits of data per register. | |
7084a42b | 530 | * @control: Control bus used. |
17a52fd6 MB |
531 | * |
532 | * Register formats are frequently shared between many I2C and SPI | |
533 | * devices. In order to promote code reuse the ASoC core provides | |
534 | * some standard implementations of CODEC read and write operations | |
535 | * which can be set up using this function. | |
536 | * | |
537 | * The caller is responsible for allocating and initialising the | |
538 | * actual cache. | |
539 | * | |
540 | * Note that at present this code cannot be used by CODECs with | |
541 | * volatile registers. | |
542 | */ | |
543 | int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec, | |
7084a42b MB |
544 | int addr_bits, int data_bits, |
545 | enum snd_soc_control_type control) | |
17a52fd6 MB |
546 | { |
547 | int i; | |
548 | ||
17a52fd6 MB |
549 | for (i = 0; i < ARRAY_SIZE(io_types); i++) |
550 | if (io_types[i].addr_bits == addr_bits && | |
551 | io_types[i].data_bits == data_bits) | |
552 | break; | |
553 | if (i == ARRAY_SIZE(io_types)) { | |
554 | printk(KERN_ERR | |
555 | "No I/O functions for %d bit address %d bit data\n", | |
556 | addr_bits, data_bits); | |
557 | return -EINVAL; | |
558 | } | |
559 | ||
560 | codec->write = io_types[i].write; | |
561 | codec->read = io_types[i].read; | |
562 | ||
7084a42b MB |
563 | switch (control) { |
564 | case SND_SOC_CUSTOM: | |
565 | break; | |
566 | ||
567 | case SND_SOC_I2C: | |
17244c24 | 568 | #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE)) |
7084a42b MB |
569 | codec->hw_write = (hw_write_t)i2c_master_send; |
570 | #endif | |
afa2f106 MB |
571 | if (io_types[i].i2c_read) |
572 | codec->hw_read = io_types[i].i2c_read; | |
7084a42b MB |
573 | break; |
574 | ||
575 | case SND_SOC_SPI: | |
27ded041 MB |
576 | if (io_types[i].spi_write) |
577 | codec->hw_write = io_types[i].spi_write; | |
7084a42b MB |
578 | break; |
579 | } | |
580 | ||
17a52fd6 MB |
581 | return 0; |
582 | } | |
583 | EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io); |