[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / soc-cache.c

/*
 * soc-cache.c  --  ASoC register cache helpers
 *
 * Copyright 2009 Wolfson Microelectronics PLC.
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <sound/soc.h>

static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u16 *cache = codec->reg_cache;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[2];
	int ret;

	BUG_ON(codec->volatile_register);

	data[0] = (reg << 4) | ((value >> 8) & 0x000f);
	data[1] = value & 0x00ff;

	if (reg < codec->reg_cache_size)
		cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	ret = codec->hw_write(codec->control_data, data, 2);
	if (ret == 2)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_4_12_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[2];

	if (len <= 0)
		return 0;

	msg[0] = data[1];
	msg[1] = data[0];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_4_12_spi_write NULL
#endif

static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u16 *cache = codec->reg_cache;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[2];
	int ret;

	BUG_ON(codec->volatile_register);

	data[0] = (reg << 1) | ((value >> 8) & 0x0001);
	data[1] = value & 0x00ff;

	if (reg < codec->reg_cache_size)
		cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	ret = codec->hw_write(codec->control_data, data, 2);
	if (ret == 2)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_7_9_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[2];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_7_9_spi_write NULL
#endif

static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u8 *cache = codec->reg_cache;
	u8 data[2];

	BUG_ON(codec->volatile_register);

	reg &= 0xff;
	data[0] = reg;
	data[1] = value & 0xff;

	if (reg < codec->reg_cache_size)
		cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	if (codec->hw_write(codec->control_data, data, 2) == 2)
		return 0;
	else
		return -EIO;
}

static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u8 *cache = codec->reg_cache;
	reg &= 0xff;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
			      unsigned int value)
{
	u16 *reg_cache = codec->reg_cache;
	u8 data[3];

	data[0] = reg;
	data[1] = (value >> 8) & 0xff;
	data[2] = value & 0xff;

	if (!snd_soc_codec_volatile_register(codec, reg))
		reg_cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	if (codec->hw_write(codec->control_data, data, 3) == 3)
		return 0;
	else
		return -EIO;
}

static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
				      unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	if (reg >= codec->reg_cache_size ||
	    snd_soc_codec_volatile_register(codec, reg)) {
		if (codec->cache_only)
			return -EINVAL;

		return codec->hw_read(codec, reg);
	} else {
		return cache[reg];
	}
}

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
					  unsigned int r)
{
	struct i2c_msg xfer[2];
	u8 reg = r;
	u8 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 1;
	xfer[0].buf = &reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 1;
	xfer[1].buf = &data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return data;
}
#else
#define snd_soc_8_8_read_i2c NULL
#endif

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
					  unsigned int r)
{
	struct i2c_msg xfer[2];
	u8 reg = r;
	u16 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 1;
	xfer[0].buf = &reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 2;
	xfer[1].buf = (u8 *)&data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return (data >> 8) | ((data & 0xff) << 8);
}
#else
#define snd_soc_8_16_read_i2c NULL
#endif

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
					  unsigned int r)
{
	struct i2c_msg xfer[2];
	u16 reg = r;
	u8 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 2;
	xfer[0].buf = (u8 *)&reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 1;
	xfer[1].buf = &data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return data;
}
#else
#define snd_soc_16_8_read_i2c NULL
#endif

static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
				     unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	reg &= 0xff;
	if (reg >= codec->reg_cache_size)
		return -1;
	return cache[reg];
}

static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
			     unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[3];
	int ret;

	BUG_ON(codec->volatile_register);

	data[0] = (reg >> 8) & 0xff;
	data[1] = reg & 0xff;
	data[2] = value;

	reg &= 0xff;
	if (reg < codec->reg_cache_size)
		cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	ret = codec->hw_write(codec->control_data, data, 3);
	if (ret == 3)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

#if defined(CONFIG_SPI_MASTER)
static int snd_soc_16_8_spi_write(void *control_data, const char *data,
				 int len)
{
	struct spi_device *spi = control_data;
	struct spi_transfer t;
	struct spi_message m;
	u8 msg[3];

	if (len <= 0)
		return 0;

	msg[0] = data[0];
	msg[1] = data[1];
	msg[2] = data[2];

	spi_message_init(&m);
	memset(&t, 0, (sizeof t));

	t.tx_buf = &msg[0];
	t.len = len;

	spi_message_add_tail(&t, &m);
	spi_sync(spi, &m);

	return len;
}
#else
#define snd_soc_16_8_spi_write NULL
#endif

#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
					   unsigned int r)
{
	struct i2c_msg xfer[2];
	u16 reg = cpu_to_be16(r);
	u16 data;
	int ret;
	struct i2c_client *client = codec->control_data;

	/* Write register */
	xfer[0].addr = client->addr;
	xfer[0].flags = 0;
	xfer[0].len = 2;
	xfer[0].buf = (u8 *)&reg;

	/* Read data */
	xfer[1].addr = client->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = 2;
	xfer[1].buf = (u8 *)&data;

	ret = i2c_transfer(client->adapter, xfer, 2);
	if (ret != 2) {
		dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
		return 0;
	}

	return be16_to_cpu(data);
}
#else
#define snd_soc_16_16_read_i2c NULL
#endif

static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
				       unsigned int reg)
{
	u16 *cache = codec->reg_cache;

	if (reg >= codec->reg_cache_size ||
	    snd_soc_codec_volatile_register(codec, reg)) {
		if (codec->cache_only)
			return -EINVAL;

		return codec->hw_read(codec, reg);
	}

	return cache[reg];
}

static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
			       unsigned int value)
{
	u16 *cache = codec->reg_cache;
	u8 data[4];
	int ret;

	data[0] = (reg >> 8) & 0xff;
	data[1] = reg & 0xff;
	data[2] = (value >> 8) & 0xff;
	data[3] = value & 0xff;

	if (reg < codec->reg_cache_size)
		cache[reg] = value;

	if (codec->cache_only) {
		codec->cache_sync = 1;
		return 0;
	}

	ret = codec->hw_write(codec->control_data, data, 4);
	if (ret == 4)
		return 0;
	if (ret < 0)
		return ret;
	else
		return -EIO;
}

static struct {
	int addr_bits;
	int data_bits;
	int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
	int (*spi_write)(void *, const char *, int);
	unsigned int (*read)(struct snd_soc_codec *, unsigned int);
	unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
} io_types[] = {
	{
		.addr_bits = 4, .data_bits = 12,
		.write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
		.spi_write = snd_soc_4_12_spi_write,
	},
	{
		.addr_bits = 7, .data_bits = 9,
		.write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
		.spi_write = snd_soc_7_9_spi_write,
	},
	{
		.addr_bits = 8, .data_bits = 8,
		.write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
		.i2c_read = snd_soc_8_8_read_i2c,
	},
	{
		.addr_bits = 8, .data_bits = 16,
		.write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
		.i2c_read = snd_soc_8_16_read_i2c,
	},
	{
		.addr_bits = 16, .data_bits = 8,
		.write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
		.i2c_read = snd_soc_16_8_read_i2c,
		.spi_write = snd_soc_16_8_spi_write,
	},
	{
		.addr_bits = 16, .data_bits = 16,
		.write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
		.i2c_read = snd_soc_16_16_read_i2c,
	},
};

/**
 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
 *
 * @codec: CODEC to configure.
 * @type: Type of cache.
 * @addr_bits: Number of bits of register address data.
 * @data_bits: Number of bits of data per register.
 * @control: Control bus used.
 *
 * Register formats are frequently shared between many I2C and SPI
 * devices.  In order to promote code reuse the ASoC core provides
 * some standard implementations of CODEC read and write operations
 * which can be set up using this function.
 *
 * The caller is responsible for allocating and initialising the
 * actual cache.
 *
 * Note that at present this code cannot be used by CODECs with
 * volatile registers.
 */
int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
			       int addr_bits, int data_bits,
			       enum snd_soc_control_type control)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(io_types); i++)
		if (io_types[i].addr_bits == addr_bits &&
		    io_types[i].data_bits == data_bits)
			break;
	if (i == ARRAY_SIZE(io_types)) {
		printk(KERN_ERR
		       "No I/O functions for %d bit address %d bit data\n",
		       addr_bits, data_bits);
		return -EINVAL;
	}

	codec->write = io_types[i].write;
	codec->read = io_types[i].read;

	switch (control) {
	case SND_SOC_CUSTOM:
		break;

	case SND_SOC_I2C:
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
		codec->hw_write = (hw_write_t)i2c_master_send;
#endif
		if (io_types[i].i2c_read)
			codec->hw_read = io_types[i].i2c_read;
		break;

	case SND_SOC_SPI:
		if (io_types[i].spi_write)
			codec->hw_write = io_types[i].spi_write;
		break;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
Commit	Line	Data
17a52fd6 MB	1	/*
	2	* soc-cache.c -- ASoC register cache helpers
	3	*
	4	* Copyright 2009 Wolfson Microelectronics PLC.
	5	*
	6	* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
7084a42b	14	#include <linux/i2c.h>
27ded041	15	#include <linux/spi/spi.h>
17a52fd6 MB	16	#include <sound/soc.h>
17a52fd6 MB	17
63b62ab0 BS	18	static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
	19	unsigned int reg)
	20	{
	21	u16 *cache = codec->reg_cache;
	22	if (reg >= codec->reg_cache_size)
	23	return -1;
	24	return cache[reg];
	25	}
	26
	27	static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
	28	unsigned int value)
	29	{
	30	u16 *cache = codec->reg_cache;
	31	u8 data[2];
	32	int ret;
	33
	34	BUG_ON(codec->volatile_register);
	35
	36	data[0] = (reg << 4) \| ((value >> 8) & 0x000f);
	37	data[1] = value & 0x00ff;
	38
	39	if (reg < codec->reg_cache_size)
	40	cache[reg] = value;
8c961bcc	41
a3032b47 MB	42	if (codec->cache_only) {
a3032b47 MB	43	codec->cache_sync = 1;
8c961bcc	44	return 0;
a3032b47	45	}
8c961bcc	46
63b62ab0 BS	47	ret = codec->hw_write(codec->control_data, data, 2);
	48	if (ret == 2)
	49	return 0;
	50	if (ret < 0)
	51	return ret;
	52	else
	53	return -EIO;
	54	}
	55
	56	#if defined(CONFIG_SPI_MASTER)
	57	static int snd_soc_4_12_spi_write(void control_data, const char data,
	58	int len)
	59	{
	60	struct spi_device *spi = control_data;
	61	struct spi_transfer t;
	62	struct spi_message m;
	63	u8 msg[2];
	64
	65	if (len <= 0)
	66	return 0;
	67
	68	msg[0] = data[1];
	69	msg[1] = data[0];
	70
	71	spi_message_init(&m);
	72	memset(&t, 0, (sizeof t));
	73
	74	t.tx_buf = &msg[0];
	75	t.len = len;
	76
	77	spi_message_add_tail(&t, &m);
	78	spi_sync(spi, &m);
	79
	80	return len;
	81	}
	82	#else
	83	#define snd_soc_4_12_spi_write NULL
	84	#endif
	85
17a52fd6 MB	86	static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
	87	unsigned int reg)
	88	{
	89	u16 *cache = codec->reg_cache;
	90	if (reg >= codec->reg_cache_size)
	91	return -1;
	92	return cache[reg];
	93	}
	94
	95	static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
	96	unsigned int value)
	97	{
	98	u16 *cache = codec->reg_cache;
	99	u8 data[2];
	100	int ret;
	101
	102	BUG_ON(codec->volatile_register);
	103
	104	data[0] = (reg << 1) \| ((value >> 8) & 0x0001);
	105	data[1] = value & 0x00ff;
	106
	107	if (reg < codec->reg_cache_size)
	108	cache[reg] = value;
8c961bcc	109
a3032b47 MB	110	if (codec->cache_only) {
a3032b47 MB	111	codec->cache_sync = 1;
8c961bcc	112	return 0;
a3032b47	113	}
8c961bcc	114
17a52fd6 MB	115	ret = codec->hw_write(codec->control_data, data, 2);
	116	if (ret == 2)
	117	return 0;
	118	if (ret < 0)
	119	return ret;
	120	else
	121	return -EIO;
	122	}
	123
27ded041 MB	124	#if defined(CONFIG_SPI_MASTER)
	125	static int snd_soc_7_9_spi_write(void control_data, const char data,
	126	int len)
	127	{
	128	struct spi_device *spi = control_data;
	129	struct spi_transfer t;
	130	struct spi_message m;
	131	u8 msg[2];
	132
	133	if (len <= 0)
	134	return 0;
	135
	136	msg[0] = data[0];
	137	msg[1] = data[1];
	138
	139	spi_message_init(&m);
	140	memset(&t, 0, (sizeof t));
	141
	142	t.tx_buf = &msg[0];
	143	t.len = len;
	144
	145	spi_message_add_tail(&t, &m);
	146	spi_sync(spi, &m);
	147
	148	return len;
	149	}
	150	#else
	151	#define snd_soc_7_9_spi_write NULL
	152	#endif
	153
341c9b84 JS	154	static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
	155	unsigned int value)
	156	{
	157	u8 *cache = codec->reg_cache;
	158	u8 data[2];
	159
	160	BUG_ON(codec->volatile_register);
	161
f4bee1bb BS	162	reg &= 0xff;
f4bee1bb BS	163	data[0] = reg;
341c9b84 JS	164	data[1] = value & 0xff;
	165
	166	if (reg < codec->reg_cache_size)
	167	cache[reg] = value;
	168
a3032b47 MB	169	if (codec->cache_only) {
a3032b47 MB	170	codec->cache_sync = 1;
8c961bcc	171	return 0;
a3032b47	172	}
8c961bcc	173
341c9b84 JS	174	if (codec->hw_write(codec->control_data, data, 2) == 2)
	175	return 0;
	176	else
	177	return -EIO;
	178	}
	179
	180	static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
	181	unsigned int reg)
	182	{
	183	u8 *cache = codec->reg_cache;
f4bee1bb	184	reg &= 0xff;
341c9b84 JS	185	if (reg >= codec->reg_cache_size)
	186	return -1;
	187	return cache[reg];
	188	}
	189
afa2f106 MB	190	static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
	191	unsigned int value)
	192	{
	193	u16 *reg_cache = codec->reg_cache;
	194	u8 data[3];
	195
	196	data[0] = reg;
	197	data[1] = (value >> 8) & 0xff;
	198	data[2] = value & 0xff;
	199
	200	if (!snd_soc_codec_volatile_register(codec, reg))
	201	reg_cache[reg] = value;
	202
a3032b47 MB	203	if (codec->cache_only) {
a3032b47 MB	204	codec->cache_sync = 1;
8c961bcc	205	return 0;
a3032b47	206	}
8c961bcc	207
afa2f106 MB	208	if (codec->hw_write(codec->control_data, data, 3) == 3)
	209	return 0;
	210	else
	211	return -EIO;
	212	}
	213
	214	static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
	215	unsigned int reg)
	216	{
	217	u16 *cache = codec->reg_cache;
	218
	219	if (reg >= codec->reg_cache_size \|\|
8c961bcc MB	220	snd_soc_codec_volatile_register(codec, reg)) {
	221	if (codec->cache_only)
	222	return -EINVAL;
	223
afa2f106	224	return codec->hw_read(codec, reg);
8c961bcc	225	} else {
afa2f106	226	return cache[reg];
8c961bcc	227	}
afa2f106 MB	228	}
afa2f106 MB	229
85dfcdff CC	230	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
	231	static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
	232	unsigned int r)
	233	{
	234	struct i2c_msg xfer[2];
	235	u8 reg = r;
	236	u8 data;
	237	int ret;
	238	struct i2c_client *client = codec->control_data;
	239
	240	/* Write register */
	241	xfer[0].addr = client->addr;
	242	xfer[0].flags = 0;
	243	xfer[0].len = 1;
	244	xfer[0].buf = ®
	245
	246	/* Read data */
	247	xfer[1].addr = client->addr;
	248	xfer[1].flags = I2C_M_RD;
	249	xfer[1].len = 1;
	250	xfer[1].buf = &data;
	251
	252	ret = i2c_transfer(client->adapter, xfer, 2);
	253	if (ret != 2) {
	254	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	255	return 0;
	256	}
	257
	258	return data;
	259	}
	260	#else
	261	#define snd_soc_8_8_read_i2c NULL
	262	#endif
	263
17244c24	264	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
afa2f106 MB	265	static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
	266	unsigned int r)
	267	{
	268	struct i2c_msg xfer[2];
	269	u8 reg = r;
	270	u16 data;
	271	int ret;
	272	struct i2c_client *client = codec->control_data;
	273
	274	/* Write register */
	275	xfer[0].addr = client->addr;
	276	xfer[0].flags = 0;
	277	xfer[0].len = 1;
	278	xfer[0].buf = ®
	279
	280	/* Read data */
	281	xfer[1].addr = client->addr;
	282	xfer[1].flags = I2C_M_RD;
	283	xfer[1].len = 2;
	284	xfer[1].buf = (u8 *)&data;
	285
	286	ret = i2c_transfer(client->adapter, xfer, 2);
	287	if (ret != 2) {
	288	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	289	return 0;
	290	}
	291
	292	return (data >> 8) \| ((data & 0xff) << 8);
	293	}
	294	#else
	295	#define snd_soc_8_16_read_i2c NULL
	296	#endif
17a52fd6	297
994dc424 BS	298	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
	299	static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
	300	unsigned int r)
	301	{
	302	struct i2c_msg xfer[2];
	303	u16 reg = r;
	304	u8 data;
	305	int ret;
	306	struct i2c_client *client = codec->control_data;
	307
	308	/* Write register */
	309	xfer[0].addr = client->addr;
	310	xfer[0].flags = 0;
	311	xfer[0].len = 2;
	312	xfer[0].buf = (u8 *)®
	313
	314	/* Read data */
	315	xfer[1].addr = client->addr;
	316	xfer[1].flags = I2C_M_RD;
	317	xfer[1].len = 1;
	318	xfer[1].buf = &data;
	319
	320	ret = i2c_transfer(client->adapter, xfer, 2);
	321	if (ret != 2) {
	322	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	323	return 0;
	324	}
	325
	326	return data;
	327	}
	328	#else
	329	#define snd_soc_16_8_read_i2c NULL
	330	#endif
	331
	332	static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
	333	unsigned int reg)
	334	{
	335	u16 *cache = codec->reg_cache;
	336
	337	reg &= 0xff;
	338	if (reg >= codec->reg_cache_size)
	339	return -1;
	340	return cache[reg];
	341	}
	342
	343	static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
	344	unsigned int value)
	345	{
	346	u16 *cache = codec->reg_cache;
	347	u8 data[3];
	348	int ret;
	349
	350	BUG_ON(codec->volatile_register);
	351
	352	data[0] = (reg >> 8) & 0xff;
	353	data[1] = reg & 0xff;
	354	data[2] = value;
	355
	356	reg &= 0xff;
	357	if (reg < codec->reg_cache_size)
	358	cache[reg] = value;
8c961bcc	359
a3032b47 MB	360	if (codec->cache_only) {
a3032b47 MB	361	codec->cache_sync = 1;
8c961bcc	362	return 0;
a3032b47	363	}
8c961bcc	364
994dc424 BS	365	ret = codec->hw_write(codec->control_data, data, 3);
	366	if (ret == 3)
	367	return 0;
	368	if (ret < 0)
	369	return ret;
	370	else
	371	return -EIO;
	372	}
	373
	374	#if defined(CONFIG_SPI_MASTER)
	375	static int snd_soc_16_8_spi_write(void control_data, const char data,
	376	int len)
	377	{
	378	struct spi_device *spi = control_data;
	379	struct spi_transfer t;
	380	struct spi_message m;
	381	u8 msg[3];
	382
	383	if (len <= 0)
	384	return 0;
	385
	386	msg[0] = data[0];
	387	msg[1] = data[1];
	388	msg[2] = data[2];
	389
	390	spi_message_init(&m);
	391	memset(&t, 0, (sizeof t));
	392
	393	t.tx_buf = &msg[0];
	394	t.len = len;
	395
	396	spi_message_add_tail(&t, &m);
	397	spi_sync(spi, &m);
	398
	399	return len;
	400	}
	401	#else
	402	#define snd_soc_16_8_spi_write NULL
	403	#endif
	404
bc6552f4 MB	405	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
	406	static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
	407	unsigned int r)
	408	{
	409	struct i2c_msg xfer[2];
	410	u16 reg = cpu_to_be16(r);
	411	u16 data;
	412	int ret;
	413	struct i2c_client *client = codec->control_data;
	414
	415	/* Write register */
	416	xfer[0].addr = client->addr;
	417	xfer[0].flags = 0;
	418	xfer[0].len = 2;
	419	xfer[0].buf = (u8 *)®
	420
	421	/* Read data */
	422	xfer[1].addr = client->addr;
	423	xfer[1].flags = I2C_M_RD;
	424	xfer[1].len = 2;
	425	xfer[1].buf = (u8 *)&data;
	426
	427	ret = i2c_transfer(client->adapter, xfer, 2);
	428	if (ret != 2) {
	429	dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
	430	return 0;
	431	}
	432
	433	return be16_to_cpu(data);
	434	}
	435	#else
	436	#define snd_soc_16_16_read_i2c NULL
	437	#endif
	438
	439	static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
	440	unsigned int reg)
	441	{
	442	u16 *cache = codec->reg_cache;
	443
	444	if (reg >= codec->reg_cache_size \|\|
	445	snd_soc_codec_volatile_register(codec, reg)) {
	446	if (codec->cache_only)
	447	return -EINVAL;
	448
	449	return codec->hw_read(codec, reg);
	450	}
	451
	452	return cache[reg];
	453	}
	454
	455	static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
	456	unsigned int value)
	457	{
	458	u16 *cache = codec->reg_cache;
	459	u8 data[4];
	460	int ret;
	461
	462	data[0] = (reg >> 8) & 0xff;
	463	data[1] = reg & 0xff;
	464	data[2] = (value >> 8) & 0xff;
	465	data[3] = value & 0xff;
	466
	467	if (reg < codec->reg_cache_size)
	468	cache[reg] = value;
469
470	if (codec->cache_only) {
471	codec->cache_sync = 1;
472	return 0;
473	}
474
475	ret = codec->hw_write(codec->control_data, data, 4);
476	if (ret == 4)
477	return 0;
478	if (ret < 0)
479	return ret;
480	else
481	return -EIO;
482	}
994dc424	483
17a52fd6 MB	484	static struct {
	485	int addr_bits;
	486	int data_bits;
afa2f106	487	int (write)(struct snd_soc_codec codec, unsigned int, unsigned int);
27ded041	488	int (spi_write)(void , const char *, int);
17a52fd6	489	unsigned int (read)(struct snd_soc_codec , unsigned int);
afa2f106	490	unsigned int (i2c_read)(struct snd_soc_codec , unsigned int);
17a52fd6	491	} io_types[] = {
63b62ab0 BS	492	{
	493	.addr_bits = 4, .data_bits = 12,
	494	.write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
	495	.spi_write = snd_soc_4_12_spi_write,
	496	},
d62ab358 MB	497	{
	498	.addr_bits = 7, .data_bits = 9,
	499	.write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
8998c899	500	.spi_write = snd_soc_7_9_spi_write,
d62ab358 MB	501	},
	502	{
	503	.addr_bits = 8, .data_bits = 8,
	504	.write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
85dfcdff	505	.i2c_read = snd_soc_8_8_read_i2c,
d62ab358 MB	506	},
	507	{
	508	.addr_bits = 8, .data_bits = 16,
	509	.write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
	510	.i2c_read = snd_soc_8_16_read_i2c,
	511	},
994dc424 BS	512	{
	513	.addr_bits = 16, .data_bits = 8,
	514	.write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
	515	.i2c_read = snd_soc_16_8_read_i2c,
	516	.spi_write = snd_soc_16_8_spi_write,
	517	},
bc6552f4 MB	518	{
	519	.addr_bits = 16, .data_bits = 16,
	520	.write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
	521	.i2c_read = snd_soc_16_16_read_i2c,
	522	},
17a52fd6 MB	523	};
	524
	525	/**
	526	* snd_soc_codec_set_cache_io: Set up standard I/O functions.
	527	*
	528	* @codec: CODEC to configure.
	529	* @type: Type of cache.
	530	* @addr_bits: Number of bits of register address data.
	531	* @data_bits: Number of bits of data per register.
7084a42b	532	* @control: Control bus used.
17a52fd6 MB	533	*
	534	* Register formats are frequently shared between many I2C and SPI
	535	* devices. In order to promote code reuse the ASoC core provides
	536	* some standard implementations of CODEC read and write operations
	537	* which can be set up using this function.
	538	*
	539	* The caller is responsible for allocating and initialising the
	540	* actual cache.
	541	*
	542	* Note that at present this code cannot be used by CODECs with
	543	* volatile registers.
	544	*/
	545	int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
7084a42b MB	546	int addr_bits, int data_bits,
7084a42b MB	547	enum snd_soc_control_type control)
17a52fd6 MB	548	{
	549	int i;
	550
17a52fd6 MB	551	for (i = 0; i < ARRAY_SIZE(io_types); i++)
	552	if (io_types[i].addr_bits == addr_bits &&
	553	io_types[i].data_bits == data_bits)
	554	break;
	555	if (i == ARRAY_SIZE(io_types)) {
	556	printk(KERN_ERR
	557	"No I/O functions for %d bit address %d bit data\n",
	558	addr_bits, data_bits);
	559	return -EINVAL;
	560	}
	561
	562	codec->write = io_types[i].write;
	563	codec->read = io_types[i].read;
	564
7084a42b MB	565	switch (control) {
	566	case SND_SOC_CUSTOM:
	567	break;
	568
	569	case SND_SOC_I2C:
17244c24	570	#if defined(CONFIG_I2C) \|\| (defined(CONFIG_I2C_MODULE) && defined(MODULE))
7084a42b MB	571	codec->hw_write = (hw_write_t)i2c_master_send;
7084a42b MB	572	#endif
afa2f106 MB	573	if (io_types[i].i2c_read)
afa2f106 MB	574	codec->hw_read = io_types[i].i2c_read;
7084a42b MB	575	break;
	576
	577	case SND_SOC_SPI:
27ded041 MB	578	if (io_types[i].spi_write)
27ded041 MB	579	codec->hw_write = io_types[i].spi_write;
7084a42b MB	580	break;
	581	}
	582
17a52fd6 MB	583	return 0;
	584	}
	585	EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);