Commit | Line | Data |
---|---|---|
dfc9403b KM |
1 | /* |
2 | * Helper routines for R-Car sound ADG. | |
3 | * | |
4 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
2a46db4a | 10 | #include <linux/clk-provider.h> |
dfc9403b KM |
11 | #include "rsnd.h" |
12 | ||
13 | #define CLKA 0 | |
14 | #define CLKB 1 | |
15 | #define CLKC 2 | |
16 | #define CLKI 3 | |
17 | #define CLKMAX 4 | |
18 | ||
2a46db4a KM |
19 | #define CLKOUT 0 |
20 | #define CLKOUT1 1 | |
21 | #define CLKOUT2 2 | |
22 | #define CLKOUT3 3 | |
23 | #define CLKOUTMAX 4 | |
24 | ||
eae6fff4 KM |
25 | #define BRRx_MASK(x) (0x3FF & x) |
26 | ||
1665a9e5 KM |
27 | static struct rsnd_mod_ops adg_ops = { |
28 | .name = "adg", | |
29 | }; | |
30 | ||
dfc9403b KM |
31 | struct rsnd_adg { |
32 | struct clk *clk[CLKMAX]; | |
2a46db4a KM |
33 | struct clk *clkout[CLKOUTMAX]; |
34 | struct clk_onecell_data onecell; | |
1665a9e5 | 35 | struct rsnd_mod mod; |
7dc20319 | 36 | u32 flags; |
b99258a3 KM |
37 | u32 ckr; |
38 | u32 rbga; | |
39 | u32 rbgb; | |
dfc9403b | 40 | |
eae6fff4 KM |
41 | int rbga_rate_for_441khz; /* RBGA */ |
42 | int rbgb_rate_for_48khz; /* RBGB */ | |
dfc9403b KM |
43 | }; |
44 | ||
7dc20319 | 45 | #define LRCLK_ASYNC (1 << 0) |
25165f79 | 46 | #define AUDIO_OUT_48 (1 << 1) |
7dc20319 KM |
47 | #define adg_mode_flags(adg) (adg->flags) |
48 | ||
dfc9403b | 49 | #define for_each_rsnd_clk(pos, adg, i) \ |
00463c11 KM |
50 | for (i = 0; \ |
51 | (i < CLKMAX) && \ | |
52 | ((pos) = adg->clk[i]); \ | |
53 | i++) | |
2a46db4a KM |
54 | #define for_each_rsnd_clkout(pos, adg, i) \ |
55 | for (i = 0; \ | |
56 | (i < CLKOUTMAX) && \ | |
57 | ((pos) = adg->clkout[i]); \ | |
58 | i++) | |
dfc9403b KM |
59 | #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) |
60 | ||
eae6fff4 KM |
61 | static u32 rsnd_adg_calculate_rbgx(unsigned long div) |
62 | { | |
63 | int i, ratio; | |
64 | ||
65 | if (!div) | |
66 | return 0; | |
67 | ||
68 | for (i = 3; i >= 0; i--) { | |
69 | ratio = 2 << (i * 2); | |
70 | if (0 == (div % ratio)) | |
71 | return (u32)((i << 8) | ((div / ratio) - 1)); | |
72 | } | |
73 | ||
74 | return ~0; | |
75 | } | |
629509c5 | 76 | |
8467dedc | 77 | static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) |
629509c5 | 78 | { |
94458364 KM |
79 | struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io); |
80 | int id = rsnd_mod_id(ssi_mod); | |
629509c5 KM |
81 | int ws = id; |
82 | ||
b415b4d3 | 83 | if (rsnd_ssi_is_pin_sharing(io)) { |
629509c5 KM |
84 | switch (id) { |
85 | case 1: | |
86 | case 2: | |
87 | ws = 0; | |
88 | break; | |
89 | case 4: | |
90 | ws = 3; | |
91 | break; | |
92 | case 8: | |
93 | ws = 7; | |
94 | break; | |
95 | } | |
96 | } | |
97 | ||
98 | return (0x6 + ws) << 8; | |
99 | } | |
100 | ||
0102eed5 KM |
101 | static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, |
102 | struct rsnd_dai_stream *io, | |
103 | unsigned int target_rate, | |
104 | unsigned int *target_val, | |
105 | unsigned int *target_en) | |
106 | { | |
107 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); | |
108 | struct device *dev = rsnd_priv_to_dev(priv); | |
109 | int idx, sel, div, step; | |
110 | unsigned int val, en; | |
111 | unsigned int min, diff; | |
112 | unsigned int sel_rate[] = { | |
113 | clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */ | |
114 | clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */ | |
115 | clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */ | |
116 | adg->rbga_rate_for_441khz, /* 0011: RBGA */ | |
117 | adg->rbgb_rate_for_48khz, /* 0100: RBGB */ | |
118 | }; | |
119 | ||
120 | min = ~0; | |
121 | val = 0; | |
122 | en = 0; | |
123 | for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { | |
124 | idx = 0; | |
125 | step = 2; | |
126 | ||
127 | if (!sel_rate[sel]) | |
128 | continue; | |
129 | ||
130 | for (div = 2; div <= 98304; div += step) { | |
131 | diff = abs(target_rate - sel_rate[sel] / div); | |
132 | if (min > diff) { | |
133 | val = (sel << 8) | idx; | |
134 | min = diff; | |
135 | en = 1 << (sel + 1); /* fixme */ | |
136 | } | |
137 | ||
138 | /* | |
139 | * step of 0_0000 / 0_0001 / 0_1101 | |
140 | * are out of order | |
141 | */ | |
142 | if ((idx > 2) && (idx % 2)) | |
143 | step *= 2; | |
144 | if (idx == 0x1c) { | |
145 | div += step; | |
146 | step *= 2; | |
147 | } | |
148 | idx++; | |
149 | } | |
150 | } | |
151 | ||
152 | if (min == ~0) { | |
153 | dev_err(dev, "no Input clock\n"); | |
154 | return; | |
155 | } | |
156 | ||
157 | *target_val = val; | |
158 | if (target_en) | |
159 | *target_en = en; | |
160 | } | |
161 | ||
162 | static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, | |
163 | struct rsnd_dai_stream *io, | |
164 | unsigned int in_rate, | |
165 | unsigned int out_rate, | |
166 | u32 *in, u32 *out, u32 *en) | |
167 | { | |
168 | struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); | |
169 | unsigned int target_rate; | |
170 | u32 *target_val; | |
171 | u32 _in; | |
172 | u32 _out; | |
173 | u32 _en; | |
174 | ||
175 | /* default = SSI WS */ | |
176 | _in = | |
177 | _out = rsnd_adg_ssi_ws_timing_gen2(io); | |
178 | ||
179 | target_rate = 0; | |
180 | target_val = NULL; | |
181 | _en = 0; | |
182 | if (runtime->rate != in_rate) { | |
183 | target_rate = out_rate; | |
184 | target_val = &_out; | |
185 | } else if (runtime->rate != out_rate) { | |
186 | target_rate = in_rate; | |
187 | target_val = &_in; | |
188 | } | |
189 | ||
190 | if (target_rate) | |
191 | __rsnd_adg_get_timesel_ratio(priv, io, | |
192 | target_rate, | |
193 | target_val, &_en); | |
194 | ||
195 | if (in) | |
196 | *in = _in; | |
197 | if (out) | |
198 | *out = _out; | |
199 | if (en) | |
200 | *en = _en; | |
201 | } | |
202 | ||
94458364 | 203 | int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod, |
bff58ea4 KM |
204 | struct rsnd_dai_stream *io) |
205 | { | |
94458364 | 206 | struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod); |
1665a9e5 KM |
207 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
208 | struct rsnd_mod *adg_mod = rsnd_mod_get(adg); | |
94458364 | 209 | int id = rsnd_mod_id(cmd_mod); |
bff58ea4 KM |
210 | int shift = (id % 2) ? 16 : 0; |
211 | u32 mask, val; | |
212 | ||
09e59075 KM |
213 | rsnd_adg_get_timesel_ratio(priv, io, |
214 | rsnd_src_get_in_rate(priv, io), | |
215 | rsnd_src_get_out_rate(priv, io), | |
216 | NULL, &val, NULL); | |
bff58ea4 KM |
217 | |
218 | val = val << shift; | |
caca324f | 219 | mask = 0x0f1f << shift; |
bff58ea4 | 220 | |
1665a9e5 | 221 | rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); |
bff58ea4 KM |
222 | |
223 | return 0; | |
224 | } | |
225 | ||
0102eed5 KM |
226 | int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod, |
227 | struct rsnd_dai_stream *io, | |
228 | unsigned int in_rate, | |
229 | unsigned int out_rate) | |
629509c5 | 230 | { |
f1df1229 | 231 | struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); |
1665a9e5 KM |
232 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
233 | struct rsnd_mod *adg_mod = rsnd_mod_get(adg); | |
0102eed5 KM |
234 | u32 in, out; |
235 | u32 mask, en; | |
f1df1229 | 236 | int id = rsnd_mod_id(src_mod); |
629509c5 | 237 | int shift = (id % 2) ? 16 : 0; |
629509c5 | 238 | |
f1df1229 KM |
239 | rsnd_mod_confirm_src(src_mod); |
240 | ||
0102eed5 KM |
241 | rsnd_adg_get_timesel_ratio(priv, io, |
242 | in_rate, out_rate, | |
243 | &in, &out, &en); | |
629509c5 KM |
244 | |
245 | in = in << shift; | |
246 | out = out << shift; | |
caca324f | 247 | mask = 0x0f1f << shift; |
629509c5 KM |
248 | |
249 | switch (id / 2) { | |
250 | case 0: | |
1665a9e5 KM |
251 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in); |
252 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out); | |
629509c5 KM |
253 | break; |
254 | case 1: | |
1665a9e5 KM |
255 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in); |
256 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out); | |
629509c5 KM |
257 | break; |
258 | case 2: | |
1665a9e5 KM |
259 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in); |
260 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out); | |
629509c5 KM |
261 | break; |
262 | case 3: | |
1665a9e5 KM |
263 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in); |
264 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out); | |
629509c5 KM |
265 | break; |
266 | case 4: | |
1665a9e5 KM |
267 | rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in); |
268 | rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out); | |
629509c5 KM |
269 | break; |
270 | } | |
271 | ||
0102eed5 KM |
272 | if (en) |
273 | rsnd_mod_bset(adg_mod, DIV_EN, en, en); | |
d2c4b80c | 274 | |
ee2c828d | 275 | return 0; |
629509c5 KM |
276 | } |
277 | ||
f1df1229 | 278 | static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) |
dfc9403b | 279 | { |
f1df1229 | 280 | struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); |
1665a9e5 KM |
281 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
282 | struct rsnd_mod *adg_mod = rsnd_mod_get(adg); | |
f1df1229 | 283 | int id = rsnd_mod_id(ssi_mod); |
e337853e KM |
284 | int shift = (id % 4) * 8; |
285 | u32 mask = 0xFF << shift; | |
286 | ||
f1df1229 KM |
287 | rsnd_mod_confirm_ssi(ssi_mod); |
288 | ||
e337853e | 289 | val = val << shift; |
dfc9403b KM |
290 | |
291 | /* | |
292 | * SSI 8 is not connected to ADG. | |
293 | * it works with SSI 7 | |
294 | */ | |
295 | if (id == 8) | |
e337853e KM |
296 | return; |
297 | ||
298 | switch (id / 4) { | |
299 | case 0: | |
1665a9e5 | 300 | rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val); |
e337853e KM |
301 | break; |
302 | case 1: | |
1665a9e5 | 303 | rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val); |
e337853e KM |
304 | break; |
305 | case 2: | |
1665a9e5 | 306 | rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val); |
e337853e KM |
307 | break; |
308 | } | |
dfc9403b KM |
309 | } |
310 | ||
1dfdc650 | 311 | int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate) |
dfc9403b | 312 | { |
dfc9403b KM |
313 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); |
314 | struct device *dev = rsnd_priv_to_dev(priv); | |
315 | struct clk *clk; | |
e337853e | 316 | int i; |
dfc9403b KM |
317 | int sel_table[] = { |
318 | [CLKA] = 0x1, | |
319 | [CLKB] = 0x2, | |
320 | [CLKC] = 0x3, | |
321 | [CLKI] = 0x0, | |
322 | }; | |
323 | ||
324 | dev_dbg(dev, "request clock = %d\n", rate); | |
325 | ||
326 | /* | |
327 | * find suitable clock from | |
328 | * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. | |
329 | */ | |
dfc9403b | 330 | for_each_rsnd_clk(clk, adg, i) { |
1dfdc650 KM |
331 | if (rate == clk_get_rate(clk)) |
332 | return sel_table[i]; | |
dfc9403b KM |
333 | } |
334 | ||
335 | /* | |
eae6fff4 | 336 | * find divided clock from BRGA/BRGB |
dfc9403b | 337 | */ |
1dfdc650 KM |
338 | if (rate == adg->rbga_rate_for_441khz) |
339 | return 0x10; | |
dfc9403b | 340 | |
1dfdc650 KM |
341 | if (rate == adg->rbgb_rate_for_48khz) |
342 | return 0x20; | |
dfc9403b KM |
343 | |
344 | return -EIO; | |
1dfdc650 KM |
345 | } |
346 | ||
347 | int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) | |
348 | { | |
349 | rsnd_adg_set_ssi_clk(ssi_mod, 0); | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) | |
355 | { | |
356 | struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); | |
357 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); | |
358 | struct device *dev = rsnd_priv_to_dev(priv); | |
359 | struct rsnd_mod *adg_mod = rsnd_mod_get(adg); | |
360 | int data; | |
361 | u32 ckr = 0; | |
dfc9403b | 362 | |
1dfdc650 KM |
363 | data = rsnd_adg_clk_query(priv, rate); |
364 | if (data < 0) | |
365 | return data; | |
dfc9403b | 366 | |
94458364 | 367 | rsnd_adg_set_ssi_clk(ssi_mod, data); |
dfc9403b | 368 | |
25165f79 KM |
369 | if (adg_mode_flags(adg) & LRCLK_ASYNC) { |
370 | if (adg_mode_flags(adg) & AUDIO_OUT_48) | |
371 | ckr = 0x80000000; | |
372 | } else { | |
7dc20319 KM |
373 | if (0 == (rate % 8000)) |
374 | ckr = 0x80000000; | |
7dc20319 KM |
375 | } |
376 | ||
caca324f | 377 | rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); |
b99258a3 KM |
378 | rsnd_mod_write(adg_mod, BRRA, adg->rbga); |
379 | rsnd_mod_write(adg_mod, BRRB, adg->rbgb); | |
380 | ||
3af6c3ac | 381 | dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n", |
94458364 | 382 | rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod), |
3af6c3ac | 383 | data, rate); |
dfc9403b KM |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
c2d31718 KM |
388 | void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable) |
389 | { | |
390 | struct rsnd_adg *adg = rsnd_priv_to_adg(priv); | |
391 | struct device *dev = rsnd_priv_to_dev(priv); | |
392 | struct clk *clk; | |
393 | int i, ret; | |
394 | ||
395 | for_each_rsnd_clk(clk, adg, i) { | |
396 | ret = 0; | |
397 | if (enable) | |
398 | ret = clk_prepare_enable(clk); | |
399 | else | |
400 | clk_disable_unprepare(clk); | |
401 | ||
402 | if (ret < 0) | |
403 | dev_warn(dev, "can't use clk %d\n", i); | |
404 | } | |
405 | } | |
406 | ||
248e88c2 KM |
407 | static void rsnd_adg_get_clkin(struct rsnd_priv *priv, |
408 | struct rsnd_adg *adg) | |
409 | { | |
410 | struct device *dev = rsnd_priv_to_dev(priv); | |
411 | struct clk *clk; | |
412 | static const char * const clk_name[] = { | |
413 | [CLKA] = "clk_a", | |
414 | [CLKB] = "clk_b", | |
415 | [CLKC] = "clk_c", | |
416 | [CLKI] = "clk_i", | |
417 | }; | |
c2d31718 | 418 | int i; |
248e88c2 KM |
419 | |
420 | for (i = 0; i < CLKMAX; i++) { | |
421 | clk = devm_clk_get(dev, clk_name[i]); | |
422 | adg->clk[i] = IS_ERR(clk) ? NULL : clk; | |
423 | } | |
424 | ||
c2d31718 | 425 | for_each_rsnd_clk(clk, adg, i) |
248e88c2 KM |
426 | dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk)); |
427 | } | |
428 | ||
2a46db4a KM |
429 | static void rsnd_adg_get_clkout(struct rsnd_priv *priv, |
430 | struct rsnd_adg *adg) | |
dfc9403b KM |
431 | { |
432 | struct clk *clk; | |
eae6fff4 | 433 | struct device *dev = rsnd_priv_to_dev(priv); |
2a46db4a | 434 | struct device_node *np = dev->of_node; |
25165f79 | 435 | struct property *prop; |
eae6fff4 | 436 | u32 ckr, rbgx, rbga, rbgb; |
25165f79 KM |
437 | u32 rate, div; |
438 | #define REQ_SIZE 2 | |
439 | u32 req_rate[REQ_SIZE] = {}; | |
2a46db4a KM |
440 | uint32_t count = 0; |
441 | unsigned long req_48kHz_rate, req_441kHz_rate; | |
25165f79 | 442 | int i, req_size; |
2a46db4a KM |
443 | const char *parent_clk_name = NULL; |
444 | static const char * const clkout_name[] = { | |
445 | [CLKOUT] = "audio_clkout", | |
446 | [CLKOUT1] = "audio_clkout1", | |
447 | [CLKOUT2] = "audio_clkout2", | |
448 | [CLKOUT3] = "audio_clkout3", | |
449 | }; | |
dfc9403b KM |
450 | int brg_table[] = { |
451 | [CLKA] = 0x0, | |
452 | [CLKB] = 0x1, | |
453 | [CLKC] = 0x4, | |
454 | [CLKI] = 0x2, | |
455 | }; | |
456 | ||
e8dffe6c MV |
457 | ckr = 0; |
458 | rbga = 2; /* default 1/6 */ | |
459 | rbgb = 2; /* default 1/6 */ | |
2a46db4a KM |
460 | |
461 | /* | |
462 | * ADG supports BRRA/BRRB output only | |
463 | * this means all clkout0/1/2/3 will be same rate | |
464 | */ | |
75f9e4ad | 465 | prop = of_find_property(np, "clock-frequency", NULL); |
e8dffe6c MV |
466 | if (!prop) |
467 | goto rsnd_adg_get_clkout_end; | |
468 | ||
25165f79 KM |
469 | req_size = prop->length / sizeof(u32); |
470 | ||
471 | of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); | |
2a46db4a KM |
472 | req_48kHz_rate = 0; |
473 | req_441kHz_rate = 0; | |
25165f79 KM |
474 | for (i = 0; i < req_size; i++) { |
475 | if (0 == (req_rate[i] % 44100)) | |
476 | req_441kHz_rate = req_rate[i]; | |
477 | if (0 == (req_rate[i] % 48000)) | |
478 | req_48kHz_rate = req_rate[i]; | |
479 | } | |
2a46db4a | 480 | |
e8dffe6c MV |
481 | if (req_rate[0] % 48000 == 0) |
482 | adg->flags = AUDIO_OUT_48; | |
483 | ||
9654f5eb KM |
484 | if (of_get_property(np, "clkout-lr-asynchronous", NULL)) |
485 | adg->flags = LRCLK_ASYNC; | |
486 | ||
dfc9403b KM |
487 | /* |
488 | * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC | |
489 | * have 44.1kHz or 48kHz base clocks for now. | |
490 | * | |
491 | * SSI itself can divide parent clock by 1/1 - 1/16 | |
dfc9403b KM |
492 | * see |
493 | * rsnd_adg_ssi_clk_try_start() | |
5c6901d9 | 494 | * rsnd_ssi_master_clk_start() |
dfc9403b | 495 | */ |
eae6fff4 KM |
496 | adg->rbga_rate_for_441khz = 0; |
497 | adg->rbgb_rate_for_48khz = 0; | |
dfc9403b KM |
498 | for_each_rsnd_clk(clk, adg, i) { |
499 | rate = clk_get_rate(clk); | |
500 | ||
501 | if (0 == rate) /* not used */ | |
502 | continue; | |
503 | ||
504 | /* RBGA */ | |
eae6fff4 KM |
505 | if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) { |
506 | div = 6; | |
2a46db4a KM |
507 | if (req_441kHz_rate) |
508 | div = rate / req_441kHz_rate; | |
eae6fff4 KM |
509 | rbgx = rsnd_adg_calculate_rbgx(div); |
510 | if (BRRx_MASK(rbgx) == rbgx) { | |
511 | rbga = rbgx; | |
512 | adg->rbga_rate_for_441khz = rate / div; | |
513 | ckr |= brg_table[i] << 20; | |
e8a3ce11 KM |
514 | if (req_441kHz_rate && |
515 | !(adg_mode_flags(adg) & AUDIO_OUT_48)) | |
2a46db4a | 516 | parent_clk_name = __clk_get_name(clk); |
eae6fff4 | 517 | } |
dfc9403b KM |
518 | } |
519 | ||
520 | /* RBGB */ | |
eae6fff4 KM |
521 | if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) { |
522 | div = 6; | |
2a46db4a KM |
523 | if (req_48kHz_rate) |
524 | div = rate / req_48kHz_rate; | |
eae6fff4 KM |
525 | rbgx = rsnd_adg_calculate_rbgx(div); |
526 | if (BRRx_MASK(rbgx) == rbgx) { | |
527 | rbgb = rbgx; | |
528 | adg->rbgb_rate_for_48khz = rate / div; | |
529 | ckr |= brg_table[i] << 16; | |
e8a3ce11 KM |
530 | if (req_48kHz_rate && |
531 | (adg_mode_flags(adg) & AUDIO_OUT_48)) | |
2a46db4a | 532 | parent_clk_name = __clk_get_name(clk); |
2a46db4a KM |
533 | } |
534 | } | |
535 | } | |
536 | ||
537 | /* | |
538 | * ADG supports BRRA/BRRB output only. | |
539 | * this means all clkout0/1/2/3 will be * same rate | |
540 | */ | |
541 | ||
e8dffe6c | 542 | of_property_read_u32(np, "#clock-cells", &count); |
2a46db4a KM |
543 | /* |
544 | * for clkout | |
545 | */ | |
546 | if (!count) { | |
462c30bc | 547 | clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], |
25165f79 | 548 | parent_clk_name, 0, req_rate[0]); |
2a46db4a KM |
549 | if (!IS_ERR(clk)) { |
550 | adg->clkout[CLKOUT] = clk; | |
551 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
552 | } | |
553 | } | |
554 | /* | |
555 | * for clkout0/1/2/3 | |
556 | */ | |
557 | else { | |
558 | for (i = 0; i < CLKOUTMAX; i++) { | |
559 | clk = clk_register_fixed_rate(dev, clkout_name[i], | |
2ebdf684 | 560 | parent_clk_name, 0, |
25165f79 | 561 | req_rate[0]); |
d7f29819 | 562 | if (!IS_ERR(clk)) |
2a46db4a | 563 | adg->clkout[i] = clk; |
dfc9403b | 564 | } |
d7f29819 KM |
565 | adg->onecell.clks = adg->clkout; |
566 | adg->onecell.clk_num = CLKOUTMAX; | |
567 | of_clk_add_provider(np, of_clk_src_onecell_get, | |
568 | &adg->onecell); | |
dfc9403b KM |
569 | } |
570 | ||
e8dffe6c | 571 | rsnd_adg_get_clkout_end: |
b99258a3 KM |
572 | adg->ckr = ckr; |
573 | adg->rbga = rbga; | |
574 | adg->rbgb = rbgb; | |
eae6fff4 | 575 | |
2a46db4a KM |
576 | for_each_rsnd_clkout(clk, adg, i) |
577 | dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk)); | |
3e58690b | 578 | dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", |
eae6fff4 | 579 | ckr, rbga, rbgb); |
dfc9403b KM |
580 | } |
581 | ||
2ea6b074 | 582 | int rsnd_adg_probe(struct rsnd_priv *priv) |
dfc9403b KM |
583 | { |
584 | struct rsnd_adg *adg; | |
585 | struct device *dev = rsnd_priv_to_dev(priv); | |
56d2c61d | 586 | int ret; |
dfc9403b KM |
587 | |
588 | adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); | |
0d7820d0 | 589 | if (!adg) |
dfc9403b | 590 | return -ENOMEM; |
dfc9403b | 591 | |
56d2c61d | 592 | ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, |
5ba17b42 | 593 | NULL, NULL, 0, 0); |
56d2c61d WS |
594 | if (ret) |
595 | return ret; | |
1665a9e5 | 596 | |
248e88c2 | 597 | rsnd_adg_get_clkin(priv, adg); |
2a46db4a | 598 | rsnd_adg_get_clkout(priv, adg); |
dfc9403b KM |
599 | |
600 | priv->adg = adg; | |
601 | ||
c2d31718 KM |
602 | rsnd_adg_clk_enable(priv); |
603 | ||
dfc9403b KM |
604 | return 0; |
605 | } | |
68a55024 | 606 | |
2ea6b074 | 607 | void rsnd_adg_remove(struct rsnd_priv *priv) |
68a55024 | 608 | { |
b5aac5a9 KM |
609 | struct device *dev = rsnd_priv_to_dev(priv); |
610 | struct device_node *np = dev->of_node; | |
e3c6de48 KM |
611 | struct rsnd_adg *adg = priv->adg; |
612 | struct clk *clk; | |
613 | int i; | |
614 | ||
615 | for_each_rsnd_clkout(clk, adg, i) | |
616 | if (adg->clkout[i]) | |
617 | clk_unregister_fixed_rate(adg->clkout[i]); | |
b5aac5a9 KM |
618 | |
619 | of_clk_del_provider(np); | |
620 | ||
c2d31718 | 621 | rsnd_adg_clk_disable(priv); |
68a55024 | 622 | } |