Commit | Line | Data |
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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a4d7d550 | 19 | #include <sound/soc.h> |
a4d7d550 | 20 | #include <sound/sh_fsi.h> |
a4d7d550 | 21 | |
e8c8b631 KM |
22 | /* PortA/PortB register */ |
23 | #define REG_DO_FMT 0x0000 | |
24 | #define REG_DOFF_CTL 0x0004 | |
25 | #define REG_DOFF_ST 0x0008 | |
26 | #define REG_DI_FMT 0x000C | |
27 | #define REG_DIFF_CTL 0x0010 | |
28 | #define REG_DIFF_ST 0x0014 | |
29 | #define REG_CKG1 0x0018 | |
30 | #define REG_CKG2 0x001C | |
31 | #define REG_DIDT 0x0020 | |
32 | #define REG_DODT 0x0024 | |
33 | #define REG_MUTE_ST 0x0028 | |
34 | #define REG_OUT_SEL 0x0030 | |
cc780d38 | 35 | |
43fa95ca KM |
36 | /* master register */ |
37 | #define MST_CLK_RST 0x0210 | |
38 | #define MST_SOFT_RST 0x0214 | |
39 | #define MST_FIFO_SZ 0x0218 | |
40 | ||
41 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
42 | #define A_MST_CTLR 0x0180 |
43 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
44 | #define CPU_INT_ST 0x01F4 |
45 | #define CPU_IEMSK 0x01F8 | |
46 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
47 | #define INT_ST 0x0200 |
48 | #define IEMSK 0x0204 | |
49 | #define IMSK 0x0208 | |
a4d7d550 KM |
50 | |
51 | /* DO_FMT */ | |
52 | /* DI_FMT */ | |
f7d711e3 KM |
53 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
54 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
55 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
56 | ||
57 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
58 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
59 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
60 | ||
a7ffb52b KM |
61 | #define CR_MONO (0x0 << 4) |
62 | #define CR_MONO_D (0x1 << 4) | |
63 | #define CR_PCM (0x2 << 4) | |
64 | #define CR_I2S (0x3 << 4) | |
65 | #define CR_TDM (0x4 << 4) | |
66 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 KM |
67 | |
68 | /* DOFF_CTL */ | |
69 | /* DIFF_CTL */ | |
70 | #define IRQ_HALF 0x00100000 | |
71 | #define FIFO_CLR 0x00000001 | |
72 | ||
73 | /* DOFF_ST */ | |
74 | #define ERR_OVER 0x00000010 | |
75 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 76 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 77 | |
ccad7b44 KM |
78 | /* CKG1 */ |
79 | #define ACKMD_MASK 0x00007000 | |
80 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
81 | #define DIMD (1 << 4) |
82 | #define DOMD (1 << 0) | |
ccad7b44 | 83 | |
3bc28070 KM |
84 | /* A/B MST_CTLR */ |
85 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
86 | #define SE (1 << 0) /* Fix the master clock */ | |
87 | ||
a4d7d550 | 88 | /* CLK_RST */ |
1f5e2a31 KM |
89 | #define CRB (1 << 4) |
90 | #define CRA (1 << 0) | |
a4d7d550 | 91 | |
cf6edd00 KM |
92 | /* IO SHIFT / MACRO */ |
93 | #define BI_SHIFT 12 | |
94 | #define BO_SHIFT 8 | |
95 | #define AI_SHIFT 4 | |
96 | #define AO_SHIFT 0 | |
97 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 98 | |
feb58cff KM |
99 | /* SOFT_RST */ |
100 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
101 | #define PASR (1 << 8) /* Port A Software Reset */ | |
102 | #define IR (1 << 4) /* Interrupt Reset */ | |
103 | #define FSISR (1 << 0) /* Software Reset */ | |
104 | ||
f7d711e3 KM |
105 | /* OUT_SEL (FSI2) */ |
106 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
107 | /* 1: Biphase and serial */ | |
108 | ||
4a942b45 | 109 | /* FIFO_SZ */ |
cf6edd00 | 110 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 111 | |
a4d7d550 KM |
112 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
113 | ||
114 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
115 | ||
d7c5762b KM |
116 | typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable); |
117 | ||
5bfb9ad0 KM |
118 | /* |
119 | * FSI driver use below type name for variable | |
120 | * | |
5bfb9ad0 | 121 | * xxx_num : number of data |
2e651baf KM |
122 | * xxx_pos : position of data |
123 | * xxx_capa : capacity of data | |
124 | */ | |
125 | ||
126 | /* | |
127 | * period/frame/sample image | |
128 | * | |
129 | * ex) PCM (2ch) | |
130 | * | |
131 | * period pos period pos | |
132 | * [n] [n + 1] | |
133 | * |<-------------------- period--------------------->| | |
134 | * ==|============================================ ... =|== | |
135 | * | | | |
136 | * ||<----- frame ----->|<------ frame ----->| ... | | |
137 | * |+--------------------+--------------------+- ... | | |
138 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
139 | * |+--------------------+--------------------+- ... | | |
140 | * ==|============================================ ... =|== | |
141 | */ | |
142 | ||
143 | /* | |
144 | * FSI FIFO image | |
145 | * | |
146 | * | | | |
147 | * | | | |
148 | * | [ sample ] | | |
149 | * | [ sample ] | | |
150 | * | [ sample ] | | |
151 | * | [ sample ] | | |
152 | * --> go to codecs | |
5bfb9ad0 KM |
153 | */ |
154 | ||
c8fe2574 KM |
155 | /* |
156 | * struct | |
157 | */ | |
a4d7d550 | 158 | |
93193c2b | 159 | struct fsi_stream { |
a4d7d550 KM |
160 | struct snd_pcm_substream *substream; |
161 | ||
2e651baf KM |
162 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
163 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
164 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
165 | int period_samples; /* sample number / 1 period */ | |
166 | int period_pos; /* current period position */ | |
1ec9bc35 KM |
167 | |
168 | int uerr_num; | |
169 | int oerr_num; | |
93193c2b KM |
170 | }; |
171 | ||
172 | struct fsi_priv { | |
173 | void __iomem *base; | |
174 | struct fsi_master *master; | |
175 | ||
176 | struct fsi_stream playback; | |
177 | struct fsi_stream capture; | |
3bc28070 | 178 | |
9478e0b6 KM |
179 | u32 do_fmt; |
180 | u32 di_fmt; | |
181 | ||
6a9ebad8 KM |
182 | int chan_num:16; |
183 | int clk_master:1; | |
9478e0b6 | 184 | int spdif:1; |
6a9ebad8 | 185 | |
d4bc99b9 | 186 | long rate; |
106c79ec KM |
187 | |
188 | /* for suspend/resume */ | |
189 | u32 saved_do_fmt; | |
190 | u32 saved_di_fmt; | |
191 | u32 saved_ckg1; | |
192 | u32 saved_ckg2; | |
193 | u32 saved_out_sel; | |
a4d7d550 KM |
194 | }; |
195 | ||
73b92c1f KM |
196 | struct fsi_core { |
197 | int ver; | |
198 | ||
cc780d38 KM |
199 | u32 int_st; |
200 | u32 iemsk; | |
201 | u32 imsk; | |
2b0e7302 KM |
202 | u32 a_mclk; |
203 | u32 b_mclk; | |
cc780d38 KM |
204 | }; |
205 | ||
a4d7d550 KM |
206 | struct fsi_master { |
207 | void __iomem *base; | |
208 | int irq; | |
a4d7d550 KM |
209 | struct fsi_priv fsia; |
210 | struct fsi_priv fsib; | |
73b92c1f | 211 | struct fsi_core *core; |
a4d7d550 | 212 | struct sh_fsi_platform_info *info; |
8fc176d5 | 213 | spinlock_t lock; |
106c79ec KM |
214 | |
215 | /* for suspend/resume */ | |
216 | u32 saved_a_mclk; | |
217 | u32 saved_b_mclk; | |
218 | u32 saved_iemsk; | |
219 | u32 saved_imsk; | |
220 | u32 saved_clk_rst; | |
1f5e2a31 | 221 | u32 saved_soft_rst; |
a4d7d550 KM |
222 | }; |
223 | ||
c8fe2574 KM |
224 | /* |
225 | * basic read write function | |
226 | */ | |
a4d7d550 | 227 | |
0f69d978 | 228 | static void __fsi_reg_write(u32 reg, u32 data) |
a4d7d550 KM |
229 | { |
230 | /* valid data area is 24bit */ | |
231 | data &= 0x00ffffff; | |
232 | ||
0f69d978 | 233 | __raw_writel(data, reg); |
a4d7d550 KM |
234 | } |
235 | ||
236 | static u32 __fsi_reg_read(u32 reg) | |
237 | { | |
0f69d978 | 238 | return __raw_readl(reg); |
a4d7d550 KM |
239 | } |
240 | ||
0f69d978 | 241 | static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
242 | { |
243 | u32 val = __fsi_reg_read(reg); | |
244 | ||
245 | val &= ~mask; | |
246 | val |= data & mask; | |
247 | ||
0f69d978 | 248 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
249 | } |
250 | ||
e8c8b631 KM |
251 | #define fsi_reg_write(p, r, d)\ |
252 | __fsi_reg_write((u32)(p->base + REG_##r), d) | |
a4d7d550 | 253 | |
e8c8b631 KM |
254 | #define fsi_reg_read(p, r)\ |
255 | __fsi_reg_read((u32)(p->base + REG_##r)) | |
a4d7d550 | 256 | |
e8c8b631 KM |
257 | #define fsi_reg_mask_set(p, r, m, d)\ |
258 | __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d) | |
a4d7d550 | 259 | |
43fa95ca KM |
260 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
261 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
262 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 263 | { |
8fc176d5 KM |
264 | u32 ret; |
265 | unsigned long flags; | |
266 | ||
8fc176d5 KM |
267 | spin_lock_irqsave(&master->lock, flags); |
268 | ret = __fsi_reg_read((u32)(master->base + reg)); | |
269 | spin_unlock_irqrestore(&master->lock, flags); | |
270 | ||
271 | return ret; | |
a4d7d550 KM |
272 | } |
273 | ||
43fa95ca KM |
274 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
275 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
276 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 277 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 278 | { |
8fc176d5 KM |
279 | unsigned long flags; |
280 | ||
8fc176d5 | 281 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 282 | __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
8fc176d5 | 283 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
284 | } |
285 | ||
c8fe2574 KM |
286 | /* |
287 | * basic function | |
288 | */ | |
a4d7d550 | 289 | |
71f6e064 | 290 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 291 | { |
71f6e064 | 292 | return fsi->master; |
a4d7d550 KM |
293 | } |
294 | ||
6a9ebad8 KM |
295 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
296 | { | |
297 | return fsi->clk_master; | |
298 | } | |
299 | ||
a4d7d550 KM |
300 | static int fsi_is_port_a(struct fsi_priv *fsi) |
301 | { | |
71f6e064 KM |
302 | return fsi->master->base == fsi->base; |
303 | } | |
a4d7d550 | 304 | |
9478e0b6 KM |
305 | static int fsi_is_spdif(struct fsi_priv *fsi) |
306 | { | |
307 | return fsi->spdif; | |
308 | } | |
309 | ||
142e8174 | 310 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
311 | { |
312 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 313 | |
f0fba2ad | 314 | return rtd->cpu_dai; |
142e8174 KM |
315 | } |
316 | ||
0d032c19 | 317 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 318 | { |
f0fba2ad | 319 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 320 | |
f0fba2ad LG |
321 | if (dai->id == 0) |
322 | return &master->fsia; | |
323 | else | |
324 | return &master->fsib; | |
a4d7d550 KM |
325 | } |
326 | ||
0d032c19 KM |
327 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
328 | { | |
329 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
330 | } | |
331 | ||
d7c5762b KM |
332 | static set_rate_func fsi_get_info_set_rate(struct fsi_master *master) |
333 | { | |
334 | if (!master->info) | |
335 | return NULL; | |
336 | ||
337 | return master->info->set_rate; | |
338 | } | |
339 | ||
a4d7d550 KM |
340 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
341 | { | |
342 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 343 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 344 | |
d7c5762b KM |
345 | if (!master->info) |
346 | return 0; | |
347 | ||
a4d7d550 KM |
348 | return is_porta ? master->info->porta_flags : |
349 | master->info->portb_flags; | |
350 | } | |
351 | ||
93193c2b KM |
352 | static inline int fsi_stream_is_play(int stream) |
353 | { | |
354 | return stream == SNDRV_PCM_STREAM_PLAYBACK; | |
355 | } | |
356 | ||
00545785 KM |
357 | static inline int fsi_is_play(struct snd_pcm_substream *substream) |
358 | { | |
93193c2b KM |
359 | return fsi_stream_is_play(substream->stream); |
360 | } | |
361 | ||
362 | static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, | |
363 | int is_play) | |
364 | { | |
365 | return is_play ? &fsi->playback : &fsi->capture; | |
00545785 KM |
366 | } |
367 | ||
cf6edd00 | 368 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
369 | { |
370 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 371 | u32 shift; |
a4d7d550 KM |
372 | |
373 | if (is_porta) | |
cf6edd00 | 374 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 375 | else |
cf6edd00 | 376 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 377 | |
cf6edd00 | 378 | return shift; |
a4d7d550 KM |
379 | } |
380 | ||
2e651baf KM |
381 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
382 | { | |
383 | return frames * fsi->chan_num; | |
384 | } | |
385 | ||
386 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
387 | { | |
388 | return samples / fsi->chan_num; | |
389 | } | |
390 | ||
a4d7d550 | 391 | static void fsi_stream_push(struct fsi_priv *fsi, |
93193c2b | 392 | int is_play, |
0ffe296a | 393 | struct snd_pcm_substream *substream) |
a4d7d550 | 394 | { |
93193c2b | 395 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
0ffe296a | 396 | struct snd_pcm_runtime *runtime = substream->runtime; |
93193c2b KM |
397 | |
398 | io->substream = substream; | |
2e651baf KM |
399 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
400 | io->buff_sample_pos = 0; | |
401 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
402 | io->period_pos = 0; | |
1ec9bc35 KM |
403 | io->oerr_num = -1; /* ignore 1st err */ |
404 | io->uerr_num = -1; /* ignore 1st err */ | |
a4d7d550 KM |
405 | } |
406 | ||
93193c2b | 407 | static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 408 | { |
93193c2b | 409 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
1ec9bc35 KM |
410 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
411 | ||
412 | ||
413 | if (io->oerr_num > 0) | |
414 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
415 | ||
416 | if (io->uerr_num > 0) | |
417 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b KM |
418 | |
419 | io->substream = NULL; | |
2e651baf KM |
420 | io->buff_sample_capa = 0; |
421 | io->buff_sample_pos = 0; | |
422 | io->period_samples = 0; | |
423 | io->period_pos = 0; | |
1ec9bc35 KM |
424 | io->oerr_num = 0; |
425 | io->uerr_num = 0; | |
a4d7d550 KM |
426 | } |
427 | ||
2e651baf | 428 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
429 | { |
430 | u32 status; | |
2e651baf | 431 | int frames; |
a4d7d550 | 432 | |
e8c8b631 KM |
433 | status = is_play ? |
434 | fsi_reg_read(fsi, DOFF_ST) : | |
435 | fsi_reg_read(fsi, DIFF_ST); | |
436 | ||
2e651baf | 437 | frames = 0x1ff & (status >> 8); |
5bfb9ad0 | 438 | |
2e651baf | 439 | return fsi_frame2sample(fsi, frames); |
cca1b235 KM |
440 | } |
441 | ||
1ec9bc35 KM |
442 | static void fsi_count_fifo_err(struct fsi_priv *fsi) |
443 | { | |
444 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
445 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
446 | ||
447 | if (ostatus & ERR_OVER) | |
448 | fsi->playback.oerr_num++; | |
449 | ||
450 | if (ostatus & ERR_UNDER) | |
451 | fsi->playback.uerr_num++; | |
452 | ||
453 | if (istatus & ERR_OVER) | |
454 | fsi->capture.oerr_num++; | |
455 | ||
456 | if (istatus & ERR_UNDER) | |
457 | fsi->capture.uerr_num++; | |
458 | ||
459 | fsi_reg_write(fsi, DOFF_ST, 0); | |
460 | fsi_reg_write(fsi, DIFF_ST, 0); | |
461 | } | |
462 | ||
b9fde18c KM |
463 | /* |
464 | * dma function | |
465 | */ | |
466 | ||
93193c2b | 467 | static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) |
c79eab3e | 468 | { |
93193c2b KM |
469 | int is_play = fsi_stream_is_play(stream); |
470 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
2e651baf | 471 | struct snd_pcm_runtime *runtime = io->substream->runtime; |
93193c2b | 472 | |
2e651baf KM |
473 | return runtime->dma_area + |
474 | samples_to_bytes(runtime, io->buff_sample_pos); | |
c79eab3e KM |
475 | } |
476 | ||
5bfb9ad0 | 477 | static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
478 | { |
479 | u16 *start; | |
480 | int i; | |
481 | ||
93193c2b | 482 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
b9fde18c | 483 | |
5bfb9ad0 | 484 | for (i = 0; i < num; i++) |
b9fde18c KM |
485 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
486 | } | |
487 | ||
5bfb9ad0 | 488 | static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
489 | { |
490 | u16 *start; | |
491 | int i; | |
492 | ||
93193c2b KM |
493 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
494 | ||
b9fde18c | 495 | |
5bfb9ad0 | 496 | for (i = 0; i < num; i++) |
b9fde18c KM |
497 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
498 | } | |
499 | ||
5bfb9ad0 | 500 | static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
501 | { |
502 | u32 *start; | |
503 | int i; | |
504 | ||
93193c2b KM |
505 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
506 | ||
b9fde18c | 507 | |
5bfb9ad0 | 508 | for (i = 0; i < num; i++) |
b9fde18c KM |
509 | fsi_reg_write(fsi, DODT, *(start + i)); |
510 | } | |
511 | ||
5bfb9ad0 | 512 | static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
513 | { |
514 | u32 *start; | |
515 | int i; | |
516 | ||
93193c2b | 517 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
b9fde18c | 518 | |
5bfb9ad0 | 519 | for (i = 0; i < num; i++) |
b9fde18c KM |
520 | *(start + i) = fsi_reg_read(fsi, DIDT); |
521 | } | |
522 | ||
c8fe2574 KM |
523 | /* |
524 | * irq function | |
525 | */ | |
a4d7d550 | 526 | |
a4d7d550 KM |
527 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
528 | { | |
cf6edd00 | 529 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 530 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 531 | |
43fa95ca KM |
532 | fsi_core_mask_set(master, imsk, data, data); |
533 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
534 | } |
535 | ||
536 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
537 | { | |
cf6edd00 | 538 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 539 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 540 | |
43fa95ca KM |
541 | fsi_core_mask_set(master, imsk, data, 0); |
542 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
543 | } |
544 | ||
10ea76cc KM |
545 | static u32 fsi_irq_get_status(struct fsi_master *master) |
546 | { | |
43fa95ca | 547 | return fsi_core_read(master, int_st); |
10ea76cc KM |
548 | } |
549 | ||
10ea76cc KM |
550 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
551 | { | |
552 | u32 data = 0; | |
553 | struct fsi_master *master = fsi_get_master(fsi); | |
554 | ||
cf6edd00 KM |
555 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
556 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
557 | |
558 | /* clear interrupt factor */ | |
43fa95ca | 559 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
560 | } |
561 | ||
c8fe2574 KM |
562 | /* |
563 | * SPDIF master clock function | |
564 | * | |
565 | * These functions are used later FSI2 | |
566 | */ | |
3bc28070 KM |
567 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
568 | { | |
569 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 570 | u32 mask, val; |
3bc28070 KM |
571 | |
572 | if (master->core->ver < 2) { | |
573 | pr_err("fsi: register access err (%s)\n", __func__); | |
574 | return; | |
575 | } | |
576 | ||
2b0e7302 KM |
577 | mask = BP | SE; |
578 | val = enable ? mask : 0; | |
579 | ||
580 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
581 | fsi_core_mask_set(master, a_mclk, mask, val) : |
582 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
583 | } |
584 | ||
c8fe2574 | 585 | /* |
1f5e2a31 | 586 | * clock function |
c8fe2574 | 587 | */ |
4f56cde1 KM |
588 | static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi, |
589 | long rate, int enable) | |
590 | { | |
591 | struct fsi_master *master = fsi_get_master(fsi); | |
592 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
593 | int fsi_ver = master->core->ver; | |
594 | int ret; | |
595 | ||
596 | ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable); | |
597 | if (ret < 0) /* error */ | |
598 | return ret; | |
599 | ||
600 | if (!enable) | |
601 | return 0; | |
602 | ||
603 | if (ret > 0) { | |
604 | u32 data = 0; | |
605 | ||
606 | switch (ret & SH_FSI_ACKMD_MASK) { | |
607 | default: | |
608 | /* FALL THROUGH */ | |
609 | case SH_FSI_ACKMD_512: | |
610 | data |= (0x0 << 12); | |
611 | break; | |
612 | case SH_FSI_ACKMD_256: | |
613 | data |= (0x1 << 12); | |
614 | break; | |
615 | case SH_FSI_ACKMD_128: | |
616 | data |= (0x2 << 12); | |
617 | break; | |
618 | case SH_FSI_ACKMD_64: | |
619 | data |= (0x3 << 12); | |
620 | break; | |
621 | case SH_FSI_ACKMD_32: | |
622 | if (fsi_ver < 2) | |
623 | dev_err(dev, "unsupported ACKMD\n"); | |
624 | else | |
625 | data |= (0x4 << 12); | |
626 | break; | |
627 | } | |
628 | ||
629 | switch (ret & SH_FSI_BPFMD_MASK) { | |
630 | default: | |
631 | /* FALL THROUGH */ | |
632 | case SH_FSI_BPFMD_32: | |
633 | data |= (0x0 << 8); | |
634 | break; | |
635 | case SH_FSI_BPFMD_64: | |
636 | data |= (0x1 << 8); | |
637 | break; | |
638 | case SH_FSI_BPFMD_128: | |
639 | data |= (0x2 << 8); | |
640 | break; | |
641 | case SH_FSI_BPFMD_256: | |
642 | data |= (0x3 << 8); | |
643 | break; | |
644 | case SH_FSI_BPFMD_512: | |
645 | data |= (0x4 << 8); | |
646 | break; | |
647 | case SH_FSI_BPFMD_16: | |
648 | if (fsi_ver < 2) | |
649 | dev_err(dev, "unsupported ACKMD\n"); | |
650 | else | |
651 | data |= (0x7 << 8); | |
652 | break; | |
653 | } | |
654 | ||
655 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
656 | udelay(10); | |
657 | ret = 0; | |
658 | } | |
659 | ||
660 | return ret; | |
661 | ||
662 | } | |
663 | ||
1f5e2a31 KM |
664 | #define fsi_module_init(m, d) __fsi_module_clk_ctrl(m, d, 1) |
665 | #define fsi_module_kill(m, d) __fsi_module_clk_ctrl(m, d, 0) | |
666 | static void __fsi_module_clk_ctrl(struct fsi_master *master, | |
667 | struct device *dev, | |
668 | int enable) | |
669 | { | |
670 | pm_runtime_get_sync(dev); | |
671 | ||
672 | if (enable) { | |
673 | /* enable only SR */ | |
674 | fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); | |
675 | fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); | |
676 | } else { | |
677 | /* clear all registers */ | |
678 | fsi_master_mask_set(master, SOFT_RST, FSISR, 0); | |
679 | } | |
680 | ||
681 | pm_runtime_put_sync(dev); | |
682 | } | |
10ea76cc | 683 | |
1ddddd36 KM |
684 | #define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1) |
685 | #define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0) | |
686 | static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable) | |
a4d7d550 | 687 | { |
71f6e064 | 688 | struct fsi_master *master = fsi_get_master(fsi); |
1f5e2a31 KM |
689 | u32 soft = fsi_is_port_a(fsi) ? PASR : PBSR; |
690 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; | |
691 | int is_master = fsi_is_clk_master(fsi); | |
a4d7d550 | 692 | |
1ddddd36 KM |
693 | if (enable) |
694 | fsi_irq_enable(fsi, is_play); | |
695 | else | |
696 | fsi_irq_disable(fsi, is_play); | |
697 | ||
1f5e2a31 KM |
698 | fsi_master_mask_set(master, SOFT_RST, soft, (enable) ? soft : 0); |
699 | if (is_master) | |
700 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); | |
a4d7d550 KM |
701 | } |
702 | ||
1f5e2a31 KM |
703 | /* |
704 | * ctrl function | |
705 | */ | |
4a942b45 KM |
706 | static void fsi_fifo_init(struct fsi_priv *fsi, |
707 | int is_play, | |
708 | struct snd_soc_dai *dai) | |
a4d7d550 | 709 | { |
4a942b45 | 710 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b | 711 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
e8c8b631 | 712 | u32 shift, i; |
2e651baf | 713 | int frame_capa; |
a4d7d550 | 714 | |
4a942b45 KM |
715 | /* get on-chip RAM capacity */ |
716 | shift = fsi_master_read(master, FIFO_SZ); | |
cf6edd00 KM |
717 | shift >>= fsi_get_port_shift(fsi, is_play); |
718 | shift &= FIFO_SZ_MASK; | |
2e651baf KM |
719 | frame_capa = 256 << shift; |
720 | dev_dbg(dai->dev, "fifo = %d words\n", frame_capa); | |
a4d7d550 | 721 | |
4a942b45 KM |
722 | /* |
723 | * The maximum number of sample data varies depending | |
724 | * on the number of channels selected for the format. | |
725 | * | |
726 | * FIFOs are used in 4-channel units in 3-channel mode | |
727 | * and in 8-channel units in 5- to 7-channel mode | |
728 | * meaning that more FIFOs than the required size of DPRAM | |
729 | * are used. | |
730 | * | |
731 | * ex) if 256 words of DP-RAM is connected | |
732 | * 1 channel: 256 (256 x 1 = 256) | |
733 | * 2 channels: 128 (128 x 2 = 256) | |
734 | * 3 channels: 64 ( 64 x 3 = 192) | |
735 | * 4 channels: 64 ( 64 x 4 = 256) | |
736 | * 5 channels: 32 ( 32 x 5 = 160) | |
737 | * 6 channels: 32 ( 32 x 6 = 192) | |
738 | * 7 channels: 32 ( 32 x 7 = 224) | |
739 | * 8 channels: 32 ( 32 x 8 = 256) | |
740 | */ | |
160afa7f | 741 | for (i = 1; i < fsi->chan_num; i <<= 1) |
2e651baf | 742 | frame_capa >>= 1; |
5bfb9ad0 | 743 | dev_dbg(dai->dev, "%d channel %d store\n", |
2e651baf KM |
744 | fsi->chan_num, frame_capa); |
745 | ||
746 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
a4d7d550 | 747 | |
e8c8b631 KM |
748 | /* |
749 | * set interrupt generation factor | |
750 | * clear FIFO | |
751 | */ | |
752 | if (is_play) { | |
753 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
754 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
755 | } else { | |
756 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
757 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
758 | } | |
a4d7d550 KM |
759 | } |
760 | ||
1ec9bc35 | 761 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream) |
a4d7d550 KM |
762 | { |
763 | struct snd_pcm_runtime *runtime; | |
764 | struct snd_pcm_substream *substream = NULL; | |
93193c2b KM |
765 | int is_play = fsi_stream_is_play(stream); |
766 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
2e651baf KM |
767 | int sample_residues; |
768 | int sample_width; | |
769 | int samples; | |
770 | int samples_max; | |
b9fde18c | 771 | int over_period; |
d8b33534 | 772 | void (*fn)(struct fsi_priv *fsi, int size); |
a4d7d550 KM |
773 | |
774 | if (!fsi || | |
93193c2b KM |
775 | !io->substream || |
776 | !io->substream->runtime) | |
a4d7d550 KM |
777 | return -EINVAL; |
778 | ||
1c418d1f | 779 | over_period = 0; |
93193c2b | 780 | substream = io->substream; |
1c418d1f | 781 | runtime = substream->runtime; |
a4d7d550 KM |
782 | |
783 | /* FSI FIFO has limit. | |
784 | * So, this driver can not send periods data at a time | |
785 | */ | |
2e651baf KM |
786 | if (io->buff_sample_pos >= |
787 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 788 | |
1c418d1f | 789 | over_period = 1; |
2e651baf | 790 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 791 | |
2e651baf KM |
792 | if (0 == io->period_pos) |
793 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
794 | } |
795 | ||
2e651baf KM |
796 | /* get 1 sample data width */ |
797 | sample_width = samples_to_bytes(runtime, 1); | |
a4d7d550 | 798 | |
2e651baf KM |
799 | /* get number of residue samples */ |
800 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
d8b33534 KM |
801 | |
802 | if (is_play) { | |
803 | /* | |
804 | * for play-back | |
805 | * | |
2e651baf KM |
806 | * samples_max : number of FSI fifo free samples space |
807 | * samples : number of ALSA residue samples | |
d8b33534 | 808 | */ |
2e651baf KM |
809 | samples_max = io->fifo_sample_capa; |
810 | samples_max -= fsi_get_current_fifo_samples(fsi, is_play); | |
d8b33534 | 811 | |
2e651baf | 812 | samples = sample_residues; |
d8b33534 | 813 | |
2e651baf | 814 | switch (sample_width) { |
d8b33534 KM |
815 | case 2: |
816 | fn = fsi_dma_soft_push16; | |
817 | break; | |
818 | case 4: | |
819 | fn = fsi_dma_soft_push32; | |
820 | break; | |
821 | default: | |
822 | return -EINVAL; | |
823 | } | |
824 | } else { | |
825 | /* | |
826 | * for capture | |
827 | * | |
2e651baf KM |
828 | * samples_max : number of ALSA free samples space |
829 | * samples : number of samples in FSI fifo | |
d8b33534 | 830 | */ |
2e651baf KM |
831 | samples_max = sample_residues; |
832 | samples = fsi_get_current_fifo_samples(fsi, is_play); | |
d8b33534 | 833 | |
2e651baf | 834 | switch (sample_width) { |
d8b33534 KM |
835 | case 2: |
836 | fn = fsi_dma_soft_pop16; | |
837 | break; | |
838 | case 4: | |
839 | fn = fsi_dma_soft_pop32; | |
840 | break; | |
841 | default: | |
842 | return -EINVAL; | |
843 | } | |
844 | } | |
a4d7d550 | 845 | |
2e651baf | 846 | samples = min(samples, samples_max); |
a4d7d550 | 847 | |
2e651baf | 848 | fn(fsi, samples); |
a4d7d550 | 849 | |
2e651baf KM |
850 | /* update buff_sample_pos */ |
851 | io->buff_sample_pos += samples; | |
a4d7d550 | 852 | |
1c418d1f | 853 | if (over_period) |
a4d7d550 KM |
854 | snd_pcm_period_elapsed(substream); |
855 | ||
47fc9a0a | 856 | return 0; |
a4d7d550 KM |
857 | } |
858 | ||
1ec9bc35 | 859 | static int fsi_data_pop(struct fsi_priv *fsi) |
07102f3c | 860 | { |
1ec9bc35 | 861 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE); |
d8b33534 | 862 | } |
07102f3c | 863 | |
1ec9bc35 | 864 | static int fsi_data_push(struct fsi_priv *fsi) |
d8b33534 | 865 | { |
1ec9bc35 | 866 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
07102f3c KM |
867 | } |
868 | ||
a4d7d550 KM |
869 | static irqreturn_t fsi_interrupt(int irq, void *data) |
870 | { | |
71f6e064 | 871 | struct fsi_master *master = data; |
10ea76cc | 872 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
873 | |
874 | /* clear irq status */ | |
feb58cff KM |
875 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
876 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 877 | |
cf6edd00 | 878 | if (int_st & AB_IO(1, AO_SHIFT)) |
1ec9bc35 | 879 | fsi_data_push(&master->fsia); |
cf6edd00 | 880 | if (int_st & AB_IO(1, BO_SHIFT)) |
1ec9bc35 | 881 | fsi_data_push(&master->fsib); |
cf6edd00 | 882 | if (int_st & AB_IO(1, AI_SHIFT)) |
1ec9bc35 | 883 | fsi_data_pop(&master->fsia); |
cf6edd00 | 884 | if (int_st & AB_IO(1, BI_SHIFT)) |
1ec9bc35 KM |
885 | fsi_data_pop(&master->fsib); |
886 | ||
887 | fsi_count_fifo_err(&master->fsia); | |
888 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 889 | |
48d78e58 KM |
890 | fsi_irq_clear_status(&master->fsia); |
891 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
892 | |
893 | return IRQ_HANDLED; | |
894 | } | |
895 | ||
c8fe2574 KM |
896 | /* |
897 | * dai ops | |
898 | */ | |
a4d7d550 | 899 | |
a4d7d550 KM |
900 | static int fsi_dai_startup(struct snd_pcm_substream *substream, |
901 | struct snd_soc_dai *dai) | |
902 | { | |
71f6e064 | 903 | struct fsi_priv *fsi = fsi_get_priv(substream); |
93193c2b | 904 | u32 flags = fsi_get_info_flags(fsi); |
9478e0b6 | 905 | u32 data = 0; |
00545785 | 906 | int is_play = fsi_is_play(substream); |
a4d7d550 | 907 | |
785d1c45 | 908 | pm_runtime_get_sync(dai->dev); |
a4d7d550 | 909 | |
9478e0b6 KM |
910 | /* clock setting */ |
911 | if (fsi_is_clk_master(fsi)) | |
912 | data = DIMD | DOMD; | |
913 | ||
914 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
915 | |
916 | /* clock inversion (CKG2) */ | |
917 | data = 0; | |
b427b44c KM |
918 | if (SH_FSI_LRM_INV & flags) |
919 | data |= 1 << 12; | |
920 | if (SH_FSI_BRM_INV & flags) | |
921 | data |= 1 << 8; | |
922 | if (SH_FSI_LRS_INV & flags) | |
923 | data |= 1 << 4; | |
924 | if (SH_FSI_BRS_INV & flags) | |
925 | data |= 1 << 0; | |
926 | ||
a4d7d550 KM |
927 | fsi_reg_write(fsi, CKG2, data); |
928 | ||
9478e0b6 KM |
929 | /* set format */ |
930 | fsi_reg_write(fsi, DO_FMT, fsi->do_fmt); | |
931 | fsi_reg_write(fsi, DI_FMT, fsi->di_fmt); | |
932 | ||
933 | /* spdif ? */ | |
934 | if (fsi_is_spdif(fsi)) { | |
935 | fsi_spdif_clk_ctrl(fsi, 1); | |
936 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
937 | } | |
938 | ||
10ea76cc KM |
939 | /* irq clear */ |
940 | fsi_irq_disable(fsi, is_play); | |
941 | fsi_irq_clear_status(fsi); | |
942 | ||
943 | /* fifo init */ | |
4a942b45 | 944 | fsi_fifo_init(fsi, is_play, dai); |
a4d7d550 | 945 | |
a68a3b4e | 946 | return 0; |
a4d7d550 KM |
947 | } |
948 | ||
949 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
950 | struct snd_soc_dai *dai) | |
951 | { | |
71f6e064 | 952 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 953 | |
1f5e2a31 | 954 | if (fsi_is_clk_master(fsi)) |
4f56cde1 | 955 | fsi_set_master_clk(dai->dev, fsi, fsi->rate, 0); |
6a9ebad8 | 956 | |
d4bc99b9 KM |
957 | fsi->rate = 0; |
958 | ||
785d1c45 | 959 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
960 | } |
961 | ||
962 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
963 | struct snd_soc_dai *dai) | |
964 | { | |
71f6e064 | 965 | struct fsi_priv *fsi = fsi_get_priv(substream); |
00545785 | 966 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
967 | int ret = 0; |
968 | ||
a4d7d550 KM |
969 | switch (cmd) { |
970 | case SNDRV_PCM_TRIGGER_START: | |
0ffe296a | 971 | fsi_stream_push(fsi, is_play, substream); |
1ec9bc35 | 972 | ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); |
1ddddd36 | 973 | fsi_port_start(fsi, is_play); |
a4d7d550 KM |
974 | break; |
975 | case SNDRV_PCM_TRIGGER_STOP: | |
1ddddd36 | 976 | fsi_port_stop(fsi, is_play); |
93193c2b | 977 | fsi_stream_pop(fsi, is_play); |
a4d7d550 KM |
978 | break; |
979 | } | |
980 | ||
981 | return ret; | |
982 | } | |
983 | ||
f17c13ca KM |
984 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
985 | { | |
986 | u32 data = 0; | |
987 | ||
988 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
989 | case SND_SOC_DAIFMT_I2S: | |
990 | data = CR_I2S; | |
991 | fsi->chan_num = 2; | |
992 | break; | |
993 | case SND_SOC_DAIFMT_LEFT_J: | |
994 | data = CR_PCM; | |
995 | fsi->chan_num = 2; | |
996 | break; | |
997 | default: | |
998 | return -EINVAL; | |
999 | } | |
1000 | ||
9478e0b6 KM |
1001 | fsi->do_fmt = data; |
1002 | fsi->di_fmt = data; | |
f17c13ca KM |
1003 | |
1004 | return 0; | |
1005 | } | |
1006 | ||
1007 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1008 | { | |
1009 | struct fsi_master *master = fsi_get_master(fsi); | |
1010 | u32 data = 0; | |
1011 | ||
1012 | if (master->core->ver < 2) | |
1013 | return -EINVAL; | |
1014 | ||
1015 | data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM; | |
1016 | fsi->chan_num = 2; | |
9478e0b6 | 1017 | fsi->spdif = 1; |
f17c13ca | 1018 | |
9478e0b6 KM |
1019 | fsi->do_fmt = data; |
1020 | fsi->di_fmt = data; | |
f17c13ca KM |
1021 | |
1022 | return 0; | |
1023 | } | |
1024 | ||
4d805f7b KM |
1025 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1026 | { | |
1027 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
6a9ebad8 KM |
1028 | struct fsi_master *master = fsi_get_master(fsi); |
1029 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
f17c13ca | 1030 | u32 flags = fsi_get_info_flags(fsi); |
4d805f7b KM |
1031 | int ret; |
1032 | ||
4d805f7b KM |
1033 | /* set master/slave audio interface */ |
1034 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1035 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1036 | fsi->clk_master = 1; |
4d805f7b KM |
1037 | break; |
1038 | case SND_SOC_DAIFMT_CBS_CFS: | |
1039 | break; | |
1040 | default: | |
9478e0b6 | 1041 | return -EINVAL; |
4d805f7b | 1042 | } |
6a9ebad8 KM |
1043 | |
1044 | if (fsi_is_clk_master(fsi) && !set_rate) { | |
1045 | dev_err(dai->dev, "platform doesn't have set_rate\n"); | |
9478e0b6 | 1046 | return -EINVAL; |
6a9ebad8 KM |
1047 | } |
1048 | ||
f17c13ca KM |
1049 | /* set format */ |
1050 | switch (flags & SH_FSI_FMT_MASK) { | |
1051 | case SH_FSI_FMT_DAI: | |
1052 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1053 | break; | |
1054 | case SH_FSI_FMT_SPDIF: | |
1055 | ret = fsi_set_fmt_spdif(fsi); | |
1056 | break; | |
1057 | default: | |
1058 | ret = -EINVAL; | |
1059 | } | |
4d805f7b | 1060 | |
4d805f7b KM |
1061 | return ret; |
1062 | } | |
1063 | ||
ccad7b44 KM |
1064 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1065 | struct snd_pcm_hw_params *params, | |
1066 | struct snd_soc_dai *dai) | |
1067 | { | |
1068 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
d4bc99b9 | 1069 | long rate = params_rate(params); |
ccad7b44 KM |
1070 | int ret; |
1071 | ||
6a9ebad8 | 1072 | if (!fsi_is_clk_master(fsi)) |
ccad7b44 KM |
1073 | return 0; |
1074 | ||
4f56cde1 KM |
1075 | ret = fsi_set_master_clk(dai->dev, fsi, rate, 1); |
1076 | if (ret < 0) | |
d4bc99b9 | 1077 | return ret; |
ccad7b44 | 1078 | |
d4bc99b9 | 1079 | fsi->rate = rate; |
ccad7b44 KM |
1080 | |
1081 | return ret; | |
ccad7b44 KM |
1082 | } |
1083 | ||
a4d7d550 KM |
1084 | static struct snd_soc_dai_ops fsi_dai_ops = { |
1085 | .startup = fsi_dai_startup, | |
1086 | .shutdown = fsi_dai_shutdown, | |
1087 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1088 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1089 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1090 | }; |
1091 | ||
c8fe2574 KM |
1092 | /* |
1093 | * pcm ops | |
1094 | */ | |
a4d7d550 | 1095 | |
a4d7d550 KM |
1096 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1097 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1098 | SNDRV_PCM_INFO_MMAP | | |
1099 | SNDRV_PCM_INFO_MMAP_VALID | | |
1100 | SNDRV_PCM_INFO_PAUSE, | |
1101 | .formats = FSI_FMTS, | |
1102 | .rates = FSI_RATES, | |
1103 | .rate_min = 8000, | |
1104 | .rate_max = 192000, | |
1105 | .channels_min = 1, | |
1106 | .channels_max = 2, | |
1107 | .buffer_bytes_max = 64 * 1024, | |
1108 | .period_bytes_min = 32, | |
1109 | .period_bytes_max = 8192, | |
1110 | .periods_min = 1, | |
1111 | .periods_max = 32, | |
1112 | .fifo_size = 256, | |
1113 | }; | |
1114 | ||
1115 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1116 | { | |
1117 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1118 | int ret = 0; | |
1119 | ||
1120 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1121 | ||
1122 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1123 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1124 | ||
1125 | return ret; | |
1126 | } | |
1127 | ||
1128 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1129 | struct snd_pcm_hw_params *hw_params) | |
1130 | { | |
1131 | return snd_pcm_lib_malloc_pages(substream, | |
1132 | params_buffer_bytes(hw_params)); | |
1133 | } | |
1134 | ||
1135 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1136 | { | |
1137 | return snd_pcm_lib_free_pages(substream); | |
1138 | } | |
1139 | ||
1140 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1141 | { | |
71f6e064 | 1142 | struct fsi_priv *fsi = fsi_get_priv(substream); |
93193c2b | 1143 | struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream)); |
2e651baf | 1144 | int samples_pos = io->buff_sample_pos - 1; |
a4d7d550 | 1145 | |
2e651baf KM |
1146 | if (samples_pos < 0) |
1147 | samples_pos = 0; | |
a4d7d550 | 1148 | |
2e651baf | 1149 | return fsi_sample2frame(fsi, samples_pos); |
a4d7d550 KM |
1150 | } |
1151 | ||
1152 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1153 | .open = fsi_pcm_open, | |
1154 | .ioctl = snd_pcm_lib_ioctl, | |
1155 | .hw_params = fsi_hw_params, | |
1156 | .hw_free = fsi_hw_free, | |
1157 | .pointer = fsi_pointer, | |
1158 | }; | |
1159 | ||
c8fe2574 KM |
1160 | /* |
1161 | * snd_soc_platform | |
1162 | */ | |
a4d7d550 | 1163 | |
a4d7d550 KM |
1164 | #define PREALLOC_BUFFER (32 * 1024) |
1165 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1166 | ||
1167 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1168 | { | |
1169 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1170 | } | |
1171 | ||
1172 | static int fsi_pcm_new(struct snd_card *card, | |
1173 | struct snd_soc_dai *dai, | |
1174 | struct snd_pcm *pcm) | |
1175 | { | |
1176 | /* | |
1177 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1178 | * in MMAP mode (i.e. aplay -M) | |
1179 | */ | |
1180 | return snd_pcm_lib_preallocate_pages_for_all( | |
1181 | pcm, | |
1182 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1183 | snd_dma_continuous_data(GFP_KERNEL), | |
1184 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1185 | } | |
1186 | ||
c8fe2574 KM |
1187 | /* |
1188 | * alsa struct | |
1189 | */ | |
a4d7d550 | 1190 | |
f0fba2ad | 1191 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1192 | { |
f0fba2ad | 1193 | .name = "fsia-dai", |
a4d7d550 KM |
1194 | .playback = { |
1195 | .rates = FSI_RATES, | |
1196 | .formats = FSI_FMTS, | |
1197 | .channels_min = 1, | |
1198 | .channels_max = 8, | |
1199 | }, | |
07102f3c KM |
1200 | .capture = { |
1201 | .rates = FSI_RATES, | |
1202 | .formats = FSI_FMTS, | |
1203 | .channels_min = 1, | |
1204 | .channels_max = 8, | |
1205 | }, | |
a4d7d550 KM |
1206 | .ops = &fsi_dai_ops, |
1207 | }, | |
1208 | { | |
f0fba2ad | 1209 | .name = "fsib-dai", |
a4d7d550 KM |
1210 | .playback = { |
1211 | .rates = FSI_RATES, | |
1212 | .formats = FSI_FMTS, | |
1213 | .channels_min = 1, | |
1214 | .channels_max = 8, | |
1215 | }, | |
07102f3c KM |
1216 | .capture = { |
1217 | .rates = FSI_RATES, | |
1218 | .formats = FSI_FMTS, | |
1219 | .channels_min = 1, | |
1220 | .channels_max = 8, | |
1221 | }, | |
a4d7d550 KM |
1222 | .ops = &fsi_dai_ops, |
1223 | }, | |
1224 | }; | |
a4d7d550 | 1225 | |
f0fba2ad LG |
1226 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1227 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1228 | .pcm_new = fsi_pcm_new, |
1229 | .pcm_free = fsi_pcm_free, | |
1230 | }; | |
a4d7d550 | 1231 | |
c8fe2574 KM |
1232 | /* |
1233 | * platform function | |
1234 | */ | |
a4d7d550 | 1235 | |
a4d7d550 KM |
1236 | static int fsi_probe(struct platform_device *pdev) |
1237 | { | |
71f6e064 | 1238 | struct fsi_master *master; |
cc780d38 | 1239 | const struct platform_device_id *id_entry; |
a4d7d550 | 1240 | struct resource *res; |
a4d7d550 KM |
1241 | unsigned int irq; |
1242 | int ret; | |
1243 | ||
cc780d38 KM |
1244 | id_entry = pdev->id_entry; |
1245 | if (!id_entry) { | |
1246 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1247 | return -ENODEV; | |
1248 | } | |
1249 | ||
a4d7d550 KM |
1250 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1251 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1252 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1253 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1254 | ret = -ENODEV; | |
1255 | goto exit; | |
1256 | } | |
1257 | ||
1258 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1259 | if (!master) { | |
1260 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1261 | ret = -ENOMEM; | |
1262 | goto exit; | |
1263 | } | |
1264 | ||
1265 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1266 | if (!master->base) { | |
1267 | ret = -ENXIO; | |
1268 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1269 | goto exit_kfree; | |
1270 | } | |
1271 | ||
3bc28070 | 1272 | /* master setting */ |
a4d7d550 KM |
1273 | master->irq = irq; |
1274 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1275 | master->core = (struct fsi_core *)id_entry->driver_data; |
1276 | spin_lock_init(&master->lock); | |
1277 | ||
1278 | /* FSI A setting */ | |
a4d7d550 | 1279 | master->fsia.base = master->base; |
71f6e064 | 1280 | master->fsia.master = master; |
3bc28070 KM |
1281 | |
1282 | /* FSI B setting */ | |
a4d7d550 | 1283 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1284 | master->fsib.master = master; |
a4d7d550 | 1285 | |
785d1c45 | 1286 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 1287 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1288 | |
1f5e2a31 | 1289 | fsi_module_init(master, &pdev->dev); |
a4d7d550 | 1290 | |
cc780d38 KM |
1291 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, |
1292 | id_entry->name, master); | |
a4d7d550 KM |
1293 | if (ret) { |
1294 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1295 | goto exit_iounmap; |
a4d7d550 KM |
1296 | } |
1297 | ||
f0fba2ad | 1298 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1299 | if (ret < 0) { |
1300 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1301 | goto exit_free_irq; | |
1302 | } | |
1303 | ||
0b5ec87d KM |
1304 | ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, |
1305 | ARRAY_SIZE(fsi_soc_dai)); | |
1306 | if (ret < 0) { | |
1307 | dev_err(&pdev->dev, "cannot snd dai register\n"); | |
1308 | goto exit_snd_soc; | |
1309 | } | |
a4d7d550 | 1310 | |
0b5ec87d KM |
1311 | return ret; |
1312 | ||
1313 | exit_snd_soc: | |
1314 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1315 | exit_free_irq: |
1316 | free_irq(irq, master); | |
a4d7d550 KM |
1317 | exit_iounmap: |
1318 | iounmap(master->base); | |
785d1c45 | 1319 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1320 | exit_kfree: |
1321 | kfree(master); | |
1322 | master = NULL; | |
1323 | exit: | |
1324 | return ret; | |
1325 | } | |
1326 | ||
1327 | static int fsi_remove(struct platform_device *pdev) | |
1328 | { | |
71f6e064 KM |
1329 | struct fsi_master *master; |
1330 | ||
f0fba2ad | 1331 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1332 | |
1f5e2a31 KM |
1333 | fsi_module_kill(master, &pdev->dev); |
1334 | ||
d985f27e | 1335 | free_irq(master->irq, master); |
785d1c45 | 1336 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1337 | |
d985f27e KM |
1338 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1339 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1340 | |
1341 | iounmap(master->base); | |
1342 | kfree(master); | |
71f6e064 | 1343 | |
a4d7d550 KM |
1344 | return 0; |
1345 | } | |
1346 | ||
106c79ec | 1347 | static void __fsi_suspend(struct fsi_priv *fsi, |
4f56cde1 | 1348 | struct device *dev) |
106c79ec KM |
1349 | { |
1350 | fsi->saved_do_fmt = fsi_reg_read(fsi, DO_FMT); | |
1351 | fsi->saved_di_fmt = fsi_reg_read(fsi, DI_FMT); | |
1352 | fsi->saved_ckg1 = fsi_reg_read(fsi, CKG1); | |
1353 | fsi->saved_ckg2 = fsi_reg_read(fsi, CKG2); | |
1354 | fsi->saved_out_sel = fsi_reg_read(fsi, OUT_SEL); | |
1355 | ||
1356 | if (fsi_is_clk_master(fsi)) | |
4f56cde1 | 1357 | fsi_set_master_clk(dev, fsi, fsi->rate, 0); |
106c79ec KM |
1358 | } |
1359 | ||
1360 | static void __fsi_resume(struct fsi_priv *fsi, | |
4f56cde1 | 1361 | struct device *dev) |
106c79ec KM |
1362 | { |
1363 | fsi_reg_write(fsi, DO_FMT, fsi->saved_do_fmt); | |
1364 | fsi_reg_write(fsi, DI_FMT, fsi->saved_di_fmt); | |
1365 | fsi_reg_write(fsi, CKG1, fsi->saved_ckg1); | |
1366 | fsi_reg_write(fsi, CKG2, fsi->saved_ckg2); | |
1367 | fsi_reg_write(fsi, OUT_SEL, fsi->saved_out_sel); | |
1368 | ||
1369 | if (fsi_is_clk_master(fsi)) | |
4f56cde1 | 1370 | fsi_set_master_clk(dev, fsi, fsi->rate, 1); |
106c79ec KM |
1371 | } |
1372 | ||
1373 | static int fsi_suspend(struct device *dev) | |
1374 | { | |
1375 | struct fsi_master *master = dev_get_drvdata(dev); | |
106c79ec KM |
1376 | |
1377 | pm_runtime_get_sync(dev); | |
1378 | ||
4f56cde1 KM |
1379 | __fsi_suspend(&master->fsia, dev); |
1380 | __fsi_suspend(&master->fsib, dev); | |
106c79ec KM |
1381 | |
1382 | master->saved_a_mclk = fsi_core_read(master, a_mclk); | |
1383 | master->saved_b_mclk = fsi_core_read(master, b_mclk); | |
1384 | master->saved_iemsk = fsi_core_read(master, iemsk); | |
1385 | master->saved_imsk = fsi_core_read(master, imsk); | |
1386 | master->saved_clk_rst = fsi_master_read(master, CLK_RST); | |
1f5e2a31 KM |
1387 | master->saved_soft_rst = fsi_master_read(master, SOFT_RST); |
1388 | ||
1389 | fsi_module_kill(master, dev); | |
106c79ec KM |
1390 | |
1391 | pm_runtime_put_sync(dev); | |
1392 | ||
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | static int fsi_resume(struct device *dev) | |
1397 | { | |
1398 | struct fsi_master *master = dev_get_drvdata(dev); | |
106c79ec KM |
1399 | |
1400 | pm_runtime_get_sync(dev); | |
1401 | ||
1f5e2a31 | 1402 | fsi_module_init(master, dev); |
106c79ec | 1403 | |
1f5e2a31 KM |
1404 | fsi_master_mask_set(master, SOFT_RST, 0xffff, master->saved_soft_rst); |
1405 | fsi_master_mask_set(master, CLK_RST, 0xffff, master->saved_clk_rst); | |
106c79ec KM |
1406 | fsi_core_mask_set(master, a_mclk, 0xffff, master->saved_a_mclk); |
1407 | fsi_core_mask_set(master, b_mclk, 0xffff, master->saved_b_mclk); | |
1408 | fsi_core_mask_set(master, iemsk, 0xffff, master->saved_iemsk); | |
1409 | fsi_core_mask_set(master, imsk, 0xffff, master->saved_imsk); | |
1f5e2a31 | 1410 | |
4f56cde1 KM |
1411 | __fsi_resume(&master->fsia, dev); |
1412 | __fsi_resume(&master->fsib, dev); | |
106c79ec KM |
1413 | |
1414 | pm_runtime_put_sync(dev); | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
785d1c45 KM |
1419 | static int fsi_runtime_nop(struct device *dev) |
1420 | { | |
1421 | /* Runtime PM callback shared between ->runtime_suspend() | |
1422 | * and ->runtime_resume(). Simply returns success. | |
1423 | * | |
1424 | * This driver re-initializes all registers after | |
1425 | * pm_runtime_get_sync() anyway so there is no need | |
1426 | * to save and restore registers here. | |
1427 | */ | |
1428 | return 0; | |
1429 | } | |
1430 | ||
1431 | static struct dev_pm_ops fsi_pm_ops = { | |
106c79ec KM |
1432 | .suspend = fsi_suspend, |
1433 | .resume = fsi_resume, | |
785d1c45 KM |
1434 | .runtime_suspend = fsi_runtime_nop, |
1435 | .runtime_resume = fsi_runtime_nop, | |
1436 | }; | |
1437 | ||
73b92c1f KM |
1438 | static struct fsi_core fsi1_core = { |
1439 | .ver = 1, | |
1440 | ||
1441 | /* Interrupt */ | |
cc780d38 KM |
1442 | .int_st = INT_ST, |
1443 | .iemsk = IEMSK, | |
1444 | .imsk = IMSK, | |
1445 | }; | |
1446 | ||
73b92c1f KM |
1447 | static struct fsi_core fsi2_core = { |
1448 | .ver = 2, | |
1449 | ||
1450 | /* Interrupt */ | |
cc780d38 KM |
1451 | .int_st = CPU_INT_ST, |
1452 | .iemsk = CPU_IEMSK, | |
1453 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
1454 | .a_mclk = A_MST_CTLR, |
1455 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
1456 | }; |
1457 | ||
1458 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1459 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1460 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1461 | {}, |
cc780d38 | 1462 | }; |
d85a6d7b | 1463 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1464 | |
a4d7d550 KM |
1465 | static struct platform_driver fsi_driver = { |
1466 | .driver = { | |
f0fba2ad | 1467 | .name = "fsi-pcm-audio", |
785d1c45 | 1468 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1469 | }, |
1470 | .probe = fsi_probe, | |
1471 | .remove = fsi_remove, | |
cc780d38 | 1472 | .id_table = fsi_id_table, |
a4d7d550 KM |
1473 | }; |
1474 | ||
1475 | static int __init fsi_mobile_init(void) | |
1476 | { | |
1477 | return platform_driver_register(&fsi_driver); | |
1478 | } | |
1479 | ||
1480 | static void __exit fsi_mobile_exit(void) | |
1481 | { | |
1482 | platform_driver_unregister(&fsi_driver); | |
1483 | } | |
d85a6d7b | 1484 | |
a4d7d550 KM |
1485 | module_init(fsi_mobile_init); |
1486 | module_exit(fsi_mobile_exit); | |
1487 | ||
1488 | MODULE_LICENSE("GPL"); | |
1489 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1490 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 1491 | MODULE_ALIAS("platform:fsi-pcm-audio"); |