[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa2xx-i2s.c

/*
 * pxa2xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * Copyright 2005 Wolfson Microelectronics PLC.
 * Author: Liam Girdwood
 *         lrg@slimlogic.co.uk
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>

#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/audio.h>

#include "pxa2xx-pcm.h"
#include "pxa2xx-i2s.h"

struct pxa2xx_gpio {
	u32 sys;
	u32	rx;
	u32 tx;
	u32 clk;
	u32 frm;
};

/*
 * I2S Controller Register and Bit Definitions
 */
#define SACR0		__REG(0x40400000)  /* Global Control Register */
#define SACR1		__REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
#define SASR0		__REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
#define SAIMR		__REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
#define SAICR		__REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
#define SADIV		__REG(0x40400060)  /* Audio Clock Divider Register. */
#define SADR		__REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */

#define SACR0_RFTH(x)	((x) << 12)	/* Rx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_TFTH(x)	((x) << 8)	/* Tx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_STRF	(1 << 5)	/* FIFO Select for EFWR Special Function */
#define SACR0_EFWR	(1 << 4)	/* Enable EFWR Function  */
#define SACR0_RST	(1 << 3)	/* FIFO, i2s Register Reset */
#define SACR0_BCKD	(1 << 2) 	/* Bit Clock Direction */
#define SACR0_ENB	(1 << 0)	/* Enable I2S Link */
#define SACR1_ENLBF	(1 << 5)	/* Enable Loopback */
#define SACR1_DRPL	(1 << 4) 	/* Disable Replaying Function */
#define SACR1_DREC	(1 << 3)	/* Disable Recording Function */
#define SACR1_AMSL	(1 << 0)	/* Specify Alternate Mode */

#define SASR0_I2SOFF	(1 << 7)	/* Controller Status */
#define SASR0_ROR	(1 << 6)	/* Rx FIFO Overrun */
#define SASR0_TUR	(1 << 5)	/* Tx FIFO Underrun */
#define SASR0_RFS	(1 << 4)	/* Rx FIFO Service Request */
#define SASR0_TFS	(1 << 3)	/* Tx FIFO Service Request */
#define SASR0_BSY	(1 << 2)	/* I2S Busy */
#define SASR0_RNE	(1 << 1)	/* Rx FIFO Not Empty */
#define SASR0_TNF	(1 << 0) 	/* Tx FIFO Not Empty */

#define SAICR_ROR	(1 << 6)	/* Clear Rx FIFO Overrun Interrupt */
#define SAICR_TUR	(1 << 5)	/* Clear Tx FIFO Underrun Interrupt */

#define SAIMR_ROR	(1 << 6)	/* Enable Rx FIFO Overrun Condition Interrupt */
#define SAIMR_TUR	(1 << 5)	/* Enable Tx FIFO Underrun Condition Interrupt */
#define SAIMR_RFS	(1 << 4)	/* Enable Rx FIFO Service Interrupt */
#define SAIMR_TFS	(1 << 3)	/* Enable Tx FIFO Service Interrupt */

struct pxa_i2s_port {
	u32 sadiv;
	u32 sacr0;
	u32 sacr1;
	u32 saimr;
	int master;
	u32 fmt;
};
static struct pxa_i2s_port pxa_i2s;
static struct clk *clk_i2s;

static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
	.name			= "I2S PCM Stereo out",
	.dev_addr		= __PREG(SADR),
	.drcmr			= &DRCMR(3),
	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
	.name			= "I2S PCM Stereo in",
	.dev_addr		= __PREG(SADR),
	.drcmr			= &DRCMR(2),
	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_gpio gpio_bus[] = {
	{ /* I2S SoC Slave */
		.rx = GPIO29_SDATA_IN_I2S_MD,
		.tx = GPIO30_SDATA_OUT_I2S_MD,
		.clk = GPIO28_BITCLK_IN_I2S_MD,
		.frm = GPIO31_SYNC_I2S_MD,
	},
	{ /* I2S SoC Master */
		.rx = GPIO29_SDATA_IN_I2S_MD,
		.tx = GPIO30_SDATA_OUT_I2S_MD,
		.clk = GPIO28_BITCLK_OUT_I2S_MD,
		.frm = GPIO31_SYNC_I2S_MD,
	},
};

static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
			      struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;

	if (IS_ERR(clk_i2s))
		return PTR_ERR(clk_i2s);

	if (!cpu_dai->active) {
		SACR0 |= SACR0_RST;
		SACR0 = 0;
	}

	return 0;
}

/* wait for I2S controller to be ready */
static int pxa_i2s_wait(void)
{
	int i;

	/* flush the Rx FIFO */
	for(i = 0; i < 16; i++)
		SADR;
	return 0;
}

static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
		unsigned int fmt)
{
	/* interface format */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		pxa_i2s.fmt = 0;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		pxa_i2s.fmt = SACR1_AMSL;
		break;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		pxa_i2s.master = 1;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		pxa_i2s.master = 0;
		break;
	default:
		break;
	}
	return 0;
}

static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
		int clk_id, unsigned int freq, int dir)
{
	if (clk_id != PXA2XX_I2S_SYSCLK)
		return -ENODEV;

	if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
		pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);

	return 0;
}

static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;

	pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
	pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
	pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
	pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
	BUG_ON(IS_ERR(clk_i2s));
	clk_enable(clk_i2s);
	pxa_i2s_wait();

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
	else
		cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;

	/* is port used by another stream */
	if (!(SACR0 & SACR0_ENB)) {

		SACR0 = 0;
		SACR1 = 0;
		if (pxa_i2s.master)
			SACR0 |= SACR0_BCKD;

		SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
		SACR1 |= pxa_i2s.fmt;
	}
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		SAIMR |= SAIMR_TFS;
	else
		SAIMR |= SAIMR_RFS;

	switch (params_rate(params)) {
	case 8000:
		SADIV = 0x48;
		break;
	case 11025:
		SADIV = 0x34;
		break;
	case 16000:
		SADIV = 0x24;
		break;
	case 22050:
		SADIV = 0x1a;
		break;
	case 44100:
		SADIV = 0xd;
		break;
	case 48000:
		SADIV = 0xc;
		break;
	case 96000: /* not in manual and possibly slightly inaccurate */
		SADIV = 0x6;
		break;
	}

	return 0;
}

static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			      struct snd_soc_dai *dai)
{
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		SACR0 |= SACR0_ENB;
		break;
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
				struct snd_soc_dai *dai)
{
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		SACR1 |= SACR1_DRPL;
		SAIMR &= ~SAIMR_TFS;
	} else {
		SACR1 |= SACR1_DREC;
		SAIMR &= ~SAIMR_RFS;
	}

	if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
		SACR0 &= ~SACR0_ENB;
		pxa_i2s_wait();
		clk_disable(clk_i2s);
	}

	clk_put(clk_i2s);
}

#ifdef CONFIG_PM
static int pxa2xx_i2s_suspend(struct snd_soc_dai *dai)
{
	if (!dai->active)
		return 0;

	/* store registers */
	pxa_i2s.sacr0 = SACR0;
	pxa_i2s.sacr1 = SACR1;
	pxa_i2s.saimr = SAIMR;
	pxa_i2s.sadiv = SADIV;

	/* deactivate link */
	SACR0 &= ~SACR0_ENB;
	pxa_i2s_wait();
	return 0;
}

static int pxa2xx_i2s_resume(struct snd_soc_dai *dai)
{
	if (!dai->active)
		return 0;

	pxa_i2s_wait();

	SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
	SACR1 = pxa_i2s.sacr1;
	SAIMR = pxa_i2s.saimr;
	SADIV = pxa_i2s.sadiv;
	SACR0 |= SACR0_ENB;

	return 0;
}

#else
#define pxa2xx_i2s_suspend	NULL
#define pxa2xx_i2s_resume	NULL
#endif

#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
		SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
		SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)

struct snd_soc_dai pxa_i2s_dai = {
	.name = "pxa2xx-i2s",
	.id = 0,
	.suspend = pxa2xx_i2s_suspend,
	.resume = pxa2xx_i2s_resume,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = {
		.startup = pxa2xx_i2s_startup,
		.shutdown = pxa2xx_i2s_shutdown,
		.trigger = pxa2xx_i2s_trigger,
		.hw_params = pxa2xx_i2s_hw_params,
		.set_fmt = pxa2xx_i2s_set_dai_fmt,
		.set_sysclk = pxa2xx_i2s_set_dai_sysclk,
	},
};

EXPORT_SYMBOL_GPL(pxa_i2s_dai);

static int pxa2xx_i2s_probe(struct platform_device *dev)
{
	int ret;

	clk_i2s = clk_get(&dev->dev, "I2SCLK");
	if (IS_ERR(clk_i2s))
		return PTR_ERR(clk_i2s);

	pxa_i2s_dai.dev = &dev->dev;
	ret = snd_soc_register_dai(&pxa_i2s_dai);
	if (ret != 0)
		clk_put(clk_i2s);

	return ret;
}

static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
{
	snd_soc_unregister_dai(&pxa_i2s_dai);
	clk_put(clk_i2s);
	clk_i2s = ERR_PTR(-ENOENT);
	return 0;
}

static struct platform_driver pxa2xx_i2s_driver = {
	.probe = pxa2xx_i2s_probe,
	.remove = __devexit_p(pxa2xx_i2s_remove),

	.driver = {
		.name = "pxa2xx-i2s",
		.owner = THIS_MODULE,
	},
};

static int __init pxa2xx_i2s_init(void)
{
	if (cpu_is_pxa27x())
		gpio_bus[1].sys = GPIO113_I2S_SYSCLK_MD;
	else
		gpio_bus[1].sys = GPIO32_SYSCLK_I2S_MD;

	clk_i2s = ERR_PTR(-ENOENT);
	return platform_driver_register(&pxa2xx_i2s_driver);
}

static void __exit pxa2xx_i2s_exit(void)
{
	platform_driver_unregister(&pxa2xx_i2s_driver);
}

module_init(pxa2xx_i2s_init);
module_exit(pxa2xx_i2s_exit);

/* Module information */
MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
3e7cc3d3 LG	1	/*
	2	* pxa2xx-i2s.c -- ALSA Soc Audio Layer
	3	*
	4	* Copyright 2005 Wolfson Microelectronics PLC.
	5	* Author: Liam Girdwood
d331124d	6	* lrg@slimlogic.co.uk
3e7cc3d3 LG	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
3e7cc3d3 LG	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/module.h>
	16	#include <linux/device.h>
	17	#include <linux/delay.h>
5a2cc50f	18	#include <linux/clk.h>
6e5ea701	19	#include <linux/platform_device.h>
3e7cc3d3 LG	20	#include <sound/core.h>
	21	#include <sound/pcm.h>
	22	#include <sound/initval.h>
	23	#include <sound/soc.h>
a6d77317	24	#include <sound/pxa2xx-lib.h>
3e7cc3d3	25
a09e64fb RK	26	#include <mach/hardware.h>
	27	#include <mach/pxa-regs.h>
	28	#include <mach/pxa2xx-gpio.h>
	29	#include <mach/audio.h>
3e7cc3d3 LG	30
3e7cc3d3 LG	31	#include "pxa2xx-pcm.h"
eaff2ae7	32	#include "pxa2xx-i2s.h"
3e7cc3d3	33
a6d77317 DES	34	struct pxa2xx_gpio {
	35	u32 sys;
	36	u32 rx;
	37	u32 tx;
	38	u32 clk;
	39	u32 frm;
	40	};
	41
52358ba3 EM	42	/*
	43	* I2S Controller Register and Bit Definitions
	44	*/
	45	#define SACR0 __REG(0x40400000) /* Global Control Register */
	46	#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
	47	#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
	48	#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
	49	#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
	50	#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
	51	#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
	52
	53	#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
	54	#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
	55	#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
	56	#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
	57	#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
	58	#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
	59	#define SACR0_ENB (1 << 0) /* Enable I2S Link */
	60	#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
	61	#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
	62	#define SACR1_DREC (1 << 3) /* Disable Recording Function */
	63	#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
	64
	65	#define SASR0_I2SOFF (1 << 7) /* Controller Status */
	66	#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
	67	#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
	68	#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
	69	#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
	70	#define SASR0_BSY (1 << 2) /* I2S Busy */
	71	#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
	72	#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
	73
	74	#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
	75	#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
	76
	77	#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
	78	#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
	79	#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
	80	#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
a6d77317	81
3e7cc3d3 LG	82	struct pxa_i2s_port {
	83	u32 sadiv;
	84	u32 sacr0;
	85	u32 sacr1;
	86	u32 saimr;
	87	int master;
eaff2ae7	88	u32 fmt;
3e7cc3d3 LG	89	};
3e7cc3d3 LG	90	static struct pxa_i2s_port pxa_i2s;
5a2cc50f	91	static struct clk *clk_i2s;
3e7cc3d3	92
3e7cc3d3 LG	93	static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
	94	.name = "I2S PCM Stereo out",
	95	.dev_addr = __PREG(SADR),
87f3dd77	96	.drcmr = &DRCMR(3),
3e7cc3d3 LG	97	.dcmd = DCMD_INCSRCADDR \| DCMD_FLOWTRG \|
	98	DCMD_BURST32 \| DCMD_WIDTH4,
	99	};
	100
	101	static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
	102	.name = "I2S PCM Stereo in",
	103	.dev_addr = __PREG(SADR),
87f3dd77	104	.drcmr = &DRCMR(2),
3e7cc3d3 LG	105	.dcmd = DCMD_INCTRGADDR \| DCMD_FLOWSRC \|
	106	DCMD_BURST32 \| DCMD_WIDTH4,
	107	};
	108
	109	static struct pxa2xx_gpio gpio_bus[] = {
	110	{ /* I2S SoC Slave */
	111	.rx = GPIO29_SDATA_IN_I2S_MD,
	112	.tx = GPIO30_SDATA_OUT_I2S_MD,
	113	.clk = GPIO28_BITCLK_IN_I2S_MD,
	114	.frm = GPIO31_SYNC_I2S_MD,
	115	},
	116	{ /* I2S SoC Master */
3e7cc3d3 LG	117	.rx = GPIO29_SDATA_IN_I2S_MD,
	118	.tx = GPIO30_SDATA_OUT_I2S_MD,
	119	.clk = GPIO28_BITCLK_OUT_I2S_MD,
	120	.frm = GPIO31_SYNC_I2S_MD,
	121	},
	122	};
	123
dee89c4d MB	124	static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
dee89c4d MB	125	struct snd_soc_dai *dai)
3e7cc3d3 LG	126	{
3e7cc3d3 LG	127	struct snd_soc_pcm_runtime *rtd = substream->private_data;
917f93ac	128	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
3e7cc3d3	129
5a2cc50f	130	if (IS_ERR(clk_i2s))
	131	return PTR_ERR(clk_i2s);
	132
eaff2ae7	133	if (!cpu_dai->active) {
3e7cc3d3 LG	134	SACR0 \|= SACR0_RST;
	135	SACR0 = 0;
	136	}
	137
	138	return 0;
	139	}
	140
	141	/* wait for I2S controller to be ready */
	142	static int pxa_i2s_wait(void)
	143	{
	144	int i;
	145
	146	/* flush the Rx FIFO */
	147	for(i = 0; i < 16; i++)
	148	SADR;
	149	return 0;
	150	}
	151
917f93ac	152	static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
eaff2ae7	153	unsigned int fmt)
3e7cc3d3	154	{
eaff2ae7 PZ	155	/* interface format */
	156	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	157	case SND_SOC_DAIFMT_I2S:
	158	pxa_i2s.fmt = 0;
	159	break;
	160	case SND_SOC_DAIFMT_LEFT_J:
	161	pxa_i2s.fmt = SACR1_AMSL;
	162	break;
	163	}
3e7cc3d3	164
eaff2ae7 PZ	165	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
eaff2ae7 PZ	166	case SND_SOC_DAIFMT_CBS_CFS:
3e7cc3d3	167	pxa_i2s.master = 1;
eaff2ae7 PZ	168	break;
	169	case SND_SOC_DAIFMT_CBM_CFS:
	170	pxa_i2s.master = 0;
	171	break;
	172	default:
	173	break;
	174	}
	175	return 0;
	176	}
3e7cc3d3	177
917f93ac	178	static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
eaff2ae7 PZ	179	int clk_id, unsigned int freq, int dir)
	180	{
	181	if (clk_id != PXA2XX_I2S_SYSCLK)
	182	return -ENODEV;
	183
	184	if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
3e7cc3d3 LG	185	pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
3e7cc3d3 LG	186
eaff2ae7 PZ	187	return 0;
	188	}
	189
	190	static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	191	struct snd_pcm_hw_params *params,
dee89c4d MB	192	struct snd_soc_dai *dai)
eaff2ae7 PZ	193	{
eaff2ae7 PZ	194	struct snd_soc_pcm_runtime *rtd = substream->private_data;
917f93ac	195	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
eaff2ae7	196
3e7cc3d3 LG	197	pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
	198	pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
	199	pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
	200	pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
6e5ea701	201	BUG_ON(IS_ERR(clk_i2s));
5a2cc50f	202	clk_enable(clk_i2s);
3e7cc3d3 LG	203	pxa_i2s_wait();
	204
	205	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
eaff2ae7	206	cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
3e7cc3d3	207	else
eaff2ae7	208	cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
3e7cc3d3 LG	209
	210	/* is port used by another stream */
	211	if (!(SACR0 & SACR0_ENB)) {
	212
	213	SACR0 = 0;
	214	SACR1 = 0;
	215	if (pxa_i2s.master)
	216	SACR0 \|= SACR0_BCKD;
	217
	218	SACR0 \|= SACR0_RFTH(14) \| SACR0_TFTH(1);
eaff2ae7	219	SACR1 \|= pxa_i2s.fmt;
3e7cc3d3 LG	220	}
	221	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	222	SAIMR \|= SAIMR_TFS;
	223	else
	224	SAIMR \|= SAIMR_RFS;
	225
eaff2ae7 PZ	226	switch (params_rate(params)) {
	227	case 8000:
	228	SADIV = 0x48;
	229	break;
	230	case 11025:
	231	SADIV = 0x34;
	232	break;
	233	case 16000:
	234	SADIV = 0x24;
	235	break;
	236	case 22050:
	237	SADIV = 0x1a;
	238	break;
	239	case 44100:
	240	SADIV = 0xd;
	241	break;
	242	case 48000:
	243	SADIV = 0xc;
	244	break;
	245	case 96000: /* not in manual and possibly slightly inaccurate */
	246	SADIV = 0x6;
	247	break;
	248	}
	249
3e7cc3d3 LG	250	return 0;
	251	}
	252
dee89c4d MB	253	static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	254	struct snd_soc_dai *dai)
3e7cc3d3 LG	255	{
	256	int ret = 0;
	257
	258	switch (cmd) {
	259	case SNDRV_PCM_TRIGGER_START:
	260	SACR0 \|= SACR0_ENB;
	261	break;
	262	case SNDRV_PCM_TRIGGER_RESUME:
	263	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	264	case SNDRV_PCM_TRIGGER_STOP:
	265	case SNDRV_PCM_TRIGGER_SUSPEND:
	266	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	267	break;
	268	default:
	269	ret = -EINVAL;
	270	}
	271
	272	return ret;
	273	}
	274
dee89c4d MB	275	static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	276	struct snd_soc_dai *dai)
3e7cc3d3 LG	277	{
	278	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	279	SACR1 \|= SACR1_DRPL;
	280	SAIMR &= ~SAIMR_TFS;
	281	} else {
	282	SACR1 \|= SACR1_DREC;
	283	SAIMR &= ~SAIMR_RFS;
	284	}
	285
	286	if (SACR1 & (SACR1_DREC \| SACR1_DRPL)) {
	287	SACR0 &= ~SACR0_ENB;
	288	pxa_i2s_wait();
5a2cc50f	289	clk_disable(clk_i2s);
3e7cc3d3	290	}
5a2cc50f	291
5a2cc50f	292	clk_put(clk_i2s);
3e7cc3d3 LG	293	}
	294
	295	#ifdef CONFIG_PM
dc7d7b83	296	static int pxa2xx_i2s_suspend(struct snd_soc_dai *dai)
3e7cc3d3 LG	297	{
	298	if (!dai->active)
	299	return 0;
	300
	301	/* store registers */
	302	pxa_i2s.sacr0 = SACR0;
	303	pxa_i2s.sacr1 = SACR1;
	304	pxa_i2s.saimr = SAIMR;
	305	pxa_i2s.sadiv = SADIV;
	306
	307	/* deactivate link */
	308	SACR0 &= ~SACR0_ENB;
	309	pxa_i2s_wait();
	310	return 0;
	311	}
	312
dc7d7b83	313	static int pxa2xx_i2s_resume(struct snd_soc_dai *dai)
3e7cc3d3 LG	314	{
	315	if (!dai->active)
	316	return 0;
	317
	318	pxa_i2s_wait();
	319
	320	SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
	321	SACR1 = pxa_i2s.sacr1;
	322	SAIMR = pxa_i2s.saimr;
	323	SADIV = pxa_i2s.sadiv;
	324	SACR0 \|= SACR0_ENB;
	325
	326	return 0;
	327	}
	328
	329	#else
	330	#define pxa2xx_i2s_suspend NULL
	331	#define pxa2xx_i2s_resume NULL
	332	#endif
	333
eaff2ae7 PZ	334	#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \|\
	335	SNDRV_PCM_RATE_16000 \| SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_44100 \| \
	336	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_96000)
3e7cc3d3	337
917f93ac	338	struct snd_soc_dai pxa_i2s_dai = {
3e7cc3d3 LG	339	.name = "pxa2xx-i2s",
3e7cc3d3 LG	340	.id = 0,
3e7cc3d3 LG	341	.suspend = pxa2xx_i2s_suspend,
3e7cc3d3 LG	342	.resume = pxa2xx_i2s_resume,
3e7cc3d3 LG	343	.playback = {
3e7cc3d3 LG	344	.channels_min = 2,
eaff2ae7 PZ	345	.channels_max = 2,
	346	.rates = PXA2XX_I2S_RATES,
	347	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
3e7cc3d3 LG	348	.capture = {
3e7cc3d3 LG	349	.channels_min = 2,
eaff2ae7 PZ	350	.channels_max = 2,
	351	.rates = PXA2XX_I2S_RATES,
	352	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
3e7cc3d3 LG	353	.ops = {
	354	.startup = pxa2xx_i2s_startup,
	355	.shutdown = pxa2xx_i2s_shutdown,
	356	.trigger = pxa2xx_i2s_trigger,
dee89c4d	357	.hw_params = pxa2xx_i2s_hw_params,
eaff2ae7 PZ	358	.set_fmt = pxa2xx_i2s_set_dai_fmt,
	359	.set_sysclk = pxa2xx_i2s_set_dai_sysclk,
	360	},
3e7cc3d3 LG	361	};
	362
	363	EXPORT_SYMBOL_GPL(pxa_i2s_dai);
	364
6e5ea701 DES	365	static int pxa2xx_i2s_probe(struct platform_device *dev)
6e5ea701 DES	366	{
3f4b783c MB	367	int ret;
3f4b783c MB	368
6e5ea701	369	clk_i2s = clk_get(&dev->dev, "I2SCLK");
3f4b783c MB	370	if (IS_ERR(clk_i2s))
	371	return PTR_ERR(clk_i2s);
	372
	373	pxa_i2s_dai.dev = &dev->dev;
	374	ret = snd_soc_register_dai(&pxa_i2s_dai);
	375	if (ret != 0)
	376	clk_put(clk_i2s);
	377
	378	return ret;
6e5ea701 DES	379	}
	380
	381	static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
	382	{
3f4b783c	383	snd_soc_unregister_dai(&pxa_i2s_dai);
6e5ea701 DES	384	clk_put(clk_i2s);
	385	clk_i2s = ERR_PTR(-ENOENT);
	386	return 0;
	387	}
	388
	389	static struct platform_driver pxa2xx_i2s_driver = {
	390	.probe = pxa2xx_i2s_probe,
	391	.remove = __devexit_p(pxa2xx_i2s_remove),
	392
	393	.driver = {
	394	.name = "pxa2xx-i2s",
	395	.owner = THIS_MODULE,
	396	},
	397	};
	398
	399	static int __init pxa2xx_i2s_init(void)
	400	{
081b355d DES	401	if (cpu_is_pxa27x())
	402	gpio_bus[1].sys = GPIO113_I2S_SYSCLK_MD;
	403	else
	404	gpio_bus[1].sys = GPIO32_SYSCLK_I2S_MD;
	405
6e5ea701 DES	406	clk_i2s = ERR_PTR(-ENOENT);
	407	return platform_driver_register(&pxa2xx_i2s_driver);
	408	}
	409
	410	static void __exit pxa2xx_i2s_exit(void)
	411	{
	412	platform_driver_unregister(&pxa2xx_i2s_driver);
	413	}
	414
	415	module_init(pxa2xx_i2s_init);
	416	module_exit(pxa2xx_i2s_exit);
	417
3e7cc3d3	418	/* Module information */
d331124d	419	MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
3e7cc3d3 LG	420	MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
3e7cc3d3 LG	421	MODULE_LICENSE("GPL");