[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa2xx-i2s.c

/*
 * pxa2xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * Copyright 2005 Wolfson Microelectronics PLC.
 * Author: Liam Girdwood
 *         liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  Revision history
 *    12th Aug 2005   Initial version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/audio.h>

#include "pxa2xx-pcm.h"
#include "pxa2xx-i2s.h"

struct pxa_i2s_port {
	u32 sadiv;
	u32 sacr0;
	u32 sacr1;
	u32 saimr;
	int master;
	u32 fmt;
};
static struct pxa_i2s_port pxa_i2s;

static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
	.name			= "I2S PCM Stereo out",
	.dev_addr		= __PREG(SADR),
	.drcmr			= &DRCMRTXSADR,
	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
	.name			= "I2S PCM Stereo in",
	.dev_addr		= __PREG(SADR),
	.drcmr			= &DRCMRRXSADR,
	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_gpio gpio_bus[] = {
	{ /* I2S SoC Slave */
		.rx = GPIO29_SDATA_IN_I2S_MD,
		.tx = GPIO30_SDATA_OUT_I2S_MD,
		.clk = GPIO28_BITCLK_IN_I2S_MD,
		.frm = GPIO31_SYNC_I2S_MD,
	},
	{ /* I2S SoC Master */
#ifdef CONFIG_PXA27x
		.sys = GPIO113_I2S_SYSCLK_MD,
#else
		.sys = GPIO32_SYSCLK_I2S_MD,
#endif
		.rx = GPIO29_SDATA_IN_I2S_MD,
		.tx = GPIO30_SDATA_OUT_I2S_MD,
		.clk = GPIO28_BITCLK_OUT_I2S_MD,
		.frm = GPIO31_SYNC_I2S_MD,
	},
};

static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;

	if (!cpu_dai->active) {
		SACR0 |= SACR0_RST;
		SACR0 = 0;
	}

	return 0;
}

/* wait for I2S controller to be ready */
static int pxa_i2s_wait(void)
{
	int i;

	/* flush the Rx FIFO */
	for(i = 0; i < 16; i++)
		SADR;
	return 0;
}

static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai,
		unsigned int fmt)
{
	/* interface format */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		pxa_i2s.fmt = 0;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		pxa_i2s.fmt = SACR1_AMSL;
		break;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		pxa_i2s.master = 1;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		pxa_i2s.master = 0;
		break;
	default:
		break;
	}
	return 0;
}

static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai,
		int clk_id, unsigned int freq, int dir)
{
	if (clk_id != PXA2XX_I2S_SYSCLK)
		return -ENODEV;

	if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
		pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);

	return 0;
}

static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;

	pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
	pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
	pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
	pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
	pxa_set_cken(CKEN_I2S, 1);
	pxa_i2s_wait();

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
	else
		cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;

	/* is port used by another stream */
	if (!(SACR0 & SACR0_ENB)) {

		SACR0 = 0;
		SACR1 = 0;
		if (pxa_i2s.master)
			SACR0 |= SACR0_BCKD;

		SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
		SACR1 |= pxa_i2s.fmt;
	}
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		SAIMR |= SAIMR_TFS;
	else
		SAIMR |= SAIMR_RFS;

	switch (params_rate(params)) {
	case 8000:
		SADIV = 0x48;
		break;
	case 11025:
		SADIV = 0x34;
		break;
	case 16000:
		SADIV = 0x24;
		break;
	case 22050:
		SADIV = 0x1a;
		break;
	case 44100:
		SADIV = 0xd;
		break;
	case 48000:
		SADIV = 0xc;
		break;
	case 96000: /* not in manual and possibly slightly inaccurate */
		SADIV = 0x6;
		break;
	}

	return 0;
}

static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
{
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		SACR0 |= SACR0_ENB;
		break;
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
{
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		SACR1 |= SACR1_DRPL;
		SAIMR &= ~SAIMR_TFS;
	} else {
		SACR1 |= SACR1_DREC;
		SAIMR &= ~SAIMR_RFS;
	}

	if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
		SACR0 &= ~SACR0_ENB;
		pxa_i2s_wait();
		pxa_set_cken(CKEN_I2S, 0);
	}
}

#ifdef CONFIG_PM
static int pxa2xx_i2s_suspend(struct platform_device *dev,
	struct snd_soc_cpu_dai *dai)
{
	if (!dai->active)
		return 0;

	/* store registers */
	pxa_i2s.sacr0 = SACR0;
	pxa_i2s.sacr1 = SACR1;
	pxa_i2s.saimr = SAIMR;
	pxa_i2s.sadiv = SADIV;

	/* deactivate link */
	SACR0 &= ~SACR0_ENB;
	pxa_i2s_wait();
	return 0;
}

static int pxa2xx_i2s_resume(struct platform_device *pdev,
	struct snd_soc_cpu_dai *dai)
{
	if (!dai->active)
		return 0;

	pxa_i2s_wait();

	SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
	SACR1 = pxa_i2s.sacr1;
	SAIMR = pxa_i2s.saimr;
	SADIV = pxa_i2s.sadiv;
	SACR0 |= SACR0_ENB;

	return 0;
}

#else
#define pxa2xx_i2s_suspend	NULL
#define pxa2xx_i2s_resume	NULL
#endif

#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
		SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
		SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)

struct snd_soc_cpu_dai pxa_i2s_dai = {
	.name = "pxa2xx-i2s",
	.id = 0,
	.type = SND_SOC_DAI_I2S,
	.suspend = pxa2xx_i2s_suspend,
	.resume = pxa2xx_i2s_resume,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = {
		.startup = pxa2xx_i2s_startup,
		.shutdown = pxa2xx_i2s_shutdown,
		.trigger = pxa2xx_i2s_trigger,
		.hw_params = pxa2xx_i2s_hw_params,},
	.dai_ops = {
		.set_fmt = pxa2xx_i2s_set_dai_fmt,
		.set_sysclk = pxa2xx_i2s_set_dai_sysclk,
	},
};

EXPORT_SYMBOL_GPL(pxa_i2s_dai);

/* Module information */
MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
3e7cc3d3 LG	1	/*
	2	* pxa2xx-i2s.c -- ALSA Soc Audio Layer
	3	*
	4	* Copyright 2005 Wolfson Microelectronics PLC.
	5	* Author: Liam Girdwood
	6	* liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* Revision history
	14	* 12th Aug 2005 Initial version.
	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/module.h>
	19	#include <linux/device.h>
	20	#include <linux/delay.h>
3e7cc3d3 LG	21	#include <sound/core.h>
	22	#include <sound/pcm.h>
	23	#include <sound/initval.h>
	24	#include <sound/soc.h>
	25
	26	#include <asm/hardware.h>
	27	#include <asm/arch/pxa-regs.h>
a683b14d	28	#include <asm/arch/pxa2xx-gpio.h>
3e7cc3d3 LG	29	#include <asm/arch/audio.h>
	30
	31	#include "pxa2xx-pcm.h"
eaff2ae7	32	#include "pxa2xx-i2s.h"
3e7cc3d3 LG	33
	34	struct pxa_i2s_port {
	35	u32 sadiv;
	36	u32 sacr0;
	37	u32 sacr1;
	38	u32 saimr;
	39	int master;
eaff2ae7	40	u32 fmt;
3e7cc3d3 LG	41	};
	42	static struct pxa_i2s_port pxa_i2s;
	43
3e7cc3d3 LG	44	static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
	45	.name = "I2S PCM Stereo out",
	46	.dev_addr = __PREG(SADR),
	47	.drcmr = &DRCMRTXSADR,
	48	.dcmd = DCMD_INCSRCADDR \| DCMD_FLOWTRG \|
	49	DCMD_BURST32 \| DCMD_WIDTH4,
	50	};
	51
	52	static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
	53	.name = "I2S PCM Stereo in",
	54	.dev_addr = __PREG(SADR),
	55	.drcmr = &DRCMRRXSADR,
	56	.dcmd = DCMD_INCTRGADDR \| DCMD_FLOWSRC \|
	57	DCMD_BURST32 \| DCMD_WIDTH4,
	58	};
	59
	60	static struct pxa2xx_gpio gpio_bus[] = {
	61	{ /* I2S SoC Slave */
	62	.rx = GPIO29_SDATA_IN_I2S_MD,
	63	.tx = GPIO30_SDATA_OUT_I2S_MD,
	64	.clk = GPIO28_BITCLK_IN_I2S_MD,
	65	.frm = GPIO31_SYNC_I2S_MD,
	66	},
	67	{ /* I2S SoC Master */
	68	#ifdef CONFIG_PXA27x
	69	.sys = GPIO113_I2S_SYSCLK_MD,
	70	#else
	71	.sys = GPIO32_SYSCLK_I2S_MD,
	72	#endif
	73	.rx = GPIO29_SDATA_IN_I2S_MD,
	74	.tx = GPIO30_SDATA_OUT_I2S_MD,
	75	.clk = GPIO28_BITCLK_OUT_I2S_MD,
	76	.frm = GPIO31_SYNC_I2S_MD,
	77	},
	78	};
	79
	80	static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
	81	{
	82	struct snd_soc_pcm_runtime *rtd = substream->private_data;
eaff2ae7	83	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
3e7cc3d3	84
eaff2ae7	85	if (!cpu_dai->active) {
3e7cc3d3 LG	86	SACR0 \|= SACR0_RST;
	87	SACR0 = 0;
	88	}
	89
	90	return 0;
	91	}
	92
	93	/* wait for I2S controller to be ready */
	94	static int pxa_i2s_wait(void)
	95	{
	96	int i;
	97
	98	/* flush the Rx FIFO */
	99	for(i = 0; i < 16; i++)
	100	SADR;
	101	return 0;
	102	}
	103
eaff2ae7 PZ	104	static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai,
eaff2ae7 PZ	105	unsigned int fmt)
3e7cc3d3	106	{
eaff2ae7 PZ	107	/* interface format */
	108	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	109	case SND_SOC_DAIFMT_I2S:
	110	pxa_i2s.fmt = 0;
	111	break;
	112	case SND_SOC_DAIFMT_LEFT_J:
	113	pxa_i2s.fmt = SACR1_AMSL;
	114	break;
	115	}
3e7cc3d3	116
eaff2ae7 PZ	117	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
eaff2ae7 PZ	118	case SND_SOC_DAIFMT_CBS_CFS:
3e7cc3d3	119	pxa_i2s.master = 1;
eaff2ae7 PZ	120	break;
	121	case SND_SOC_DAIFMT_CBM_CFS:
	122	pxa_i2s.master = 0;
	123	break;
	124	default:
	125	break;
	126	}
	127	return 0;
	128	}
3e7cc3d3	129
eaff2ae7 PZ	130	static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai,
	131	int clk_id, unsigned int freq, int dir)
	132	{
	133	if (clk_id != PXA2XX_I2S_SYSCLK)
	134	return -ENODEV;
	135
	136	if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
3e7cc3d3 LG	137	pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
3e7cc3d3 LG	138
eaff2ae7 PZ	139	return 0;
	140	}
	141
	142	static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
	143	struct snd_pcm_hw_params *params)
	144	{
	145	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	146	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
	147
3e7cc3d3 LG	148	pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
	149	pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
	150	pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
	151	pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
7053acbd	152	pxa_set_cken(CKEN_I2S, 1);
3e7cc3d3 LG	153	pxa_i2s_wait();
	154
	155	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
eaff2ae7	156	cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
3e7cc3d3	157	else
eaff2ae7	158	cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
3e7cc3d3 LG	159
	160	/* is port used by another stream */
	161	if (!(SACR0 & SACR0_ENB)) {
	162
	163	SACR0 = 0;
	164	SACR1 = 0;
	165	if (pxa_i2s.master)
	166	SACR0 \|= SACR0_BCKD;
	167
	168	SACR0 \|= SACR0_RFTH(14) \| SACR0_TFTH(1);
eaff2ae7	169	SACR1 \|= pxa_i2s.fmt;
3e7cc3d3 LG	170	}
	171	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	172	SAIMR \|= SAIMR_TFS;
	173	else
	174	SAIMR \|= SAIMR_RFS;
	175
eaff2ae7 PZ	176	switch (params_rate(params)) {
	177	case 8000:
	178	SADIV = 0x48;
	179	break;
	180	case 11025:
	181	SADIV = 0x34;
	182	break;
	183	case 16000:
	184	SADIV = 0x24;
	185	break;
	186	case 22050:
	187	SADIV = 0x1a;
	188	break;
	189	case 44100:
	190	SADIV = 0xd;
	191	break;
	192	case 48000:
	193	SADIV = 0xc;
	194	break;
	195	case 96000: /* not in manual and possibly slightly inaccurate */
	196	SADIV = 0x6;
	197	break;
	198	}
	199
3e7cc3d3 LG	200	return 0;
	201	}
	202
	203	static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
	204	{
	205	int ret = 0;
	206
	207	switch (cmd) {
	208	case SNDRV_PCM_TRIGGER_START:
	209	SACR0 \|= SACR0_ENB;
	210	break;
	211	case SNDRV_PCM_TRIGGER_RESUME:
	212	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	213	case SNDRV_PCM_TRIGGER_STOP:
	214	case SNDRV_PCM_TRIGGER_SUSPEND:
	215	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	216	break;
	217	default:
	218	ret = -EINVAL;
	219	}
	220
	221	return ret;
	222	}
	223
	224	static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
	225	{
	226	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	227	SACR1 \|= SACR1_DRPL;
	228	SAIMR &= ~SAIMR_TFS;
	229	} else {
	230	SACR1 \|= SACR1_DREC;
	231	SAIMR &= ~SAIMR_RFS;
	232	}
	233
	234	if (SACR1 & (SACR1_DREC \| SACR1_DRPL)) {
	235	SACR0 &= ~SACR0_ENB;
	236	pxa_i2s_wait();
7053acbd	237	pxa_set_cken(CKEN_I2S, 0);
3e7cc3d3 LG	238	}
	239	}
	240
	241	#ifdef CONFIG_PM
	242	static int pxa2xx_i2s_suspend(struct platform_device *dev,
	243	struct snd_soc_cpu_dai *dai)
	244	{
	245	if (!dai->active)
	246	return 0;
	247
	248	/* store registers */
	249	pxa_i2s.sacr0 = SACR0;
	250	pxa_i2s.sacr1 = SACR1;
	251	pxa_i2s.saimr = SAIMR;
	252	pxa_i2s.sadiv = SADIV;
	253
	254	/* deactivate link */
	255	SACR0 &= ~SACR0_ENB;
	256	pxa_i2s_wait();
	257	return 0;
	258	}
	259
	260	static int pxa2xx_i2s_resume(struct platform_device *pdev,
	261	struct snd_soc_cpu_dai *dai)
	262	{
	263	if (!dai->active)
	264	return 0;
	265
	266	pxa_i2s_wait();
	267
	268	SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
	269	SACR1 = pxa_i2s.sacr1;
	270	SAIMR = pxa_i2s.saimr;
	271	SADIV = pxa_i2s.sadiv;
	272	SACR0 \|= SACR0_ENB;
	273
	274	return 0;
	275	}
	276
	277	#else
	278	#define pxa2xx_i2s_suspend NULL
	279	#define pxa2xx_i2s_resume NULL
	280	#endif
	281
eaff2ae7 PZ	282	#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \|\
	283	SNDRV_PCM_RATE_16000 \| SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_44100 \| \
	284	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_96000)
3e7cc3d3 LG	285
	286	struct snd_soc_cpu_dai pxa_i2s_dai = {
	287	.name = "pxa2xx-i2s",
	288	.id = 0,
	289	.type = SND_SOC_DAI_I2S,
	290	.suspend = pxa2xx_i2s_suspend,
	291	.resume = pxa2xx_i2s_resume,
3e7cc3d3 LG	292	.playback = {
3e7cc3d3 LG	293	.channels_min = 2,
eaff2ae7 PZ	294	.channels_max = 2,
	295	.rates = PXA2XX_I2S_RATES,
	296	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
3e7cc3d3 LG	297	.capture = {
3e7cc3d3 LG	298	.channels_min = 2,
eaff2ae7 PZ	299	.channels_max = 2,
	300	.rates = PXA2XX_I2S_RATES,
	301	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
3e7cc3d3 LG	302	.ops = {
	303	.startup = pxa2xx_i2s_startup,
	304	.shutdown = pxa2xx_i2s_shutdown,
	305	.trigger = pxa2xx_i2s_trigger,
	306	.hw_params = pxa2xx_i2s_hw_params,},
eaff2ae7 PZ	307	.dai_ops = {
	308	.set_fmt = pxa2xx_i2s_set_dai_fmt,
	309	.set_sysclk = pxa2xx_i2s_set_dai_sysclk,
	310	},
3e7cc3d3 LG	311	};
	312
	313	EXPORT_SYMBOL_GPL(pxa_i2s_dai);
	314
	315	/* Module information */
	316	MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
	317	MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
	318	MODULE_LICENSE("GPL");