[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa2xx-i2s.c

/*
 * pxa2xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * Copyright 2005 Wolfson Microelectronics PLC.
 * Author: Liam Girdwood
 *         liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/audio.h>

#include "pxa2xx-pcm.h"
#include "pxa2xx-i2s.h"

struct pxa_i2s_port {
	u32 sadiv;
	u32 sacr0;
	u32 sacr1;
	u32 saimr;
	int master;
	u32 fmt;
};
static struct pxa_i2s_port pxa_i2s;

static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
	.name			= "I2S PCM Stereo out",
	.dev_addr		= __PREG(SADR),
	.drcmr			= &DRCMRTXSADR,
	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
	.name			= "I2S PCM Stereo in",
	.dev_addr		= __PREG(SADR),
	.drcmr			= &DRCMRRXSADR,
	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
				  DCMD_BURST32 | DCMD_WIDTH4,
};

static struct pxa2xx_gpio gpio_bus[] = {
	{ /* I2S SoC Slave */
		.rx = GPIO29_SDATA_IN_I2S_MD,
		.tx = GPIO30_SDATA_OUT_I2S_MD,
		.clk = GPIO28_BITCLK_IN_I2S_MD,
		.frm = GPIO31_SYNC_I2S_MD,
	},
	{ /* I2S SoC Master */
#ifdef CONFIG_PXA27x
		.sys = GPIO113_I2S_SYSCLK_MD,
#else
		.sys = GPIO32_SYSCLK_I2S_MD,
#endif
		.rx = GPIO29_SDATA_IN_I2S_MD,
		.tx = GPIO30_SDATA_OUT_I2S_MD,
		.clk = GPIO28_BITCLK_OUT_I2S_MD,
		.frm = GPIO31_SYNC_I2S_MD,
	},
};

static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;

	if (!cpu_dai->active) {
		SACR0 |= SACR0_RST;
		SACR0 = 0;
	}

	return 0;
}

/* wait for I2S controller to be ready */
static int pxa_i2s_wait(void)
{
	int i;

	/* flush the Rx FIFO */
	for(i = 0; i < 16; i++)
		SADR;
	return 0;
}

static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai,
		unsigned int fmt)
{
	/* interface format */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		pxa_i2s.fmt = 0;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		pxa_i2s.fmt = SACR1_AMSL;
		break;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		pxa_i2s.master = 1;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		pxa_i2s.master = 0;
		break;
	default:
		break;
	}
	return 0;
}

static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai,
		int clk_id, unsigned int freq, int dir)
{
	if (clk_id != PXA2XX_I2S_SYSCLK)
		return -ENODEV;

	if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
		pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);

	return 0;
}

static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;

	pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
	pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
	pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
	pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
	pxa_set_cken(CKEN_I2S, 1);
	pxa_i2s_wait();

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
	else
		cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;

	/* is port used by another stream */
	if (!(SACR0 & SACR0_ENB)) {

		SACR0 = 0;
		SACR1 = 0;
		if (pxa_i2s.master)
			SACR0 |= SACR0_BCKD;

		SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
		SACR1 |= pxa_i2s.fmt;
	}
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		SAIMR |= SAIMR_TFS;
	else
		SAIMR |= SAIMR_RFS;

	switch (params_rate(params)) {
	case 8000:
		SADIV = 0x48;
		break;
	case 11025:
		SADIV = 0x34;
		break;
	case 16000:
		SADIV = 0x24;
		break;
	case 22050:
		SADIV = 0x1a;
		break;
	case 44100:
		SADIV = 0xd;
		break;
	case 48000:
		SADIV = 0xc;
		break;
	case 96000: /* not in manual and possibly slightly inaccurate */
		SADIV = 0x6;
		break;
	}

	return 0;
}

static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
{
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		SACR0 |= SACR0_ENB;
		break;
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
{
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		SACR1 |= SACR1_DRPL;
		SAIMR &= ~SAIMR_TFS;
	} else {
		SACR1 |= SACR1_DREC;
		SAIMR &= ~SAIMR_RFS;
	}

	if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
		SACR0 &= ~SACR0_ENB;
		pxa_i2s_wait();
		pxa_set_cken(CKEN_I2S, 0);
	}
}

#ifdef CONFIG_PM
static int pxa2xx_i2s_suspend(struct platform_device *dev,
	struct snd_soc_cpu_dai *dai)
{
	if (!dai->active)
		return 0;

	/* store registers */
	pxa_i2s.sacr0 = SACR0;
	pxa_i2s.sacr1 = SACR1;
	pxa_i2s.saimr = SAIMR;
	pxa_i2s.sadiv = SADIV;

	/* deactivate link */
	SACR0 &= ~SACR0_ENB;
	pxa_i2s_wait();
	return 0;
}

static int pxa2xx_i2s_resume(struct platform_device *pdev,
	struct snd_soc_cpu_dai *dai)
{
	if (!dai->active)
		return 0;

	pxa_i2s_wait();

	SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
	SACR1 = pxa_i2s.sacr1;
	SAIMR = pxa_i2s.saimr;
	SADIV = pxa_i2s.sadiv;
	SACR0 |= SACR0_ENB;

	return 0;
}

#else
#define pxa2xx_i2s_suspend	NULL
#define pxa2xx_i2s_resume	NULL
#endif

#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
		SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
		SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)

struct snd_soc_cpu_dai pxa_i2s_dai = {
	.name = "pxa2xx-i2s",
	.id = 0,
	.type = SND_SOC_DAI_I2S,
	.suspend = pxa2xx_i2s_suspend,
	.resume = pxa2xx_i2s_resume,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = {
		.startup = pxa2xx_i2s_startup,
		.shutdown = pxa2xx_i2s_shutdown,
		.trigger = pxa2xx_i2s_trigger,
		.hw_params = pxa2xx_i2s_hw_params,},
	.dai_ops = {
		.set_fmt = pxa2xx_i2s_set_dai_fmt,
		.set_sysclk = pxa2xx_i2s_set_dai_sysclk,
	},
};

EXPORT_SYMBOL_GPL(pxa_i2s_dai);

/* Module information */
MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
3e7cc3d3 LG	1	/*
	2	* pxa2xx-i2s.c -- ALSA Soc Audio Layer
	3	*
	4	* Copyright 2005 Wolfson Microelectronics PLC.
	5	* Author: Liam Girdwood
	6	* liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
3e7cc3d3 LG	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/module.h>
	16	#include <linux/device.h>
	17	#include <linux/delay.h>
3e7cc3d3 LG	18	#include <sound/core.h>
	19	#include <sound/pcm.h>
	20	#include <sound/initval.h>
	21	#include <sound/soc.h>
	22
	23	#include <asm/hardware.h>
	24	#include <asm/arch/pxa-regs.h>
a683b14d	25	#include <asm/arch/pxa2xx-gpio.h>
3e7cc3d3 LG	26	#include <asm/arch/audio.h>
	27
	28	#include "pxa2xx-pcm.h"
eaff2ae7	29	#include "pxa2xx-i2s.h"
3e7cc3d3 LG	30
	31	struct pxa_i2s_port {
	32	u32 sadiv;
	33	u32 sacr0;
	34	u32 sacr1;
	35	u32 saimr;
	36	int master;
eaff2ae7	37	u32 fmt;
3e7cc3d3 LG	38	};
	39	static struct pxa_i2s_port pxa_i2s;
	40
3e7cc3d3 LG	41	static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
	42	.name = "I2S PCM Stereo out",
	43	.dev_addr = __PREG(SADR),
	44	.drcmr = &DRCMRTXSADR,
	45	.dcmd = DCMD_INCSRCADDR \| DCMD_FLOWTRG \|
	46	DCMD_BURST32 \| DCMD_WIDTH4,
	47	};
	48
	49	static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
	50	.name = "I2S PCM Stereo in",
	51	.dev_addr = __PREG(SADR),
	52	.drcmr = &DRCMRRXSADR,
	53	.dcmd = DCMD_INCTRGADDR \| DCMD_FLOWSRC \|
	54	DCMD_BURST32 \| DCMD_WIDTH4,
	55	};
	56
	57	static struct pxa2xx_gpio gpio_bus[] = {
	58	{ /* I2S SoC Slave */
	59	.rx = GPIO29_SDATA_IN_I2S_MD,
	60	.tx = GPIO30_SDATA_OUT_I2S_MD,
	61	.clk = GPIO28_BITCLK_IN_I2S_MD,
	62	.frm = GPIO31_SYNC_I2S_MD,
	63	},
	64	{ /* I2S SoC Master */
	65	#ifdef CONFIG_PXA27x
	66	.sys = GPIO113_I2S_SYSCLK_MD,
	67	#else
	68	.sys = GPIO32_SYSCLK_I2S_MD,
	69	#endif
	70	.rx = GPIO29_SDATA_IN_I2S_MD,
	71	.tx = GPIO30_SDATA_OUT_I2S_MD,
	72	.clk = GPIO28_BITCLK_OUT_I2S_MD,
	73	.frm = GPIO31_SYNC_I2S_MD,
	74	},
	75	};
	76
	77	static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
	78	{
	79	struct snd_soc_pcm_runtime *rtd = substream->private_data;
eaff2ae7	80	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
3e7cc3d3	81
eaff2ae7	82	if (!cpu_dai->active) {
3e7cc3d3 LG	83	SACR0 \|= SACR0_RST;
	84	SACR0 = 0;
	85	}
	86
	87	return 0;
	88	}
	89
	90	/* wait for I2S controller to be ready */
	91	static int pxa_i2s_wait(void)
	92	{
	93	int i;
	94
	95	/* flush the Rx FIFO */
	96	for(i = 0; i < 16; i++)
	97	SADR;
	98	return 0;
	99	}
	100
eaff2ae7 PZ	101	static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai,
eaff2ae7 PZ	102	unsigned int fmt)
3e7cc3d3	103	{
eaff2ae7 PZ	104	/* interface format */
	105	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	106	case SND_SOC_DAIFMT_I2S:
	107	pxa_i2s.fmt = 0;
	108	break;
	109	case SND_SOC_DAIFMT_LEFT_J:
	110	pxa_i2s.fmt = SACR1_AMSL;
	111	break;
	112	}
3e7cc3d3	113
eaff2ae7 PZ	114	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
eaff2ae7 PZ	115	case SND_SOC_DAIFMT_CBS_CFS:
3e7cc3d3	116	pxa_i2s.master = 1;
eaff2ae7 PZ	117	break;
	118	case SND_SOC_DAIFMT_CBM_CFS:
	119	pxa_i2s.master = 0;
	120	break;
	121	default:
	122	break;
	123	}
	124	return 0;
	125	}
3e7cc3d3	126
eaff2ae7 PZ	127	static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai,
	128	int clk_id, unsigned int freq, int dir)
	129	{
	130	if (clk_id != PXA2XX_I2S_SYSCLK)
	131	return -ENODEV;
	132
	133	if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
3e7cc3d3 LG	134	pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
3e7cc3d3 LG	135
eaff2ae7 PZ	136	return 0;
	137	}
	138
	139	static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
	140	struct snd_pcm_hw_params *params)
	141	{
	142	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	143	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
	144
3e7cc3d3 LG	145	pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
	146	pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
	147	pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
	148	pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
7053acbd	149	pxa_set_cken(CKEN_I2S, 1);
3e7cc3d3 LG	150	pxa_i2s_wait();
	151
	152	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
eaff2ae7	153	cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
3e7cc3d3	154	else
eaff2ae7	155	cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
3e7cc3d3 LG	156
	157	/* is port used by another stream */
	158	if (!(SACR0 & SACR0_ENB)) {
	159
	160	SACR0 = 0;
	161	SACR1 = 0;
	162	if (pxa_i2s.master)
	163	SACR0 \|= SACR0_BCKD;
	164
	165	SACR0 \|= SACR0_RFTH(14) \| SACR0_TFTH(1);
eaff2ae7	166	SACR1 \|= pxa_i2s.fmt;
3e7cc3d3 LG	167	}
	168	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	169	SAIMR \|= SAIMR_TFS;
	170	else
	171	SAIMR \|= SAIMR_RFS;
	172
eaff2ae7 PZ	173	switch (params_rate(params)) {
	174	case 8000:
	175	SADIV = 0x48;
	176	break;
	177	case 11025:
	178	SADIV = 0x34;
	179	break;
	180	case 16000:
	181	SADIV = 0x24;
	182	break;
	183	case 22050:
	184	SADIV = 0x1a;
	185	break;
	186	case 44100:
	187	SADIV = 0xd;
	188	break;
	189	case 48000:
	190	SADIV = 0xc;
	191	break;
	192	case 96000: /* not in manual and possibly slightly inaccurate */
	193	SADIV = 0x6;
	194	break;
	195	}
	196
3e7cc3d3 LG	197	return 0;
	198	}
	199
	200	static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
	201	{
	202	int ret = 0;
	203
	204	switch (cmd) {
	205	case SNDRV_PCM_TRIGGER_START:
	206	SACR0 \|= SACR0_ENB;
	207	break;
	208	case SNDRV_PCM_TRIGGER_RESUME:
	209	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	210	case SNDRV_PCM_TRIGGER_STOP:
	211	case SNDRV_PCM_TRIGGER_SUSPEND:
	212	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	213	break;
	214	default:
	215	ret = -EINVAL;
	216	}
	217
	218	return ret;
	219	}
	220
	221	static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
	222	{
	223	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	224	SACR1 \|= SACR1_DRPL;
	225	SAIMR &= ~SAIMR_TFS;
	226	} else {
	227	SACR1 \|= SACR1_DREC;
	228	SAIMR &= ~SAIMR_RFS;
	229	}
	230
	231	if (SACR1 & (SACR1_DREC \| SACR1_DRPL)) {
	232	SACR0 &= ~SACR0_ENB;
	233	pxa_i2s_wait();
7053acbd	234	pxa_set_cken(CKEN_I2S, 0);
3e7cc3d3 LG	235	}
	236	}
	237
	238	#ifdef CONFIG_PM
	239	static int pxa2xx_i2s_suspend(struct platform_device *dev,
	240	struct snd_soc_cpu_dai *dai)
	241	{
	242	if (!dai->active)
	243	return 0;
	244
	245	/* store registers */
	246	pxa_i2s.sacr0 = SACR0;
	247	pxa_i2s.sacr1 = SACR1;
	248	pxa_i2s.saimr = SAIMR;
	249	pxa_i2s.sadiv = SADIV;
	250
	251	/* deactivate link */
	252	SACR0 &= ~SACR0_ENB;
	253	pxa_i2s_wait();
	254	return 0;
	255	}
	256
	257	static int pxa2xx_i2s_resume(struct platform_device *pdev,
	258	struct snd_soc_cpu_dai *dai)
	259	{
	260	if (!dai->active)
	261	return 0;
	262
	263	pxa_i2s_wait();
	264
	265	SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
	266	SACR1 = pxa_i2s.sacr1;
	267	SAIMR = pxa_i2s.saimr;
	268	SADIV = pxa_i2s.sadiv;
	269	SACR0 \|= SACR0_ENB;
	270
	271	return 0;
	272	}
	273
	274	#else
	275	#define pxa2xx_i2s_suspend NULL
	276	#define pxa2xx_i2s_resume NULL
	277	#endif
	278
eaff2ae7 PZ	279	#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 \| SNDRV_PCM_RATE_11025 \|\
	280	SNDRV_PCM_RATE_16000 \| SNDRV_PCM_RATE_22050 \| SNDRV_PCM_RATE_44100 \| \
	281	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_96000)
3e7cc3d3 LG	282
	283	struct snd_soc_cpu_dai pxa_i2s_dai = {
	284	.name = "pxa2xx-i2s",
	285	.id = 0,
	286	.type = SND_SOC_DAI_I2S,
	287	.suspend = pxa2xx_i2s_suspend,
	288	.resume = pxa2xx_i2s_resume,
3e7cc3d3 LG	289	.playback = {
3e7cc3d3 LG	290	.channels_min = 2,
eaff2ae7 PZ	291	.channels_max = 2,
	292	.rates = PXA2XX_I2S_RATES,
	293	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
3e7cc3d3 LG	294	.capture = {
3e7cc3d3 LG	295	.channels_min = 2,
eaff2ae7 PZ	296	.channels_max = 2,
	297	.rates = PXA2XX_I2S_RATES,
	298	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
3e7cc3d3 LG	299	.ops = {
	300	.startup = pxa2xx_i2s_startup,
	301	.shutdown = pxa2xx_i2s_shutdown,
	302	.trigger = pxa2xx_i2s_trigger,
	303	.hw_params = pxa2xx_i2s_hw_params,},
eaff2ae7 PZ	304	.dai_ops = {
	305	.set_fmt = pxa2xx_i2s_set_dai_fmt,
	306	.set_sysclk = pxa2xx_i2s_set_dai_sysclk,
	307	},
3e7cc3d3 LG	308	};
	309
	310	EXPORT_SYMBOL_GPL(pxa_i2s_dai);
	311
	312	/* Module information */
	313	MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
	314	MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
	315	MODULE_LICENSE("GPL");