[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / omap / omap-mcpdm.c

/*
 * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
 *
 * Copyright (C) 2009 - 2011 Texas Instruments
 *
 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
 *          Margarita Olaya <magi.olaya@ti.com>
 *          Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#include "omap-mcpdm.h"

struct mcpdm_link_config {
	u32 link_mask; /* channel mask for the direction */
	u32 threshold; /* FIFO threshold */
};

struct omap_mcpdm {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	int irq;

	struct mutex mutex;

	/* Playback/Capture configuration */
	struct mcpdm_link_config config[2];

	/* McPDM dn offsets for rx1, and 2 channels */
	u32 dn_rx_offset;

	/* McPDM needs to be restarted due to runtime reconfiguration */
	bool restart;

	struct snd_dmaengine_dai_dma_data dma_data[2];
	unsigned int dma_req[2];
};

/*
 * Stream DMA parameters
 */

static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
{
	__raw_writel(val, mcpdm->io_base + reg);
}

static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
{
	return __raw_readl(mcpdm->io_base + reg);
}

#ifdef DEBUG
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
{
	dev_dbg(mcpdm->dev, "***********************\n");
	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
			omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	dev_dbg(mcpdm->dev, "***********************\n");
}
#else
static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
#endif

/*
 * Enables the transfer through the PDM interface to/from the Phoenix
 * codec by enabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl |= link_mask;
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
}

/*
 * Disables the transfer through the PDM interface to/from the Phoenix
 * codec by disabling the corresponding UP or DN channels.
 */
static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
{
	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
	u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;

	ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(link_mask);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

	ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);

}

/*
 * Is the physical McPDM interface active.
 */
static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
{
	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
					(MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
}

/*
 * Configures McPDM uplink, and downlink for audio.
 * This function should be called before omap_mcpdm_start.
 */
static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
{
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Enable DN RX1/2 offset cancellation feature, if configured */
	if (mcpdm->dn_rx_offset) {
		u32 dn_offset = mcpdm->dn_rx_offset;

		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
		dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	}

	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
			 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
			 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);

	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
			MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
}

/*
 * Cleans McPDM uplink, and downlink configuration.
 * This function should be called when the stream is closed.
 */
static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
{
	/* Disable irq request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);

	/* Disable DMA request generation for downlink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);

	/* Disable irq request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
			MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);

	/* Disable DMA request generation for uplink */
	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);

	/* Disable RX1/2 offset cancellation */
	if (mcpdm->dn_rx_offset)
		omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
}

static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
{
	struct omap_mcpdm *mcpdm = dev_id;
	int irq_status;

	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);

	/* Acknowledge irq event */
	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);

	if (irq_status & MCPDM_DN_IRQ_FULL)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");

	if (irq_status & MCPDM_DN_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");

	if (irq_status & MCPDM_DN_IRQ)
		dev_dbg(mcpdm->dev, "DN (playback) write request\n");

	if (irq_status & MCPDM_UP_IRQ_FULL)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");

	if (irq_status & MCPDM_UP_IRQ_EMPTY)
		dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");

	if (irq_status & MCPDM_UP_IRQ)
		dev_dbg(mcpdm->dev, "UP (capture) write request\n");

	return IRQ_HANDLED;
}

static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);

		omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
		omap_mcpdm_open_streams(mcpdm);
	}
	mutex_unlock(&mcpdm->mutex);

	snd_soc_dai_set_dma_data(dai, substream,
				 &mcpdm->dma_data[substream->stream]);

	return 0;
}

static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	mutex_lock(&mcpdm->mutex);

	if (!dai->active) {
		if (omap_mcpdm_active(mcpdm)) {
			omap_mcpdm_stop(mcpdm);
			omap_mcpdm_close_streams(mcpdm);
			mcpdm->config[0].link_mask = 0;
			mcpdm->config[1].link_mask = 0;
		}
	}

	mutex_unlock(&mcpdm->mutex);
}

static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int stream = substream->stream;
	struct snd_dmaengine_dai_dma_data *dma_data;
	u32 threshold;
	int channels;
	int link_mask = 0;

	channels = params_channels(params);
	switch (channels) {
	case 5:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 4;
	case 4:
		if (stream == SNDRV_PCM_STREAM_CAPTURE)
			/* up to 3 channels for capture */
			return -EINVAL;
		link_mask |= 1 << 3;
	case 3:
		link_mask |= 1 << 2;
	case 2:
		link_mask |= 1 << 1;
	case 1:
		link_mask |= 1 << 0;
		break;
	default:
		/* unsupported number of channels */
		return -EINVAL;
	}

	dma_data = snd_soc_dai_get_dma_data(dai, substream);

	threshold = mcpdm->config[stream].threshold;
	/* Configure McPDM channels, and DMA packet size */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		link_mask <<= 3;

		/* If capture is not running assume a stereo stream to come */
		if (!mcpdm->config[!stream].link_mask)
			mcpdm->config[!stream].link_mask = 0x3;

		dma_data->maxburst =
				(MCPDM_DN_THRES_MAX - threshold) * channels;
	} else {
		/* If playback is not running assume a stereo stream to come */
		if (!mcpdm->config[!stream].link_mask)
			mcpdm->config[!stream].link_mask = (0x3 << 3);

		dma_data->maxburst = threshold * channels;
	}

	/* Check if we need to restart McPDM with this stream */
	if (mcpdm->config[stream].link_mask &&
	    mcpdm->config[stream].link_mask != link_mask)
		mcpdm->restart = true;

	mcpdm->config[stream].link_mask = link_mask;

	return 0;
}

static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	if (!omap_mcpdm_active(mcpdm)) {
		omap_mcpdm_start(mcpdm);
		omap_mcpdm_reg_dump(mcpdm);
	} else if (mcpdm->restart) {
		omap_mcpdm_stop(mcpdm);
		omap_mcpdm_start(mcpdm);
		mcpdm->restart = false;
		omap_mcpdm_reg_dump(mcpdm);
	}

	return 0;
}

static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
	.startup	= omap_mcpdm_dai_startup,
	.shutdown	= omap_mcpdm_dai_shutdown,
	.hw_params	= omap_mcpdm_dai_hw_params,
	.prepare	= omap_mcpdm_prepare,
};

static int omap_mcpdm_probe(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	int ret;

	pm_runtime_enable(mcpdm->dev);

	/* Disable lines while request is ongoing */
	pm_runtime_get_sync(mcpdm->dev);
	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);

	ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
				0, "McPDM", (void *)mcpdm);

	pm_runtime_put_sync(mcpdm->dev);

	if (ret) {
		dev_err(mcpdm->dev, "Request for IRQ failed\n");
		pm_runtime_disable(mcpdm->dev);
	}

	/* Configure McPDM threshold values */
	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
							MCPDM_UP_THRES_MAX - 3;
	return ret;
}

static int omap_mcpdm_remove(struct snd_soc_dai *dai)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);

	pm_runtime_disable(mcpdm->dev);

	return 0;
}

#define OMAP_MCPDM_RATES	(SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS	SNDRV_PCM_FMTBIT_S32_LE

static struct snd_soc_dai_driver omap_mcpdm_dai = {
	.probe = omap_mcpdm_probe,
	.remove = omap_mcpdm_remove,
	.probe_order = SND_SOC_COMP_ORDER_LATE,
	.remove_order = SND_SOC_COMP_ORDER_EARLY,
	.playback = {
		.channels_min = 1,
		.channels_max = 5,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 3,
		.rates = OMAP_MCPDM_RATES,
		.formats = OMAP_MCPDM_FORMATS,
		.sig_bits = 24,
	},
	.ops = &omap_mcpdm_dai_ops,
};

static const struct snd_soc_component_driver omap_mcpdm_component = {
	.name		= "omap-mcpdm",
};

void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
				    u8 rx1, u8 rx2)
{
	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);

	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
}
EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);

static int asoc_mcpdm_probe(struct platform_device *pdev)
{
	struct omap_mcpdm *mcpdm;
	struct resource *res;

	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
	if (!mcpdm)
		return -ENOMEM;

	platform_set_drvdata(pdev, mcpdm);

	mutex_init(&mcpdm->mutex);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	if (res == NULL)
		return -ENOMEM;

	mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
	mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
	if (!res)
		return -ENODEV;

	mcpdm->dma_req[0] = res->start;
	mcpdm->dma_data[0].filter_data = &mcpdm->dma_req[0];

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
	if (!res)
		return -ENODEV;

	mcpdm->dma_req[1] = res->start;
	mcpdm->dma_data[1].filter_data = &mcpdm->dma_req[1];

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	if (res == NULL)
		return -ENOMEM;

	mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mcpdm->io_base))
		return PTR_ERR(mcpdm->io_base);

	mcpdm->irq = platform_get_irq(pdev, 0);
	if (mcpdm->irq < 0)
		return mcpdm->irq;

	mcpdm->dev = &pdev->dev;

	return snd_soc_register_component(&pdev->dev, &omap_mcpdm_component,
					  &omap_mcpdm_dai, 1);
}

static int asoc_mcpdm_remove(struct platform_device *pdev)
{
	snd_soc_unregister_component(&pdev->dev);
	return 0;
}

static const struct of_device_id omap_mcpdm_of_match[] = {
	{ .compatible = "ti,omap4-mcpdm", },
	{ }
};
MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);

static struct platform_driver asoc_mcpdm_driver = {
	.driver = {
		.name	= "omap-mcpdm",
		.owner	= THIS_MODULE,
		.of_match_table = omap_mcpdm_of_match,
	},

	.probe	= asoc_mcpdm_probe,
	.remove	= asoc_mcpdm_remove,
};

module_platform_driver(asoc_mcpdm_driver);

MODULE_ALIAS("platform:omap-mcpdm");
MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
MODULE_DESCRIPTION("OMAP PDM SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
db72c2f8 MLC	1	/*
	2	* omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
	3	*
f5f9d7bf	4	* Copyright (C) 2009 - 2011 Texas Instruments
db72c2f8	5	*
f5f9d7bf	6	* Author: Misael Lopez Cruz <misael.lopez@ti.com>
db72c2f8 MLC	7	* Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
db72c2f8 MLC	8	* Margarita Olaya <magi.olaya@ti.com>
f5f9d7bf	9	* Peter Ujfalusi <peter.ujfalusi@ti.com>
db72c2f8 MLC	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* version 2 as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but
	16	* WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	23	* 02110-1301 USA
	24	*
	25	*/
	26
	27	#include <linux/init.h>
	28	#include <linux/module.h>
f5f9d7bf MLC	29	#include <linux/platform_device.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/err.h>
	32	#include <linux/io.h>
	33	#include <linux/irq.h>
	34	#include <linux/slab.h>
	35	#include <linux/pm_runtime.h>
7cb8a1b5	36	#include <linux/of_device.h>
f5f9d7bf	37
db72c2f8 MLC	38	#include <sound/core.h>
	39	#include <sound/pcm.h>
	40	#include <sound/pcm_params.h>
db72c2f8	41	#include <sound/soc.h>
09ae3aaf	42	#include <sound/dmaengine_pcm.h>
db72c2f8	43
f5f9d7bf	44	#include "omap-mcpdm.h"
db72c2f8	45
62376631 PU	46	struct mcpdm_link_config {
	47	u32 link_mask; /* channel mask for the direction */
	48	u32 threshold; /* FIFO threshold */
	49	};
dbc04161	50
f5f9d7bf MLC	51	struct omap_mcpdm {
	52	struct device *dev;
	53	unsigned long phys_base;
	54	void __iomem *io_base;
	55	int irq;
db72c2f8	56
f5f9d7bf MLC	57	struct mutex mutex;
f5f9d7bf MLC	58
62376631 PU	59	/* Playback/Capture configuration */
62376631 PU	60	struct mcpdm_link_config config[2];
89b0d550 PU	61
	62	/* McPDM dn offsets for rx1, and 2 channels */
	63	u32 dn_rx_offset;
81054b22 PU	64
	65	/* McPDM needs to be restarted due to runtime reconfiguration */
	66	bool restart;
09ae3aaf LPC	67
	68	struct snd_dmaengine_dai_dma_data dma_data[2];
	69	unsigned int dma_req[2];
db72c2f8 MLC	70	};
	71
	72	/*
	73	* Stream DMA parameters
	74	*/
db72c2f8	75
f5f9d7bf	76	static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
db72c2f8	77	{
f5f9d7bf MLC	78	__raw_writel(val, mcpdm->io_base + reg);
f5f9d7bf MLC	79	}
db72c2f8	80
f5f9d7bf MLC	81	static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
	82	{
	83	return __raw_readl(mcpdm->io_base + reg);
	84	}
db72c2f8	85
f5f9d7bf MLC	86	#ifdef DEBUG
	87	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
	88	{
	89	dev_dbg(mcpdm->dev, "***********************\n");
	90	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
	91	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
	92	dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
	93	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
	94	dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
	95	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
	96	dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
	97	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
	98	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
	99	omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
	100	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
	101	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
	102	dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
	103	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
	104	dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
	105	omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
	106	dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
	107	omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
	108	dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
	109	omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
	110	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
	111	omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
	112	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
	113	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
	114	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
	115	omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
	116	dev_dbg(mcpdm->dev, "***********************\n");
db72c2f8	117	}
f5f9d7bf MLC	118	#else
	119	static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
	120	#endif
db72c2f8	121
f5f9d7bf MLC	122	/*
	123	* Enables the transfer through the PDM interface to/from the Phoenix
	124	* codec by enabling the corresponding UP or DN channels.
	125	*/
	126	static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
	127	{
	128	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
62376631	129	u32 link_mask = mcpdm->config[0].link_mask \| mcpdm->config[1].link_mask;
f5f9d7bf MLC	130
	131	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	132	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	133
62376631	134	ctrl \|= link_mask;
f5f9d7bf MLC	135	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	136
	137	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	138	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	139	}
	140
	141	/*
	142	* Disables the transfer through the PDM interface to/from the Phoenix
	143	* codec by disabling the corresponding UP or DN channels.
	144	*/
	145	static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
	146	{
	147	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
81054b22	148	u32 link_mask = MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK;
f5f9d7bf MLC	149
	150	ctrl \|= (MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	151	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	152
62376631	153	ctrl &= ~(link_mask);
f5f9d7bf MLC	154	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	155
	156	ctrl &= ~(MCPDM_SW_DN_RST \| MCPDM_SW_UP_RST);
	157	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
	158
	159	}
	160
	161	/*
	162	* Is the physical McPDM interface active.
	163	*/
	164	static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
	165	{
	166	return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
	167	(MCPDM_PDM_DN_MASK \| MCPDM_PDM_UP_MASK);
	168	}
	169
	170	/*
	171	* Configures McPDM uplink, and downlink for audio.
	172	* This function should be called before omap_mcpdm_start.
	173	*/
	174	static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
	175	{
	176	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
	177	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL \|
	178	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	179
89b0d550 PU	180	/* Enable DN RX1/2 offset cancellation feature, if configured */
	181	if (mcpdm->dn_rx_offset) {
	182	u32 dn_offset = mcpdm->dn_rx_offset;
	183
	184	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	185	dn_offset \|= (MCPDM_DN_OFST_RX1_EN \| MCPDM_DN_OFST_RX2_EN);
	186	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
	187	}
	188
62376631 PU	189	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
	190	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
	191	omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
	192	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
f5f9d7bf MLC	193
	194	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
	195	MCPDM_DMA_DN_ENABLE \| MCPDM_DMA_UP_ENABLE);
	196	}
	197
	198	/*
	199	* Cleans McPDM uplink, and downlink configuration.
	200	* This function should be called when the stream is closed.
	201	*/
	202	static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
db72c2f8	203	{
f5f9d7bf MLC	204	/* Disable irq request generation for downlink */
	205	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	206	MCPDM_DN_IRQ_EMPTY \| MCPDM_DN_IRQ_FULL);
	207
	208	/* Disable DMA request generation for downlink */
	209	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
	210
	211	/* Disable irq request generation for uplink */
	212	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
	213	MCPDM_UP_IRQ_EMPTY \| MCPDM_UP_IRQ_FULL);
	214
	215	/* Disable DMA request generation for uplink */
	216	omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
89b0d550 PU	217
	218	/* Disable RX1/2 offset cancellation */
	219	if (mcpdm->dn_rx_offset)
	220	omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
f5f9d7bf MLC	221	}
	222
	223	static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
	224	{
	225	struct omap_mcpdm *mcpdm = dev_id;
	226	int irq_status;
	227
	228	irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
	229
	230	/* Acknowledge irq event */
	231	omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
	232
	233	if (irq_status & MCPDM_DN_IRQ_FULL)
	234	dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
	235
	236	if (irq_status & MCPDM_DN_IRQ_EMPTY)
	237	dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
	238
	239	if (irq_status & MCPDM_DN_IRQ)
	240	dev_dbg(mcpdm->dev, "DN (playback) write request\n");
	241
	242	if (irq_status & MCPDM_UP_IRQ_FULL)
	243	dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
	244
	245	if (irq_status & MCPDM_UP_IRQ_EMPTY)
	246	dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
	247
	248	if (irq_status & MCPDM_UP_IRQ)
	249	dev_dbg(mcpdm->dev, "UP (capture) write request\n");
	250
	251	return IRQ_HANDLED;
db72c2f8 MLC	252	}
db72c2f8 MLC	253
f5f9d7bf	254	static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
db72c2f8 MLC	255	struct snd_soc_dai *dai)
db72c2f8 MLC	256	{
f5f9d7bf	257	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	258
f5f9d7bf MLC	259	mutex_lock(&mcpdm->mutex);
	260
	261	if (!dai->active) {
68214d99	262	u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
f5f9d7bf	263
68214d99	264	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl \| MCPDM_WD_EN);
f5f9d7bf	265	omap_mcpdm_open_streams(mcpdm);
db72c2f8	266	}
f5f9d7bf MLC	267	mutex_unlock(&mcpdm->mutex);
f5f9d7bf MLC	268
bcd6da7b	269	snd_soc_dai_set_dma_data(dai, substream,
09ae3aaf	270	&mcpdm->dma_data[substream->stream]);
bcd6da7b	271
f5f9d7bf MLC	272	return 0;
	273	}
	274
	275	static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
	276	struct snd_soc_dai *dai)
	277	{
	278	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	279
	280	mutex_lock(&mcpdm->mutex);
	281
	282	if (!dai->active) {
	283	if (omap_mcpdm_active(mcpdm)) {
	284	omap_mcpdm_stop(mcpdm);
	285	omap_mcpdm_close_streams(mcpdm);
81054b22 PU	286	mcpdm->config[0].link_mask = 0;
81054b22 PU	287	mcpdm->config[1].link_mask = 0;
f5f9d7bf	288	}
f5f9d7bf MLC	289	}
	290
	291	mutex_unlock(&mcpdm->mutex);
db72c2f8 MLC	292	}
	293
	294	static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
	295	struct snd_pcm_hw_params *params,
	296	struct snd_soc_dai *dai)
	297	{
f5f9d7bf	298	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	299	int stream = substream->stream;
09ae3aaf	300	struct snd_dmaengine_dai_dma_data *dma_data;
62376631	301	u32 threshold;
f5f9d7bf MLC	302	int channels;
f5f9d7bf MLC	303	int link_mask = 0;
db72c2f8	304
db72c2f8 MLC	305	channels = params_channels(params);
db72c2f8 MLC	306	switch (channels) {
3b5b516f PU	307	case 5:
	308	if (stream == SNDRV_PCM_STREAM_CAPTURE)
	309	/* up to 3 channels for capture */
	310	return -EINVAL;
	311	link_mask \|= 1 << 4;
db72c2f8 MLC	312	case 4:
db72c2f8 MLC	313	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3b5b516f	314	/* up to 3 channels for capture */
db72c2f8 MLC	315	return -EINVAL;
	316	link_mask \|= 1 << 3;
	317	case 3:
db72c2f8 MLC	318	link_mask \|= 1 << 2;
	319	case 2:
	320	link_mask \|= 1 << 1;
	321	case 1:
	322	link_mask \|= 1 << 0;
	323	break;
	324	default:
	325	/* unsupported number of channels */
	326	return -EINVAL;
	327	}
	328
bcd6da7b	329	dma_data = snd_soc_dai_get_dma_data(dai, substream);
b199adfd	330
62376631	331	threshold = mcpdm->config[stream].threshold;
f5f9d7bf	332	/* Configure McPDM channels, and DMA packet size */
db72c2f8	333	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
62376631	334	link_mask <<= 3;
81054b22 PU	335
	336	/* If capture is not running assume a stereo stream to come */
	337	if (!mcpdm->config[!stream].link_mask)
	338	mcpdm->config[!stream].link_mask = 0x3;
	339
09ae3aaf	340	dma_data->maxburst =
62376631	341	(MCPDM_DN_THRES_MAX - threshold) * channels;
db72c2f8	342	} else {
81054b22 PU	343	/* If playback is not running assume a stereo stream to come */
	344	if (!mcpdm->config[!stream].link_mask)
	345	mcpdm->config[!stream].link_mask = (0x3 << 3);
	346
09ae3aaf	347	dma_data->maxburst = threshold * channels;
db72c2f8 MLC	348	}
db72c2f8 MLC	349
81054b22 PU	350	/* Check if we need to restart McPDM with this stream */
	351	if (mcpdm->config[stream].link_mask &&
	352	mcpdm->config[stream].link_mask != link_mask)
	353	mcpdm->restart = true;
	354
62376631	355	mcpdm->config[stream].link_mask = link_mask;
db72c2f8	356
f5f9d7bf	357	return 0;
db72c2f8 MLC	358	}
db72c2f8 MLC	359
f5f9d7bf	360	static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
db72c2f8 MLC	361	struct snd_soc_dai *dai)
db72c2f8 MLC	362	{
f5f9d7bf	363	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
db72c2f8	364
f5f9d7bf MLC	365	if (!omap_mcpdm_active(mcpdm)) {
	366	omap_mcpdm_start(mcpdm);
	367	omap_mcpdm_reg_dump(mcpdm);
81054b22 PU	368	} else if (mcpdm->restart) {
	369	omap_mcpdm_stop(mcpdm);
	370	omap_mcpdm_start(mcpdm);
	371	mcpdm->restart = false;
	372	omap_mcpdm_reg_dump(mcpdm);
f5f9d7bf	373	}
db72c2f8	374
f5f9d7bf	375	return 0;
db72c2f8 MLC	376	}
db72c2f8 MLC	377
85e7652d	378	static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
db72c2f8 MLC	379	.startup = omap_mcpdm_dai_startup,
db72c2f8 MLC	380	.shutdown = omap_mcpdm_dai_shutdown,
db72c2f8	381	.hw_params = omap_mcpdm_dai_hw_params,
f5f9d7bf	382	.prepare = omap_mcpdm_prepare,
db72c2f8 MLC	383	};
db72c2f8 MLC	384
f5f9d7bf MLC	385	static int omap_mcpdm_probe(struct snd_soc_dai *dai)
	386	{
	387	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
	388	int ret;
	389
	390	pm_runtime_enable(mcpdm->dev);
	391
	392	/* Disable lines while request is ongoing */
	393	pm_runtime_get_sync(mcpdm->dev);
	394	omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
	395
ddd17531	396	ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
f5f9d7bf	397	0, "McPDM", (void *)mcpdm);
db72c2f8	398
f5f9d7bf MLC	399	pm_runtime_put_sync(mcpdm->dev);
	400
	401	if (ret) {
	402	dev_err(mcpdm->dev, "Request for IRQ failed\n");
	403	pm_runtime_disable(mcpdm->dev);
	404	}
	405
	406	/* Configure McPDM threshold values */
62376631 PU	407	mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
	408	mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
	409	MCPDM_UP_THRES_MAX - 3;
f5f9d7bf MLC	410	return ret;
	411	}
	412
	413	static int omap_mcpdm_remove(struct snd_soc_dai *dai)
f0fba2ad	414	{
f5f9d7bf MLC	415	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
f5f9d7bf MLC	416
f5f9d7bf MLC	417	pm_runtime_disable(mcpdm->dev);
f5f9d7bf MLC	418
f0fba2ad LG	419	return 0;
	420	}
	421
f5f9d7bf MLC	422	#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000)
	423	#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
	424
f0fba2ad	425	static struct snd_soc_dai_driver omap_mcpdm_dai = {
f5f9d7bf MLC	426	.probe = omap_mcpdm_probe,
	427	.remove = omap_mcpdm_remove,
	428	.probe_order = SND_SOC_COMP_ORDER_LATE,
	429	.remove_order = SND_SOC_COMP_ORDER_EARLY,
db72c2f8 MLC	430	.playback = {
db72c2f8 MLC	431	.channels_min = 1,
3b5b516f	432	.channels_max = 5,
db72c2f8 MLC	433	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	434	.formats = OMAP_MCPDM_FORMATS,
b4badd49	435	.sig_bits = 24,
db72c2f8 MLC	436	},
	437	.capture = {
	438	.channels_min = 1,
3b5b516f	439	.channels_max = 3,
db72c2f8 MLC	440	.rates = OMAP_MCPDM_RATES,
db72c2f8 MLC	441	.formats = OMAP_MCPDM_FORMATS,
b4badd49	442	.sig_bits = 24,
db72c2f8 MLC	443	},
db72c2f8 MLC	444	.ops = &omap_mcpdm_dai_ops,
db72c2f8	445	};
f0fba2ad	446
58709a32 KM	447	static const struct snd_soc_component_driver omap_mcpdm_component = {
	448	.name = "omap-mcpdm",
	449	};
	450
89b0d550 PU	451	void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
	452	u8 rx1, u8 rx2)
	453	{
	454	struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
	455
	456	mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) \| MCPDM_DNOFST_RX2(rx2);
	457	}
	458	EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
	459
7ff60006	460	static int asoc_mcpdm_probe(struct platform_device *pdev)
f0fba2ad	461	{
f5f9d7bf MLC	462	struct omap_mcpdm *mcpdm;
f5f9d7bf MLC	463	struct resource *res;
f5f9d7bf	464
d77ae332	465	mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
f5f9d7bf MLC	466	if (!mcpdm)
	467	return -ENOMEM;
	468
	469	platform_set_drvdata(pdev, mcpdm);
	470
	471	mutex_init(&mcpdm->mutex);
	472
5a40c57a PU	473	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
	474	if (res == NULL)
	475	return -ENOMEM;
	476
09ae3aaf LPC	477	mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
09ae3aaf LPC	478	mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
5a40c57a	479
5a40c57a PU	480	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
	481	if (!res)
	482	return -ENODEV;
f5f9d7bf	483
09ae3aaf LPC	484	mcpdm->dma_req[0] = res->start;
09ae3aaf LPC	485	mcpdm->dma_data[0].filter_data = &mcpdm->dma_req[0];
5a40c57a PU	486
	487	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
	488	if (!res)
	489	return -ENODEV;
	490
09ae3aaf LPC	491	mcpdm->dma_req[1] = res->start;
09ae3aaf LPC	492	mcpdm->dma_data[1].filter_data = &mcpdm->dma_req[1];
5a40c57a PU	493
	494	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
	495	if (res == NULL)
	496	return -ENOMEM;
	497
77c641d3 SMP	498	mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
	499	if (IS_ERR(mcpdm->io_base))
	500	return PTR_ERR(mcpdm->io_base);
f5f9d7bf MLC	501
f5f9d7bf MLC	502	mcpdm->irq = platform_get_irq(pdev, 0);
d77ae332 PU	503	if (mcpdm->irq < 0)
d77ae332 PU	504	return mcpdm->irq;
f5f9d7bf MLC	505
f5f9d7bf MLC	506	mcpdm->dev = &pdev->dev;
f0fba2ad	507
58709a32 KM	508	return snd_soc_register_component(&pdev->dev, &omap_mcpdm_component,
58709a32 KM	509	&omap_mcpdm_dai, 1);
f0fba2ad LG	510	}
f0fba2ad LG	511
7ff60006	512	static int asoc_mcpdm_remove(struct platform_device *pdev)
f0fba2ad	513	{
58709a32	514	snd_soc_unregister_component(&pdev->dev);
f0fba2ad LG	515	return 0;
	516	}
	517
7cb8a1b5 PU	518	static const struct of_device_id omap_mcpdm_of_match[] = {
	519	{ .compatible = "ti,omap4-mcpdm", },
	520	{ }
	521	};
	522	MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
	523
f0fba2ad LG	524	static struct platform_driver asoc_mcpdm_driver = {
f0fba2ad LG	525	.driver = {
f5f9d7bf MLC	526	.name = "omap-mcpdm",
f5f9d7bf MLC	527	.owner = THIS_MODULE,
7cb8a1b5	528	.of_match_table = omap_mcpdm_of_match,
f0fba2ad LG	529	},
f0fba2ad LG	530
f5f9d7bf	531	.probe = asoc_mcpdm_probe,
7ff60006	532	.remove = asoc_mcpdm_remove,
f0fba2ad	533	};
db72c2f8	534
beda5bf5	535	module_platform_driver(asoc_mcpdm_driver);
db72c2f8	536
d66a547c	537	MODULE_ALIAS("platform:omap-mcpdm");
f5f9d7bf	538	MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
db72c2f8 MLC	539	MODULE_DESCRIPTION("OMAP PDM SoC Interface");
db72c2f8 MLC	540	MODULE_LICENSE("GPL");