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2a24f2ce DA |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
08641c7c SG |
21 | #include <linux/of.h> |
22 | #include <linux/of_device.h> | |
2a24f2ce DA |
23 | #include <linux/platform_device.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/delay.h> | |
76067540 | 28 | #include <linux/time.h> |
39468604 | 29 | #include <linux/fsl/mxs-dma.h> |
f755865f | 30 | #include <linux/pinctrl/consumer.h> |
2a24f2ce DA |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/soc.h> | |
76067540 | 35 | #include <sound/saif.h> |
2a24f2ce DA |
36 | #include <asm/mach-types.h> |
37 | #include <mach/hardware.h> | |
38 | #include <mach/mxs.h> | |
39 | ||
40 | #include "mxs-saif.h" | |
41 | ||
42 | static struct mxs_saif *mxs_saif[2]; | |
43 | ||
76067540 DA |
44 | /* |
45 | * SAIF is a little different with other normal SOC DAIs on clock using. | |
46 | * | |
47 | * For MXS, two SAIF modules are instantiated on-chip. | |
48 | * Each SAIF has a set of clock pins and can be operating in master | |
49 | * mode simultaneously if they are connected to different off-chip codecs. | |
50 | * Also, one of the two SAIFs can master or drive the clock pins while the | |
51 | * other SAIF, in slave mode, receives clocking from the master SAIF. | |
52 | * This also means that both SAIFs must operate at the same sample rate. | |
53 | * | |
54 | * We abstract this as each saif has a master, the master could be | |
55 | * himself or other saifs. In the generic saif driver, saif does not need | |
56 | * to know the different clkmux. Saif only needs to know who is his master | |
57 | * and operating his master to generate the proper clock rate for him. | |
58 | * The master id is provided in mach-specific layer according to different | |
59 | * clkmux setting. | |
60 | */ | |
61 | ||
2a24f2ce DA |
62 | static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
63 | int clk_id, unsigned int freq, int dir) | |
64 | { | |
65 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
66 | ||
67 | switch (clk_id) { | |
68 | case MXS_SAIF_MCLK: | |
69 | saif->mclk = freq; | |
70 | break; | |
71 | default: | |
72 | return -EINVAL; | |
73 | } | |
74 | return 0; | |
75 | } | |
76 | ||
76067540 DA |
77 | /* |
78 | * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK | |
79 | * is provided by other SAIF, we provide a interface here to get its master | |
80 | * from its master_id. | |
81 | * Note that the master could be himself. | |
82 | */ | |
83 | static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) | |
84 | { | |
85 | return mxs_saif[saif->master_id]; | |
86 | } | |
87 | ||
2a24f2ce DA |
88 | /* |
89 | * Set SAIF clock and MCLK | |
90 | */ | |
91 | static int mxs_saif_set_clk(struct mxs_saif *saif, | |
92 | unsigned int mclk, | |
93 | unsigned int rate) | |
94 | { | |
95 | u32 scr; | |
96 | int ret; | |
76067540 | 97 | struct mxs_saif *master_saif; |
2a24f2ce | 98 | |
76067540 DA |
99 | dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); |
100 | ||
101 | /* Set master saif to generate proper clock */ | |
102 | master_saif = mxs_saif_get_master(saif); | |
103 | if (!master_saif) | |
104 | return -EINVAL; | |
105 | ||
106 | dev_dbg(saif->dev, "master saif%d\n", master_saif->id); | |
107 | ||
108 | /* Checking if can playback and capture simutaneously */ | |
109 | if (master_saif->ongoing && rate != master_saif->cur_rate) { | |
110 | dev_err(saif->dev, | |
111 | "can not change clock, master saif%d(rate %d) is ongoing\n", | |
112 | master_saif->id, master_saif->cur_rate); | |
113 | return -EINVAL; | |
114 | } | |
115 | ||
116 | scr = __raw_readl(master_saif->base + SAIF_CTRL); | |
2a24f2ce DA |
117 | scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; |
118 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
119 | ||
120 | /* | |
121 | * Set SAIF clock | |
122 | * | |
123 | * The SAIF clock should be either 384*fs or 512*fs. | |
124 | * If MCLK is used, the SAIF clk ratio need to match mclk ratio. | |
125 | * For 32x mclk, set saif clk as 512*fs. | |
126 | * For 48x mclk, set saif clk as 384*fs. | |
127 | * | |
128 | * If MCLK is not used, we just set saif clk to 512*fs. | |
129 | */ | |
6b35f924 FE |
130 | clk_prepare_enable(master_saif->clk); |
131 | ||
76067540 | 132 | if (master_saif->mclk_in_use) { |
2a24f2ce DA |
133 | if (mclk % 32 == 0) { |
134 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
76067540 | 135 | ret = clk_set_rate(master_saif->clk, 512 * rate); |
2a24f2ce DA |
136 | } else if (mclk % 48 == 0) { |
137 | scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; | |
76067540 | 138 | ret = clk_set_rate(master_saif->clk, 384 * rate); |
2a24f2ce DA |
139 | } else { |
140 | /* SAIF MCLK should be either 32x or 48x */ | |
6b35f924 | 141 | clk_disable_unprepare(master_saif->clk); |
2a24f2ce DA |
142 | return -EINVAL; |
143 | } | |
144 | } else { | |
76067540 | 145 | ret = clk_set_rate(master_saif->clk, 512 * rate); |
2a24f2ce DA |
146 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; |
147 | } | |
148 | ||
6b35f924 FE |
149 | clk_disable_unprepare(master_saif->clk); |
150 | ||
2a24f2ce DA |
151 | if (ret) |
152 | return ret; | |
153 | ||
76067540 DA |
154 | master_saif->cur_rate = rate; |
155 | ||
156 | if (!master_saif->mclk_in_use) { | |
157 | __raw_writel(scr, master_saif->base + SAIF_CTRL); | |
2a24f2ce DA |
158 | return 0; |
159 | } | |
160 | ||
161 | /* | |
162 | * Program the over-sample rate for MCLK output | |
163 | * | |
164 | * The available MCLK range is 32x, 48x... 512x. The rate | |
165 | * could be from 8kHz to 192kH. | |
166 | */ | |
167 | switch (mclk / rate) { | |
168 | case 32: | |
169 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); | |
170 | break; | |
171 | case 64: | |
172 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); | |
173 | break; | |
174 | case 128: | |
175 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); | |
176 | break; | |
177 | case 256: | |
178 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); | |
179 | break; | |
180 | case 512: | |
181 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); | |
182 | break; | |
183 | case 48: | |
184 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); | |
185 | break; | |
186 | case 96: | |
187 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); | |
188 | break; | |
189 | case 192: | |
190 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); | |
191 | break; | |
192 | case 384: | |
193 | scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); | |
194 | break; | |
195 | default: | |
196 | return -EINVAL; | |
197 | } | |
198 | ||
76067540 | 199 | __raw_writel(scr, master_saif->base + SAIF_CTRL); |
2a24f2ce DA |
200 | |
201 | return 0; | |
202 | } | |
203 | ||
204 | /* | |
205 | * Put and disable MCLK. | |
206 | */ | |
207 | int mxs_saif_put_mclk(unsigned int saif_id) | |
208 | { | |
209 | struct mxs_saif *saif = mxs_saif[saif_id]; | |
210 | u32 stat; | |
211 | ||
212 | if (!saif) | |
213 | return -EINVAL; | |
214 | ||
215 | stat = __raw_readl(saif->base + SAIF_STAT); | |
216 | if (stat & BM_SAIF_STAT_BUSY) { | |
217 | dev_err(saif->dev, "error: busy\n"); | |
218 | return -EBUSY; | |
219 | } | |
220 | ||
67939b22 | 221 | clk_disable_unprepare(saif->clk); |
2a24f2ce DA |
222 | |
223 | /* disable MCLK output */ | |
224 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
225 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
226 | __raw_writel(BM_SAIF_CTRL_RUN, | |
227 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
228 | ||
229 | saif->mclk_in_use = 0; | |
230 | return 0; | |
231 | } | |
232 | ||
233 | /* | |
234 | * Get MCLK and set clock rate, then enable it | |
235 | * | |
236 | * This interface is used for codecs who are using MCLK provided | |
237 | * by saif. | |
238 | */ | |
239 | int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, | |
240 | unsigned int rate) | |
241 | { | |
242 | struct mxs_saif *saif = mxs_saif[saif_id]; | |
243 | u32 stat; | |
244 | int ret; | |
76067540 | 245 | struct mxs_saif *master_saif; |
2a24f2ce DA |
246 | |
247 | if (!saif) | |
248 | return -EINVAL; | |
249 | ||
bbe8ff5e DA |
250 | /* Clear Reset */ |
251 | __raw_writel(BM_SAIF_CTRL_SFTRST, | |
252 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
253 | ||
254 | /* FIXME: need clear clk gate for register r/w */ | |
255 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
256 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
257 | ||
76067540 DA |
258 | master_saif = mxs_saif_get_master(saif); |
259 | if (saif != master_saif) { | |
260 | dev_err(saif->dev, "can not get mclk from a non-master saif\n"); | |
261 | return -EINVAL; | |
262 | } | |
263 | ||
2a24f2ce DA |
264 | stat = __raw_readl(saif->base + SAIF_STAT); |
265 | if (stat & BM_SAIF_STAT_BUSY) { | |
266 | dev_err(saif->dev, "error: busy\n"); | |
267 | return -EBUSY; | |
268 | } | |
269 | ||
2a24f2ce DA |
270 | saif->mclk_in_use = 1; |
271 | ret = mxs_saif_set_clk(saif, mclk, rate); | |
272 | if (ret) | |
273 | return ret; | |
274 | ||
67939b22 | 275 | ret = clk_prepare_enable(saif->clk); |
2a24f2ce DA |
276 | if (ret) |
277 | return ret; | |
278 | ||
279 | /* enable MCLK output */ | |
2a24f2ce DA |
280 | __raw_writel(BM_SAIF_CTRL_RUN, |
281 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | /* | |
287 | * SAIF DAI format configuration. | |
288 | * Should only be called when port is inactive. | |
289 | */ | |
290 | static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
291 | { | |
292 | u32 scr, stat; | |
293 | u32 scr0; | |
294 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
295 | ||
296 | stat = __raw_readl(saif->base + SAIF_STAT); | |
297 | if (stat & BM_SAIF_STAT_BUSY) { | |
298 | dev_err(cpu_dai->dev, "error: busy\n"); | |
299 | return -EBUSY; | |
300 | } | |
301 | ||
302 | scr0 = __raw_readl(saif->base + SAIF_CTRL); | |
303 | scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ | |
304 | & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; | |
305 | scr = 0; | |
306 | ||
307 | /* DAI mode */ | |
308 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
309 | case SND_SOC_DAIFMT_I2S: | |
310 | /* data frame low 1clk before data */ | |
311 | scr |= BM_SAIF_CTRL_DELAY; | |
312 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
313 | break; | |
314 | case SND_SOC_DAIFMT_LEFT_J: | |
315 | /* data frame high with data */ | |
316 | scr &= ~BM_SAIF_CTRL_DELAY; | |
317 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
318 | scr &= ~BM_SAIF_CTRL_JUSTIFY; | |
319 | break; | |
320 | default: | |
321 | return -EINVAL; | |
322 | } | |
323 | ||
324 | /* DAI clock inversion */ | |
325 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
326 | case SND_SOC_DAIFMT_IB_IF: | |
327 | scr |= BM_SAIF_CTRL_BITCLK_EDGE; | |
328 | scr |= BM_SAIF_CTRL_LRCLK_POLARITY; | |
329 | break; | |
330 | case SND_SOC_DAIFMT_IB_NF: | |
331 | scr |= BM_SAIF_CTRL_BITCLK_EDGE; | |
332 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
333 | break; | |
334 | case SND_SOC_DAIFMT_NB_IF: | |
335 | scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; | |
336 | scr |= BM_SAIF_CTRL_LRCLK_POLARITY; | |
337 | break; | |
338 | case SND_SOC_DAIFMT_NB_NF: | |
339 | scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; | |
340 | scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; | |
341 | break; | |
342 | } | |
343 | ||
344 | /* | |
345 | * Note: We simply just support master mode since SAIF TX can only | |
346 | * work as master. | |
76067540 DA |
347 | * Here the master is relative to codec side. |
348 | * Saif internally could be slave when working on EXTMASTER mode. | |
349 | * We just hide this to machine driver. | |
2a24f2ce DA |
350 | */ |
351 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
352 | case SND_SOC_DAIFMT_CBS_CFS: | |
76067540 DA |
353 | if (saif->id == saif->master_id) |
354 | scr &= ~BM_SAIF_CTRL_SLAVE_MODE; | |
355 | else | |
356 | scr |= BM_SAIF_CTRL_SLAVE_MODE; | |
357 | ||
2a24f2ce DA |
358 | __raw_writel(scr | scr0, saif->base + SAIF_CTRL); |
359 | break; | |
360 | default: | |
361 | return -EINVAL; | |
362 | } | |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
367 | static int mxs_saif_startup(struct snd_pcm_substream *substream, | |
368 | struct snd_soc_dai *cpu_dai) | |
369 | { | |
370 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
371 | snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param); | |
372 | ||
373 | /* clear error status to 0 for each re-open */ | |
374 | saif->fifo_underrun = 0; | |
375 | saif->fifo_overrun = 0; | |
376 | ||
377 | /* Clear Reset for normal operations */ | |
378 | __raw_writel(BM_SAIF_CTRL_SFTRST, | |
379 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
380 | ||
bbe8ff5e DA |
381 | /* clear clock gate */ |
382 | __raw_writel(BM_SAIF_CTRL_CLKGATE, | |
383 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
384 | ||
2a24f2ce DA |
385 | return 0; |
386 | } | |
387 | ||
388 | /* | |
389 | * Should only be called when port is inactive. | |
390 | * although can be called multiple times by upper layers. | |
391 | */ | |
392 | static int mxs_saif_hw_params(struct snd_pcm_substream *substream, | |
393 | struct snd_pcm_hw_params *params, | |
394 | struct snd_soc_dai *cpu_dai) | |
395 | { | |
396 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
397 | u32 scr, stat; | |
398 | int ret; | |
399 | ||
400 | /* mclk should already be set */ | |
401 | if (!saif->mclk && saif->mclk_in_use) { | |
402 | dev_err(cpu_dai->dev, "set mclk first\n"); | |
403 | return -EINVAL; | |
404 | } | |
405 | ||
406 | stat = __raw_readl(saif->base + SAIF_STAT); | |
407 | if (stat & BM_SAIF_STAT_BUSY) { | |
408 | dev_err(cpu_dai->dev, "error: busy\n"); | |
409 | return -EBUSY; | |
410 | } | |
411 | ||
412 | /* | |
413 | * Set saif clk based on sample rate. | |
414 | * If mclk is used, we also set mclk, if not, saif->mclk is | |
415 | * default 0, means not used. | |
416 | */ | |
417 | ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); | |
418 | if (ret) { | |
419 | dev_err(cpu_dai->dev, "unable to get proper clk\n"); | |
420 | return ret; | |
421 | } | |
422 | ||
423 | scr = __raw_readl(saif->base + SAIF_CTRL); | |
424 | ||
425 | scr &= ~BM_SAIF_CTRL_WORD_LENGTH; | |
426 | scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
427 | switch (params_format(params)) { | |
428 | case SNDRV_PCM_FORMAT_S16_LE: | |
429 | scr |= BF_SAIF_CTRL_WORD_LENGTH(0); | |
430 | break; | |
431 | case SNDRV_PCM_FORMAT_S20_3LE: | |
432 | scr |= BF_SAIF_CTRL_WORD_LENGTH(4); | |
433 | scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
434 | break; | |
435 | case SNDRV_PCM_FORMAT_S24_LE: | |
436 | scr |= BF_SAIF_CTRL_WORD_LENGTH(8); | |
437 | scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; | |
438 | break; | |
439 | default: | |
440 | return -EINVAL; | |
441 | } | |
442 | ||
443 | /* Tx/Rx config */ | |
444 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
445 | /* enable TX mode */ | |
446 | scr &= ~BM_SAIF_CTRL_READ_MODE; | |
447 | } else { | |
448 | /* enable RX mode */ | |
449 | scr |= BM_SAIF_CTRL_READ_MODE; | |
450 | } | |
451 | ||
452 | __raw_writel(scr, saif->base + SAIF_CTRL); | |
453 | return 0; | |
454 | } | |
455 | ||
456 | static int mxs_saif_prepare(struct snd_pcm_substream *substream, | |
457 | struct snd_soc_dai *cpu_dai) | |
458 | { | |
459 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
460 | ||
2a24f2ce DA |
461 | /* enable FIFO error irqs */ |
462 | __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, | |
463 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
468 | static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, | |
469 | struct snd_soc_dai *cpu_dai) | |
470 | { | |
471 | struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); | |
76067540 DA |
472 | struct mxs_saif *master_saif; |
473 | u32 delay; | |
474 | ||
475 | master_saif = mxs_saif_get_master(saif); | |
476 | if (!master_saif) | |
477 | return -EINVAL; | |
2a24f2ce DA |
478 | |
479 | switch (cmd) { | |
480 | case SNDRV_PCM_TRIGGER_START: | |
481 | case SNDRV_PCM_TRIGGER_RESUME: | |
482 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
483 | dev_dbg(cpu_dai->dev, "start\n"); | |
484 | ||
76067540 DA |
485 | clk_enable(master_saif->clk); |
486 | if (!master_saif->mclk_in_use) | |
487 | __raw_writel(BM_SAIF_CTRL_RUN, | |
488 | master_saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
489 | ||
490 | /* | |
491 | * If the saif's master is not himself, we also need to enable | |
492 | * itself clk for its internal basic logic to work. | |
493 | */ | |
494 | if (saif != master_saif) { | |
495 | clk_enable(saif->clk); | |
2a24f2ce DA |
496 | __raw_writel(BM_SAIF_CTRL_RUN, |
497 | saif->base + SAIF_CTRL + MXS_SET_ADDR); | |
76067540 | 498 | } |
2a24f2ce DA |
499 | |
500 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
501 | /* | |
502 | * write a data to saif data register to trigger | |
503 | * the transfer | |
504 | */ | |
505 | __raw_writel(0, saif->base + SAIF_DATA); | |
506 | } else { | |
507 | /* | |
508 | * read a data from saif data register to trigger | |
509 | * the receive | |
510 | */ | |
511 | __raw_readl(saif->base + SAIF_DATA); | |
512 | } | |
513 | ||
76067540 DA |
514 | master_saif->ongoing = 1; |
515 | ||
516 | dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", | |
2a24f2ce DA |
517 | __raw_readl(saif->base + SAIF_CTRL), |
518 | __raw_readl(saif->base + SAIF_STAT)); | |
519 | ||
76067540 DA |
520 | dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", |
521 | __raw_readl(master_saif->base + SAIF_CTRL), | |
522 | __raw_readl(master_saif->base + SAIF_STAT)); | |
2a24f2ce DA |
523 | break; |
524 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
525 | case SNDRV_PCM_TRIGGER_STOP: | |
526 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
527 | dev_dbg(cpu_dai->dev, "stop\n"); | |
528 | ||
76067540 DA |
529 | /* wait a while for the current sample to complete */ |
530 | delay = USEC_PER_SEC / master_saif->cur_rate; | |
531 | ||
532 | if (!master_saif->mclk_in_use) { | |
533 | __raw_writel(BM_SAIF_CTRL_RUN, | |
534 | master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
535 | udelay(delay); | |
536 | } | |
537 | clk_disable(master_saif->clk); | |
538 | ||
539 | if (saif != master_saif) { | |
2a24f2ce DA |
540 | __raw_writel(BM_SAIF_CTRL_RUN, |
541 | saif->base + SAIF_CTRL + MXS_CLR_ADDR); | |
76067540 DA |
542 | udelay(delay); |
543 | clk_disable(saif->clk); | |
544 | } | |
545 | ||
546 | master_saif->ongoing = 0; | |
2a24f2ce DA |
547 | |
548 | break; | |
549 | default: | |
550 | return -EINVAL; | |
551 | } | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
556 | #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 | |
557 | #define MXS_SAIF_FORMATS \ | |
558 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
559 | SNDRV_PCM_FMTBIT_S24_LE) | |
560 | ||
85e7652d | 561 | static const struct snd_soc_dai_ops mxs_saif_dai_ops = { |
2a24f2ce DA |
562 | .startup = mxs_saif_startup, |
563 | .trigger = mxs_saif_trigger, | |
564 | .prepare = mxs_saif_prepare, | |
565 | .hw_params = mxs_saif_hw_params, | |
566 | .set_sysclk = mxs_saif_set_dai_sysclk, | |
567 | .set_fmt = mxs_saif_set_dai_fmt, | |
568 | }; | |
569 | ||
570 | static int mxs_saif_dai_probe(struct snd_soc_dai *dai) | |
571 | { | |
572 | struct mxs_saif *saif = dev_get_drvdata(dai->dev); | |
573 | ||
574 | snd_soc_dai_set_drvdata(dai, saif); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | static struct snd_soc_dai_driver mxs_saif_dai = { | |
580 | .name = "mxs-saif", | |
581 | .probe = mxs_saif_dai_probe, | |
582 | .playback = { | |
583 | .channels_min = 2, | |
584 | .channels_max = 2, | |
585 | .rates = MXS_SAIF_RATES, | |
586 | .formats = MXS_SAIF_FORMATS, | |
587 | }, | |
588 | .capture = { | |
589 | .channels_min = 2, | |
590 | .channels_max = 2, | |
591 | .rates = MXS_SAIF_RATES, | |
592 | .formats = MXS_SAIF_FORMATS, | |
593 | }, | |
594 | .ops = &mxs_saif_dai_ops, | |
595 | }; | |
596 | ||
597 | static irqreturn_t mxs_saif_irq(int irq, void *dev_id) | |
598 | { | |
599 | struct mxs_saif *saif = dev_id; | |
600 | unsigned int stat; | |
601 | ||
602 | stat = __raw_readl(saif->base + SAIF_STAT); | |
603 | if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | | |
604 | BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) | |
605 | return IRQ_NONE; | |
606 | ||
607 | if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { | |
608 | dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); | |
609 | __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, | |
610 | saif->base + SAIF_STAT + MXS_CLR_ADDR); | |
611 | } | |
612 | ||
613 | if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { | |
614 | dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); | |
615 | __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, | |
616 | saif->base + SAIF_STAT + MXS_CLR_ADDR); | |
617 | } | |
618 | ||
619 | dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", | |
620 | __raw_readl(saif->base + SAIF_CTRL), | |
621 | __raw_readl(saif->base + SAIF_STAT)); | |
622 | ||
623 | return IRQ_HANDLED; | |
624 | } | |
625 | ||
9d0403e8 | 626 | static int __devinit mxs_saif_probe(struct platform_device *pdev) |
2a24f2ce | 627 | { |
08641c7c | 628 | struct device_node *np = pdev->dev.of_node; |
226d0f22 | 629 | struct resource *iores, *dmares; |
2a24f2ce | 630 | struct mxs_saif *saif; |
76067540 | 631 | struct mxs_saif_platform_data *pdata; |
f755865f | 632 | struct pinctrl *pinctrl; |
2a24f2ce DA |
633 | int ret = 0; |
634 | ||
08641c7c SG |
635 | |
636 | if (!np && pdev->id >= ARRAY_SIZE(mxs_saif)) | |
0bb98ba2 JL |
637 | return -EINVAL; |
638 | ||
830eb876 | 639 | saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); |
2a24f2ce DA |
640 | if (!saif) |
641 | return -ENOMEM; | |
642 | ||
08641c7c SG |
643 | if (np) { |
644 | struct device_node *master; | |
645 | saif->id = of_alias_get_id(np, "saif"); | |
646 | if (saif->id < 0) | |
647 | return saif->id; | |
648 | /* | |
649 | * If there is no "fsl,saif-master" phandle, it's a saif | |
650 | * master. Otherwise, it's a slave and its phandle points | |
651 | * to the master. | |
652 | */ | |
653 | master = of_parse_phandle(np, "fsl,saif-master", 0); | |
654 | if (!master) { | |
655 | saif->master_id = saif->id; | |
656 | } else { | |
657 | saif->master_id = of_alias_get_id(master, "saif"); | |
658 | if (saif->master_id < 0) | |
659 | return saif->master_id; | |
77882580 DA |
660 | } |
661 | } else { | |
08641c7c SG |
662 | saif->id = pdev->id; |
663 | pdata = pdev->dev.platform_data; | |
664 | if (pdata && !pdata->master_mode) | |
665 | saif->master_id = pdata->master_id; | |
666 | else | |
667 | saif->master_id = saif->id; | |
668 | } | |
669 | ||
670 | if (saif->master_id < 0 || saif->master_id >= ARRAY_SIZE(mxs_saif)) { | |
671 | dev_err(&pdev->dev, "get wrong master id\n"); | |
672 | return -EINVAL; | |
76067540 | 673 | } |
2a24f2ce | 674 | |
08641c7c SG |
675 | mxs_saif[saif->id] = saif; |
676 | ||
f755865f SG |
677 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
678 | if (IS_ERR(pinctrl)) { | |
679 | ret = PTR_ERR(pinctrl); | |
680 | return ret; | |
681 | } | |
682 | ||
2a24f2ce DA |
683 | saif->clk = clk_get(&pdev->dev, NULL); |
684 | if (IS_ERR(saif->clk)) { | |
685 | ret = PTR_ERR(saif->clk); | |
686 | dev_err(&pdev->dev, "Cannot get the clock: %d\n", | |
687 | ret); | |
830eb876 | 688 | return ret; |
2a24f2ce DA |
689 | } |
690 | ||
226d0f22 | 691 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2a24f2ce | 692 | |
830eb876 | 693 | saif->base = devm_request_and_ioremap(&pdev->dev, iores); |
2a24f2ce DA |
694 | if (!saif->base) { |
695 | dev_err(&pdev->dev, "ioremap failed\n"); | |
696 | ret = -ENODEV; | |
830eb876 | 697 | goto failed_get_resource; |
2a24f2ce DA |
698 | } |
699 | ||
226d0f22 JL |
700 | dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
701 | if (!dmares) { | |
08641c7c SG |
702 | /* |
703 | * TODO: This is a temporary solution and should be changed | |
704 | * to use generic DMA binding later when the helplers get in. | |
705 | */ | |
706 | ret = of_property_read_u32(np, "fsl,saif-dma-channel", | |
707 | &saif->dma_param.chan_num); | |
708 | if (ret) { | |
709 | dev_err(&pdev->dev, "failed to get dma channel\n"); | |
710 | goto failed_get_resource; | |
711 | } | |
712 | } else { | |
713 | saif->dma_param.chan_num = dmares->start; | |
2a24f2ce | 714 | } |
2a24f2ce DA |
715 | |
716 | saif->irq = platform_get_irq(pdev, 0); | |
717 | if (saif->irq < 0) { | |
718 | ret = saif->irq; | |
719 | dev_err(&pdev->dev, "failed to get irq resource: %d\n", | |
720 | ret); | |
830eb876 | 721 | goto failed_get_resource; |
2a24f2ce DA |
722 | } |
723 | ||
724 | saif->dev = &pdev->dev; | |
830eb876 JL |
725 | ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0, |
726 | "mxs-saif", saif); | |
2a24f2ce DA |
727 | if (ret) { |
728 | dev_err(&pdev->dev, "failed to request irq\n"); | |
830eb876 | 729 | goto failed_get_resource; |
2a24f2ce DA |
730 | } |
731 | ||
732 | saif->dma_param.chan_irq = platform_get_irq(pdev, 1); | |
733 | if (saif->dma_param.chan_irq < 0) { | |
734 | ret = saif->dma_param.chan_irq; | |
735 | dev_err(&pdev->dev, "failed to get dma irq resource: %d\n", | |
736 | ret); | |
830eb876 | 737 | goto failed_get_resource; |
2a24f2ce DA |
738 | } |
739 | ||
740 | platform_set_drvdata(pdev, saif); | |
741 | ||
742 | ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai); | |
743 | if (ret) { | |
744 | dev_err(&pdev->dev, "register DAI failed\n"); | |
830eb876 | 745 | goto failed_get_resource; |
2a24f2ce DA |
746 | } |
747 | ||
4da3fe78 | 748 | ret = mxs_pcm_platform_register(&pdev->dev); |
2a24f2ce | 749 | if (ret) { |
4da3fe78 SG |
750 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); |
751 | goto failed_pdev_alloc; | |
2a24f2ce DA |
752 | } |
753 | ||
754 | return 0; | |
755 | ||
2a24f2ce DA |
756 | failed_pdev_alloc: |
757 | snd_soc_unregister_dai(&pdev->dev); | |
2a24f2ce DA |
758 | failed_get_resource: |
759 | clk_put(saif->clk); | |
2a24f2ce DA |
760 | |
761 | return ret; | |
762 | } | |
763 | ||
764 | static int __devexit mxs_saif_remove(struct platform_device *pdev) | |
765 | { | |
2a24f2ce DA |
766 | struct mxs_saif *saif = platform_get_drvdata(pdev); |
767 | ||
4da3fe78 | 768 | mxs_pcm_platform_unregister(&pdev->dev); |
2a24f2ce | 769 | snd_soc_unregister_dai(&pdev->dev); |
2a24f2ce | 770 | clk_put(saif->clk); |
2a24f2ce DA |
771 | |
772 | return 0; | |
773 | } | |
774 | ||
08641c7c SG |
775 | static const struct of_device_id mxs_saif_dt_ids[] = { |
776 | { .compatible = "fsl,imx28-saif", }, | |
777 | { /* sentinel */ } | |
778 | }; | |
779 | MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); | |
780 | ||
2a24f2ce DA |
781 | static struct platform_driver mxs_saif_driver = { |
782 | .probe = mxs_saif_probe, | |
783 | .remove = __devexit_p(mxs_saif_remove), | |
784 | ||
785 | .driver = { | |
786 | .name = "mxs-saif", | |
787 | .owner = THIS_MODULE, | |
08641c7c | 788 | .of_match_table = mxs_saif_dt_ids, |
2a24f2ce DA |
789 | }, |
790 | }; | |
791 | ||
85aa0960 | 792 | module_platform_driver(mxs_saif_driver); |
2a24f2ce | 793 | |
2a24f2ce DA |
794 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); |
795 | MODULE_DESCRIPTION("MXS ASoC SAIF driver"); | |
796 | MODULE_LICENSE("GPL"); |